LLVM  15.0.0git
TargetInstrInfo.cpp
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1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DataLayout.h"
30 #include "llvm/MC/MCAsmInfo.h"
35 
36 using namespace llvm;
37 
39  "disable-sched-hazard", cl::Hidden, cl::init(false),
40  cl::desc("Disable hazard detection during preRA scheduling"));
41 
43 
45 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
46  const TargetRegisterInfo *TRI,
47  const MachineFunction &MF) const {
48  if (OpNum >= MCID.getNumOperands())
49  return nullptr;
50 
51  short RegClass = MCID.OpInfo[OpNum].RegClass;
52  if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
53  return TRI->getPointerRegClass(MF, RegClass);
54 
55  // Instructions like INSERT_SUBREG do not have fixed register classes.
56  if (RegClass < 0)
57  return nullptr;
58 
59  // Otherwise just look it up normally.
60  return TRI->getRegClass(RegClass);
61 }
62 
63 /// insertNoop - Insert a noop into the instruction stream at the specified
64 /// point.
67  llvm_unreachable("Target didn't implement insertNoop!");
68 }
69 
70 /// insertNoops - Insert noops into the instruction stream at the specified
71 /// point.
74  unsigned Quantity) const {
75  for (unsigned i = 0; i < Quantity; ++i)
76  insertNoop(MBB, MI);
77 }
78 
79 static bool isAsmComment(const char *Str, const MCAsmInfo &MAI) {
80  return strncmp(Str, MAI.getCommentString().data(),
81  MAI.getCommentString().size()) == 0;
82 }
83 
84 /// Measure the specified inline asm to determine an approximation of its
85 /// length.
86 /// Comments (which run till the next SeparatorString or newline) do not
87 /// count as an instruction.
88 /// Any other non-whitespace text is considered an instruction, with
89 /// multiple instructions separated by SeparatorString or newlines.
90 /// Variable-length instructions are not handled here; this function
91 /// may be overloaded in the target code to do that.
92 /// We implement a special case of the .space directive which takes only a
93 /// single integer argument in base 10 that is the size in bytes. This is a
94 /// restricted form of the GAS directive in that we only interpret
95 /// simple--i.e. not a logical or arithmetic expression--size values without
96 /// the optional fill value. This is primarily used for creating arbitrary
97 /// sized inline asm blocks for testing purposes.
99  const char *Str,
100  const MCAsmInfo &MAI, const TargetSubtargetInfo *STI) const {
101  // Count the number of instructions in the asm.
102  bool AtInsnStart = true;
103  unsigned Length = 0;
104  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
105  for (; *Str; ++Str) {
106  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
107  strlen(MAI.getSeparatorString())) == 0) {
108  AtInsnStart = true;
109  } else if (isAsmComment(Str, MAI)) {
110  // Stop counting as an instruction after a comment until the next
111  // separator.
112  AtInsnStart = false;
113  }
114 
115  if (AtInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
116  unsigned AddLength = MaxInstLength;
117  if (strncmp(Str, ".space", 6) == 0) {
118  char *EStr;
119  int SpaceSize;
120  SpaceSize = strtol(Str + 6, &EStr, 10);
121  SpaceSize = SpaceSize < 0 ? 0 : SpaceSize;
122  while (*EStr != '\n' && isSpace(static_cast<unsigned char>(*EStr)))
123  ++EStr;
124  if (*EStr == '\0' || *EStr == '\n' ||
125  isAsmComment(EStr, MAI)) // Successfully parsed .space argument
126  AddLength = SpaceSize;
127  }
128  Length += AddLength;
129  AtInsnStart = false;
130  }
131  }
132 
133  return Length;
134 }
135 
136 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
137 /// after it, replacing it with an unconditional branch to NewDest.
138 void
140  MachineBasicBlock *NewDest) const {
141  MachineBasicBlock *MBB = Tail->getParent();
142 
143  // Remove all the old successors of MBB from the CFG.
144  while (!MBB->succ_empty())
146 
147  // Save off the debug loc before erasing the instruction.
148  DebugLoc DL = Tail->getDebugLoc();
149 
150  // Update call site info and remove all the dead instructions
151  // from the end of MBB.
152  while (Tail != MBB->end()) {
153  auto MI = Tail++;
154  if (MI->shouldUpdateCallSiteInfo())
156  MBB->erase(MI);
157  }
158 
159  // If MBB isn't immediately before MBB, insert a branch to it.
161  insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL);
162  MBB->addSuccessor(NewDest);
163 }
164 
166  bool NewMI, unsigned Idx1,
167  unsigned Idx2) const {
168  const MCInstrDesc &MCID = MI.getDesc();
169  bool HasDef = MCID.getNumDefs();
170  if (HasDef && !MI.getOperand(0).isReg())
171  // No idea how to commute this instruction. Target should implement its own.
172  return nullptr;
173 
174  unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
175  unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
176  assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
177  CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
178  "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
179  assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
180  "This only knows how to commute register operands so far");
181 
182  Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
183  Register Reg1 = MI.getOperand(Idx1).getReg();
184  Register Reg2 = MI.getOperand(Idx2).getReg();
185  unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
186  unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
187  unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
188  bool Reg1IsKill = MI.getOperand(Idx1).isKill();
189  bool Reg2IsKill = MI.getOperand(Idx2).isKill();
190  bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
191  bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
192  bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
193  bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
194  // Avoid calling isRenamable for virtual registers since we assert that
195  // renamable property is only queried/set for physical registers.
196  bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1)
197  ? MI.getOperand(Idx1).isRenamable()
198  : false;
199  bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
200  ? MI.getOperand(Idx2).isRenamable()
201  : false;
202  // If destination is tied to either of the commuted source register, then
203  // it must be updated.
204  if (HasDef && Reg0 == Reg1 &&
205  MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
206  Reg2IsKill = false;
207  Reg0 = Reg2;
208  SubReg0 = SubReg2;
209  } else if (HasDef && Reg0 == Reg2 &&
210  MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
211  Reg1IsKill = false;
212  Reg0 = Reg1;
213  SubReg0 = SubReg1;
214  }
215 
216  MachineInstr *CommutedMI = nullptr;
217  if (NewMI) {
218  // Create a new instruction.
219  MachineFunction &MF = *MI.getMF();
220  CommutedMI = MF.CloneMachineInstr(&MI);
221  } else {
222  CommutedMI = &MI;
223  }
224 
225  if (HasDef) {
226  CommutedMI->getOperand(0).setReg(Reg0);
227  CommutedMI->getOperand(0).setSubReg(SubReg0);
228  }
229  CommutedMI->getOperand(Idx2).setReg(Reg1);
230  CommutedMI->getOperand(Idx1).setReg(Reg2);
231  CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
232  CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
233  CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
234  CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
235  CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
236  CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
237  CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
238  CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
239  // Avoid calling setIsRenamable for virtual registers since we assert that
240  // renamable property is only queried/set for physical registers.
242  CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
244  CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
245  return CommutedMI;
246 }
247 
249  unsigned OpIdx1,
250  unsigned OpIdx2) const {
251  // If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
252  // any commutable operand, which is done in findCommutedOpIndices() method
253  // called below.
254  if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
255  !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
256  assert(MI.isCommutable() &&
257  "Precondition violation: MI must be commutable.");
258  return nullptr;
259  }
260  return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
261 }
262 
263 bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,
264  unsigned &ResultIdx2,
265  unsigned CommutableOpIdx1,
266  unsigned CommutableOpIdx2) {
267  if (ResultIdx1 == CommuteAnyOperandIndex &&
268  ResultIdx2 == CommuteAnyOperandIndex) {
269  ResultIdx1 = CommutableOpIdx1;
270  ResultIdx2 = CommutableOpIdx2;
271  } else if (ResultIdx1 == CommuteAnyOperandIndex) {
272  if (ResultIdx2 == CommutableOpIdx1)
273  ResultIdx1 = CommutableOpIdx2;
274  else if (ResultIdx2 == CommutableOpIdx2)
275  ResultIdx1 = CommutableOpIdx1;
276  else
277  return false;
278  } else if (ResultIdx2 == CommuteAnyOperandIndex) {
279  if (ResultIdx1 == CommutableOpIdx1)
280  ResultIdx2 = CommutableOpIdx2;
281  else if (ResultIdx1 == CommutableOpIdx2)
282  ResultIdx2 = CommutableOpIdx1;
283  else
284  return false;
285  } else
286  // Check that the result operand indices match the given commutable
287  // operand indices.
288  return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
289  (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
290 
291  return true;
292 }
293 
295  unsigned &SrcOpIdx1,
296  unsigned &SrcOpIdx2) const {
297  assert(!MI.isBundle() &&
298  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
299 
300  const MCInstrDesc &MCID = MI.getDesc();
301  if (!MCID.isCommutable())
302  return false;
303 
304  // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
305  // is not true, then the target must implement this.
306  unsigned CommutableOpIdx1 = MCID.getNumDefs();
307  unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
308  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
309  CommutableOpIdx1, CommutableOpIdx2))
310  return false;
311 
312  if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
313  // No idea.
314  return false;
315  return true;
316 }
317 
319  if (!MI.isTerminator()) return false;
320 
321  // Conditional branch is a special case.
322  if (MI.isBranch() && !MI.isBarrier())
323  return true;
324  if (!MI.isPredicable())
325  return true;
326  return !isPredicated(MI);
327 }
328 
331  bool MadeChange = false;
332 
333  assert(!MI.isBundle() &&
334  "TargetInstrInfo::PredicateInstruction() can't handle bundles");
335 
336  const MCInstrDesc &MCID = MI.getDesc();
337  if (!MI.isPredicable())
338  return false;
339 
340  for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
341  if (MCID.OpInfo[i].isPredicate()) {
342  MachineOperand &MO = MI.getOperand(i);
343  if (MO.isReg()) {
344  MO.setReg(Pred[j].getReg());
345  MadeChange = true;
346  } else if (MO.isImm()) {
347  MO.setImm(Pred[j].getImm());
348  MadeChange = true;
349  } else if (MO.isMBB()) {
350  MO.setMBB(Pred[j].getMBB());
351  MadeChange = true;
352  }
353  ++j;
354  }
355  }
356  return MadeChange;
357 }
358 
360  const MachineInstr &MI,
362  size_t StartSize = Accesses.size();
363  for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
364  oe = MI.memoperands_end();
365  o != oe; ++o) {
366  if ((*o)->isLoad() &&
367  isa_and_nonnull<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
368  Accesses.push_back(*o);
369  }
370  return Accesses.size() != StartSize;
371 }
372 
374  const MachineInstr &MI,
376  size_t StartSize = Accesses.size();
377  for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
378  oe = MI.memoperands_end();
379  o != oe; ++o) {
380  if ((*o)->isStore() &&
381  isa_and_nonnull<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
382  Accesses.push_back(*o);
383  }
384  return Accesses.size() != StartSize;
385 }
386 
388  unsigned SubIdx, unsigned &Size,
389  unsigned &Offset,
390  const MachineFunction &MF) const {
392  if (!SubIdx) {
393  Size = TRI->getSpillSize(*RC);
394  Offset = 0;
395  return true;
396  }
397  unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
398  // Convert bit size to byte size.
399  if (BitSize % 8)
400  return false;
401 
402  int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
403  if (BitOffset < 0 || BitOffset % 8)
404  return false;
405 
406  Size = BitSize / 8;
407  Offset = (unsigned)BitOffset / 8;
408 
409  assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
410 
411  if (!MF.getDataLayout().isLittleEndian()) {
412  Offset = TRI->getSpillSize(*RC) - (Offset + Size);
413  }
414  return true;
415 }
416 
419  Register DestReg, unsigned SubIdx,
420  const MachineInstr &Orig,
421  const TargetRegisterInfo &TRI) const {
423  MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
424  MBB.insert(I, MI);
425 }
426 
428  const MachineInstr &MI1,
429  const MachineRegisterInfo *MRI) const {
431 }
432 
434  MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const {
435  assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
436  MachineFunction &MF = *MBB.getParent();
437  return MF.cloneMachineInstrBundle(MBB, InsertBefore, Orig);
438 }
439 
440 // If the COPY instruction in MI can be folded to a stack operation, return
441 // the register class to use.
443  unsigned FoldIdx) {
444  assert(MI.isCopy() && "MI must be a COPY instruction");
445  if (MI.getNumOperands() != 2)
446  return nullptr;
447  assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
448 
449  const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
450  const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
451 
452  if (FoldOp.getSubReg() || LiveOp.getSubReg())
453  return nullptr;
454 
455  Register FoldReg = FoldOp.getReg();
456  Register LiveReg = LiveOp.getReg();
457 
458  assert(Register::isVirtualRegister(FoldReg) && "Cannot fold physregs");
459 
460  const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
461  const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
462 
463  if (Register::isPhysicalRegister(LiveOp.getReg()))
464  return RC->contains(LiveOp.getReg()) ? RC : nullptr;
465 
466  if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
467  return RC;
468 
469  // FIXME: Allow folding when register classes are memory compatible.
470  return nullptr;
471 }
472 
473 MCInst TargetInstrInfo::getNop() const { llvm_unreachable("Not implemented"); }
474 
475 std::pair<unsigned, unsigned>
477  switch (MI.getOpcode()) {
478  case TargetOpcode::STACKMAP:
479  // StackMapLiveValues are foldable
480  return std::make_pair(0, StackMapOpers(&MI).getVarIdx());
481  case TargetOpcode::PATCHPOINT:
482  // For PatchPoint, the call args are not foldable (even if reported in the
483  // stackmap e.g. via anyregcc).
484  return std::make_pair(0, PatchPointOpers(&MI).getVarIdx());
485  case TargetOpcode::STATEPOINT:
486  // For statepoints, fold deopt and gc arguments, but not call arguments.
487  return std::make_pair(MI.getNumDefs(), StatepointOpers(&MI).getVarIdx());
488  default:
489  llvm_unreachable("unexpected stackmap opcode");
490  }
491 }
492 
495  const TargetInstrInfo &TII) {
496  unsigned StartIdx = 0;
497  unsigned NumDefs = 0;
498  // getPatchpointUnfoldableRange throws guarantee if MI is not a patchpoint.
499  std::tie(NumDefs, StartIdx) = TII.getPatchpointUnfoldableRange(MI);
500 
501  unsigned DefToFoldIdx = MI.getNumOperands();
502 
503  // Return false if any operands requested for folding are not foldable (not
504  // part of the stackmap's live values).
505  for (unsigned Op : Ops) {
506  if (Op < NumDefs) {
507  assert(DefToFoldIdx == MI.getNumOperands() && "Folding multiple defs");
508  DefToFoldIdx = Op;
509  } else if (Op < StartIdx) {
510  return nullptr;
511  }
512  if (MI.getOperand(Op).isTied())
513  return nullptr;
514  }
515 
516  MachineInstr *NewMI =
517  MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
518  MachineInstrBuilder MIB(MF, NewMI);
519 
520  // No need to fold return, the meta data, and function arguments
521  for (unsigned i = 0; i < StartIdx; ++i)
522  if (i != DefToFoldIdx)
523  MIB.add(MI.getOperand(i));
524 
525  for (unsigned i = StartIdx, e = MI.getNumOperands(); i < e; ++i) {
526  MachineOperand &MO = MI.getOperand(i);
527  unsigned TiedTo = e;
528  (void)MI.isRegTiedToDefOperand(i, &TiedTo);
529 
530  if (is_contained(Ops, i)) {
531  assert(TiedTo == e && "Cannot fold tied operands");
532  unsigned SpillSize;
533  unsigned SpillOffset;
534  // Compute the spill slot size and offset.
535  const TargetRegisterClass *RC =
536  MF.getRegInfo().getRegClass(MO.getReg());
537  bool Valid =
538  TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
539  if (!Valid)
540  report_fatal_error("cannot spill patchpoint subregister operand");
541  MIB.addImm(StackMaps::IndirectMemRefOp);
542  MIB.addImm(SpillSize);
544  MIB.addImm(SpillOffset);
545  } else {
546  MIB.add(MO);
547  if (TiedTo < e) {
548  assert(TiedTo < NumDefs && "Bad tied operand");
549  if (TiedTo > DefToFoldIdx)
550  --TiedTo;
551  NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1);
552  }
553  }
554  }
555  return NewMI;
556 }
557 
559  ArrayRef<unsigned> Ops, int FI,
560  LiveIntervals *LIS,
561  VirtRegMap *VRM) const {
562  auto Flags = MachineMemOperand::MONone;
563  for (unsigned OpIdx : Ops)
564  Flags |= MI.getOperand(OpIdx).isDef() ? MachineMemOperand::MOStore
566 
567  MachineBasicBlock *MBB = MI.getParent();
568  assert(MBB && "foldMemoryOperand needs an inserted instruction");
569  MachineFunction &MF = *MBB->getParent();
570 
571  // If we're not folding a load into a subreg, the size of the load is the
572  // size of the spill slot. But if we are, we need to figure out what the
573  // actual load size is.
574  int64_t MemSize = 0;
575  const MachineFrameInfo &MFI = MF.getFrameInfo();
577 
578  if (Flags & MachineMemOperand::MOStore) {
579  MemSize = MFI.getObjectSize(FI);
580  } else {
581  for (unsigned OpIdx : Ops) {
582  int64_t OpSize = MFI.getObjectSize(FI);
583 
584  if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
585  unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
586  if (SubRegSize > 0 && !(SubRegSize % 8))
587  OpSize = SubRegSize / 8;
588  }
589 
590  MemSize = std::max(MemSize, OpSize);
591  }
592  }
593 
594  assert(MemSize && "Did not expect a zero-sized stack slot");
595 
596  MachineInstr *NewMI = nullptr;
597 
598  if (MI.getOpcode() == TargetOpcode::STACKMAP ||
599  MI.getOpcode() == TargetOpcode::PATCHPOINT ||
600  MI.getOpcode() == TargetOpcode::STATEPOINT) {
601  // Fold stackmap/patchpoint.
602  NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
603  if (NewMI)
604  MBB->insert(MI, NewMI);
605  } else {
606  // Ask the target to do the actual folding.
607  NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS, VRM);
608  }
609 
610  if (NewMI) {
611  NewMI->setMemRefs(MF, MI.memoperands());
612  // Add a memory operand, foldMemoryOperandImpl doesn't do that.
613  assert((!(Flags & MachineMemOperand::MOStore) ||
614  NewMI->mayStore()) &&
615  "Folded a def to a non-store!");
616  assert((!(Flags & MachineMemOperand::MOLoad) ||
617  NewMI->mayLoad()) &&
618  "Folded a use to a non-load!");
619  assert(MFI.getObjectOffset(FI) != -1);
620  MachineMemOperand *MMO =
622  Flags, MemSize, MFI.getObjectAlign(FI));
623  NewMI->addMemOperand(MF, MMO);
624 
625  // The pass "x86 speculative load hardening" always attaches symbols to
626  // call instructions. We need copy it form old instruction.
627  NewMI->cloneInstrSymbols(MF, MI);
628 
629  return NewMI;
630  }
631 
632  // Straight COPY may fold as load/store.
633  if (!MI.isCopy() || Ops.size() != 1)
634  return nullptr;
635 
636  const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
637  if (!RC)
638  return nullptr;
639 
640  const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
642 
643  if (Flags == MachineMemOperand::MOStore)
644  storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
645  else
646  loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
647  return &*--Pos;
648 }
649 
651  ArrayRef<unsigned> Ops,
652  MachineInstr &LoadMI,
653  LiveIntervals *LIS) const {
654  assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
655 #ifndef NDEBUG
656  for (unsigned OpIdx : Ops)
657  assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
658 #endif
659 
660  MachineBasicBlock &MBB = *MI.getParent();
661  MachineFunction &MF = *MBB.getParent();
662 
663  // Ask the target to do the actual folding.
664  MachineInstr *NewMI = nullptr;
665  int FrameIndex = 0;
666 
667  if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
668  MI.getOpcode() == TargetOpcode::PATCHPOINT ||
669  MI.getOpcode() == TargetOpcode::STATEPOINT) &&
670  isLoadFromStackSlot(LoadMI, FrameIndex)) {
671  // Fold stackmap/patchpoint.
672  NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
673  if (NewMI)
674  NewMI = &*MBB.insert(MI, NewMI);
675  } else {
676  // Ask the target to do the actual folding.
677  NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS);
678  }
679 
680  if (!NewMI)
681  return nullptr;
682 
683  // Copy the memoperands from the load to the folded instruction.
684  if (MI.memoperands_empty()) {
685  NewMI->setMemRefs(MF, LoadMI.memoperands());
686  } else {
687  // Handle the rare case of folding multiple loads.
688  NewMI->setMemRefs(MF, MI.memoperands());
690  E = LoadMI.memoperands_end();
691  I != E; ++I) {
692  NewMI->addMemOperand(MF, *I);
693  }
694  }
695  return NewMI;
696 }
697 
699  const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
700  const MachineOperand &Op1 = Inst.getOperand(1);
701  const MachineOperand &Op2 = Inst.getOperand(2);
703 
704  // We need virtual register definitions for the operands that we will
705  // reassociate.
706  MachineInstr *MI1 = nullptr;
707  MachineInstr *MI2 = nullptr;
708  if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
709  MI1 = MRI.getUniqueVRegDef(Op1.getReg());
710  if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
711  MI2 = MRI.getUniqueVRegDef(Op2.getReg());
712 
713  // And they need to be in the trace (otherwise, they won't have a depth).
714  return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
715 }
716 
718  bool &Commuted) const {
719  const MachineBasicBlock *MBB = Inst.getParent();
723  unsigned AssocOpcode = Inst.getOpcode();
724 
725  // If only one operand has the same opcode and it's the second source operand,
726  // the operands must be commuted.
727  Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
728  if (Commuted)
729  std::swap(MI1, MI2);
730 
731  // 1. The previous instruction must be the same type as Inst.
732  // 2. The previous instruction must also be associative/commutative (this can
733  // be different even for instructions with the same opcode if traits like
734  // fast-math-flags are included).
735  // 3. The previous instruction must have virtual register definitions for its
736  // operands in the same basic block as Inst.
737  // 4. The previous instruction's result must only be used by Inst.
738  return MI1->getOpcode() == AssocOpcode && isAssociativeAndCommutative(*MI1) &&
739  hasReassociableOperands(*MI1, MBB) &&
741 }
742 
743 // 1. The operation must be associative and commutative.
744 // 2. The instruction must have virtual register definitions for its
745 // operands in the same basic block.
746 // 3. The instruction must have a reassociable sibling.
748  bool &Commuted) const {
749  return isAssociativeAndCommutative(Inst) &&
750  hasReassociableOperands(Inst, Inst.getParent()) &&
751  hasReassociableSibling(Inst, Commuted);
752 }
753 
754 // The concept of the reassociation pass is that these operations can benefit
755 // from this kind of transformation:
756 //
757 // A = ? op ?
758 // B = A op X (Prev)
759 // C = B op Y (Root)
760 // -->
761 // A = ? op ?
762 // B = X op Y
763 // C = A op B
764 //
765 // breaking the dependency between A and B, allowing them to be executed in
766 // parallel (or back-to-back in a pipeline) instead of depending on each other.
767 
768 // FIXME: This has the potential to be expensive (compile time) while not
769 // improving the code at all. Some ways to limit the overhead:
770 // 1. Track successful transforms; bail out if hit rate gets too low.
771 // 2. Only enable at -O3 or some other non-default optimization level.
772 // 3. Pre-screen pattern candidates here: if an operand of the previous
773 // instruction is known to not increase the critical path, then don't match
774 // that pattern.
777  bool DoRegPressureReduce) const {
778  bool Commute;
779  if (isReassociationCandidate(Root, Commute)) {
780  // We found a sequence of instructions that may be suitable for a
781  // reassociation of operands to increase ILP. Specify each commutation
782  // possibility for the Prev instruction in the sequence and let the
783  // machine combiner decide if changing the operands is worthwhile.
784  if (Commute) {
785  Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB);
786  Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB);
787  } else {
788  Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY);
789  Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY);
790  }
791  return true;
792  }
793 
794  return false;
795 }
796 
797 /// Return true when a code sequence can improve loop throughput.
798 bool
800  return false;
801 }
802 
803 /// Attempt the reassociation transformation to reduce critical path length.
804 /// See the above comments before getMachineCombinerPatterns().
806  MachineInstr &Root, MachineInstr &Prev,
810  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
811  MachineFunction *MF = Root.getMF();
813  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
815  const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
816 
817  // This array encodes the operand index for each parameter because the
818  // operands may be commuted. Each row corresponds to a pattern value,
819  // and each column specifies the index of A, B, X, Y.
820  unsigned OpIdx[4][4] = {
821  { 1, 1, 2, 2 },
822  { 1, 2, 2, 1 },
823  { 2, 1, 1, 2 },
824  { 2, 2, 1, 1 }
825  };
826 
827  int Row;
828  switch (Pattern) {
829  case MachineCombinerPattern::REASSOC_AX_BY: Row = 0; break;
830  case MachineCombinerPattern::REASSOC_AX_YB: Row = 1; break;
831  case MachineCombinerPattern::REASSOC_XA_BY: Row = 2; break;
832  case MachineCombinerPattern::REASSOC_XA_YB: Row = 3; break;
833  default: llvm_unreachable("unexpected MachineCombinerPattern");
834  }
835 
836  MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
837  MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
838  MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
839  MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
840  MachineOperand &OpC = Root.getOperand(0);
841 
842  Register RegA = OpA.getReg();
843  Register RegB = OpB.getReg();
844  Register RegX = OpX.getReg();
845  Register RegY = OpY.getReg();
846  Register RegC = OpC.getReg();
847 
848  if (Register::isVirtualRegister(RegA))
849  MRI.constrainRegClass(RegA, RC);
850  if (Register::isVirtualRegister(RegB))
851  MRI.constrainRegClass(RegB, RC);
852  if (Register::isVirtualRegister(RegX))
853  MRI.constrainRegClass(RegX, RC);
854  if (Register::isVirtualRegister(RegY))
855  MRI.constrainRegClass(RegY, RC);
856  if (Register::isVirtualRegister(RegC))
857  MRI.constrainRegClass(RegC, RC);
858 
859  // Create a new virtual register for the result of (X op Y) instead of
860  // recycling RegB because the MachineCombiner's computation of the critical
861  // path requires a new register definition rather than an existing one.
862  Register NewVR = MRI.createVirtualRegister(RC);
863  InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
864 
865  unsigned Opcode = Root.getOpcode();
866  bool KillA = OpA.isKill();
867  bool KillX = OpX.isKill();
868  bool KillY = OpY.isKill();
869 
870  // Create new instructions for insertion.
871  MachineInstrBuilder MIB1 =
872  BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
873  .addReg(RegX, getKillRegState(KillX))
874  .addReg(RegY, getKillRegState(KillY))
875  .setMIFlags(Prev.getFlags());
876  MachineInstrBuilder MIB2 =
877  BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
878  .addReg(RegA, getKillRegState(KillA))
879  .addReg(NewVR, getKillRegState(true))
880  .setMIFlags(Root.getFlags());
881 
882  setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
883 
884  // Record new instructions for insertion and old instructions for deletion.
885  InsInstrs.push_back(MIB1);
886  InsInstrs.push_back(MIB2);
887  DelInstrs.push_back(&Prev);
888  DelInstrs.push_back(&Root);
889 }
890 
895  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
897 
898  // Select the previous instruction in the sequence based on the input pattern.
899  MachineInstr *Prev = nullptr;
900  switch (Pattern) {
903  Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
904  break;
907  Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
908  break;
909  default:
910  break;
911  }
912 
913  assert(Prev && "Unknown pattern for machine combiner");
914 
915  reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
916 }
917 
918 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
919  const MachineInstr &MI, AAResults *AA) const {
920  const MachineFunction &MF = *MI.getMF();
921  const MachineRegisterInfo &MRI = MF.getRegInfo();
922 
923  // Remat clients assume operand 0 is the defined register.
924  if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
925  return false;
926  Register DefReg = MI.getOperand(0).getReg();
927 
928  // A sub-register definition can only be rematerialized if the instruction
929  // doesn't read the other parts of the register. Otherwise it is really a
930  // read-modify-write operation on the full virtual register which cannot be
931  // moved safely.
932  if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
933  MI.readsVirtualRegister(DefReg))
934  return false;
935 
936  // A load from a fixed stack slot can be rematerialized. This may be
937  // redundant with subsequent checks, but it's target-independent,
938  // simple, and a common case.
939  int FrameIdx = 0;
940  if (isLoadFromStackSlot(MI, FrameIdx) &&
941  MF.getFrameInfo().isImmutableObjectIndex(FrameIdx))
942  return true;
943 
944  // Avoid instructions obviously unsafe for remat.
945  if (MI.isNotDuplicable() || MI.mayStore() || MI.mayRaiseFPException() ||
946  MI.hasUnmodeledSideEffects())
947  return false;
948 
949  // Don't remat inline asm. We have no idea how expensive it is
950  // even if it's side effect free.
951  if (MI.isInlineAsm())
952  return false;
953 
954  // Avoid instructions which load from potentially varying memory.
955  if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
956  return false;
957 
958  // If any of the registers accessed are non-constant, conservatively assume
959  // the instruction is not rematerializable.
960  for (const MachineOperand &MO : MI.operands()) {
961  if (!MO.isReg()) continue;
962  Register Reg = MO.getReg();
963  if (Reg == 0)
964  continue;
965 
966  // Check for a well-behaved physical register.
968  if (MO.isUse()) {
969  // If the physreg has no defs anywhere, it's just an ambient register
970  // and we can freely move its uses. Alternatively, if it's allocatable,
971  // it could get allocated to something with a def during allocation.
972  if (!MRI.isConstantPhysReg(Reg))
973  return false;
974  } else {
975  // A physreg def. We can't remat it.
976  return false;
977  }
978  continue;
979  }
980 
981  // Only allow one virtual-register def. There may be multiple defs of the
982  // same virtual register, though.
983  if (MO.isDef() && Reg != DefReg)
984  return false;
985 
986  // Don't allow any virtual-register uses. Rematting an instruction with
987  // virtual register uses would length the live ranges of the uses, which
988  // is not necessarily a good idea, certainly not "trivial".
989  if (MO.isUse())
990  return false;
991  }
992 
993  // Everything checked out.
994  return true;
995 }
996 
998  const MachineFunction *MF = MI.getMF();
1000  bool StackGrowsDown =
1002 
1003  unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
1004  unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
1005 
1006  if (!isFrameInstr(MI))
1007  return 0;
1008 
1009  int SPAdj = TFI->alignSPAdjust(getFrameSize(MI));
1010 
1011  if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
1012  (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
1013  SPAdj = -SPAdj;
1014 
1015  return SPAdj;
1016 }
1017 
1018 /// isSchedulingBoundary - Test if the given instruction should be
1019 /// considered a scheduling boundary. This primarily includes labels
1020 /// and terminators.
1022  const MachineBasicBlock *MBB,
1023  const MachineFunction &MF) const {
1024  // Terminators and labels can't be scheduled around.
1025  if (MI.isTerminator() || MI.isPosition())
1026  return true;
1027 
1028  // INLINEASM_BR can jump to another block
1029  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1030  return true;
1031 
1032  // Don't attempt to schedule around any instruction that defines
1033  // a stack-oriented pointer, as it's unlikely to be profitable. This
1034  // saves compile time, because it doesn't require every single
1035  // stack slot reference to depend on the instruction that does the
1036  // modification.
1037  const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
1039  return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
1040 }
1041 
1042 // Provide a global flag for disabling the PreRA hazard recognizer that targets
1043 // may choose to honor.
1045  return !DisableHazardRecognizer;
1046 }
1047 
1048 // Default implementation of CreateTargetRAHazardRecognizer.
1051  const ScheduleDAG *DAG) const {
1052  // Dummy hazard recognizer allows all instructions to issue.
1053  return new ScheduleHazardRecognizer();
1054 }
1055 
1056 // Default implementation of CreateTargetMIHazardRecognizer.
1058  const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
1059  return new ScoreboardHazardRecognizer(II, DAG, "machine-scheduler");
1060 }
1061 
1062 // Default implementation of CreateTargetPostRAHazardRecognizer.
1065  const ScheduleDAG *DAG) const {
1066  return new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
1067 }
1068 
1069 // Default implementation of getMemOperandWithOffset.
1071  const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
1072  bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
1074  unsigned Width;
1075  if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
1076  Width, TRI) ||
1077  BaseOps.size() != 1)
1078  return false;
1079  BaseOp = BaseOps.front();
1080  return true;
1081 }
1082 
1083 //===----------------------------------------------------------------------===//
1084 // SelectionDAG latency interface.
1085 //===----------------------------------------------------------------------===//
1086 
1087 int
1089  SDNode *DefNode, unsigned DefIdx,
1090  SDNode *UseNode, unsigned UseIdx) const {
1091  if (!ItinData || ItinData->isEmpty())
1092  return -1;
1093 
1094  if (!DefNode->isMachineOpcode())
1095  return -1;
1096 
1097  unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1098  if (!UseNode->isMachineOpcode())
1099  return ItinData->getOperandCycle(DefClass, DefIdx);
1100  unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1101  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1102 }
1103 
1105  SDNode *N) const {
1106  if (!ItinData || ItinData->isEmpty())
1107  return 1;
1108 
1109  if (!N->isMachineOpcode())
1110  return 1;
1111 
1112  return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1113 }
1114 
1115 //===----------------------------------------------------------------------===//
1116 // MachineInstr latency interface.
1117 //===----------------------------------------------------------------------===//
1118 
1120  const MachineInstr &MI) const {
1121  if (!ItinData || ItinData->isEmpty())
1122  return 1;
1123 
1124  unsigned Class = MI.getDesc().getSchedClass();
1125  int UOps = ItinData->Itineraries[Class].NumMicroOps;
1126  if (UOps >= 0)
1127  return UOps;
1128 
1129  // The # of u-ops is dynamically determined. The specific target should
1130  // override this function to return the right number.
1131  return 1;
1132 }
1133 
1134 /// Return the default expected latency for a def based on it's opcode.
1136  const MachineInstr &DefMI) const {
1137  if (DefMI.isTransient())
1138  return 0;
1139  if (DefMI.mayLoad())
1140  return SchedModel.LoadLatency;
1141  if (isHighLatencyDef(DefMI.getOpcode()))
1142  return SchedModel.HighLatency;
1143  return 1;
1144 }
1145 
1147  return 0;
1148 }
1149 
1151  const MachineInstr &MI,
1152  unsigned *PredCost) const {
1153  // Default to one cycle for no itinerary. However, an "empty" itinerary may
1154  // still have a MinLatency property, which getStageLatency checks.
1155  if (!ItinData)
1156  return MI.mayLoad() ? 2 : 1;
1157 
1158  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1159 }
1160 
1162  const MachineInstr &DefMI,
1163  unsigned DefIdx) const {
1164  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1165  if (!ItinData || ItinData->isEmpty())
1166  return false;
1167 
1168  unsigned DefClass = DefMI.getDesc().getSchedClass();
1169  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1170  return (DefCycle != -1 && DefCycle <= 1);
1171 }
1172 
1175  Register Reg) const {
1176  const MachineFunction *MF = MI.getMF();
1179  int64_t Offset;
1180  bool OffsetIsScalable;
1181 
1182  // To simplify the sub-register handling, verify that we only need to
1183  // consider physical registers.
1186 
1187  if (auto DestSrc = isCopyInstr(MI)) {
1188  Register DestReg = DestSrc->Destination->getReg();
1189 
1190  // If the copy destination is the forwarding reg, describe the forwarding
1191  // reg using the copy source as the backup location. Example:
1192  //
1193  // x0 = MOV x7
1194  // call callee(x0) ; x0 described as x7
1195  if (Reg == DestReg)
1196  return ParamLoadedValue(*DestSrc->Source, Expr);
1197 
1198  // Cases where super- or sub-registers needs to be described should
1199  // be handled by the target's hook implementation.
1200  assert(!TRI->isSuperOrSubRegisterEq(Reg, DestReg) &&
1201  "TargetInstrInfo::describeLoadedValue can't describe super- or "
1202  "sub-regs for copy instructions");
1203  return None;
1204  } else if (auto RegImm = isAddImmediate(MI, Reg)) {
1205  Register SrcReg = RegImm->Reg;
1206  Offset = RegImm->Imm;
1207  Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
1208  return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
1209  } else if (MI.hasOneMemOperand()) {
1210  // Only describe memory which provably does not escape the function. As
1211  // described in llvm.org/PR43343, escaped memory may be clobbered by the
1212  // callee (or by another thread).
1213  const auto &TII = MF->getSubtarget().getInstrInfo();
1214  const MachineFrameInfo &MFI = MF->getFrameInfo();
1215  const MachineMemOperand *MMO = MI.memoperands()[0];
1216  const PseudoSourceValue *PSV = MMO->getPseudoValue();
1217 
1218  // If the address points to "special" memory (e.g. a spill slot), it's
1219  // sufficient to check that it isn't aliased by any high-level IR value.
1220  if (!PSV || PSV->mayAlias(&MFI))
1221  return None;
1222 
1223  const MachineOperand *BaseOp;
1224  if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
1225  TRI))
1226  return None;
1227 
1228  // FIXME: Scalable offsets are not yet handled in the offset code below.
1229  if (OffsetIsScalable)
1230  return None;
1231 
1232  // TODO: Can currently only handle mem instructions with a single define.
1233  // An example from the x86 target:
1234  // ...
1235  // DIV64m $rsp, 1, $noreg, 24, $noreg, implicit-def dead $rax, implicit-def $rdx
1236  // ...
1237  //
1238  if (MI.getNumExplicitDefs() != 1)
1239  return None;
1240 
1241  // TODO: In what way do we need to take Reg into consideration here?
1242 
1244  DIExpression::appendOffset(Ops, Offset);
1245  Ops.push_back(dwarf::DW_OP_deref_size);
1246  Ops.push_back(MMO->getSize());
1247  Expr = DIExpression::prependOpcodes(Expr, Ops);
1248  return ParamLoadedValue(*BaseOp, Expr);
1249  }
1250 
1251  return None;
1252 }
1253 
1254 /// Both DefMI and UseMI must be valid. By default, call directly to the
1255 /// itinerary. This may be overriden by the target.
1257  const MachineInstr &DefMI,
1258  unsigned DefIdx,
1259  const MachineInstr &UseMI,
1260  unsigned UseIdx) const {
1261  unsigned DefClass = DefMI.getDesc().getSchedClass();
1262  unsigned UseClass = UseMI.getDesc().getSchedClass();
1263  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1264 }
1265 
1267  const MachineInstr &MI, unsigned DefIdx,
1268  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1269  assert((MI.isRegSequence() ||
1270  MI.isRegSequenceLike()) && "Instruction do not have the proper type");
1271 
1272  if (!MI.isRegSequence())
1273  return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
1274 
1275  // We are looking at:
1276  // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1277  assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
1278  for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
1279  OpIdx += 2) {
1280  const MachineOperand &MOReg = MI.getOperand(OpIdx);
1281  if (MOReg.isUndef())
1282  continue;
1283  const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
1284  assert(MOSubIdx.isImm() &&
1285  "One of the subindex of the reg_sequence is not an immediate");
1286  // Record Reg:SubReg, SubIdx.
1287  InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1288  (unsigned)MOSubIdx.getImm()));
1289  }
1290  return true;
1291 }
1292 
1294  const MachineInstr &MI, unsigned DefIdx,
1295  RegSubRegPairAndIdx &InputReg) const {
1296  assert((MI.isExtractSubreg() ||
1297  MI.isExtractSubregLike()) && "Instruction do not have the proper type");
1298 
1299  if (!MI.isExtractSubreg())
1300  return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
1301 
1302  // We are looking at:
1303  // Def = EXTRACT_SUBREG v0.sub1, sub0.
1304  assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
1305  const MachineOperand &MOReg = MI.getOperand(1);
1306  if (MOReg.isUndef())
1307  return false;
1308  const MachineOperand &MOSubIdx = MI.getOperand(2);
1309  assert(MOSubIdx.isImm() &&
1310  "The subindex of the extract_subreg is not an immediate");
1311 
1312  InputReg.Reg = MOReg.getReg();
1313  InputReg.SubReg = MOReg.getSubReg();
1314  InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
1315  return true;
1316 }
1317 
1319  const MachineInstr &MI, unsigned DefIdx,
1320  RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
1321  assert((MI.isInsertSubreg() ||
1322  MI.isInsertSubregLike()) && "Instruction do not have the proper type");
1323 
1324  if (!MI.isInsertSubreg())
1325  return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
1326 
1327  // We are looking at:
1328  // Def = INSERT_SEQUENCE v0, v1, sub0.
1329  assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
1330  const MachineOperand &MOBaseReg = MI.getOperand(1);
1331  const MachineOperand &MOInsertedReg = MI.getOperand(2);
1332  if (MOInsertedReg.isUndef())
1333  return false;
1334  const MachineOperand &MOSubIdx = MI.getOperand(3);
1335  assert(MOSubIdx.isImm() &&
1336  "One of the subindex of the reg_sequence is not an immediate");
1337  BaseReg.Reg = MOBaseReg.getReg();
1338  BaseReg.SubReg = MOBaseReg.getSubReg();
1339 
1340  InsertedReg.Reg = MOInsertedReg.getReg();
1341  InsertedReg.SubReg = MOInsertedReg.getSubReg();
1342  InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
1343  return true;
1344 }
1345 
1346 // Returns a MIRPrinter comment for this machine operand.
1348  const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
1349  const TargetRegisterInfo *TRI) const {
1350 
1351  if (!MI.isInlineAsm())
1352  return "";
1353 
1354  std::string Flags;
1355  raw_string_ostream OS(Flags);
1356 
1357  if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
1358  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1359  unsigned ExtraInfo = Op.getImm();
1360  bool First = true;
1361  for (StringRef Info : InlineAsm::getExtraInfoNames(ExtraInfo)) {
1362  if (!First)
1363  OS << " ";
1364  First = false;
1365  OS << Info;
1366  }
1367 
1368  return OS.str();
1369  }
1370 
1371  int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
1372  if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
1373  return "";
1374 
1375  assert(Op.isImm() && "Expected flag operand to be an immediate");
1376  // Pretty print the inline asm operand descriptor.
1377  unsigned Flag = Op.getImm();
1378  unsigned Kind = InlineAsm::getKind(Flag);
1380 
1381  unsigned RCID = 0;
1384  if (TRI) {
1385  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1386  } else
1387  OS << ":RC" << RCID;
1388  }
1389 
1390  if (InlineAsm::isMemKind(Flag)) {
1391  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1392  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1393  }
1394 
1395  unsigned TiedTo = 0;
1397  OS << " tiedto:$" << TiedTo;
1398 
1399  return OS.str();
1400 }
1401 
1403 
1405  Function &F, std::vector<outliner::Candidate> &Candidates) const {
1406  // Include target features from an arbitrary candidate for the outlined
1407  // function. This makes sure the outlined function knows what kinds of
1408  // instructions are going into it. This is fine, since all parent functions
1409  // must necessarily support the instructions that are in the outlined region.
1410  outliner::Candidate &FirstCand = Candidates.front();
1411  const Function &ParentFn = FirstCand.getMF()->getFunction();
1412  if (ParentFn.hasFnAttribute("target-features"))
1413  F.addFnAttr(ParentFn.getFnAttribute("target-features"));
1414 
1415  // Set nounwind, so we don't generate eh_frame.
1416  if (llvm::all_of(Candidates, [](const outliner::Candidate &C) {
1417  return C.getMF()->getFunction().hasFnAttribute(Attribute::NoUnwind);
1418  }))
1419  F.addFnAttr(Attribute::NoUnwind);
1420 }
1421 
1423  unsigned &Flags) const {
1424  // Some instrumentations create special TargetOpcode at the start which
1425  // expands to special code sequences which must be present.
1426  auto First = MBB.getFirstNonDebugInstr();
1427  if (First != MBB.end() &&
1428  (First->getOpcode() == TargetOpcode::FENTRY_CALL ||
1429  First->getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER))
1430  return false;
1431 
1432  return true;
1433 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1451
i
i
Definition: README.txt:29
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::TargetInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
Definition: TargetInstrInfo.cpp:717
llvm::MCSchedModel::HighLatency
unsigned HighLatency
Definition: MCSchedule.h:292
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:192
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1788
llvm::TargetInstrInfo::getMemOperandWithOffset
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.cpp:1070
ScoreboardHazardRecognizer.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:653
llvm::StackMapOpers
MI-level stackmap operands.
Definition: StackMaps.h:35
llvm::MachineOperand::setIsInternalRead
void setIsInternalRead(bool Val=true)
Definition: MachineOperand.h:527
llvm::MCAsmInfo::getSeparatorString
const char * getSeparatorString() const
Definition: MCAsmInfo.h:647
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
TargetFrameLowering.h
llvm::TargetInstrInfo::duplicate
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: TargetInstrInfo.cpp:433
llvm::TargetInstrInfo::CreateTargetHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1050
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
DebugInfoMetadata.h
llvm::MachineInstr::isNotDuplicable
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:928
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
getFunction
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:236
llvm::TargetInstrInfo::isThroughputPattern
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
Definition: TargetInstrInfo.cpp:799
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:709
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:406
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:632
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1012
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::TargetInstrInfo::getExtractSubregInputs
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1293
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:618
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::TargetInstrInfo::RegSubRegPairAndIdx
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition: TargetInstrInfo.h:509
llvm::TargetInstrInfo::getMachineCombinerPatterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: TargetInstrInfo.cpp:775
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:53
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetInstrInfo::insertNoops
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:72
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:319
llvm::MachineFunction::CreateMachineInstr
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
Definition: MachineFunction.cpp:373
llvm::MCSchedModel::LoadLatency
unsigned LoadLatency
Definition: MCSchedule.h:285
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:361
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:139
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:636
llvm::Optional
Definition: APInt.h:33
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1025
llvm::TargetInstrInfo::getNop
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Definition: TargetInstrInfo.cpp:473
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
llvm::TargetInstrInfo::getInsertSubregInputs
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1318
llvm::MachineFunction::cloneMachineInstrBundle
MachineInstr & cloneMachineInstrBundle(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig)
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: MachineFunction.cpp:388
llvm::TargetSchedModel::getInstrItineraries
const InstrItineraryData * getInstrItineraries() const
Definition: TargetSchedule.h:82
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
llvm::InstrItineraryData::getOperandCycle
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
Definition: MCInstrItineraries.h:167
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MCOperandInfo::isLookupPtrRegClass
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
Definition: MCInstrDesc.h:103
isAsmComment
static bool isAsmComment(const char *Str, const MCAsmInfo &MAI)
Definition: TargetInstrInfo.cpp:79
llvm::MDNode::get
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1384
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:355
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1638
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:491
llvm::InstrItineraryData::getOperandLatency
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
Definition: MCInstrItineraries.h:205
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::TargetInstrInfo::insertBranch
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition: TargetInstrInfo.h:709
DisableHazardRecognizer
static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))
llvm::MachineCombinerPattern::REASSOC_AX_YB
@ REASSOC_AX_YB
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:327
llvm::TargetInstrInfo::getFrameSize
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition: TargetInstrInfo.h:220
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:747
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
CommandLine.h
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:45
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1617
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
MCInstrItineraries.h
llvm::TargetInstrInfo::usePreRAHazardRecognizer
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition: TargetInstrInfo.cpp:1044
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:165
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::TargetInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
Definition: TargetInstrInfo.h:1066
llvm::AAResults
Definition: AliasAnalysis.h:511
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::DIExpression::ApplyOffset
@ ApplyOffset
Definition: DebugInfoMetadata.h:2763
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:344
llvm::TargetInstrInfo::getInsertSubregLikeInputs
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition: TargetInstrInfo.h:1279
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::outliner::Candidate::getMF
MachineFunction * getMF() const
Definition: MachineOutliner.h:140
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition: TargetInstrInfo.h:1204
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:480
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetInstrInfo::getRegSequenceLikeInputs
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition: TargetInstrInfo.h:1250
llvm::TargetInstrInfo::isReassociationCandidate
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
Definition: TargetInstrInfo.cpp:747
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:747
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:65
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1119
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:224
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::ScoreboardHazardRecognizer
Definition: ScoreboardHazardRecognizer.h:29
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:651
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:478
llvm::TargetInstrInfo::~TargetInstrInfo
virtual ~TargetInstrInfo()
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::TargetInstrInfo::mergeOutliningCandidateAttributes
virtual void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const
Optional target hook to create the LLVM IR attributes for the outlined function.
Definition: TargetInstrInfo.cpp:1404
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1135
llvm::InstrItineraryData::Itineraries
const InstrItinerary * Itineraries
Array of itineraries selected.
Definition: MCInstrItineraries.h:116
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:565
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::TargetInstrInfo::isMBBSafeToOutlineFrom
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
Definition: TargetInstrInfo.cpp:1422
llvm::None
const NoneType None
Definition: None.h:24
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:344
RegSubRegPairAndIdx
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
Definition: PeepholeOptimizer.cpp:101
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetInstrInfo::hasReassociableOperands
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition: TargetInstrInfo.cpp:698
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:296
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:770
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::TargetInstrInfo::createMIROperandComment
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
Definition: TargetInstrInfo.cpp:1347
llvm::InstrItinerary::NumMicroOps
int16_t NumMicroOps
Definition: MCInstrItineraries.h:99
llvm::MCAsmInfo::getMaxInstLength
virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const
Returns the maximum possible encoded instruction size in bytes.
Definition: MCAsmInfo.h:639
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:109
llvm::TargetInstrInfo::isAssociativeAndCommutative
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
Definition: TargetInstrInfo.h:1164
llvm::TargetInstrInfo::PredicateInstruction
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
Definition: TargetInstrInfo.cpp:329
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::cl::opt< bool >
llvm::TargetInstrInfo::getStackSlotRange
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
Definition: TargetInstrInfo.cpp:387
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
llvm::TargetFrameLowering::alignSPAdjust
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
Definition: TargetFrameLowering.h:105
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
TargetSchedule.h
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::TargetInstrInfo::RegSubRegPair::Reg
Register Reg
Definition: TargetInstrInfo.h:492
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:756
llvm::MachineFunction::CloneMachineInstr
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
Definition: MachineFunction.cpp:383
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1435
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::DataLayout::isLittleEndian
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:244
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:295
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::outliner::Candidate::front
MachineBasicBlock::iterator & front()
Definition: MachineOutliner.h:138
llvm::TargetInstrInfo::hasStoreToStackSlot
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
Definition: TargetInstrInfo.cpp:373
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1682
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::TargetInstrInfo::commuteInstruction
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:248
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:70
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:342
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1174
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo
virtual ~PipelinerLoopInfo()
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:716
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:348
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::TargetFrameLowering::getStackGrowthDirection
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
Definition: TargetFrameLowering.h:89
llvm::TargetInstrInfo::produceSameValue
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
Definition: TargetInstrInfo.cpp:427
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineCombinerPattern::REASSOC_AX_BY
@ REASSOC_AX_BY
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::TargetInstrInfo::getPatchpointUnfoldableRange
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
Definition: TargetInstrInfo.cpp:476
llvm::SDNode::isMachineOpcode
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
Definition: SelectionDAGNodes.h:687
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1151
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::TargetInstrInfo::getSPAdjust
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
Definition: TargetInstrInfo.cpp:997
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:357
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::TargetInstrInfo::getPredicationCost
virtual unsigned getPredicationCost(const MachineInstr &MI) const
Definition: TargetInstrInfo.cpp:1146
llvm::TargetInstrInfo::hasLoadFromStackSlot
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Definition: TargetInstrInfo.cpp:359
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::TargetInstrInfo::RegSubRegPair::SubReg
unsigned SubReg
Definition: TargetInstrInfo.h:493
MCAsmInfo.h
DataLayout.h
llvm::MachineBasicBlock::getFirstNonDebugInstr
iterator getFirstNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the first non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:257
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
Dwarf.h
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::TargetInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
Definition: TargetInstrInfo.h:1054
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:520
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:425
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:288
llvm::TargetInstrInfo::isUnpredicatedTerminator
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition: TargetInstrInfo.cpp:318
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:833
llvm::DenseMapBase::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:209
llvm::TargetInstrInfo::isFrameInstr
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition: TargetInstrInfo.h:202
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetInstrInfo::fixCommutedOpIndices
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Definition: TargetInstrInfo.cpp:263
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:509
llvm::TargetInstrInfo::isSchedulingBoundary
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
Definition: TargetInstrInfo.cpp:1021
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::MachineInstr::canFoldAsLoad
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:958
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
j
return j(j<< 16)
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1383
llvm::DIExpression::prependOpcodes
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
Definition: DebugInfoMetadata.cpp:1513
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::TargetInstrInfo::getCallFrameDestroyOpcode
unsigned getCallFrameDestroyOpcode() const
Definition: TargetInstrInfo.h:199
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::InstrItineraryData::getStageLatency
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
Definition: MCInstrItineraries.h:149
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:370
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:785
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.h:1352
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:487
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1312
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1025
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
foldPatchpoint
static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)
Definition: TargetInstrInfo.cpp:493
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::TargetInstrInfo::reassociateOps
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Definition: TargetInstrInfo.cpp:805
llvm::InlineAsm::getExtraInfoNames
static std::vector< StringRef > getExtraInfoNames(unsigned ExtraInfo)
Definition: InlineAsm.h:382
llvm::TargetInstrInfo::getRegSequenceInputs
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1266
llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1057
StackMaps.h
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1150
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:436
llvm::SDNode::getMachineOpcode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
Definition: SelectionDAGNodes.h:692
llvm::TargetInstrInfo::hasLowDefLatency
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
Definition: TargetInstrInfo.cpp:1161
llvm::TargetInstrInfo::getCallFrameSetupOpcode
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition: TargetInstrInfo.h:198
AA
canFoldCopy
static const TargetRegisterClass * canFoldCopy(const MachineInstr &MI, unsigned FoldIdx)
Definition: TargetInstrInfo.cpp:442
llvm::MachineFrameInfo::isImmutableObjectIndex
bool isImmutableObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to an immutable object.
Definition: MachineFrameInfo.h:693
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
MachineScheduler.h
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:97
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1222
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:558
MachineInstrBuilder.h
llvm::RISCVMatInt::RegImm
@ RegImm
Definition: RISCVMatInt.h:22
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:294
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::TargetInstrInfo::genAlternativeCodeSequence
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: TargetInstrInfo.cpp:891
llvm::MachineCombinerPattern::REASSOC_XA_BY
@ REASSOC_XA_BY
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1088
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:698
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::StringRef::data
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:149
llvm::MCRegisterInfo::getSubRegIdxOffset
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:62
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:691
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1064
llvm::TargetFrameLowering::StackGrowsDown
@ StackGrowsDown
Definition: TargetFrameLowering.h:47
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:127
llvm::MachineCombinerPattern::REASSOC_XA_YB
@ REASSOC_XA_YB
llvm::MCRegisterInfo::isSuperOrSubRegisterEq
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:580
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
raw_ostream.h
llvm::TargetInstrInfo::CommuteAnyOperandIndex
static const unsigned CommuteAnyOperandIndex
Definition: TargetInstrInfo.h:438
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1052
llvm::MachineFunction::eraseCallSiteInfo
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
Definition: MachineFunction.cpp:922
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::InstrItineraryData::isEmpty
bool isEmpty() const
Returns true if there are no itineraries.
Definition: MCInstrItineraries.h:126
llvm::TargetInstrInfo::isAddImmediate
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
Definition: TargetInstrInfo.h:1036
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:650
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
TargetRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::TargetInstrInfo::getExtractSubregLikeInputs
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition: TargetInstrInfo.h:1264
llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx
unsigned SubIdx
Definition: TargetInstrInfo.h:510
llvm::TargetInstrInfo::getInlineAsmLength
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
Definition: TargetInstrInfo.cpp:98
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition: TargetInstrInfo.h:262
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56