LLVM  14.0.0git
TargetInstrInfo.cpp
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1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCAsmInfo.h"
35 #include <cctype>
36 
37 using namespace llvm;
38 
40  "disable-sched-hazard", cl::Hidden, cl::init(false),
41  cl::desc("Disable hazard detection during preRA scheduling"));
42 
44 }
45 
47 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
48  const TargetRegisterInfo *TRI,
49  const MachineFunction &MF) const {
50  if (OpNum >= MCID.getNumOperands())
51  return nullptr;
52 
53  short RegClass = MCID.OpInfo[OpNum].RegClass;
54  if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
55  return TRI->getPointerRegClass(MF, RegClass);
56 
57  // Instructions like INSERT_SUBREG do not have fixed register classes.
58  if (RegClass < 0)
59  return nullptr;
60 
61  // Otherwise just look it up normally.
62  return TRI->getRegClass(RegClass);
63 }
64 
65 /// insertNoop - Insert a noop into the instruction stream at the specified
66 /// point.
69  llvm_unreachable("Target didn't implement insertNoop!");
70 }
71 
72 /// insertNoops - Insert noops into the instruction stream at the specified
73 /// point.
76  unsigned Quantity) const {
77  for (unsigned i = 0; i < Quantity; ++i)
78  insertNoop(MBB, MI);
79 }
80 
81 static bool isAsmComment(const char *Str, const MCAsmInfo &MAI) {
82  return strncmp(Str, MAI.getCommentString().data(),
83  MAI.getCommentString().size()) == 0;
84 }
85 
86 /// Measure the specified inline asm to determine an approximation of its
87 /// length.
88 /// Comments (which run till the next SeparatorString or newline) do not
89 /// count as an instruction.
90 /// Any other non-whitespace text is considered an instruction, with
91 /// multiple instructions separated by SeparatorString or newlines.
92 /// Variable-length instructions are not handled here; this function
93 /// may be overloaded in the target code to do that.
94 /// We implement a special case of the .space directive which takes only a
95 /// single integer argument in base 10 that is the size in bytes. This is a
96 /// restricted form of the GAS directive in that we only interpret
97 /// simple--i.e. not a logical or arithmetic expression--size values without
98 /// the optional fill value. This is primarily used for creating arbitrary
99 /// sized inline asm blocks for testing purposes.
101  const char *Str,
102  const MCAsmInfo &MAI, const TargetSubtargetInfo *STI) const {
103  // Count the number of instructions in the asm.
104  bool AtInsnStart = true;
105  unsigned Length = 0;
106  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
107  for (; *Str; ++Str) {
108  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
109  strlen(MAI.getSeparatorString())) == 0) {
110  AtInsnStart = true;
111  } else if (isAsmComment(Str, MAI)) {
112  // Stop counting as an instruction after a comment until the next
113  // separator.
114  AtInsnStart = false;
115  }
116 
117  if (AtInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
118  unsigned AddLength = MaxInstLength;
119  if (strncmp(Str, ".space", 6) == 0) {
120  char *EStr;
121  int SpaceSize;
122  SpaceSize = strtol(Str + 6, &EStr, 10);
123  SpaceSize = SpaceSize < 0 ? 0 : SpaceSize;
124  while (*EStr != '\n' && isSpace(static_cast<unsigned char>(*EStr)))
125  ++EStr;
126  if (*EStr == '\0' || *EStr == '\n' ||
127  isAsmComment(EStr, MAI)) // Successfully parsed .space argument
128  AddLength = SpaceSize;
129  }
130  Length += AddLength;
131  AtInsnStart = false;
132  }
133  }
134 
135  return Length;
136 }
137 
138 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
139 /// after it, replacing it with an unconditional branch to NewDest.
140 void
142  MachineBasicBlock *NewDest) const {
143  MachineBasicBlock *MBB = Tail->getParent();
144 
145  // Remove all the old successors of MBB from the CFG.
146  while (!MBB->succ_empty())
148 
149  // Save off the debug loc before erasing the instruction.
150  DebugLoc DL = Tail->getDebugLoc();
151 
152  // Update call site info and remove all the dead instructions
153  // from the end of MBB.
154  while (Tail != MBB->end()) {
155  auto MI = Tail++;
156  if (MI->shouldUpdateCallSiteInfo())
158  MBB->erase(MI);
159  }
160 
161  // If MBB isn't immediately before MBB, insert a branch to it.
163  insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL);
164  MBB->addSuccessor(NewDest);
165 }
166 
168  bool NewMI, unsigned Idx1,
169  unsigned Idx2) const {
170  const MCInstrDesc &MCID = MI.getDesc();
171  bool HasDef = MCID.getNumDefs();
172  if (HasDef && !MI.getOperand(0).isReg())
173  // No idea how to commute this instruction. Target should implement its own.
174  return nullptr;
175 
176  unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
177  unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
178  assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
179  CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
180  "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
181  assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
182  "This only knows how to commute register operands so far");
183 
184  Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
185  Register Reg1 = MI.getOperand(Idx1).getReg();
186  Register Reg2 = MI.getOperand(Idx2).getReg();
187  unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
188  unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
189  unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
190  bool Reg1IsKill = MI.getOperand(Idx1).isKill();
191  bool Reg2IsKill = MI.getOperand(Idx2).isKill();
192  bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
193  bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
194  bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
195  bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
196  // Avoid calling isRenamable for virtual registers since we assert that
197  // renamable property is only queried/set for physical registers.
198  bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1)
199  ? MI.getOperand(Idx1).isRenamable()
200  : false;
201  bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
202  ? MI.getOperand(Idx2).isRenamable()
203  : false;
204  // If destination is tied to either of the commuted source register, then
205  // it must be updated.
206  if (HasDef && Reg0 == Reg1 &&
207  MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
208  Reg2IsKill = false;
209  Reg0 = Reg2;
210  SubReg0 = SubReg2;
211  } else if (HasDef && Reg0 == Reg2 &&
212  MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
213  Reg1IsKill = false;
214  Reg0 = Reg1;
215  SubReg0 = SubReg1;
216  }
217 
218  MachineInstr *CommutedMI = nullptr;
219  if (NewMI) {
220  // Create a new instruction.
221  MachineFunction &MF = *MI.getMF();
222  CommutedMI = MF.CloneMachineInstr(&MI);
223  } else {
224  CommutedMI = &MI;
225  }
226 
227  if (HasDef) {
228  CommutedMI->getOperand(0).setReg(Reg0);
229  CommutedMI->getOperand(0).setSubReg(SubReg0);
230  }
231  CommutedMI->getOperand(Idx2).setReg(Reg1);
232  CommutedMI->getOperand(Idx1).setReg(Reg2);
233  CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
234  CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
235  CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
236  CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
237  CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
238  CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
239  CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
240  CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
241  // Avoid calling setIsRenamable for virtual registers since we assert that
242  // renamable property is only queried/set for physical registers.
244  CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
246  CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
247  return CommutedMI;
248 }
249 
251  unsigned OpIdx1,
252  unsigned OpIdx2) const {
253  // If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
254  // any commutable operand, which is done in findCommutedOpIndices() method
255  // called below.
256  if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
257  !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
258  assert(MI.isCommutable() &&
259  "Precondition violation: MI must be commutable.");
260  return nullptr;
261  }
262  return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
263 }
264 
265 bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,
266  unsigned &ResultIdx2,
267  unsigned CommutableOpIdx1,
268  unsigned CommutableOpIdx2) {
269  if (ResultIdx1 == CommuteAnyOperandIndex &&
270  ResultIdx2 == CommuteAnyOperandIndex) {
271  ResultIdx1 = CommutableOpIdx1;
272  ResultIdx2 = CommutableOpIdx2;
273  } else if (ResultIdx1 == CommuteAnyOperandIndex) {
274  if (ResultIdx2 == CommutableOpIdx1)
275  ResultIdx1 = CommutableOpIdx2;
276  else if (ResultIdx2 == CommutableOpIdx2)
277  ResultIdx1 = CommutableOpIdx1;
278  else
279  return false;
280  } else if (ResultIdx2 == CommuteAnyOperandIndex) {
281  if (ResultIdx1 == CommutableOpIdx1)
282  ResultIdx2 = CommutableOpIdx2;
283  else if (ResultIdx1 == CommutableOpIdx2)
284  ResultIdx2 = CommutableOpIdx1;
285  else
286  return false;
287  } else
288  // Check that the result operand indices match the given commutable
289  // operand indices.
290  return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
291  (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
292 
293  return true;
294 }
295 
297  unsigned &SrcOpIdx1,
298  unsigned &SrcOpIdx2) const {
299  assert(!MI.isBundle() &&
300  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
301 
302  const MCInstrDesc &MCID = MI.getDesc();
303  if (!MCID.isCommutable())
304  return false;
305 
306  // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
307  // is not true, then the target must implement this.
308  unsigned CommutableOpIdx1 = MCID.getNumDefs();
309  unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
310  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
311  CommutableOpIdx1, CommutableOpIdx2))
312  return false;
313 
314  if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
315  // No idea.
316  return false;
317  return true;
318 }
319 
321  if (!MI.isTerminator()) return false;
322 
323  // Conditional branch is a special case.
324  if (MI.isBranch() && !MI.isBarrier())
325  return true;
326  if (!MI.isPredicable())
327  return true;
328  return !isPredicated(MI);
329 }
330 
333  bool MadeChange = false;
334 
335  assert(!MI.isBundle() &&
336  "TargetInstrInfo::PredicateInstruction() can't handle bundles");
337 
338  const MCInstrDesc &MCID = MI.getDesc();
339  if (!MI.isPredicable())
340  return false;
341 
342  for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
343  if (MCID.OpInfo[i].isPredicate()) {
344  MachineOperand &MO = MI.getOperand(i);
345  if (MO.isReg()) {
346  MO.setReg(Pred[j].getReg());
347  MadeChange = true;
348  } else if (MO.isImm()) {
349  MO.setImm(Pred[j].getImm());
350  MadeChange = true;
351  } else if (MO.isMBB()) {
352  MO.setMBB(Pred[j].getMBB());
353  MadeChange = true;
354  }
355  ++j;
356  }
357  }
358  return MadeChange;
359 }
360 
362  const MachineInstr &MI,
364  size_t StartSize = Accesses.size();
365  for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
366  oe = MI.memoperands_end();
367  o != oe; ++o) {
368  if ((*o)->isLoad() &&
369  dyn_cast_or_null<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
370  Accesses.push_back(*o);
371  }
372  return Accesses.size() != StartSize;
373 }
374 
376  const MachineInstr &MI,
378  size_t StartSize = Accesses.size();
379  for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
380  oe = MI.memoperands_end();
381  o != oe; ++o) {
382  if ((*o)->isStore() &&
383  dyn_cast_or_null<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
384  Accesses.push_back(*o);
385  }
386  return Accesses.size() != StartSize;
387 }
388 
390  unsigned SubIdx, unsigned &Size,
391  unsigned &Offset,
392  const MachineFunction &MF) const {
394  if (!SubIdx) {
395  Size = TRI->getSpillSize(*RC);
396  Offset = 0;
397  return true;
398  }
399  unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
400  // Convert bit size to byte size.
401  if (BitSize % 8)
402  return false;
403 
404  int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
405  if (BitOffset < 0 || BitOffset % 8)
406  return false;
407 
408  Size = BitSize / 8;
409  Offset = (unsigned)BitOffset / 8;
410 
411  assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
412 
413  if (!MF.getDataLayout().isLittleEndian()) {
414  Offset = TRI->getSpillSize(*RC) - (Offset + Size);
415  }
416  return true;
417 }
418 
421  Register DestReg, unsigned SubIdx,
422  const MachineInstr &Orig,
423  const TargetRegisterInfo &TRI) const {
425  MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
426  MBB.insert(I, MI);
427 }
428 
430  const MachineInstr &MI1,
431  const MachineRegisterInfo *MRI) const {
433 }
434 
436  MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const {
437  assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
438  MachineFunction &MF = *MBB.getParent();
439  return MF.CloneMachineInstrBundle(MBB, InsertBefore, Orig);
440 }
441 
442 // If the COPY instruction in MI can be folded to a stack operation, return
443 // the register class to use.
445  unsigned FoldIdx) {
446  assert(MI.isCopy() && "MI must be a COPY instruction");
447  if (MI.getNumOperands() != 2)
448  return nullptr;
449  assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
450 
451  const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
452  const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
453 
454  if (FoldOp.getSubReg() || LiveOp.getSubReg())
455  return nullptr;
456 
457  Register FoldReg = FoldOp.getReg();
458  Register LiveReg = LiveOp.getReg();
459 
460  assert(Register::isVirtualRegister(FoldReg) && "Cannot fold physregs");
461 
462  const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
463  const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
464 
465  if (Register::isPhysicalRegister(LiveOp.getReg()))
466  return RC->contains(LiveOp.getReg()) ? RC : nullptr;
467 
468  if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
469  return RC;
470 
471  // FIXME: Allow folding when register classes are memory compatible.
472  return nullptr;
473 }
474 
475 MCInst TargetInstrInfo::getNop() const { llvm_unreachable("Not implemented"); }
476 
477 std::pair<unsigned, unsigned>
479  switch (MI.getOpcode()) {
480  case TargetOpcode::STACKMAP:
481  // StackMapLiveValues are foldable
482  return std::make_pair(0, StackMapOpers(&MI).getVarIdx());
483  case TargetOpcode::PATCHPOINT:
484  // For PatchPoint, the call args are not foldable (even if reported in the
485  // stackmap e.g. via anyregcc).
486  return std::make_pair(0, PatchPointOpers(&MI).getVarIdx());
487  case TargetOpcode::STATEPOINT:
488  // For statepoints, fold deopt and gc arguments, but not call arguments.
489  return std::make_pair(MI.getNumDefs(), StatepointOpers(&MI).getVarIdx());
490  default:
491  llvm_unreachable("unexpected stackmap opcode");
492  }
493 }
494 
497  const TargetInstrInfo &TII) {
498  unsigned StartIdx = 0;
499  unsigned NumDefs = 0;
500  // getPatchpointUnfoldableRange throws guarantee if MI is not a patchpoint.
501  std::tie(NumDefs, StartIdx) = TII.getPatchpointUnfoldableRange(MI);
502 
503  unsigned DefToFoldIdx = MI.getNumOperands();
504 
505  // Return false if any operands requested for folding are not foldable (not
506  // part of the stackmap's live values).
507  for (unsigned Op : Ops) {
508  if (Op < NumDefs) {
509  assert(DefToFoldIdx == MI.getNumOperands() && "Folding multiple defs");
510  DefToFoldIdx = Op;
511  } else if (Op < StartIdx) {
512  return nullptr;
513  }
514  if (MI.getOperand(Op).isTied())
515  return nullptr;
516  }
517 
518  MachineInstr *NewMI =
519  MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
520  MachineInstrBuilder MIB(MF, NewMI);
521 
522  // No need to fold return, the meta data, and function arguments
523  for (unsigned i = 0; i < StartIdx; ++i)
524  if (i != DefToFoldIdx)
525  MIB.add(MI.getOperand(i));
526 
527  for (unsigned i = StartIdx, e = MI.getNumOperands(); i < e; ++i) {
528  MachineOperand &MO = MI.getOperand(i);
529  unsigned TiedTo = e;
530  (void)MI.isRegTiedToDefOperand(i, &TiedTo);
531 
532  if (is_contained(Ops, i)) {
533  assert(TiedTo == e && "Cannot fold tied operands");
534  unsigned SpillSize;
535  unsigned SpillOffset;
536  // Compute the spill slot size and offset.
537  const TargetRegisterClass *RC =
538  MF.getRegInfo().getRegClass(MO.getReg());
539  bool Valid =
540  TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
541  if (!Valid)
542  report_fatal_error("cannot spill patchpoint subregister operand");
543  MIB.addImm(StackMaps::IndirectMemRefOp);
544  MIB.addImm(SpillSize);
546  MIB.addImm(SpillOffset);
547  } else {
548  MIB.add(MO);
549  if (TiedTo < e) {
550  assert(TiedTo < NumDefs && "Bad tied operand");
551  if (TiedTo > DefToFoldIdx)
552  --TiedTo;
553  NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1);
554  }
555  }
556  }
557  return NewMI;
558 }
559 
561  ArrayRef<unsigned> Ops, int FI,
562  LiveIntervals *LIS,
563  VirtRegMap *VRM) const {
564  auto Flags = MachineMemOperand::MONone;
565  for (unsigned OpIdx : Ops)
566  Flags |= MI.getOperand(OpIdx).isDef() ? MachineMemOperand::MOStore
568 
569  MachineBasicBlock *MBB = MI.getParent();
570  assert(MBB && "foldMemoryOperand needs an inserted instruction");
571  MachineFunction &MF = *MBB->getParent();
572 
573  // If we're not folding a load into a subreg, the size of the load is the
574  // size of the spill slot. But if we are, we need to figure out what the
575  // actual load size is.
576  int64_t MemSize = 0;
577  const MachineFrameInfo &MFI = MF.getFrameInfo();
579 
580  if (Flags & MachineMemOperand::MOStore) {
581  MemSize = MFI.getObjectSize(FI);
582  } else {
583  for (unsigned OpIdx : Ops) {
584  int64_t OpSize = MFI.getObjectSize(FI);
585 
586  if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
587  unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
588  if (SubRegSize > 0 && !(SubRegSize % 8))
589  OpSize = SubRegSize / 8;
590  }
591 
592  MemSize = std::max(MemSize, OpSize);
593  }
594  }
595 
596  assert(MemSize && "Did not expect a zero-sized stack slot");
597 
598  MachineInstr *NewMI = nullptr;
599 
600  if (MI.getOpcode() == TargetOpcode::STACKMAP ||
601  MI.getOpcode() == TargetOpcode::PATCHPOINT ||
602  MI.getOpcode() == TargetOpcode::STATEPOINT) {
603  // Fold stackmap/patchpoint.
604  NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
605  if (NewMI)
606  MBB->insert(MI, NewMI);
607  } else {
608  // Ask the target to do the actual folding.
609  NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS, VRM);
610  }
611 
612  if (NewMI) {
613  NewMI->setMemRefs(MF, MI.memoperands());
614  // Add a memory operand, foldMemoryOperandImpl doesn't do that.
615  assert((!(Flags & MachineMemOperand::MOStore) ||
616  NewMI->mayStore()) &&
617  "Folded a def to a non-store!");
618  assert((!(Flags & MachineMemOperand::MOLoad) ||
619  NewMI->mayLoad()) &&
620  "Folded a use to a non-load!");
621  assert(MFI.getObjectOffset(FI) != -1);
622  MachineMemOperand *MMO =
624  Flags, MemSize, MFI.getObjectAlign(FI));
625  NewMI->addMemOperand(MF, MMO);
626 
627  // The pass "x86 speculative load hardening" always attaches symbols to
628  // call instructions. We need copy it form old instruction.
629  NewMI->cloneInstrSymbols(MF, MI);
630 
631  return NewMI;
632  }
633 
634  // Straight COPY may fold as load/store.
635  if (!MI.isCopy() || Ops.size() != 1)
636  return nullptr;
637 
638  const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
639  if (!RC)
640  return nullptr;
641 
642  const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
644 
645  if (Flags == MachineMemOperand::MOStore)
646  storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
647  else
648  loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
649  return &*--Pos;
650 }
651 
653  ArrayRef<unsigned> Ops,
654  MachineInstr &LoadMI,
655  LiveIntervals *LIS) const {
656  assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
657 #ifndef NDEBUG
658  for (unsigned OpIdx : Ops)
659  assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
660 #endif
661 
662  MachineBasicBlock &MBB = *MI.getParent();
663  MachineFunction &MF = *MBB.getParent();
664 
665  // Ask the target to do the actual folding.
666  MachineInstr *NewMI = nullptr;
667  int FrameIndex = 0;
668 
669  if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
670  MI.getOpcode() == TargetOpcode::PATCHPOINT ||
671  MI.getOpcode() == TargetOpcode::STATEPOINT) &&
672  isLoadFromStackSlot(LoadMI, FrameIndex)) {
673  // Fold stackmap/patchpoint.
674  NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
675  if (NewMI)
676  NewMI = &*MBB.insert(MI, NewMI);
677  } else {
678  // Ask the target to do the actual folding.
679  NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS);
680  }
681 
682  if (!NewMI)
683  return nullptr;
684 
685  // Copy the memoperands from the load to the folded instruction.
686  if (MI.memoperands_empty()) {
687  NewMI->setMemRefs(MF, LoadMI.memoperands());
688  } else {
689  // Handle the rare case of folding multiple loads.
690  NewMI->setMemRefs(MF, MI.memoperands());
692  E = LoadMI.memoperands_end();
693  I != E; ++I) {
694  NewMI->addMemOperand(MF, *I);
695  }
696  }
697  return NewMI;
698 }
699 
701  const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
702  const MachineOperand &Op1 = Inst.getOperand(1);
703  const MachineOperand &Op2 = Inst.getOperand(2);
705 
706  // We need virtual register definitions for the operands that we will
707  // reassociate.
708  MachineInstr *MI1 = nullptr;
709  MachineInstr *MI2 = nullptr;
710  if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
711  MI1 = MRI.getUniqueVRegDef(Op1.getReg());
712  if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
713  MI2 = MRI.getUniqueVRegDef(Op2.getReg());
714 
715  // And they need to be in the trace (otherwise, they won't have a depth).
716  return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
717 }
718 
720  bool &Commuted) const {
721  const MachineBasicBlock *MBB = Inst.getParent();
725  unsigned AssocOpcode = Inst.getOpcode();
726 
727  // If only one operand has the same opcode and it's the second source operand,
728  // the operands must be commuted.
729  Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
730  if (Commuted)
731  std::swap(MI1, MI2);
732 
733  // 1. The previous instruction must be the same type as Inst.
734  // 2. The previous instruction must also be associative/commutative (this can
735  // be different even for instructions with the same opcode if traits like
736  // fast-math-flags are included).
737  // 3. The previous instruction must have virtual register definitions for its
738  // operands in the same basic block as Inst.
739  // 4. The previous instruction's result must only be used by Inst.
740  return MI1->getOpcode() == AssocOpcode && isAssociativeAndCommutative(*MI1) &&
741  hasReassociableOperands(*MI1, MBB) &&
743 }
744 
745 // 1. The operation must be associative and commutative.
746 // 2. The instruction must have virtual register definitions for its
747 // operands in the same basic block.
748 // 3. The instruction must have a reassociable sibling.
750  bool &Commuted) const {
751  return isAssociativeAndCommutative(Inst) &&
752  hasReassociableOperands(Inst, Inst.getParent()) &&
753  hasReassociableSibling(Inst, Commuted);
754 }
755 
756 // The concept of the reassociation pass is that these operations can benefit
757 // from this kind of transformation:
758 //
759 // A = ? op ?
760 // B = A op X (Prev)
761 // C = B op Y (Root)
762 // -->
763 // A = ? op ?
764 // B = X op Y
765 // C = A op B
766 //
767 // breaking the dependency between A and B, allowing them to be executed in
768 // parallel (or back-to-back in a pipeline) instead of depending on each other.
769 
770 // FIXME: This has the potential to be expensive (compile time) while not
771 // improving the code at all. Some ways to limit the overhead:
772 // 1. Track successful transforms; bail out if hit rate gets too low.
773 // 2. Only enable at -O3 or some other non-default optimization level.
774 // 3. Pre-screen pattern candidates here: if an operand of the previous
775 // instruction is known to not increase the critical path, then don't match
776 // that pattern.
779  bool DoRegPressureReduce) const {
780  bool Commute;
781  if (isReassociationCandidate(Root, Commute)) {
782  // We found a sequence of instructions that may be suitable for a
783  // reassociation of operands to increase ILP. Specify each commutation
784  // possibility for the Prev instruction in the sequence and let the
785  // machine combiner decide if changing the operands is worthwhile.
786  if (Commute) {
787  Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB);
788  Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB);
789  } else {
790  Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY);
791  Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY);
792  }
793  return true;
794  }
795 
796  return false;
797 }
798 
799 /// Return true when a code sequence can improve loop throughput.
800 bool
802  return false;
803 }
804 
805 /// Attempt the reassociation transformation to reduce critical path length.
806 /// See the above comments before getMachineCombinerPatterns().
808  MachineInstr &Root, MachineInstr &Prev,
812  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
813  MachineFunction *MF = Root.getMF();
815  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
817  const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
818 
819  // This array encodes the operand index for each parameter because the
820  // operands may be commuted. Each row corresponds to a pattern value,
821  // and each column specifies the index of A, B, X, Y.
822  unsigned OpIdx[4][4] = {
823  { 1, 1, 2, 2 },
824  { 1, 2, 2, 1 },
825  { 2, 1, 1, 2 },
826  { 2, 2, 1, 1 }
827  };
828 
829  int Row;
830  switch (Pattern) {
831  case MachineCombinerPattern::REASSOC_AX_BY: Row = 0; break;
832  case MachineCombinerPattern::REASSOC_AX_YB: Row = 1; break;
833  case MachineCombinerPattern::REASSOC_XA_BY: Row = 2; break;
834  case MachineCombinerPattern::REASSOC_XA_YB: Row = 3; break;
835  default: llvm_unreachable("unexpected MachineCombinerPattern");
836  }
837 
838  MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
839  MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
840  MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
841  MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
842  MachineOperand &OpC = Root.getOperand(0);
843 
844  Register RegA = OpA.getReg();
845  Register RegB = OpB.getReg();
846  Register RegX = OpX.getReg();
847  Register RegY = OpY.getReg();
848  Register RegC = OpC.getReg();
849 
850  if (Register::isVirtualRegister(RegA))
851  MRI.constrainRegClass(RegA, RC);
852  if (Register::isVirtualRegister(RegB))
853  MRI.constrainRegClass(RegB, RC);
854  if (Register::isVirtualRegister(RegX))
855  MRI.constrainRegClass(RegX, RC);
856  if (Register::isVirtualRegister(RegY))
857  MRI.constrainRegClass(RegY, RC);
858  if (Register::isVirtualRegister(RegC))
859  MRI.constrainRegClass(RegC, RC);
860 
861  // Create a new virtual register for the result of (X op Y) instead of
862  // recycling RegB because the MachineCombiner's computation of the critical
863  // path requires a new register definition rather than an existing one.
864  Register NewVR = MRI.createVirtualRegister(RC);
865  InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
866 
867  unsigned Opcode = Root.getOpcode();
868  bool KillA = OpA.isKill();
869  bool KillX = OpX.isKill();
870  bool KillY = OpY.isKill();
871 
872  // Create new instructions for insertion.
873  MachineInstrBuilder MIB1 =
874  BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
875  .addReg(RegX, getKillRegState(KillX))
876  .addReg(RegY, getKillRegState(KillY));
877  MachineInstrBuilder MIB2 =
878  BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
879  .addReg(RegA, getKillRegState(KillA))
880  .addReg(NewVR, getKillRegState(true));
881 
882  setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
883 
884  // Record new instructions for insertion and old instructions for deletion.
885  InsInstrs.push_back(MIB1);
886  InsInstrs.push_back(MIB2);
887  DelInstrs.push_back(&Prev);
888  DelInstrs.push_back(&Root);
889 }
890 
895  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
897 
898  // Select the previous instruction in the sequence based on the input pattern.
899  MachineInstr *Prev = nullptr;
900  switch (Pattern) {
903  Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
904  break;
907  Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
908  break;
909  default:
910  break;
911  }
912 
913  assert(Prev && "Unknown pattern for machine combiner");
914 
915  reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
916 }
917 
918 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
919  const MachineInstr &MI, AAResults *AA) const {
920  const MachineFunction &MF = *MI.getMF();
921  const MachineRegisterInfo &MRI = MF.getRegInfo();
922 
923  // Remat clients assume operand 0 is the defined register.
924  if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
925  return false;
926  Register DefReg = MI.getOperand(0).getReg();
927 
928  // A sub-register definition can only be rematerialized if the instruction
929  // doesn't read the other parts of the register. Otherwise it is really a
930  // read-modify-write operation on the full virtual register which cannot be
931  // moved safely.
932  if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
933  MI.readsVirtualRegister(DefReg))
934  return false;
935 
936  // A load from a fixed stack slot can be rematerialized. This may be
937  // redundant with subsequent checks, but it's target-independent,
938  // simple, and a common case.
939  int FrameIdx = 0;
940  if (isLoadFromStackSlot(MI, FrameIdx) &&
941  MF.getFrameInfo().isImmutableObjectIndex(FrameIdx))
942  return true;
943 
944  // Avoid instructions obviously unsafe for remat.
945  if (MI.isNotDuplicable() || MI.mayStore() || MI.mayRaiseFPException() ||
946  MI.hasUnmodeledSideEffects())
947  return false;
948 
949  // Don't remat inline asm. We have no idea how expensive it is
950  // even if it's side effect free.
951  if (MI.isInlineAsm())
952  return false;
953 
954  // Avoid instructions which load from potentially varying memory.
955  if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
956  return false;
957 
958  // If any of the registers accessed are non-constant, conservatively assume
959  // the instruction is not rematerializable.
960  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
961  const MachineOperand &MO = MI.getOperand(i);
962  if (!MO.isReg()) continue;
963  Register Reg = MO.getReg();
964  if (Reg == 0)
965  continue;
966 
967  // Check for a well-behaved physical register.
969  if (MO.isUse()) {
970  // If the physreg has no defs anywhere, it's just an ambient register
971  // and we can freely move its uses. Alternatively, if it's allocatable,
972  // it could get allocated to something with a def during allocation.
973  if (!MRI.isConstantPhysReg(Reg))
974  return false;
975  } else {
976  // A physreg def. We can't remat it.
977  return false;
978  }
979  continue;
980  }
981 
982  // Only allow one virtual-register def. There may be multiple defs of the
983  // same virtual register, though.
984  if (MO.isDef() && Reg != DefReg)
985  return false;
986 
987  // Don't allow any virtual-register uses. Rematting an instruction with
988  // virtual register uses would length the live ranges of the uses, which
989  // is not necessarily a good idea, certainly not "trivial".
990  if (MO.isUse())
991  return false;
992  }
993 
994  // Everything checked out.
995  return true;
996 }
997 
999  const MachineFunction *MF = MI.getMF();
1000  const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1001  bool StackGrowsDown =
1003 
1004  unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
1005  unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
1006 
1007  if (!isFrameInstr(MI))
1008  return 0;
1009 
1010  int SPAdj = TFI->alignSPAdjust(getFrameSize(MI));
1011 
1012  if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
1013  (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
1014  SPAdj = -SPAdj;
1015 
1016  return SPAdj;
1017 }
1018 
1019 /// isSchedulingBoundary - Test if the given instruction should be
1020 /// considered a scheduling boundary. This primarily includes labels
1021 /// and terminators.
1023  const MachineBasicBlock *MBB,
1024  const MachineFunction &MF) const {
1025  // Terminators and labels can't be scheduled around.
1026  if (MI.isTerminator() || MI.isPosition())
1027  return true;
1028 
1029  // INLINEASM_BR can jump to another block
1030  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1031  return true;
1032 
1033  // Don't attempt to schedule around any instruction that defines
1034  // a stack-oriented pointer, as it's unlikely to be profitable. This
1035  // saves compile time, because it doesn't require every single
1036  // stack slot reference to depend on the instruction that does the
1037  // modification.
1038  const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
1040  return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
1041 }
1042 
1043 // Provide a global flag for disabling the PreRA hazard recognizer that targets
1044 // may choose to honor.
1046  return !DisableHazardRecognizer;
1047 }
1048 
1049 // Default implementation of CreateTargetRAHazardRecognizer.
1052  const ScheduleDAG *DAG) const {
1053  // Dummy hazard recognizer allows all instructions to issue.
1054  return new ScheduleHazardRecognizer();
1055 }
1056 
1057 // Default implementation of CreateTargetMIHazardRecognizer.
1059  const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
1060  return new ScoreboardHazardRecognizer(II, DAG, "machine-scheduler");
1061 }
1062 
1063 // Default implementation of CreateTargetPostRAHazardRecognizer.
1066  const ScheduleDAG *DAG) const {
1067  return new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
1068 }
1069 
1070 // Default implementation of getMemOperandWithOffset.
1072  const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
1073  bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
1075  unsigned Width;
1076  if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
1077  Width, TRI) ||
1078  BaseOps.size() != 1)
1079  return false;
1080  BaseOp = BaseOps.front();
1081  return true;
1082 }
1083 
1084 //===----------------------------------------------------------------------===//
1085 // SelectionDAG latency interface.
1086 //===----------------------------------------------------------------------===//
1087 
1088 int
1090  SDNode *DefNode, unsigned DefIdx,
1091  SDNode *UseNode, unsigned UseIdx) const {
1092  if (!ItinData || ItinData->isEmpty())
1093  return -1;
1094 
1095  if (!DefNode->isMachineOpcode())
1096  return -1;
1097 
1098  unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1099  if (!UseNode->isMachineOpcode())
1100  return ItinData->getOperandCycle(DefClass, DefIdx);
1101  unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1102  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1103 }
1104 
1106  SDNode *N) const {
1107  if (!ItinData || ItinData->isEmpty())
1108  return 1;
1109 
1110  if (!N->isMachineOpcode())
1111  return 1;
1112 
1113  return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1114 }
1115 
1116 //===----------------------------------------------------------------------===//
1117 // MachineInstr latency interface.
1118 //===----------------------------------------------------------------------===//
1119 
1121  const MachineInstr &MI) const {
1122  if (!ItinData || ItinData->isEmpty())
1123  return 1;
1124 
1125  unsigned Class = MI.getDesc().getSchedClass();
1126  int UOps = ItinData->Itineraries[Class].NumMicroOps;
1127  if (UOps >= 0)
1128  return UOps;
1129 
1130  // The # of u-ops is dynamically determined. The specific target should
1131  // override this function to return the right number.
1132  return 1;
1133 }
1134 
1135 /// Return the default expected latency for a def based on it's opcode.
1137  const MachineInstr &DefMI) const {
1138  if (DefMI.isTransient())
1139  return 0;
1140  if (DefMI.mayLoad())
1141  return SchedModel.LoadLatency;
1142  if (isHighLatencyDef(DefMI.getOpcode()))
1143  return SchedModel.HighLatency;
1144  return 1;
1145 }
1146 
1148  return 0;
1149 }
1150 
1152  const MachineInstr &MI,
1153  unsigned *PredCost) const {
1154  // Default to one cycle for no itinerary. However, an "empty" itinerary may
1155  // still have a MinLatency property, which getStageLatency checks.
1156  if (!ItinData)
1157  return MI.mayLoad() ? 2 : 1;
1158 
1159  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1160 }
1161 
1163  const MachineInstr &DefMI,
1164  unsigned DefIdx) const {
1165  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1166  if (!ItinData || ItinData->isEmpty())
1167  return false;
1168 
1169  unsigned DefClass = DefMI.getDesc().getSchedClass();
1170  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1171  return (DefCycle != -1 && DefCycle <= 1);
1172 }
1173 
1176  Register Reg) const {
1177  const MachineFunction *MF = MI.getMF();
1180  int64_t Offset;
1181  bool OffsetIsScalable;
1182 
1183  // To simplify the sub-register handling, verify that we only need to
1184  // consider physical registers.
1187 
1188  if (auto DestSrc = isCopyInstr(MI)) {
1189  Register DestReg = DestSrc->Destination->getReg();
1190 
1191  // If the copy destination is the forwarding reg, describe the forwarding
1192  // reg using the copy source as the backup location. Example:
1193  //
1194  // x0 = MOV x7
1195  // call callee(x0) ; x0 described as x7
1196  if (Reg == DestReg)
1197  return ParamLoadedValue(*DestSrc->Source, Expr);
1198 
1199  // Cases where super- or sub-registers needs to be described should
1200  // be handled by the target's hook implementation.
1201  assert(!TRI->isSuperOrSubRegisterEq(Reg, DestReg) &&
1202  "TargetInstrInfo::describeLoadedValue can't describe super- or "
1203  "sub-regs for copy instructions");
1204  return None;
1205  } else if (auto RegImm = isAddImmediate(MI, Reg)) {
1206  Register SrcReg = RegImm->Reg;
1207  Offset = RegImm->Imm;
1209  return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
1210  } else if (MI.hasOneMemOperand()) {
1211  // Only describe memory which provably does not escape the function. As
1212  // described in llvm.org/PR43343, escaped memory may be clobbered by the
1213  // callee (or by another thread).
1214  const auto &TII = MF->getSubtarget().getInstrInfo();
1215  const MachineFrameInfo &MFI = MF->getFrameInfo();
1216  const MachineMemOperand *MMO = MI.memoperands()[0];
1217  const PseudoSourceValue *PSV = MMO->getPseudoValue();
1218 
1219  // If the address points to "special" memory (e.g. a spill slot), it's
1220  // sufficient to check that it isn't aliased by any high-level IR value.
1221  if (!PSV || PSV->mayAlias(&MFI))
1222  return None;
1223 
1224  const MachineOperand *BaseOp;
1225  if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
1226  TRI))
1227  return None;
1228 
1229  // FIXME: Scalable offsets are not yet handled in the offset code below.
1230  if (OffsetIsScalable)
1231  return None;
1232 
1233  // TODO: Can currently only handle mem instructions with a single define.
1234  // An example from the x86 target:
1235  // ...
1236  // DIV64m $rsp, 1, $noreg, 24, $noreg, implicit-def dead $rax, implicit-def $rdx
1237  // ...
1238  //
1239  if (MI.getNumExplicitDefs() != 1)
1240  return None;
1241 
1242  // TODO: In what way do we need to take Reg into consideration here?
1243 
1246  Ops.push_back(dwarf::DW_OP_deref_size);
1247  Ops.push_back(MMO->getSize());
1248  Expr = DIExpression::prependOpcodes(Expr, Ops);
1249  return ParamLoadedValue(*BaseOp, Expr);
1250  }
1251 
1252  return None;
1253 }
1254 
1255 /// Both DefMI and UseMI must be valid. By default, call directly to the
1256 /// itinerary. This may be overriden by the target.
1258  const MachineInstr &DefMI,
1259  unsigned DefIdx,
1260  const MachineInstr &UseMI,
1261  unsigned UseIdx) const {
1262  unsigned DefClass = DefMI.getDesc().getSchedClass();
1263  unsigned UseClass = UseMI.getDesc().getSchedClass();
1264  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1265 }
1266 
1268  const MachineInstr &MI, unsigned DefIdx,
1269  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1270  assert((MI.isRegSequence() ||
1271  MI.isRegSequenceLike()) && "Instruction do not have the proper type");
1272 
1273  if (!MI.isRegSequence())
1274  return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
1275 
1276  // We are looking at:
1277  // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1278  assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
1279  for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
1280  OpIdx += 2) {
1281  const MachineOperand &MOReg = MI.getOperand(OpIdx);
1282  if (MOReg.isUndef())
1283  continue;
1284  const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
1285  assert(MOSubIdx.isImm() &&
1286  "One of the subindex of the reg_sequence is not an immediate");
1287  // Record Reg:SubReg, SubIdx.
1288  InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1289  (unsigned)MOSubIdx.getImm()));
1290  }
1291  return true;
1292 }
1293 
1295  const MachineInstr &MI, unsigned DefIdx,
1296  RegSubRegPairAndIdx &InputReg) const {
1297  assert((MI.isExtractSubreg() ||
1298  MI.isExtractSubregLike()) && "Instruction do not have the proper type");
1299 
1300  if (!MI.isExtractSubreg())
1301  return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
1302 
1303  // We are looking at:
1304  // Def = EXTRACT_SUBREG v0.sub1, sub0.
1305  assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
1306  const MachineOperand &MOReg = MI.getOperand(1);
1307  if (MOReg.isUndef())
1308  return false;
1309  const MachineOperand &MOSubIdx = MI.getOperand(2);
1310  assert(MOSubIdx.isImm() &&
1311  "The subindex of the extract_subreg is not an immediate");
1312 
1313  InputReg.Reg = MOReg.getReg();
1314  InputReg.SubReg = MOReg.getSubReg();
1315  InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
1316  return true;
1317 }
1318 
1320  const MachineInstr &MI, unsigned DefIdx,
1321  RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
1322  assert((MI.isInsertSubreg() ||
1323  MI.isInsertSubregLike()) && "Instruction do not have the proper type");
1324 
1325  if (!MI.isInsertSubreg())
1326  return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
1327 
1328  // We are looking at:
1329  // Def = INSERT_SEQUENCE v0, v1, sub0.
1330  assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
1331  const MachineOperand &MOBaseReg = MI.getOperand(1);
1332  const MachineOperand &MOInsertedReg = MI.getOperand(2);
1333  if (MOInsertedReg.isUndef())
1334  return false;
1335  const MachineOperand &MOSubIdx = MI.getOperand(3);
1336  assert(MOSubIdx.isImm() &&
1337  "One of the subindex of the reg_sequence is not an immediate");
1338  BaseReg.Reg = MOBaseReg.getReg();
1339  BaseReg.SubReg = MOBaseReg.getSubReg();
1340 
1341  InsertedReg.Reg = MOInsertedReg.getReg();
1342  InsertedReg.SubReg = MOInsertedReg.getSubReg();
1343  InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
1344  return true;
1345 }
1346 
1347 // Returns a MIRPrinter comment for this machine operand.
1349  const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
1350  const TargetRegisterInfo *TRI) const {
1351 
1352  if (!MI.isInlineAsm())
1353  return "";
1354 
1355  std::string Flags;
1356  raw_string_ostream OS(Flags);
1357 
1358  if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
1359  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1360  unsigned ExtraInfo = Op.getImm();
1361  bool First = true;
1362  for (StringRef Info : InlineAsm::getExtraInfoNames(ExtraInfo)) {
1363  if (!First)
1364  OS << " ";
1365  First = false;
1366  OS << Info;
1367  }
1368 
1369  return OS.str();
1370  }
1371 
1372  int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
1373  if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
1374  return "";
1375 
1376  assert(Op.isImm() && "Expected flag operand to be an immediate");
1377  // Pretty print the inline asm operand descriptor.
1378  unsigned Flag = Op.getImm();
1379  unsigned Kind = InlineAsm::getKind(Flag);
1381 
1382  unsigned RCID = 0;
1385  if (TRI) {
1386  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1387  } else
1388  OS << ":RC" << RCID;
1389  }
1390 
1391  if (InlineAsm::isMemKind(Flag)) {
1392  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1393  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1394  }
1395 
1396  unsigned TiedTo = 0;
1398  OS << " tiedto:$" << TiedTo;
1399 
1400  return OS.str();
1401 }
1402 
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1296
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::TargetInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
Definition: TargetInstrInfo.cpp:719
llvm::MCSchedModel::HighLatency
unsigned HighLatency
Definition: MCSchedule.h:293
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:165
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1738
llvm::TargetInstrInfo::getMemOperandWithOffset
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.cpp:1071
ScoreboardHazardRecognizer.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:641
llvm::StackMapOpers
MI-level stackmap operands.
Definition: StackMaps.h:35
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineOperand::setIsInternalRead
void setIsInternalRead(bool Val=true)
Definition: MachineOperand.h:518
llvm::MCAsmInfo::getSeparatorString
const char * getSeparatorString() const
Definition: MCAsmInfo.h:635
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
TargetFrameLowering.h
llvm::TargetInstrInfo::duplicate
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: TargetInstrInfo.cpp:435
llvm::TargetInstrInfo::CreateTargetHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1051
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
DebugInfoMetadata.h
llvm::MachineInstr::isNotDuplicable
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:921
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::TargetInstrInfo::isThroughputPattern
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
Definition: TargetInstrInfo.cpp:801
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:708
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:390
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::TargetInstrInfo::getExtractSubregInputs
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1294
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:612
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::TargetInstrInfo::RegSubRegPairAndIdx
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition: TargetInstrInfo.h:494
llvm::TargetInstrInfo::getMachineCombinerPatterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: TargetInstrInfo.cpp:777
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:56
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetInstrInfo::insertNoops
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:74
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::MCSchedModel::LoadLatency
unsigned LoadLatency
Definition: MCSchedule.h:286
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:345
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:141
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:663
llvm::Optional
Definition: APInt.h:33
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1007
llvm::TargetInstrInfo::getNop
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Definition: TargetInstrInfo.cpp:475
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2586
llvm::TargetInstrInfo::getInsertSubregInputs
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1319
llvm::TargetSchedModel::getInstrItineraries
const InstrItineraryData * getInstrItineraries() const
Definition: TargetSchedule.h:83
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
llvm::InstrItineraryData::getOperandCycle
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
Definition: MCInstrItineraries.h:167
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MCOperandInfo::isLookupPtrRegClass
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
Definition: MCInstrDesc.h:102
isAsmComment
static bool isAsmComment(const char *Str, const MCAsmInfo &MAI)
Definition: TargetInstrInfo.cpp:81
llvm::MDNode::get
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1208
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:382
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1629
MachineRegisterInfo.h
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:476
llvm::InstrItineraryData::getOperandLatency
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
Definition: MCInstrItineraries.h:205
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::TargetInstrInfo::insertBranch
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition: TargetInstrInfo.h:695
DisableHazardRecognizer
static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))
llvm::MachineCombinerPattern::REASSOC_AX_YB
@ REASSOC_AX_YB
llvm::TargetInstrInfo::getFrameSize
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition: TargetInstrInfo.h:220
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:746
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
CommandLine.h
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:47
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:93
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
MCInstrItineraries.h
llvm::TargetInstrInfo::usePreRAHazardRecognizer
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition: TargetInstrInfo.cpp:1045
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:167
TargetMachine.h
llvm::TargetInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
Definition: TargetInstrInfo.h:1048
llvm::AAResults
Definition: AliasAnalysis.h:508
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::DIExpression::ApplyOffset
@ ApplyOffset
Definition: DebugInfoMetadata.h:2793
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:371
llvm::TargetInstrInfo::getInsertSubregLikeInputs
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition: TargetInstrInfo.h:1263
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition: TargetInstrInfo.h:1186
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:471
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetInstrInfo::getRegSequenceLikeInputs
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition: TargetInstrInfo.h:1234
llvm::TargetInstrInfo::isReassociationCandidate
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
Definition: TargetInstrInfo.cpp:749
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:717
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:67
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:329
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1120
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::ScoreboardHazardRecognizer
Definition: ScoreboardHazardRecognizer.h:29
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:472
llvm::TargetInstrInfo::~TargetInstrInfo
virtual ~TargetInstrInfo()
Definition: TargetInstrInfo.cpp:43
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1136
llvm::InstrItineraryData::Itineraries
const InstrItinerary * Itineraries
Array of itineraries selected.
Definition: MCInstrItineraries.h:116
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:592
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::None
const NoneType None
Definition: None.h:23
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:328
RegSubRegPairAndIdx
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
Definition: PeepholeOptimizer.cpp:102
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::TargetInstrInfo::hasReassociableOperands
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition: TargetInstrInfo.cpp:700
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:280
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:759
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::TargetInstrInfo::createMIROperandComment
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
Definition: TargetInstrInfo.cpp:1348
llvm::InstrItinerary::NumMicroOps
int16_t NumMicroOps
Definition: MCInstrItineraries.h:99
llvm::MCAsmInfo::getMaxInstLength
virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const
Returns the maximum possible encoded instruction size in bytes.
Definition: MCAsmInfo.h:627
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:108
llvm::TargetInstrInfo::isAssociativeAndCommutative
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
Definition: TargetInstrInfo.h:1146
llvm::TargetInstrInfo::PredicateInstruction
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
Definition: TargetInstrInfo.cpp:331
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::cl::opt< bool >
llvm::TargetInstrInfo::getStackSlotRange
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
Definition: TargetInstrInfo.cpp:389
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::TargetFrameLowering::alignSPAdjust
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
Definition: TargetFrameLowering.h:105
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
TargetSchedule.h
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::TargetInstrInfo::RegSubRegPair::Reg
Register Reg
Definition: TargetInstrInfo.h:477
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:31
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::MachineFunction::CloneMachineInstr
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
Definition: MachineFunction.cpp:358
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1426
llvm::DataLayout::isLittleEndian
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:242
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:279
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::TargetInstrInfo::hasStoreToStackSlot
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
Definition: TargetInstrInfo.cpp:375
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1616
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::TargetInstrInfo::commuteInstruction
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:250
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:68
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1175
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo
virtual ~PipelinerLoopInfo()
Definition: TargetInstrInfo.cpp:1403
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:715
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:332
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::TargetFrameLowering::getStackGrowthDirection
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
Definition: TargetFrameLowering.h:89
llvm::TargetInstrInfo::produceSameValue
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
Definition: TargetInstrInfo.cpp:429
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineCombinerPattern::REASSOC_AX_BY
@ REASSOC_AX_BY
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::TargetInstrInfo::getPatchpointUnfoldableRange
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
Definition: TargetInstrInfo.cpp:478
llvm::SDNode::isMachineOpcode
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
Definition: SelectionDAGNodes.h:681
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1144
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::TargetInstrInfo::getSPAdjust
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
Definition: TargetInstrInfo.cpp:998
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::TargetInstrInfo::getPredicationCost
virtual unsigned getPredicationCost(const MachineInstr &MI) const
Definition: TargetInstrInfo.cpp:1147
llvm::TargetInstrInfo::hasLoadFromStackSlot
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Definition: TargetInstrInfo.cpp:361
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::TargetInstrInfo::RegSubRegPair::SubReg
unsigned SubReg
Definition: TargetInstrInfo.h:478
MCAsmInfo.h
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:419
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::TargetInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
Definition: TargetInstrInfo.h:1036
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:511
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:136
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:409
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::TargetInstrInfo::isUnpredicatedTerminator
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition: TargetInstrInfo.cpp:320
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:880
llvm::DenseMapBase::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::TargetInstrInfo::isFrameInstr
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition: TargetInstrInfo.h:202
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::MachineFunction::CloneMachineInstrBundle
MachineInstr & CloneMachineInstrBundle(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig)
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: MachineFunction.cpp:363
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetInstrInfo::fixCommutedOpIndices
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Definition: TargetInstrInfo.cpp:265
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:513
llvm::TargetInstrInfo::isSchedulingBoundary
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
Definition: TargetInstrInfo.cpp:1022
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::MachineInstr::canFoldAsLoad
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:951
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
j
return j(j<< 16)
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1228
llvm::DIExpression::prependOpcodes
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
Definition: DebugInfoMetadata.cpp:1358
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::TargetInstrInfo::getCallFrameDestroyOpcode
unsigned getCallFrameDestroyOpcode() const
Definition: TargetInstrInfo.h:199
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
llvm::InstrItineraryData::getStageLatency
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
Definition: MCInstrItineraries.h:149
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:354
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:784
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.h:1343
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:514
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1312
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1018
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
foldPatchpoint
static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)
Definition: TargetInstrInfo.cpp:495
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:983
llvm::TargetInstrInfo::reassociateOps
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Definition: TargetInstrInfo.cpp:807
llvm::InlineAsm::getExtraInfoNames
static std::vector< StringRef > getExtraInfoNames(unsigned ExtraInfo)
Definition: InlineAsm.h:366
llvm::TargetInstrInfo::getRegSequenceInputs
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1267
llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1058
StackMaps.h
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:245
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1151
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::SDNode::getMachineOpcode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
Definition: SelectionDAGNodes.h:686
llvm::TargetInstrInfo::hasLowDefLatency
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
Definition: TargetInstrInfo.cpp:1162
llvm::TargetInstrInfo::getCallFrameSetupOpcode
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition: TargetInstrInfo.h:198
canFoldCopy
static const TargetRegisterClass * canFoldCopy(const MachineInstr &MI, unsigned FoldIdx)
Definition: TargetInstrInfo.cpp:444
llvm::MachineFrameInfo::isImmutableObjectIndex
bool isImmutableObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to an immutable object.
Definition: MachineFrameInfo.h:669
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
MachineScheduler.h
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:96
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1206
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:560
MachineInstrBuilder.h
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:219
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:296
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::TargetInstrInfo::genAlternativeCodeSequence
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: TargetInstrInfo.cpp:891
llvm::MachineCombinerPattern::REASSOC_XA_BY
@ REASSOC_XA_BY
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1089
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:689
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::StringRef::data
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:149
llvm::MCRegisterInfo::getSubRegIdxOffset
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:62
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:690
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1065
llvm::TargetFrameLowering::StackGrowsDown
@ StackGrowsDown
Definition: TargetFrameLowering.h:47
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:126
llvm::MachineCombinerPattern::REASSOC_XA_YB
@ REASSOC_XA_YB
llvm::MCRegisterInfo::isSuperOrSubRegisterEq
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:580
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::MachineFunction::CreateMachineInstr
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
Definition: MachineFunction.cpp:348
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:414
raw_ostream.h
llvm::TargetInstrInfo::CommuteAnyOperandIndex
static const unsigned CommuteAnyOperandIndex
Definition: TargetInstrInfo.h:423
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1099
llvm::MachineFunction::eraseCallSiteInfo
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
Definition: MachineFunction.cpp:918
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::InstrItineraryData::isEmpty
bool isEmpty() const
Returns true if there are no itineraries.
Definition: MCInstrItineraries.h:126
llvm::TargetInstrInfo::isAddImmediate
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
Definition: TargetInstrInfo.h:1018
llvm::raw_string_ostream::str
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:643
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
TargetRegisterInfo.h
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::TargetInstrInfo::getExtractSubregLikeInputs
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition: TargetInstrInfo.h:1248
llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx
unsigned SubIdx
Definition: TargetInstrInfo.h:495
llvm::TargetInstrInfo::getInlineAsmLength
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
Definition: TargetInstrInfo.cpp:100
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition: TargetInstrInfo.h:262
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56