This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen. More...

#include "llvm/CodeGen/TargetLowering.h"

Inheritance diagram for llvm::TargetLoweringBase:

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Collaboration diagram for llvm::TargetLoweringBase:

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Classes
struct	AddrMode
	This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null, there is no BaseGV. More...

class	ArgListEntry

struct	IntrinsicInfo

class	ValueTypeActionImpl

Public Types
enum	LegalizeAction : uint8_t { Legal , Promote , Expand , LibCall , Custom }
	This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...

enum	LegalizeTypeAction : uint8_t { TypeLegal , TypePromoteInteger , TypeExpandInteger , TypeSoftenFloat , TypeExpandFloat , TypeScalarizeVector , TypeSplitVector , TypeWidenVector , TypePromoteFloat , TypeSoftPromoteHalf , TypeScalarizeScalableVector }
	This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...

enum	BooleanContent { UndefinedBooleanContent , ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect , ScalarCondVectorVal , VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

enum class	AtomicExpansionKind { None , CastToInteger , LLSC , LLOnly , CmpXChg , MaskedIntrinsic , BitTestIntrinsic , CmpArithIntrinsic , Expand , NotAtomic }
	Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...

enum class	MulExpansionKind { Always , OnlyLegalOrCustom }
	Enum that specifies when a multiplication should be expanded. More...

enum class	NegatibleCost { Cheaper = 0 , Neutral = 1 , Expensive = 2 }
	Enum that specifies when a float negation is beneficial. More...

enum	ReciprocalEstimate : int { Unspecified = -1 , Disabled = 0 , Enabled = 1 }
	Reciprocal estimate status values used by the functions below. More...

enum class	ShiftLegalizationStrategy { ExpandToParts , ExpandThroughStack , LowerToLibcall }
	Return the preferred strategy to legalize tihs SHIFT instruction, with `ExpansionFactor` being the recursion depth - how many expansion needed. More...

using	LegalizeKind = std::pair< LegalizeTypeAction, EVT >
	LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

using	ArgListTy = std::vector< ArgListEntry >

Public Member Functions
virtual void	markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const

	TargetLoweringBase (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF.

	TargetLoweringBase (const TargetLoweringBase &)=delete

TargetLoweringBase &	operator= (const TargetLoweringBase &)=delete

virtual	~TargetLoweringBase ()=default

bool	isStrictFPEnabled () const
	Return true if the target support strict float operation.

const TargetMachine &	getTargetMachine () const

virtual bool	useSoftFloat () const

virtual MVT	getPointerTy (const DataLayout &DL, uint32_t AS=0) const
	Return the pointer type for the given address space, defaults to the pointer type from the data layout.

virtual MVT	getPointerMemTy (const DataLayout &DL, uint32_t AS=0) const
	Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.

MVT	getFrameIndexTy (const DataLayout &DL) const
	Return the type for frame index, which is determined by the alloca address space specified through the data layout.

MVT	getProgramPointerTy (const DataLayout &DL) const
	Return the type for code pointers, which is determined by the program address space specified through the data layout.

virtual MVT	getFenceOperandTy (const DataLayout &DL) const
	Return the type for operands of fence.

virtual MVT	getScalarShiftAmountTy (const DataLayout &, EVT) const
	Return the type to use for a scalar shift opcode, given the shifted amount type.

EVT	getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
	Returns the type for the shift amount of a shift opcode.

virtual LLVM_READONLY LLT	getPreferredShiftAmountTy (LLT ShiftValueTy) const
	Return the preferred type to use for a shift opcode, given the shifted amount type is `ShiftValueTy`.

virtual MVT	getVectorIdxTy (const DataLayout &DL) const
	Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.

virtual MVT	getVPExplicitVectorLengthTy () const
	Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.

virtual MachineMemOperand::Flags	getTargetMMOFlags (const Instruction &I) const
	This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.

MachineMemOperand::Flags	getLoadMemOperandFlags (const LoadInst &LI, const DataLayout &DL, AssumptionCache AC=nullptr, const TargetLibraryInfo LibInfo=nullptr) const

MachineMemOperand::Flags	getStoreMemOperandFlags (const StoreInst &SI, const DataLayout &DL) const

MachineMemOperand::Flags	getAtomicMemOperandFlags (const Instruction &AI, const DataLayout &DL) const

virtual bool	isSelectSupported (SelectSupportKind) const

virtual bool	shouldExpandGetActiveLaneMask (EVT VT, EVT OpVT) const
	Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.

virtual bool	reduceSelectOfFPConstantLoads (EVT CmpOpVT) const
	Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.

bool	hasMultipleConditionRegisters () const
	Return true if multiple condition registers are available.

bool	hasExtractBitsInsn () const
	Return true if the target has BitExtract instructions.

virtual TargetLoweringBase::LegalizeTypeAction	getPreferredVectorAction (MVT VT) const
	Return the preferred vector type legalization action.

virtual bool	softPromoteHalfType () const

virtual bool	shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const

virtual bool	isIntDivCheap (EVT VT, AttributeList Attr) const
	Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

virtual bool	hasStandaloneRem (EVT VT) const
	Return true if the target can handle a standalone remainder operation.

virtual bool	isFsqrtCheap (SDValue X, SelectionDAG &DAG) const
	Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

int	getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.

int	getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.

int	getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a square root of the given type based on the function's attributes.

int	getDivRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a division of the given type based on the function's attributes.

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed.

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const
	Returns map of slow types for division or remainder with corresponding fast types.

virtual bool	isVScaleKnownToBeAPowerOfTwo () const
	Return true only if vscale must be a power of two.

bool	isJumpExpensive () const
	Return true if Flow Control is an expensive operation that should be avoided.

bool	isPredictableSelectExpensive () const
	Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

virtual bool	fallBackToDAGISel (const Instruction &Inst) const

virtual bool	isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
	Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

virtual bool	isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
	Return true if the following transform is beneficial: (store (y (conv x)), y)) -> (store x, (x))

virtual bool	storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
	Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.

virtual bool	mergeStoresAfterLegalization (EVT MemVT) const
	Allow store merging for the specified type after legalization in addition to before legalization.

virtual bool	canMergeStoresTo (unsigned AS, EVT MemVT, const MachineFunction &MF) const
	Returns if it's reasonable to merge stores to MemVT size.

virtual bool	isCheapToSpeculateCttz (Type *Ty) const
	Return true if it is cheap to speculate a call to intrinsic cttz.

virtual bool	isCheapToSpeculateCtlz (Type *Ty) const
	Return true if it is cheap to speculate a call to intrinsic ctlz.

virtual bool	isCtlzFast () const
	Return true if ctlz instruction is fast.

virtual unsigned	getCustomCtpopCost (EVT VT, ISD::CondCode Cond) const
	Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.

virtual bool	isEqualityCmpFoldedWithSignedCmp () const
	Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.

virtual bool	preferZeroCompareBranch () const
	Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.

virtual bool	hasBitPreservingFPLogic (EVT VT) const
	Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.

virtual bool	isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
	Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.

virtual bool	isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
	Return if the target supports combining a chain like:

virtual bool	convertSetCCLogicToBitwiseLogic (EVT VT) const
	Use bitwise logic to make pairs of compares more efficient.

virtual MVT	hasFastEqualityCompare (unsigned NumBits) const
	Return the preferred operand type if the target has a quick way to compare integer values of the given size.

virtual bool	hasAndNotCompare (SDValue Y) const
	Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.

virtual bool	hasAndNot (SDValue X) const
	Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.

virtual bool	hasBitTest (SDValue X, SDValue Y) const
	Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.

virtual bool	shouldFoldMaskToVariableShiftPair (SDValue X) const
	There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred.

virtual bool	shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const
	Return true if it is profitable to fold a pair of shifts into a mask.

virtual bool	shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const
	Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.

virtual bool	shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode XC, ConstantSDNode CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const
	Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.

virtual bool	preferIncOfAddToSubOfNot (EVT VT) const
	These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.

virtual bool	preferScalarizeSplat (unsigned Opc) const

bool	enableExtLdPromotion () const
	Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

virtual bool	canCombineStoreAndExtract (Type VectorTy, Value Idx, unsigned &Cost) const
	Return true if the target can combine store(extractelement VectorTy, Idx).

virtual bool	shouldSplatInsEltVarIndex (EVT) const
	Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.

virtual bool	enableAggressiveFMAFusion (EVT VT) const
	Return true if target always benefits from combining into FMA for a given value type.

virtual bool	enableAggressiveFMAFusion (LLT Ty) const
	Return true if target always benefits from combining into FMA for a given value type.

virtual EVT	getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
	Return the ValueType of the result of SETCC operations.

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const
	Return the ValueType for comparison libcalls.

BooleanContent	getBooleanContents (bool isVec, bool isFloat) const
	For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

BooleanContent	getBooleanContents (EVT Type) const

SDValue	promoteTargetBoolean (SelectionDAG &DAG, SDValue Bool, EVT ValVT) const
	Promote the given target boolean to a target boolean of the given type.

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference.

virtual Sched::Preference	getSchedulingPreference (SDNode *) const
	Some scheduler, e.g.

virtual const TargetRegisterClass *	getRegClassFor (MVT VT, bool isDivergent=false) const
	Return the register class that should be used for the specified value type.

virtual bool	requiresUniformRegister (MachineFunction &MF, const Value *) const
	Allows target to decide about the register class of the specific value that is live outside the defining block.

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const
	Return the 'representative' register class for the specified value type.

virtual uint8_t	getRepRegClassCostFor (MVT VT) const
	Return the cost of the 'representative' register class for the specified value type.

virtual ShiftLegalizationStrategy	preferredShiftLegalizationStrategy (SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const

bool	isTypeLegal (EVT VT) const
	Return true if the target has native support for the specified value type.

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeKind	getTypeConversion (LLVMContext &Context, EVT VT) const
	Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it.

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const
	Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').

LegalizeTypeAction	getTypeAction (MVT VT) const

virtual EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function.

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function.

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Vector types are broken down into some number of legal first class types.

virtual unsigned	getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
	Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).

virtual bool	isFPImmLegal (const APFloat &, EVT, bool ForCodeSize=false) const
	Returns true if the target can instruction select the specified FP immediate natively.

virtual bool	isShuffleMaskLegal (ArrayRef< int >, EVT) const
	Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

virtual bool	canOpTrap (unsigned Op, EVT VT) const
	Returns true if the operation can trap for the value type.

virtual bool	isVectorClearMaskLegal (ArrayRef< int >, EVT) const
	Similar to isShuffleMaskLegal.

virtual LegalizeAction	getCustomOperationAction (SDNode &Op) const
	How to legalize this custom operation?

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const
	Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

virtual bool	isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const
	Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.

LegalizeAction	getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const
	Some fixed point operations may be natively supported by the target but only for specific scales.

LegalizeAction	getStrictFPOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT, bool LegalOnly=false) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering.

bool	isOperationLegalOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const
	Return true if the specified operation is legal on this target or can be made legal using promotion.

bool	isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.

bool	isOperationCustom (unsigned Op, EVT VT) const
	Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

virtual bool	areJTsAllowed (const Function *Fn) const
	Return true if lowering to a jump table is allowed.

bool	rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
	Check whether the range [Low,High] fits in a machine word.

virtual bool	isSuitableForJumpTable (const SwitchInst SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo PSI, BlockFrequencyInfo *BFI) const
	Return true if lowering to a jump table is suitable for a set of case clusters which may contain `NumCases` cases, `Range` range of values.

virtual MVT	getPreferredSwitchConditionType (LLVMContext &Context, EVT ConditionVT) const
	Returns preferred type for switch condition.

bool	isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
	Return true if lowering to a bit test is suitable for a set of case clusters which contains `NumDests` unique destinations, `Low` and `High` as its lowest and highest case values, and expects `NumCmps` case value comparisons.

bool	isOperationExpand (unsigned Op, EVT VT) const
	Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target.

LegalizeAction	getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal on this target.

bool	isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal or custom on this target.

LegalizeAction	getTruncStoreAction (EVT ValVT, EVT MemVT) const
	Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation is legal on this target.

bool	isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation has solution on this target.

virtual bool	canCombineTruncStore (EVT ValVT, EVT MemVT, bool LegalOnly) const

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const
	Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const
	Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

LegalizeAction	getIndexedMaskedLoadAction (unsigned IdxMode, MVT VT) const
	Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedMaskedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

LegalizeAction	getIndexedMaskedStoreAction (unsigned IdxMode, MVT VT) const
	Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedMaskedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

virtual bool	shouldExtendGSIndex (EVT VT, EVT &EltTy) const
	Returns true if the index type for a masked gather/scatter requires extending.

virtual bool	shouldRemoveExtendFromGSIndex (EVT IndexVT, EVT DataVT) const

virtual bool	isLegalScaleForGatherScatter (uint64_t Scale, uint64_t ElemSize) const

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const
	Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target.

bool	isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal or custom on this target.

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const
	If the action for this operation is to promote, this method returns the ValueType to promote to.

virtual EVT	getAsmOperandValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

EVT	getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the EVT corresponding to this LLVM type.

EVT	getMemValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

MVT	getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType.

virtual uint64_t	getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
	Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require.

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require.

virtual unsigned	getNumRegisters (LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
	Return the number of registers that this ValueType will eventually require.

virtual MVT	getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.

virtual unsigned	getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain targets require unusual breakdowns of certain types.

virtual Align	getABIAlignmentForCallingConv (Type *ArgTy, const DataLayout &DL) const
	Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.

virtual bool	ShouldShrinkFPConstant (EVT) const
	If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

virtual bool	shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
	Return true if it is profitable to reduce a load to a smaller type.

bool	hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
	When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

bool	hasTargetDAGCombine (ISD::NodeType NT) const
	If true, the target has custom DAG combine transformations that it can perform for the specified node.

unsigned	getGatherAllAliasesMaxDepth () const

virtual unsigned	getVaListSizeInBits (const DataLayout &DL) const
	Returns the size of the platform's va_list object.

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset.

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy.

virtual unsigned	getMaxGluedStoresPerMemcpy () const
	Get maximum # of store operations to be glued together.

unsigned	getMaxExpandSizeMemcmp (bool OptSize) const
	Get maximum # of load operations permitted for memcmp.

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove.

virtual bool	allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
	Determine if the target supports unaligned memory accesses.

virtual bool	allowsMisalignedMemoryAccesses (LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
	LLT handling variant.

bool	allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
	This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.

bool	allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
	Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.

virtual bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
	Return true if the target supports a memory access of this type for the given address space and alignment.

bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
	Return true if the target supports a memory access of this type for the given MachineMemOperand.

bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
	LLT handling variant.

virtual EVT	getOptimalMemOpType (const MemOp &Op, const AttributeList &) const
	Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

virtual LLT	getOptimalMemOpLLT (const MemOp &Op, const AttributeList &) const
	LLT returning variant.

virtual bool	isSafeMemOpType (MVT) const
	Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

virtual unsigned	getMinimumJumpTableEntries () const
	Return lower limit for number of blocks in a jump table.

unsigned	getMinimumJumpTableDensity (bool OptForSize) const
	Return lower limit of the density in a jump table.

unsigned	getMaximumJumpTableSize () const
	Return upper limit for number of entries in a jump table.

virtual bool	isJumpTableRelative () const

Register	getStackPointerRegisterToSaveRestore () const
	If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

virtual Register	getExceptionPointerRegister (const Constant *PersonalityFn) const
	If a physical register, this returns the register that receives the exception address on entry to an EH pad.

virtual Register	getExceptionSelectorRegister (const Constant *PersonalityFn) const
	If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

virtual bool	needsFixedCatchObjects () const

Align	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument.

Align	getMinFunctionAlignment () const
	Return the minimum function alignment.

Align	getPrefFunctionAlignment () const
	Return the preferred function alignment.

virtual Align	getPrefLoopAlignment (MachineLoop *ML=nullptr) const
	Return the preferred loop alignment.

virtual unsigned	getMaxPermittedBytesForAlignment (MachineBasicBlock *MBB) const
	Return the maximum amount of bytes allowed to be emitted when padding for alignment.

virtual bool	alignLoopsWithOptSize () const
	Should loops be aligned even when the function is marked OptSize (but not MinSize).

virtual Value *	getIRStackGuard (IRBuilderBase &IRB) const
	If the target has a standard location for the stack protector guard, returns the address of that location.

virtual void	insertSSPDeclarations (Module &M) const
	Inserts necessary declarations for SSP (stack protection) purpose.

virtual Value *	getSDagStackGuard (const Module &M) const
	Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.

virtual bool	useStackGuardXorFP () const
	If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.

virtual Function *	getSSPStackGuardCheck (const Module &M) const
	If the target has a standard stack protection check function that performs validation and error handling, returns the function.

virtual bool	isConstantUnsignedBitfieldExtractLegal (unsigned Opc, LLT Ty1, LLT Ty2) const

virtual Value *	getSafeStackPointerLocation (IRBuilderBase &IRB) const
	Returns the target-specific address of the unsafe stack pointer.

virtual bool	hasStackProbeSymbol (const MachineFunction &MF) const
	Returns the name of the symbol used to emit stack probes or the empty string if not applicable.

virtual bool	hasInlineStackProbe (const MachineFunction &MF) const

virtual StringRef	getStackProbeSymbolName (const MachineFunction &MF) const

virtual bool	isFreeAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

virtual bool	shouldAlignPointerArgs (CallInst *, unsigned &, Align &) const
	Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

virtual void	emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder) const

virtual bool	shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
	Returns true if arguments should be sign-extended in lib calls.

virtual bool	shouldExtendTypeInLibCall (EVT Type) const
	Returns true if arguments should be extended in lib calls.

virtual AtomicExpansionKind	shouldExpandAtomicLoadInIR (LoadInst *LI) const
	Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

virtual AtomicExpansionKind	shouldCastAtomicLoadInIR (LoadInst *LI) const
	Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.

virtual AtomicExpansionKind	shouldExpandAtomicStoreInIR (StoreInst *SI) const
	Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.

virtual AtomicExpansionKind	shouldCastAtomicStoreInIR (StoreInst *SI) const
	Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.

virtual AtomicExpansionKind	shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const
	Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

virtual AtomicExpansionKind	shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW) const
	Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

virtual AtomicExpansionKind	shouldCastAtomicRMWIInIR (AtomicRMWInst *RMWI) const
	Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.

virtual LoadInst *	lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
	On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.

virtual ISD::NodeType	getExtendForAtomicOps () const
	Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

virtual ISD::NodeType	getExtendForAtomicCmpSwapArg () const
	Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

virtual bool	shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
	Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0\|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.

virtual bool	isProfitableToCombineMinNumMaxNum (EVT VT) const

virtual bool	convertSelectOfConstantsToMath (EVT VT) const
	Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.

virtual bool	decomposeMulByConstant (LLVMContext &Context, EVT VT, SDValue C) const
	Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.

virtual bool	isMulAddWithConstProfitable (SDValue AddNode, SDValue ConstNode) const
	Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).

virtual bool	shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const
	Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.

bool	isBeneficialToExpandPowI (int Exponent, bool OptForSize) const
	Return true if it is beneficial to expand an @llvm.powi.

virtual bool	getAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const
	CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.

virtual bool	isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type Ty, unsigned AddrSpace, Instruction I=nullptr) const
	Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

virtual bool	isLegalICmpImmediate (int64_t) const
	Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

virtual bool	isLegalAddImmediate (int64_t) const
	Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

virtual bool	isLegalStoreImmediate (int64_t Value) const
	Return true if the specified immediate is legal for the value input of a store instruction.

virtual bool	isVectorShiftByScalarCheap (Type *Ty) const
	Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.

virtual Type *	shouldConvertSplatType (ShuffleVectorInst *SVI) const
	Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable.

virtual bool	shouldConvertPhiType (Type From, Type To) const
	Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.

virtual bool	isCommutativeBinOp (unsigned Opcode) const
	Returns true if the opcode is a commutative binary operation.

virtual bool	isBinOp (unsigned Opcode) const
	Return true if the node is a math/logic binary operator.

virtual bool	isTruncateFree (Type FromTy, Type ToTy) const
	Return true if it's free to truncate a value of type FromTy to type ToTy.

virtual bool	allowTruncateForTailCall (Type FromTy, Type ToTy) const
	Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.

virtual bool	isTruncateFree (EVT FromVT, EVT ToVT) const

virtual bool	isTruncateFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const

virtual bool	isProfitableToHoist (Instruction *I) const

bool	isExtFree (const Instruction *I) const
	Return true if the extension represented by `I` is free.

bool	isExtLoad (const LoadInst Load, const Instruction Ext, const DataLayout &DL) const
	Return true if `Load` and `Ext` can form an ExtLoad.

virtual bool	isZExtFree (Type FromTy, Type ToTy) const
	Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.

virtual bool	isZExtFree (EVT FromTy, EVT ToTy) const

virtual bool	isZExtFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const

virtual bool	isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const
	Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.

virtual bool	signExtendConstant (const ConstantInt *C) const
	Return true if this constant should be sign extended when promoting to a larger type.

virtual bool	shouldSinkOperands (Instruction I, SmallVectorImpl< Use > &Ops) const
	Return true if sinking I's operands to the same basic block as I is profitable, e.g.

virtual bool	optimizeExtendOrTruncateConversion (Instruction I, Loop L) const
	Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.

virtual bool	hasPairedLoad (EVT, Align &) const
	Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.

virtual bool	hasVectorBlend () const
	Return true if the target has a vector blend instruction.

virtual unsigned	getMaxSupportedInterleaveFactor () const
	Get the maximum supported factor for interleaved memory accesses.

virtual bool	lowerInterleavedLoad (LoadInst LI, ArrayRef< ShuffleVectorInst > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
	Lower an interleaved load to target specific intrinsics.

virtual bool	lowerInterleavedStore (StoreInst SI, ShuffleVectorInst SVI, unsigned Factor) const
	Lower an interleaved store to target specific intrinsics.

virtual bool	isZExtFree (SDValue Val, EVT VT2) const
	Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

virtual bool	isFPExtFree (EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

virtual bool	isFPExtFoldable (const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const
	Return true if an fpext operation input to an `Opcode` operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

virtual bool	isFPExtFoldable (const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation input to an `Opcode` operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

virtual bool	isVectorLoadExtDesirable (SDValue ExtVal) const
	Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

virtual bool	isFNegFree (EVT VT) const
	Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

virtual bool	isFAbsFree (EVT VT) const
	Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

virtual bool	isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, EVT) const
	Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

virtual bool	isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, LLT) const
	Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

virtual bool	isFMAFasterThanFMulAndFAdd (const Function &F, Type *) const
	IR version.

virtual bool	isFMADLegal (const MachineInstr &MI, LLT Ty) const
	Returns true if `MI` can be combined with another instruction to form TargetOpcode::G_FMAD.

virtual bool	isFMADLegal (const SelectionDAG &DAG, const SDNode *N) const
	Returns true if be combined with to form an ISD::FMAD.

virtual bool	generateFMAsInMachineCombiner (EVT VT, CodeGenOpt::Level OptLevel) const

virtual bool	isNarrowingProfitable (EVT, EVT) const
	Return true if it's profitable to narrow operations of type VT1 to VT2.

virtual bool	shouldFoldSelectWithIdentityConstant (unsigned BinOpcode, EVT VT) const
	Return true if pulling a binary operation into a select with an identity constant is profitable.

virtual bool	shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
	Return true if it is beneficial to convert a load of a constant to just the constant itself.

virtual bool	isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const
	Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.

virtual bool	shouldScalarizeBinop (SDValue VecOp) const
	Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.

virtual bool	isExtractVecEltCheap (EVT VT, unsigned Index) const
	Return true if extraction of a scalar element from the given vector type at the given index is cheap.

virtual bool	shouldFormOverflowOp (unsigned Opcode, EVT VT, bool MathUsed) const
	Try to convert math with an overflow comparison into the corresponding DAG node operation.

virtual bool	aggressivelyPreferBuildVectorSources (EVT VecVT) const

virtual bool	shouldConsiderGEPOffsetSplit () const

virtual bool	shouldAvoidTransformToShift (EVT VT, unsigned Amount) const
	Return true if creating a shift of the type by the given amount is not profitable.

virtual bool	shouldKeepZExtForFP16Conv () const
	Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.

virtual bool	shouldConvertFpToSat (unsigned Op, EVT FPVT, EVT VT) const
	Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.

virtual bool	isComplexDeinterleavingSupported () const
	Does this target support complex deinterleaving.

virtual bool	isComplexDeinterleavingOperationSupported (ComplexDeinterleavingOperation Operation, Type *Ty) const
	Does this target support complex deinterleaving with the given operation and type.

virtual Value *	createComplexDeinterleavingIR (Instruction I, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value InputA, Value InputB, Value Accumulator=nullptr) const
	Create the IR node for the given complex deinterleaving operation.

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall.

void	setLibcallName (ArrayRef< RTLIB::Libcall > Calls, const char *Name)

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall.

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
	Override the default CondCode to be used to test the result of the comparison libcall against zero.

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const
	Get the CondCode that's to be used to test the result of the comparison libcall against zero.

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall.

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall.

virtual void	finalizeLowering (MachineFunction &MF) const
	Execute target specific actions to finalize target lowering.

virtual bool	shouldLocalize (const MachineInstr &MI, const TargetTransformInfo *TTI) const
	Check whether or not `MI` needs to be moved close to its uses.

Helpers for TargetTransformInfo implementations
int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode.

Helpers for atomic expansion.
unsigned	getMaxAtomicSizeInBitsSupported () const
	Returns the maximum atomic operation size (in bits) supported by the backend.

unsigned	getMaxDivRemBitWidthSupported () const
	Returns the size in bits of the maximum div/rem the backend supports.

unsigned	getMaxLargeFPConvertBitWidthSupported () const
	Returns the size in bits of the maximum larget fp convert the backend supports.

unsigned	getMinCmpXchgSizeInBits () const
	Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.

bool	supportsUnalignedAtomics () const
	Whether the target supports unaligned atomic operations.

virtual bool	shouldInsertFencesForAtomic (const Instruction *I) const
	Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

virtual bool	shouldInsertTrailingFenceForAtomicStore (const Instruction *I) const
	Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic.

virtual Value *	emitLoadLinked (IRBuilderBase &Builder, Type ValueTy, Value Addr, AtomicOrdering Ord) const
	Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

virtual Value *	emitStoreConditional (IRBuilderBase &Builder, Value Val, Value Addr, AtomicOrdering Ord) const
	Perform a store-conditional operation to Addr.

virtual Value *	emitMaskedAtomicRMWIntrinsic (IRBuilderBase &Builder, AtomicRMWInst AI, Value AlignedAddr, Value Incr, Value Mask, Value *ShiftAmt, AtomicOrdering Ord) const
	Perform a masked atomicrmw using a target-specific intrinsic.

virtual void	emitExpandAtomicRMW (AtomicRMWInst *AI) const
	Perform a atomicrmw expansion using a target-specific way.

virtual void	emitBitTestAtomicRMWIntrinsic (AtomicRMWInst *AI) const
	Perform a bit test atomicrmw using a target-specific intrinsic.

virtual void	emitCmpArithAtomicRMWIntrinsic (AtomicRMWInst *AI) const
	Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.

virtual Value *	emitMaskedAtomicCmpXchgIntrinsic (IRBuilderBase &Builder, AtomicCmpXchgInst CI, Value AlignedAddr, Value CmpVal, Value NewVal, Value *Mask, AtomicOrdering Ord) const
	Perform a masked cmpxchg using a target-specific intrinsic.

virtual Instruction *	emitLeadingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
	Inserts in the IR a target-specific intrinsic specifying a fence.

virtual Instruction *	emitTrailingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Static Public Member Functions
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Member Functions
void	initActions ()
	Initialize all of the actions to default values.

Value *	getDefaultSafeStackPointerLocation (IRBuilderBase &IRB, bool UseTLS) const

void	setBooleanContents (BooleanContent Ty)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

void	setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

void	setBooleanVectorContents (BooleanContent Ty)
	Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type.

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference.

void	setMinimumJumpTableEntries (unsigned Val)
	Indicate the minimum number of blocks to generate jump tables.

void	setMaximumJumpTableSize (unsigned)
	Indicate the maximum number of entries in jump tables.

void	setStackPointerRegisterToSaveRestore (Register R)
	If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

void	setHasMultipleConditionRegisters (bool hasManyRegs=true)
	Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.

void	setHasExtractBitsInsn (bool hasExtractInsn=true)
	Tells the code generator that the target has BitExtract instructions.

void	setJumpIsExpensive (bool isExpensive=true)
	Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass.

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)
	Add the specified register class as an available regclass for the specified value type.

virtual std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
	Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

void	computeRegisterProperties (const TargetRegisterInfo *TRI)
	Once all of the register classes are added, this allows us to compute derived properties we expose.

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
	Indicate that the specified operation does not work with the specified type and indicate what to do about it.

void	setOperationAction (ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)

void	setOperationAction (ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)

void	setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

void	setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

void	setIndexedLoadAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

void	setIndexedLoadAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)

void	setIndexedStoreAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

void	setIndexedStoreAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)

void	setIndexedMaskedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.

void	setIndexedMaskedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it.

void	setCondCodeAction (ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
	Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

void	setCondCodeAction (ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.

void	setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	Convenience method to set an operation to Promote and specify the type in a single call.

void	setTargetDAGCombine (ArrayRef< ISD::NodeType > NTs)
	Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

void	setMinFunctionAlignment (Align Alignment)
	Set the target's minimum function alignment.

void	setPrefFunctionAlignment (Align Alignment)
	Set the target's preferred function alignment.

void	setPrefLoopAlignment (Align Alignment)
	Set the target's preferred loop alignment.

void	setMaxBytesForAlignment (unsigned MaxBytes)

void	setMinStackArgumentAlignment (Align Alignment)
	Set the minimum stack alignment of an argument.

void	setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
	Set the maximum atomic operation size supported by the backend.

void	setMaxDivRemBitWidthSupported (unsigned SizeInBits)
	Set the size in bits of the maximum div/rem the backend supports.

void	setMaxLargeFPConvertBitWidthSupported (unsigned SizeInBits)
	Set the size in bits of the maximum fp convert the backend supports.

void	setMinCmpXchgSizeInBits (unsigned SizeInBits)
	Sets the minimum cmpxchg or ll/sc size supported by the backend.

void	setSupportsUnalignedAtomics (bool UnalignedSupported)
	Sets whether unaligned atomic operations are supported.

virtual bool	isExtFreeImpl (const Instruction *I) const
	Return true if the extension represented by `I` is free.

bool	isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
	Return true if the value types that can be represented by the specified register class are all legal.

MachineBasicBlock *	emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Protected Attributes
unsigned	GatherAllAliasesMaxDepth
	Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain.

unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call.

unsigned	MaxStoresPerMemsetOptSize
	Likewise for functions with the OptSize attribute.

unsigned	MaxStoresPerMemcpy
	Specify maximum number of store instructions per memcpy call.

unsigned	MaxStoresPerMemcpyOptSize
	Likewise for functions with the OptSize attribute.

unsigned	MaxGluedStoresPerMemcpy = 0
	Specify max number of store instructions to glue in inlined memcpy.

unsigned	MaxLoadsPerMemcmp
	Specify maximum number of load instructions per memcmp call.

unsigned	MaxLoadsPerMemcmpOptSize
	Likewise for functions with the OptSize attribute.

unsigned	MaxStoresPerMemmove
	Specify maximum number of store instructions per memmove call.

unsigned	MaxStoresPerMemmoveOptSize
	Likewise for functions with the OptSize attribute.

bool	PredictableSelectIsExpensive
	Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

bool	EnableExtLdPromotion

bool	IsStrictFPEnabled

Detailed Description

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.

Definition at line 192 of file TargetLowering.h.

Member Typedef Documentation

◆ ArgListTy

using llvm::TargetLoweringBase::ArgListTy = std::vector<ArgListEntry>

Definition at line 315 of file TargetLowering.h.

◆ LegalizeKind

using llvm::TargetLoweringBase::LegalizeKind = std::pair<LegalizeTypeAction, EVT>

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 228 of file TargetLowering.h.

Member Enumeration Documentation

◆ AtomicExpansionKind

enum class llvm::TargetLoweringBase::AtomicExpansionKind

strong

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

Exists because different targets have different levels of support for these atomic instructions, and also have different options w.r.t. what they should expand to.

Enumerator
None
CastToInteger
LLSC
LLOnly
CmpXChg
MaskedIntrinsic
BitTestIntrinsic
CmpArithIntrinsic
Expand
NotAtomic

Definition at line 250 of file TargetLowering.h.

◆ BooleanContent

enum llvm::TargetLoweringBase::BooleanContent

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent
ZeroOrOneBooleanContent
ZeroOrNegativeOneBooleanContent

Definition at line 231 of file TargetLowering.h.

◆ LegalizeAction

enum llvm::TargetLoweringBase::LegalizeAction : uint8_t

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal
Promote
Expand
LibCall
Custom

Definition at line 196 of file TargetLowering.h.

◆ LegalizeTypeAction

enum llvm::TargetLoweringBase::LegalizeTypeAction : uint8_t

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal
TypePromoteInteger
TypeExpandInteger
TypeSoftenFloat
TypeExpandFloat
TypeScalarizeVector
TypeSplitVector
TypeWidenVector
TypePromoteFloat
TypeSoftPromoteHalf
TypeScalarizeScalableVector

Definition at line 206 of file TargetLowering.h.

◆ MulExpansionKind

enum class llvm::TargetLoweringBase::MulExpansionKind

strong

Enum that specifies when a multiplication should be expanded.

Enumerator
Always
OnlyLegalOrCustom

Definition at line 272 of file TargetLowering.h.

◆ NegatibleCost

enum class llvm::TargetLoweringBase::NegatibleCost

strong

Enum that specifies when a float negation is beneficial.

Enumerator
Cheaper
Neutral
Expensive

Definition at line 279 of file TargetLowering.h.

◆ ReciprocalEstimate

enum llvm::TargetLoweringBase::ReciprocalEstimate : int

Reciprocal estimate status values used by the functions below.

Enumerator
Unspecified
Disabled
Enabled

Definition at line 515 of file TargetLowering.h.

◆ SelectSupportKind

enum llvm::TargetLoweringBase::SelectSupportKind

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect
ScalarCondVectorVal
VectorMaskSelect

Definition at line 238 of file TargetLowering.h.

◆ ShiftLegalizationStrategy

enum class llvm::TargetLoweringBase::ShiftLegalizationStrategy

strong

Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recursion depth - how many expansion needed.

Enumerator
ExpandToParts
ExpandThroughStack
LowerToLibcall

Definition at line 920 of file TargetLowering.h.

Constructor & Destructor Documentation

◆ TargetLoweringBase() [1/2]

TargetLoweringBase::TargetLoweringBase ( const TargetMachine & TM )

explicit

◆ TargetLoweringBase() [2/2]

llvm::TargetLoweringBase::TargetLoweringBase ( const TargetLoweringBase & )

delete

◆ ~TargetLoweringBase()

virtual llvm::TargetLoweringBase::~TargetLoweringBase ( )

virtualdefault

Member Function Documentation

◆ addBypassSlowDiv()

void llvm::TargetLoweringBase::addBypassSlowDiv	(	unsigned int	SlowBitWidth,
		unsigned int	FastBitWidth
	)

inlineprotected

Tells the code generator which bitwidths to bypass.

Definition at line 2346 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ AddPromotedToType()

void llvm::TargetLoweringBase::AddPromotedToType	(	unsigned	Opc,
		MVT	OrigVT,
		MVT	DestVT
	)

inlineprotected

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.

If that default is insufficient, this method can be used by the target to override the default.

Definition at line 2494 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), setOperationPromotedToType(), and llvm::SITargetLowering::SITargetLowering().

◆ addRegisterClass()

void llvm::TargetLoweringBase::addRegisterClass	(	MVT	VT,
		const TargetRegisterClass *	RC
	)

inlineprotected

Add the specified register class as an available regclass for the specified value type.

This indicates the selector can handle values of that class natively.

Definition at line 2353 of file TargetLowering.h.

References assert(), and llvm::MVT::SimpleTy.

◆ aggressivelyPreferBuildVectorSources()

virtual bool llvm::TargetLoweringBase::aggressivelyPreferBuildVectorSources ( EVT VecVT ) const

inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 3115 of file TargetLowering.h.

◆ alignLoopsWithOptSize()

virtual bool llvm::TargetLoweringBase::alignLoopsWithOptSize ( ) const

inlinevirtual

Should loops be aligned even when the function is marked OptSize (but not MinSize).

Reimplemented in llvm::ARMTargetLowering.

Definition at line 1867 of file TargetLowering.h.

◆ allowsMemoryAccess() [1/3]

bool TargetLoweringBase::allowsMemoryAccess	(	LLVMContext &	Context,
		const DataLayout &	DL,
		EVT	VT,
		const MachineMemOperand &	MMO,
		unsigned *	Fast = `nullptr`
	)		const

Return true if the target supports a memory access of this type for the given MachineMemOperand.

If the access is allowed, the optional final parameter returns the relative access speed (as defined by the target).

Definition at line 1763 of file TargetLoweringBase.cpp.

References allowsMemoryAccess(), Context, DL, llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), and llvm::MachineMemOperand::getFlags().

◆ allowsMemoryAccess() [2/3]

bool TargetLoweringBase::allowsMemoryAccess	(	LLVMContext &	Context,
		const DataLayout &	DL,
		EVT	VT,
		unsigned	AddrSpace = `0`,
		Align	Alignment = `Align(1)`,
		MachineMemOperand::Flags	Flags = `MachineMemOperand::MONone`,
		unsigned *	Fast = `nullptr`
	)		const

virtual

Return true if the target supports a memory access of this type for the given address space and alignment.

If the access is allowed, the optional final parameter returns the relative speed of the access (as defined by the target).

Reimplemented in llvm::HexagonTargetLowering, and llvm::X86TargetLowering.

Definition at line 1754 of file TargetLoweringBase.cpp.

References allowsMemoryAccessForAlignment(), Context, DL, and llvm::CallingConv::Fast.

Referenced by allowsMemoryAccess(), llvm::HexagonTargetLowering::allowsMemoryAccess(), combineLoad(), combineStore(), isLoadBitCastBeneficial(), llvm::LegalizerHelper::lowerLoad(), llvm::LegalizerHelper::lowerStore(), llvm::CombinerHelper::matchTruncStoreMerge(), and ShrinkLoadReplaceStoreWithStore().

◆ allowsMemoryAccess() [3/3]

bool TargetLoweringBase::allowsMemoryAccess	(	LLVMContext &	Context,
		const DataLayout &	DL,
		LLT	Ty,
		const MachineMemOperand &	MMO,
		unsigned *	Fast = `nullptr`
	)		const

LLT handling variant.

Definition at line 1771 of file TargetLoweringBase.cpp.

References allowsMemoryAccess(), Context, DL, llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::getApproximateEVTForLLT(), and llvm::MachineMemOperand::getFlags().

◆ allowsMemoryAccessForAlignment() [1/2]

bool TargetLoweringBase::allowsMemoryAccessForAlignment	(	LLVMContext &	Context,
		const DataLayout &	DL,
		EVT	VT,
		const MachineMemOperand &	MMO,
		unsigned *	Fast = `nullptr`
	)		const

Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.

If the access is allowed, the optional final parameter returns a relative speed of the access (as defined by the target).

Definition at line 1747 of file TargetLoweringBase.cpp.

References allowsMemoryAccessForAlignment(), Context, DL, llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), and llvm::MachineMemOperand::getFlags().

◆ allowsMemoryAccessForAlignment() [2/2]

bool TargetLoweringBase::allowsMemoryAccessForAlignment	(	LLVMContext &	Context,
		const DataLayout &	DL,
		EVT	VT,
		unsigned	AddrSpace = `0`,
		Align	Alignment = `Align(1)`,
		MachineMemOperand::Flags	Flags = `MachineMemOperand::MONone`,
		unsigned *	Fast = `nullptr`
	)		const

This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.

If the access is allowed, the optional final parameter returns a relative speed of the access (as defined by the target).

Definition at line 1727 of file TargetLoweringBase.cpp.

References allowsMisalignedMemoryAccesses(), Context, DL, llvm::CallingConv::Fast, llvm::EVT::getTypeForEVT(), and llvm::EVT::isZeroSized().

Referenced by allowsMemoryAccess(), allowsMemoryAccessForAlignment(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), and llvm::HexagonTargetLowering::LowerUnalignedLoad().

◆ allowsMisalignedMemoryAccesses() [1/2]

virtual bool llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses	(	EVT	,
		unsigned	AddrSpace = `0`,
		Align	Alignment = `Align(1)`,
		MachineMemOperand::Flags	Flags = `MachineMemOperand::MONone`,
		unsigned *	= `nullptr`
	)		const

inlinevirtual

Determine if the target supports unaligned memory accesses.

This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns a relative speed of the unaligned memory access in the last argument by reference. The higher the speed number the faster the operation comparing to a number returned by another such call. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Reimplemented in llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::Mips16TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, llvm::VETargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::R600TargetLowering, llvm::SITargetLowering, and llvm::MipsSETargetLowering.

Definition at line 1727 of file TargetLowering.h.

Referenced by allowsMemoryAccessForAlignment(), llvm::BasicTTIImplBase< T >::allowsMisalignedMemoryAccesses(), findGISelOptimalMemOpLowering(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::AMDGPUTargetLowering::performLoadCombine(), and llvm::AMDGPUTargetLowering::performStoreCombine().

◆ allowsMisalignedMemoryAccesses() [2/2]

virtual bool llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses	(	LLT	,
		unsigned	AddrSpace = `0`,
		Align	Alignment = `Align(1)`,
		MachineMemOperand::Flags	Flags = `MachineMemOperand::MONone`,
		unsigned *	= `nullptr`
	)		const

inlinevirtual

LLT handling variant.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 1735 of file TargetLowering.h.

◆ allowTruncateForTailCall()

virtual bool llvm::TargetLoweringBase::allowTruncateForTailCall	(	Type *	FromTy,
		Type *	ToTy
	)		const

inlinevirtual

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.

Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.

Reimplemented in llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::X86TargetLowering.

Definition at line 2745 of file TargetLowering.h.

Referenced by getNoopInput().

◆ areJTsAllowed()

virtual bool llvm::TargetLoweringBase::areJTsAllowed ( const Function * Fn ) const

inlinevirtual

Return true if lowering to a jump table is allowed.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1227 of file TargetLowering.h.

References llvm::ISD::BR_JT, llvm::ISD::BRIND, llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsBool(), isOperationLegalOrCustom(), and llvm::MVT::Other.

Referenced by llvm::X86TargetLowering::areJTsAllowed(), llvm::SwitchCG::SwitchLowering::findJumpTables(), and llvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().

◆ canCombineStoreAndExtract()

virtual bool llvm::TargetLoweringBase::canCombineStoreAndExtract	(	Type *	VectorTy,
		Value *	Idx,
		unsigned &	Cost
	)		const

inlinevirtual

Return true if the target can combine store(extractelement VectorTy, Idx).

Cost[out] gives the cost of that transformation when this is true.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 803 of file TargetLowering.h.

◆ canCombineTruncStore()

virtual bool llvm::TargetLoweringBase::canCombineTruncStore	(	EVT	ValVT,
		EVT	MemVT,
		bool	LegalOnly
	)		const

inlinevirtual

Reimplemented in llvm::R600TargetLowering.

Definition at line 1346 of file TargetLowering.h.

References isTruncStoreLegal(), and isTruncStoreLegalOrCustom().

◆ canMergeStoresTo()

virtual bool llvm::TargetLoweringBase::canMergeStoresTo	(	unsigned	AS,
		EVT	MemVT,
		const MachineFunction &	MF
	)		const

inlinevirtual

Returns if it's reasonable to merge stores to MemVT size.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::X86TargetLowering, llvm::R600TargetLowering, and llvm::SITargetLowering.

Definition at line 607 of file TargetLowering.h.

◆ canOpTrap()

bool TargetLoweringBase::canOpTrap	(	unsigned	Op,
		EVT	VT
	)		const

virtual

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.

Definition at line 933 of file TargetLoweringBase.cpp.

References assert(), isTypeLegal(), llvm::ISD::SDIV, llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.

◆ computeRegisterProperties()

void TargetLoweringBase::computeRegisterProperties ( const TargetRegisterInfo * TRI )

protected

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1285 of file TargetLoweringBase.cpp.

References assert(), llvm::MVT::bf16, Cost, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, findRepresentativeClass(), llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::MVT::getPow2VectorType(), getPreferredVectorAction(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), getVectorTypeBreakdownMVT(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::isPowerOf2_32(), llvm::MVT::isScalableVector(), isTypeLegal(), llvm::MVT::isVoid, llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE, llvm::MVT::LAST_INTEGER_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm_unreachable, llvm::MVT::MAX_ALLOWED_VALUETYPE, llvm::MVT::Other, llvm::MVT::ppcf128, llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), softPromoteHalfType(), TRI, TypeExpandFloat, TypeExpandInteger, TypePromoteFloat, TypePromoteInteger, TypeScalarizeScalableVector, TypeScalarizeVector, TypeSoftenFloat, TypeSoftPromoteHalf, TypeSplitVector, TypeWidenVector, and llvm::MVT::VALUETYPE_SIZE.

◆ convertSelectOfConstantsToMath()

virtual bool llvm::TargetLoweringBase::convertSelectOfConstantsToMath ( EVT VT ) const

inlinevirtual

Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.

For example: select Cond, C1, C1-1 --> add (zext Cond), C1-1

Reimplemented in llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 2230 of file TargetLowering.h.

Referenced by shouldConvertSelectOfConstantsToMath().

◆ convertSetCCLogicToBitwiseLogic()

virtual bool llvm::TargetLoweringBase::convertSetCCLogicToBitwiseLogic ( EVT VT ) const

inlinevirtual

Use bitwise logic to make pairs of compares more efficient.

For example: and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 674 of file TargetLowering.h.

◆ createComplexDeinterleavingIR()

virtual Value * llvm::TargetLoweringBase::createComplexDeinterleavingIR	(	Instruction *	I,
		ComplexDeinterleavingOperation	OperationType,
		ComplexDeinterleavingRotation	Rotation,
		Value *	InputA,
		Value *	InputB,
		Value *	Accumulator = `nullptr`
	)		const

inlinevirtual

Create the IR node for the given complex deinterleaving operation.

If one cannot be created using all the given inputs, nullptr should be returned.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3153 of file TargetLowering.h.

◆ decomposeMulByConstant()

virtual bool llvm::TargetLoweringBase::decomposeMulByConstant	(	LLVMContext &	Context,
		EVT	VT,
		SDValue	C
	)		const

inlinevirtual

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.

This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 2239 of file TargetLowering.h.

◆ emitAtomicCmpXchgNoStoreLLBalance()

virtual void llvm::TargetLoweringBase::emitAtomicCmpXchgNoStoreLLBalance ( IRBuilderBase & Builder ) const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2103 of file TargetLowering.h.

◆ emitBitTestAtomicRMWIntrinsic()

virtual void llvm::TargetLoweringBase::emitBitTestAtomicRMWIntrinsic ( AtomicRMWInst * AI ) const

inlinevirtual

Perform a bit test atomicrmw using a target-specific intrinsic.

This represents the combined bit test intrinsic which will be lowered at a late stage by the backend.

Definition at line 2032 of file TargetLowering.h.

References llvm_unreachable.

◆ emitCmpArithAtomicRMWIntrinsic()

virtual void llvm::TargetLoweringBase::emitCmpArithAtomicRMWIntrinsic ( AtomicRMWInst * AI ) const

inlinevirtual

Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.

This represents the combined atomic and compare intrinsic which will be lowered at a late stage by the backend.

Definition at line 2040 of file TargetLowering.h.

References llvm_unreachable.

◆ emitExpandAtomicRMW()

virtual void llvm::TargetLoweringBase::emitExpandAtomicRMW ( AtomicRMWInst * AI ) const

inlinevirtual

Perform a atomicrmw expansion using a target-specific way.

This is expected to be called when masked atomicrmw and bit test atomicrmw don't work, and the target supports another way to lower atomicrmw.

Reimplemented in llvm::SITargetLowering.

Definition at line 2024 of file TargetLowering.h.

References llvm_unreachable.

◆ emitLeadingFence()

Instruction * TargetLoweringBase::emitLeadingFence	(	IRBuilderBase &	Builder,
		Instruction *	Inst,
		AtomicOrdering	Ord
	)		const

virtual

Inserts in the IR a target-specific intrinsic specifying a fence.

It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.

Inst is the original atomic instruction, prior to other expansions that may be performed.

This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::VETargetLowering.

Definition at line 2305 of file TargetLoweringBase.cpp.

References Builder, llvm::Instruction::hasAtomicStore(), and llvm::isReleaseOrStronger().

◆ emitLoadLinked()

virtual Value * llvm::TargetLoweringBase::emitLoadLinked	(	IRBuilderBase &	Builder,
		Type *	ValueTy,
		Value *	Addr,
		AtomicOrdering	Ord
	)		const

inlinevirtual

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1997 of file TargetLowering.h.

References llvm_unreachable.

◆ emitMaskedAtomicCmpXchgIntrinsic()

virtual Value * llvm::TargetLoweringBase::emitMaskedAtomicCmpXchgIntrinsic	(	IRBuilderBase &	Builder,
		AtomicCmpXchgInst *	CI,
		Value *	AlignedAddr,
		Value *	CmpVal,
		Value *	NewVal,
		Value *	Mask,
		AtomicOrdering	Ord
	)		const

inlinevirtual

Perform a masked cmpxchg using a target-specific intrinsic.

This represents the core LL/SC loop which will be lowered at a late stage by the backend. The target-specific intrinsic returns the loaded value and is not responsible for masking and shifting the result.

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2049 of file TargetLowering.h.

References llvm_unreachable.

◆ emitMaskedAtomicRMWIntrinsic()

virtual Value * llvm::TargetLoweringBase::emitMaskedAtomicRMWIntrinsic	(	IRBuilderBase &	Builder,
		AtomicRMWInst *	AI,
		Value *	AlignedAddr,
		Value *	Incr,
		Value *	Mask,
		Value *	ShiftAmt,
		AtomicOrdering	Ord
	)		const

inlinevirtual

Perform a masked atomicrmw using a target-specific intrinsic.

This represents the core LL/SC loop which will be lowered at a late stage by the backend. The target-specific intrinsic returns the loaded value and is not responsible for masking and shifting the result.

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2013 of file TargetLowering.h.

References llvm_unreachable.

◆ emitPatchPoint()

MachineBasicBlock * TargetLoweringBase::emitPatchPoint	(	MachineInstr &	MI,
		MachineBasicBlock *	MBB
	)		const

protected

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Definition at line 1165 of file TargetLoweringBase.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addMemOperand(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineFunction::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineInstr::getNumOperands(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::DataLayout::getPointerSize(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isReg(), llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex(), llvm::MachineOperand::isTied(), llvm::MachineInstr::mayLoad(), MBB, MI, llvm::MachineMemOperand::MOLoad, llvm::none_of(), and llvm::MachineInstr::tieOperands().

Referenced by llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), and llvm::X86TargetLowering::EmitInstrWithCustomInserter().

◆ emitStoreConditional()

virtual Value * llvm::TargetLoweringBase::emitStoreConditional	(	IRBuilderBase &	Builder,
		Value *	Val,
		Value *	Addr,
		AtomicOrdering	Ord
	)		const

inlinevirtual

Perform a store-conditional operation to Addr.

Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 2004 of file TargetLowering.h.

References llvm_unreachable.

◆ emitTrailingFence()

Instruction * TargetLoweringBase::emitTrailingFence	(	IRBuilderBase &	Builder,
		Instruction *	Inst,
		AtomicOrdering	Ord
	)		const

virtual

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::VETargetLowering.

Definition at line 2314 of file TargetLoweringBase.cpp.

References Builder, and llvm::isAcquireOrStronger().

◆ enableAggressiveFMAFusion() [1/2]

virtual bool llvm::TargetLoweringBase::enableAggressiveFMAFusion ( EVT VT ) const

inlinevirtual

Return true if target always benefits from combining into FMA for a given value type.

This must typically return false on targets where FMA takes more cycles to execute than FADD.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::NVPTXTargetLowering, and llvm::PPCTargetLowering.

Definition at line 817 of file TargetLowering.h.

◆ enableAggressiveFMAFusion() [2/2]

virtual bool llvm::TargetLoweringBase::enableAggressiveFMAFusion ( LLT Ty ) const

inlinevirtual

Return true if target always benefits from combining into FMA for a given value type.

This must typically return false on targets where FMA takes more cycles to execute than FADD.

Reimplemented in llvm::SITargetLowering.

Definition at line 822 of file TargetLowering.h.

◆ enableExtLdPromotion()

bool llvm::TargetLoweringBase::enableExtLdPromotion ( ) const

inline

Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

Definition at line 798 of file TargetLowering.h.

References EnableExtLdPromotion.

◆ fallBackToDAGISel()

virtual bool llvm::TargetLoweringBase::fallBackToDAGISel ( const Instruction & Inst ) const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 567 of file TargetLowering.h.

◆ finalizeLowering()

void TargetLoweringBase::finalizeLowering ( MachineFunction & MF ) const

virtual

Execute target specific actions to finalize target lowering.

This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.

Reimplemented in llvm::SITargetLowering, and llvm::ARMTargetLowering.

Definition at line 2244 of file TargetLoweringBase.cpp.

References llvm::MachineRegisterInfo::freezeReservedRegs(), and llvm::MachineFunction::getRegInfo().

Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::ARMTargetLowering::finalizeLowering(), INITIALIZE_PASS(), and llvm::InstructionSelect::runOnMachineFunction().

◆ findRepresentativeClass()

std::pair< const TargetRegisterClass *, uint8_t > TargetLoweringBase::findRepresentativeClass	(	const TargetRegisterInfo *	TRI,
		MVT	VT
	)		const

protectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented in llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 1258 of file TargetLoweringBase.cpp.

References isLegalRC(), llvm::SuperRegClassIterator::isValid(), llvm::BitVector::set_bits(), llvm::BitVector::setBitsInMask(), llvm::MVT::SimpleTy, and TRI.

Referenced by computeRegisterProperties(), llvm::ARMTargetLowering::findRepresentativeClass(), and llvm::X86TargetLowering::findRepresentativeClass().

◆ generateFMAsInMachineCombiner()

virtual bool llvm::TargetLoweringBase::generateFMAsInMachineCombiner	(	EVT	VT,
		CodeGenOpt::Level	OptLevel
	)		const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 3039 of file TargetLowering.h.

◆ getABIAlignmentForCallingConv()

virtual Align llvm::TargetLoweringBase::getABIAlignmentForCallingConv	(	Type *	ArgTy,
		const DataLayout &	DL
	)		const

inlinevirtual

Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.

Reimplemented in llvm::ARMTargetLowering, and llvm::MipsTargetLowering.

Definition at line 1623 of file TargetLowering.h.

References DL.

Referenced by llvm::TargetLowering::LowerCallTo().

◆ getAddrModeArguments()

virtual bool llvm::TargetLoweringBase::getAddrModeArguments	(	IntrinsicInst *	,
		SmallVectorImpl< Value * > &	,
		Type *&
	)		const

inlinevirtual

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.

This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Reimplemented in llvm::SITargetLowering.

Definition at line 2579 of file TargetLowering.h.

◆ getAsmOperandValueType()

virtual EVT llvm::TargetLoweringBase::getAsmOperandValueType	(	const DataLayout &	DL,
		Type *	Ty,
		bool	AllowUnknown = `false`
	)		const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1485 of file TargetLowering.h.

References DL, and getValueType().

Referenced by llvm::AArch64TargetLowering::getAsmOperandValueType(), llvm::InlineAsmLowering::lowerInlineAsm(), and llvm::TargetLowering::ParseConstraints().

◆ getAtomicMemOperandFlags()

MachineMemOperand::Flags TargetLoweringBase::getAtomicMemOperandFlags	(	const Instruction &	AI,
		const DataLayout &	DL
	)		const

Definition at line 2287 of file TargetLoweringBase.cpp.

References getTargetMMOFlags(), llvm_unreachable, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::MachineMemOperand::MOVolatile.

◆ getBooleanContents() [1/2]

BooleanContent llvm::TargetLoweringBase::getBooleanContents	(	bool	isVec,
		bool	isFloat
	)		const

inline

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 847 of file TargetLowering.h.

◆ getBooleanContents() [2/2]

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT Type ) const

inline

Definition at line 853 of file TargetLowering.h.

References getBooleanContents().

◆ getBypassSlowDivWidths()

const DenseMap< unsigned int, unsigned int > & llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const

inline

Returns map of slow types for division or remainder with corresponding fast types.

Definition at line 550 of file TargetLowering.h.

◆ getByValTypeAlignment()

uint64_t TargetLoweringBase::getByValTypeAlignment	(	Type *	Ty,
		const DataLayout &	DL
	)		const

virtual

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.

This is the actual alignment, not its logarithm.

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 1722 of file TargetLoweringBase.cpp.

References DL.

Referenced by llvm::FastISel::lowerCallTo(), and llvm::TargetLowering::LowerCallTo().

◆ getCmpLibcallCC()

ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall Call ) const

inline

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 3186 of file TargetLowering.h.

Referenced by llvm::TargetLowering::softenSetCCOperands().

◆ getCmpLibcallReturnType()

MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const

virtual

Return the ValueType for comparison libcalls.

Comparison libcalls include floating point comparison calls, and Ordered/Unordered check calls on floating point numbers.

Reimplemented in llvm::AVRTargetLowering, and llvm::MSP430TargetLowering.

Definition at line 1537 of file TargetLoweringBase.cpp.

References llvm::MVT::i32.

Referenced by llvm::TargetLowering::softenSetCCOperands().

◆ getCondCodeAction()

LegalizeAction llvm::TargetLoweringBase::getCondCodeAction	(	ISD::CondCode	CC,
		MVT	VT
	)		const

inline

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1436 of file TargetLowering.h.

References assert(), CC, Promote, and llvm::MVT::SimpleTy.

Referenced by isCondCodeLegal(), isCondCodeLegalOrCustom(), and llvm::TargetLowering::LegalizeSetCCCondCode().

◆ getCustomCtpopCost()

virtual unsigned llvm::TargetLoweringBase::getCustomCtpopCost	(	EVT	VT,
		ISD::CondCode	Cond
	)		const

inlinevirtual

Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.

Definition at line 629 of file TargetLowering.h.

Referenced by simplifySetCCWithCTPOP().

◆ getCustomOperationAction()

virtual LegalizeAction llvm::TargetLoweringBase::getCustomOperationAction ( SDNode & Op ) const

inlinevirtual

How to legalize this custom operation?

Reimplemented in llvm::VETargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1106 of file TargetLowering.h.

References Legal.

◆ getDefaultSafeStackPointerLocation()

Value * TargetLoweringBase::getDefaultSafeStackPointerLocation	(	IRBuilderBase &	IRB,
		bool	UseTLS
	)		const

protected

Definition at line 1864 of file TargetLoweringBase.cpp.

References llvm::GlobalValue::ExternalLinkage, llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), llvm::GlobalValue::InitialExecTLSModel, llvm::GlobalValue::NotThreadLocal, and llvm::report_fatal_error().

Referenced by getSafeStackPointerLocation(), and llvm::X86TargetLowering::getSafeStackPointerLocation().

◆ getDivRefinementSteps()

int TargetLoweringBase::getDivRefinementSteps	(	EVT	VT,
		MachineFunction &	MF
	)		const

Return the refinement step count for a division of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2211 of file TargetLoweringBase.cpp.

References getOpRefinementSteps(), and getRecipEstimateForFunc().

◆ getExceptionPointerRegister()

virtual Register llvm::TargetLoweringBase::getExceptionPointerRegister ( const Constant * PersonalityFn ) const

inlinevirtual

If a physical register, this returns the register that receives the exception address on entry to an EH pad.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 1831 of file TargetLowering.h.

Referenced by GetEHSpillList(), and llvm::MachineBasicBlock::liveout_begin().

◆ getExceptionSelectorRegister()

virtual Register llvm::TargetLoweringBase::getExceptionSelectorRegister ( const Constant * PersonalityFn ) const

inlinevirtual

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 1838 of file TargetLowering.h.

Referenced by GetEHSpillList(), and llvm::MachineBasicBlock::liveout_begin().

◆ getExtendForAtomicCmpSwapArg()

virtual ISD::NodeType llvm::TargetLoweringBase::getExtendForAtomicCmpSwapArg ( ) const

inlinevirtual

Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

This is separate from getExtendForAtomicOps, which is concerned with the sign-extension of the instruction's output, whereas here we are concerned with the sign-extension of the input. For targets with compare-and-swap instructions (or sub-word comparisons in their LL/SC loop expansions), the input can be ANY_EXTEND, but the output will still have a specific extension.

Reimplemented in llvm::RISCVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 2201 of file TargetLowering.h.

References llvm::ISD::ANY_EXTEND.

◆ getExtendForAtomicOps()

virtual ISD::NodeType llvm::TargetLoweringBase::getExtendForAtomicOps ( ) const

inlinevirtual

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

Reimplemented in llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::VETargetLowering.

Definition at line 2189 of file TargetLowering.h.

References llvm::ISD::ZERO_EXTEND.

Referenced by llvm::SelectionDAG::computeKnownBits(), and llvm::SelectionDAG::ComputeNumSignBits().

◆ getExtendForContent()

static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent Content )

inlinestatic

Definition at line 320 of file TargetLowering.h.

References llvm::ISD::ANY_EXTEND, Content, llvm_unreachable, llvm::ISD::SIGN_EXTEND, UndefinedBooleanContent, llvm::ISD::ZERO_EXTEND, ZeroOrNegativeOneBooleanContent, and ZeroOrOneBooleanContent.

Referenced by llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), promoteTargetBoolean(), and llvm::TargetLowering::SimplifySetCC().

◆ getFenceOperandTy()

virtual MVT llvm::TargetLoweringBase::getFenceOperandTy ( const DataLayout & DL ) const

inlinevirtual

Return the type for operands of fence.

TODO: Let fence operands be of i32 type and remove this.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 382 of file TargetLowering.h.

References DL, and getPointerTy().

◆ getFixedPointOperationAction()

LegalizeAction llvm::TargetLoweringBase::getFixedPointOperationAction	(	unsigned	Op,
		EVT	VT,
		unsigned	Scale
	)		const

inline

Some fixed point operations may be natively supported by the target but only for specific scales.

This method allows for checking if the width is supported by the target for a given operation that may depend on scale.

Definition at line 1134 of file TargetLowering.h.

References Expand, getOperationAction(), isSupportedFixedPointOperation(), Legal, llvm_unreachable, llvm::ISD::SDIVFIX, llvm::ISD::SDIVFIXSAT, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::UDIVFIX, llvm::ISD::UDIVFIXSAT, llvm::ISD::UMULFIX, and llvm::ISD::UMULFIXSAT.

Referenced by expandDivFix().

◆ getFrameIndexTy()

MVT llvm::TargetLoweringBase::getFrameIndexTy ( const DataLayout & DL ) const

inline

Return the type for frame index, which is determined by the alloca address space specified through the data layout.

Definition at line 370 of file TargetLowering.h.

References DL, and getPointerTy().

Referenced by llvm::SelectionDAG::CreateStackTemporary(), getAddressForMemoryInput(), llvm::SelectionDAGBuilder::getFrameIndexTy(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), and llvm::TargetLowering::LowerCallTo().

◆ getGatherAllAliasesMaxDepth()

unsigned llvm::TargetLoweringBase::getGatherAllAliasesMaxDepth ( ) const

inline

Definition at line 1659 of file TargetLowering.h.

References GatherAllAliasesMaxDepth.

◆ getIndexedLoadAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction	(	unsigned	IdxMode,
		MVT	VT
	)		const

inline

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1357 of file TargetLowering.h.

Referenced by isIndexedLoadLegal().

◆ getIndexedMaskedLoadAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedMaskedLoadAction	(	unsigned	IdxMode,
		MVT	VT
	)		const

inline

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1385 of file TargetLowering.h.

Referenced by isIndexedMaskedLoadLegal().

◆ getIndexedMaskedStoreAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedMaskedStoreAction	(	unsigned	IdxMode,
		MVT	VT
	)		const

inline

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1399 of file TargetLowering.h.

Referenced by isIndexedMaskedStoreLegal().

◆ getIndexedStoreAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction	(	unsigned	IdxMode,
		MVT	VT
	)		const

inline

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1371 of file TargetLowering.h.

Referenced by isIndexedStoreLegal().

◆ getIRStackGuard()

Value * TargetLoweringBase::getIRStackGuard ( IRBuilderBase & IRB ) const

virtual

If the target has a standard location for the stack protector guard, returns the address of that location.

Otherwise, returns nullptr. DEPRECATED: please override useLoadStackGuardNode and customize LOAD_STACK_GUARD, or customize @llvm.stackguard().

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 1957 of file TargetLoweringBase.cpp.

References llvm::CallingConv::C, G, llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), getTargetMachine(), and llvm::GlobalValue::HiddenVisibility.

Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), llvm::RISCVTargetLowering::getIRStackGuard(), llvm::X86TargetLowering::getIRStackGuard(), and getStackGuard().

◆ getLibcallCallingConv()

CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall Call ) const

inline

Get the CallingConv that should be used for the specified libcall.

Definition at line 3196 of file TargetLowering.h.

Referenced by llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SelectionDAG::getAtomicMemcpy(), llvm::SelectionDAG::getAtomicMemmove(), llvm::SelectionDAG::getAtomicMemset(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), and llvm::TargetLowering::makeLibCall().

◆ getLibcallName()

const char * llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall Call ) const

inline

Get the libcall routine name for the specified libcall.

Definition at line 3174 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::SelectionDAG::getAtomicMemcpy(), llvm::SelectionDAG::getAtomicMemmove(), llvm::SelectionDAG::getAtomicMemset(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), isDivRemLibcallAvailable(), isSinCosLibcallAvailable(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), LowerFSINCOS(), llvm::SparcTargetLowering::LowerOperation(), LowerSINT_TO_FP(), LowerUINT_TO_FP(), llvm::TargetLowering::makeLibCall(), optimizeCall(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::returnTypeIsEligibleForTailCall(), and llvm::X86TargetLowering::X86TargetLowering().

◆ getLoadExtAction()

LegalizeAction llvm::TargetLoweringBase::getLoadExtAction	(	unsigned	ExtType,
		EVT	ValVT,
		EVT	MemVT
	)		const

inline

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1297 of file TargetLowering.h.

References assert(), Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::ISD::LAST_LOADEXT_TYPE, llvm::MVT::SimpleTy, and llvm::MVT::VALUETYPE_SIZE.

Referenced by isLoadExtLegal(), and isLoadExtLegalOrCustom().

◆ getLoadMemOperandFlags()

MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags	(	const LoadInst &	LI,
		const DataLayout &	DL,
		AssumptionCache *	AC = `nullptr`,
		const TargetLibraryInfo *	LibInfo = `nullptr`
	)		const

Definition at line 2248 of file TargetLoweringBase.cpp.

References DL, llvm::LoadInst::getAlign(), llvm::LoadInst::getPointerOperand(), getTargetMMOFlags(), llvm::Value::getType(), llvm::Instruction::hasMetadata(), llvm::isDereferenceableAndAlignedPointer(), llvm::LoadInst::isVolatile(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONonTemporal, and llvm::MachineMemOperand::MOVolatile.

◆ getMaxAtomicSizeInBitsSupported()

unsigned llvm::TargetLoweringBase::getMaxAtomicSizeInBitsSupported ( ) const

inline

Returns the maximum atomic operation size (in bits) supported by the backend.

Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.

Definition at line 1951 of file TargetLowering.h.

Referenced by atomicSizeSupported().

◆ getMaxDivRemBitWidthSupported()

unsigned llvm::TargetLoweringBase::getMaxDivRemBitWidthSupported ( ) const

inline

Returns the size in bits of the maximum div/rem the backend supports.

Larger operations will be expanded by ExpandLargeDivRem.

Definition at line 1957 of file TargetLowering.h.

Referenced by runImpl().

◆ getMaxExpandSizeMemcmp()

unsigned llvm::TargetLoweringBase::getMaxExpandSizeMemcmp ( bool OptSize ) const

inline

Get maximum # of load operations permitted for memcmp.

This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1703 of file TargetLowering.h.

References MaxLoadsPerMemcmp, and MaxLoadsPerMemcmpOptSize.

Referenced by llvm::AArch64TTIImpl::enableMemCmpExpansion(), llvm::BPFTTIImpl::enableMemCmpExpansion(), llvm::PPCTTIImpl::enableMemCmpExpansion(), and llvm::X86TTIImpl::enableMemCmpExpansion().

◆ getMaxGluedStoresPerMemcpy()

virtual unsigned llvm::TargetLoweringBase::getMaxGluedStoresPerMemcpy ( ) const

inlinevirtual

Get maximum # of store operations to be glued together.

This function returns the maximum number of store operations permitted to glue together during lowering of llvm.memcpy. The value is set by

Definition at line 1693 of file TargetLowering.h.

References MaxGluedStoresPerMemcpy.

Referenced by getMemcpyLoadsAndStores().

◆ getMaximumJumpTableSize()

unsigned TargetLoweringBase::getMaximumJumpTableSize ( ) const

Return upper limit for number of entries in a jump table.

Zero if no limit.

Definition at line 2007 of file TargetLoweringBase.cpp.

References MaximumJumpTableSize.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), and isSuitableForJumpTable().

◆ getMaxLargeFPConvertBitWidthSupported()

unsigned llvm::TargetLoweringBase::getMaxLargeFPConvertBitWidthSupported ( ) const

inline

Returns the size in bits of the maximum larget fp convert the backend supports.

Larger operations will be expanded by ExpandLargeFPConvert.

Definition at line 1963 of file TargetLowering.h.

Referenced by runImpl().

◆ getMaxPermittedBytesForAlignment()

unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment ( MachineBasicBlock * MBB ) const

virtual

Return the maximum amount of bytes allowed to be emitted when padding for alignment.

Definition at line 2025 of file TargetLoweringBase.cpp.

◆ getMaxStoresPerMemcpy()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool OptSize ) const

inline

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1684 of file TargetLowering.h.

References MaxStoresPerMemcpy, and MaxStoresPerMemcpyOptSize.

Referenced by getMemcpyLoadsAndStores(), llvm::ARMTTIImpl::getNumMemOps(), and llvm::LegalizerHelper::lowerMemCpyFamily().

◆ getMaxStoresPerMemmove()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool OptSize ) const

inline

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1713 of file TargetLowering.h.

References MaxStoresPerMemmove, and MaxStoresPerMemmoveOptSize.

Referenced by getMemmoveLoadsAndStores(), and llvm::ARMTTIImpl::getNumMemOps().

◆ getMaxStoresPerMemset()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool OptSize ) const

inline

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1674 of file TargetLowering.h.

References MaxStoresPerMemset, and MaxStoresPerMemsetOptSize.

Referenced by getMemsetStores(), and llvm::ARMTTIImpl::getNumMemOps().

◆ getMaxSupportedInterleaveFactor()

virtual unsigned llvm::TargetLoweringBase::getMaxSupportedInterleaveFactor ( ) const

inlinevirtual

Get the maximum supported factor for interleaved memory accesses.

Default to be the minimum interleave factor: 2.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 2894 of file TargetLowering.h.

Referenced by llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().

◆ getMemValueType()

EVT llvm::TargetLoweringBase::getMemValueType	(	const DataLayout &	DL,
		Type *	Ty,
		bool	AllowUnknown = `false`
	)		const

inline

Definition at line 1514 of file TargetLowering.h.

References DL, llvm::Type::getContext(), llvm::EVT::getEVT(), getPointerMemTy(), getValueType(), and llvm::EVT::getVectorVT().

Referenced by llvm::ComputeValueVTs(), getAddressForMemoryInput(), setInfoSVEStN(), and llvm::SelectionDAGBuilder::visitSwitchCase().

◆ getMinCmpXchgSizeInBits()

unsigned llvm::TargetLoweringBase::getMinCmpXchgSizeInBits ( ) const

inline

Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.

Any smaller operations are widened in AtomicExpandPass.

Note that unlike operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.

Definition at line 1974 of file TargetLowering.h.

Referenced by llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode().

◆ getMinFunctionAlignment()

Align llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const

inline

Return the minimum function alignment.

Definition at line 1852 of file TargetLowering.h.

◆ getMinimumJumpTableDensity()

unsigned TargetLoweringBase::getMinimumJumpTableDensity ( bool OptForSize ) const

Return lower limit of the density in a jump table.

Definition at line 2003 of file TargetLoweringBase.cpp.

References JumpTableDensity, and OptsizeJumpTableDensity.

Referenced by isSuitableForJumpTable().

◆ getMinimumJumpTableEntries()

unsigned TargetLoweringBase::getMinimumJumpTableEntries ( ) const

virtual

Return lower limit for number of blocks in a jump table.

Reimplemented in llvm::VETargetLowering.

Definition at line 1995 of file TargetLoweringBase.cpp.

References MinimumJumpTableEntries.

Referenced by llvm::SwitchCG::SwitchLowering::findJumpTables(), and llvm::VETargetLowering::getMinimumJumpTableEntries().

◆ getMinStackArgumentAlignment()

Align llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const

inline

Return the minimum stack alignment of an argument.

Definition at line 1847 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::expandVAArg().

◆ getNumRegisters()

virtual unsigned llvm::TargetLoweringBase::getNumRegisters	(	LLVMContext &	Context,
		EVT	VT,
		std::optional< MVT >	RegisterVT = `std::nullopt`
	)		const

inlinevirtual

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

RegisterVT may be passed as a way to override the default settings, for instance with i128 inline assembly operands on SystemZ.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 1583 of file TargetLowering.h.

References assert(), llvm::BitWidth, Context, getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::computeLegalValueVTs(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::SystemZTargetLowering::getNumRegisters(), getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), getRegistersForValue(), llvm::BasicTTIImplBase< T >::getRegUsageForType(), llvm::FunctionLoweringInfo::getValueFromVirtualReg(), llvm::FastISel::lowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RegsForValue::RegsForValue(), llvm::FastISel::selectExtractValue(), and llvm::FunctionLoweringInfo::set().

◆ getNumRegistersForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getNumRegistersForCallingConv	(	LLVMContext &	Context,
		CallingConv::ID	CC,
		EVT	VT
	)		const

inlinevirtual

Certain targets require unusual breakdowns of certain types.

For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.

Reimplemented in llvm::SITargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, llvm::SPIRVTargetLowering, and llvm::X86TargetLowering.

Definition at line 1615 of file TargetLowering.h.

References Context, and getNumRegisters().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::CallLowering::determineAssignments(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::CallLowering::getReturnInfo(), llvm::GetReturnInfo(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::AArch64CallLowering::lowerReturn(), and llvm::RegsForValue::RegsForValue().

◆ getOperationAction()

LegalizeAction llvm::TargetLoweringBase::getOperationAction	(	unsigned	Op,
		EVT	VT
	)		const

inline

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1113 of file TargetLowering.h.

References Custom, Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), and llvm::MVT::SimpleTy.

Referenced by getFixedPointOperationAction(), getStrictFPOperationAction(), getTypeToPromoteTo(), isLoadBitCastBeneficial(), isOperationCustom(), isOperationExpand(), isOperationLegal(), isOperationLegalOrCustom(), isOperationLegalOrCustomOrPromote(), isOperationLegalOrPromote(), llvm::ARMTTIImpl::maybeLoweredToCall(), and llvm::SystemZTargetLowering::SystemZTargetLowering().

◆ getOptimalMemOpLLT()

virtual LLT llvm::TargetLoweringBase::getOptimalMemOpLLT	(	const MemOp &	Op,
		const AttributeList &
	)		const

inlinevirtual

LLT returning variant.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1796 of file TargetLowering.h.

Referenced by findGISelOptimalMemOpLowering().

◆ getOptimalMemOpType()

virtual EVT llvm::TargetLoweringBase::getOptimalMemOpType	(	const MemOp &	Op,
		const AttributeList &
	)		const

inlinevirtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 1789 of file TargetLowering.h.

References llvm::MVT::Other.

Referenced by llvm::TargetLowering::findOptimalMemOpLowering().

◆ getPointerMemTy()

virtual MVT llvm::TargetLoweringBase::getPointerMemTy	(	const DataLayout &	DL,
		uint32_t	AS = `0`
	)		const

inlinevirtual

Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.

FIXME: The default needs to be removed once all the code is updated.

Reimplemented in llvm::WebAssemblyTargetLowering.

Definition at line 364 of file TargetLowering.h.

References DL, and llvm::MVT::getIntegerVT().

Referenced by getLoadStackGuard(), getMemValueType(), llvm::WebAssemblyTargetLowering::getPointerMemTy(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getPointerTy()

virtual MVT llvm::TargetLoweringBase::getPointerTy	(	const DataLayout &	DL,
		uint32_t	AS = `0`
	)		const

inlinevirtual

Return the pointer type for the given address space, defaults to the pointer type from the data layout.

FIXME: The default needs to be removed once all the code is updated.

Reimplemented in llvm::AArch64TargetLowering, and llvm::WebAssemblyTargetLowering.

Definition at line 357 of file TargetLowering.h.

References DL, and llvm::MVT::getIntegerVT().

◆ getPreferredShiftAmountTy()

virtual LLVM_READONLY LLT llvm::TargetLoweringBase::getPreferredShiftAmountTy ( LLT ShiftValueTy ) const

inlinevirtual

Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.

Reimplemented in llvm::SITargetLowering.

Definition at line 404 of file TargetLowering.h.

Referenced by llvm::CombinerHelper::applyUMulHToLShr(), llvm::CombinerHelper::buildSDivUsingMul(), llvm::CombinerHelper::buildUDivUsingMul(), llvm::CombinerHelper::matchBitfieldExtractFromAnd(), llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg(), llvm::CombinerHelper::matchBitfieldExtractFromShr(), llvm::CombinerHelper::matchBitfieldExtractFromShrAnd(), llvm::CombinerHelper::matchCombineShlOfExtend(), and llvm::CombinerHelper::matchUMulHToLShr().

◆ getPreferredSwitchConditionType()

MVT TargetLoweringBase::getPreferredSwitchConditionType	(	LLVMContext &	Context,
		EVT	ConditionVT
	)		const

virtual

Returns preferred type for switch condition.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1661 of file TargetLoweringBase.cpp.

References Context, and getRegisterType().

Referenced by llvm::X86TargetLowering::getPreferredSwitchConditionType().

◆ getPreferredVectorAction()

virtual TargetLoweringBase::LegalizeTypeAction llvm::TargetLoweringBase::getPreferredVectorAction ( MVT VT ) const

inlinevirtual

Return the preferred vector type legalization action.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 465 of file TargetLowering.h.

References llvm::MVT::getVectorElementCount(), llvm::MVT::isPow2VectorType(), llvm::ElementCount::isScalar(), TypePromoteInteger, TypeScalarizeVector, and TypeWidenVector.

Referenced by computeRegisterProperties(), llvm::AArch64TargetLowering::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), and llvm::X86TargetLowering::getPreferredVectorAction().

◆ getPrefFunctionAlignment()

Align llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const

inline

Return the preferred function alignment.

Definition at line 1855 of file TargetLowering.h.

◆ getPrefLoopAlignment()

Align TargetLoweringBase::getPrefLoopAlignment ( MachineLoop * ML = nullptr ) const

virtual

Return the preferred loop alignment.

Reimplemented in llvm::SITargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 2019 of file TargetLoweringBase.cpp.

References llvm::TargetOptions::LoopAlignment, and llvm::TargetMachine::Options.

Referenced by llvm::SITargetLowering::getPrefLoopAlignment(), llvm::PPCTargetLowering::getPrefLoopAlignment(), and llvm::X86TargetLowering::getPrefLoopAlignment().

◆ getProgramPointerTy()

MVT llvm::TargetLoweringBase::getProgramPointerTy ( const DataLayout & DL ) const

inline

Return the type for code pointers, which is determined by the program address space specified through the data layout.

Definition at line 376 of file TargetLowering.h.

References DL, and getPointerTy().

◆ getRecipEstimateDivEnabled()

int TargetLoweringBase::getRecipEstimateDivEnabled	(	EVT	VT,
		MachineFunction &	MF
	)		const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2201 of file TargetLoweringBase.cpp.

References getOpEnabled(), and getRecipEstimateForFunc().

◆ getRecipEstimateSqrtEnabled()

int TargetLoweringBase::getRecipEstimateSqrtEnabled	(	EVT	VT,
		MachineFunction &	MF
	)		const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2196 of file TargetLoweringBase.cpp.

References getOpEnabled(), and getRecipEstimateForFunc().

◆ getRegClassFor()

virtual const TargetRegisterClass * llvm::TargetLoweringBase::getRegClassFor	(	MVT	VT,
		bool	isDivergent = `false`
	)		const

inlinevirtual

Return the register class that should be used for the specified value type.

Reimplemented in llvm::SITargetLowering, and llvm::ARMTargetLowering.

Definition at line 885 of file TargetLowering.h.

References assert(), and llvm::MVT::SimpleTy.

Referenced by allocateRVVReg(), llvm::CCState::analyzeMustTailForwardedRegisters(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), llvm::FunctionLoweringInfo::CreateReg(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), llvm::SITargetLowering::getRegClassFor(), llvm::ARMTargetLowering::getRegClassFor(), llvm::GenericScheduler::initPolicy(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::SwiftErrorValueTracking::propagateVRegs(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::FastISel::selectFreeze(), llvm::FastISel::selectPatchpoint(), unpackFromRegLoc(), and llvm::X86TargetLowering::X86TargetLowering().

◆ getRegisterType() [1/2]

MVT llvm::TargetLoweringBase::getRegisterType	(	LLVMContext &	Context,
		EVT	VT
	)		const

inline

Return the type of registers that this ValueType will eventually require.

Definition at line 1551 of file TargetLowering.h.

References assert(), Context, getRegisterType(), llvm::EVT::getSimpleVT(), getTypeToTransformTo(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

◆ getRegisterType() [2/2]

MVT llvm::TargetLoweringBase::getRegisterType ( MVT VT ) const

inline

Return the type of registers that this ValueType will eventually require.

Definition at line 1545 of file TargetLowering.h.

References assert(), and llvm::MVT::SimpleTy.

Referenced by llvm::computeLegalValueVTs(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getNumRegisters(), getPreferredSwitchConditionType(), getRegisterType(), getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::GetReturnInfo(), llvm::TargetLowering::getTypeForExtReturn(), llvm::MipsTargetLowering::getTypeForExtReturn(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), llvm::FastISel::lowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::RegsForValue::RegsForValue(), and shouldTransformMulToShiftsAddsSubs().

◆ getRegisterTypeForCallingConv()

virtual MVT llvm::TargetLoweringBase::getRegisterTypeForCallingConv	(	LLVMContext &	Context,
		CallingConv::ID	CC,
		EVT	VT
	)		const

inlinevirtual

Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.

For MIPS all vector types must be passed through the integer register set.

Reimplemented in llvm::SITargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, llvm::SPIRVTargetLowering, and llvm::X86TargetLowering.

Definition at line 1607 of file TargetLowering.h.

References Context, and getRegisterType().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::CallLowering::determineAssignments(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::CallLowering::getReturnInfo(), llvm::GetReturnInfo(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::AArch64CallLowering::lowerReturn(), and llvm::RegsForValue::RegsForValue().

◆ getRepRegClassCostFor()

virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT VT ) const

inlinevirtual

Return the cost of the 'representative' register class for the specified value type.

Definition at line 914 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef().

◆ getRepRegClassFor()

virtual const TargetRegisterClass * llvm::TargetLoweringBase::getRepRegClassFor ( MVT VT ) const

inlinevirtual

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 907 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef(), and llvm::MipsSETargetLowering::getRepRegClassFor().

◆ getSafeStackPointerLocation()

Value * TargetLoweringBase::getSafeStackPointerLocation ( IRBuilderBase & IRB ) const

virtual

Returns the target-specific address of the unsafe stack pointer.

Reimplemented in llvm::AArch64TargetLowering, and llvm::X86TargetLowering.

Definition at line 1897 of file TargetLoweringBase.cpp.

References llvm::IRBuilderBase::CreateCall(), getDefaultSafeStackPointerLocation(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), llvm::Type::getPointerTo(), llvm::TargetMachine::getTargetTriple(), and llvm::Triple::isAndroid().

Referenced by llvm::AArch64TargetLowering::getSafeStackPointerLocation(), and llvm::X86TargetLowering::getSafeStackPointerLocation().

◆ getScalarShiftAmountTy()

MVT TargetLoweringBase::getScalarShiftAmountTy	(	const DataLayout &	DL,
		EVT
	)		const

virtual

Return the type to use for a scalar shift opcode, given the shifted amount type.

Targets should return a legal type if the input type is legal. Targets can return a type that is too small if the input type is illegal.

Reimplemented in llvm::AVRTargetLowering, llvm::X86TargetLowering, llvm::SITargetLowering, llvm::BPFTargetLowering, llvm::M68kTargetLowering, llvm::MipsTargetLowering, llvm::MSP430TargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::AArch64TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 912 of file TargetLoweringBase.cpp.

References DL, and llvm::MVT::getIntegerVT().

Referenced by getShiftAmountTy().

◆ getSchedulingPreference() [1/2]

Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const

inline

Return target scheduling preference.

Definition at line 872 of file TargetLowering.h.

Referenced by llvm::createDefaultScheduler(), llvm::PPCTargetLowering::getSchedulingPreference(), and llvm::ScheduleDAGSDNodes::newSUnit().

◆ getSchedulingPreference() [2/2]

virtual Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( SDNode * ) const

inlinevirtual

Some scheduler, e.g.

hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented in llvm::ARMTargetLowering, and llvm::PPCTargetLowering.

Definition at line 879 of file TargetLowering.h.

References llvm::Sched::None.

◆ getSDagStackGuard()

Value * TargetLoweringBase::getSDagStackGuard ( const Module & M ) const

virtual

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.

Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 1987 of file TargetLoweringBase.cpp.

Referenced by getLoadStackGuard(), llvm::AArch64TargetLowering::getSDagStackGuard(), llvm::ARMTargetLowering::getSDagStackGuard(), llvm::PPCTargetLowering::getSDagStackGuard(), llvm::X86TargetLowering::getSDagStackGuard(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getSetCCResultType()

EVT TargetLoweringBase::getSetCCResultType	(	const DataLayout &	DL,
		LLVMContext &	Context,
		EVT	VT
	)		const

virtual

Return the ValueType of the result of SETCC operations.

Reimplemented in llvm::HexagonTargetLowering, llvm::R600TargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::BPFTargetLowering, llvm::CSKYTargetLowering, llvm::LoongArchTargetLowering, llvm::M68kTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::NVPTXTargetLowering.

Definition at line 1531 of file TargetLoweringBase.cpp.

References assert(), DL, getPointerTy(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.

◆ getShiftAmountTy()

EVT TargetLoweringBase::getShiftAmountTy	(	EVT	LHSTy,
		const DataLayout &	DL,
		bool	LegalTypes = `true`
	)		const

Returns the type for the shift amount of a shift opcode.

For vectors, returns the input type. For scalars, behavior depends on LegalTypes. If LegalTypes is true, calls getScalarShiftAmountTy, otherwise uses pointer type. If getScalarShiftAmountTy or pointer type cannot represent all possible shift amounts, returns MVT::i32. In general, LegalTypes should be set to true for calls during type legalization and after type legalization has been completed.

Definition at line 917 of file TargetLoweringBase.cpp.

References assert(), DL, getPointerTy(), getScalarShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::EVT::isVector(), and llvm::Log2_32_Ceil().

◆ getSimpleValueType()

MVT llvm::TargetLoweringBase::getSimpleValueType	(	const DataLayout &	DL,
		Type *	Ty,
		bool	AllowUnknown = `false`
	)		const

inline

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 1534 of file TargetLowering.h.

References DL, llvm::EVT::getSimpleVT(), and getValueType().

Referenced by llvm::InlineAsmLowering::lowerInlineAsm(), and llvm::TargetLowering::ParseConstraints().

◆ getSqrtRefinementSteps()

int TargetLoweringBase::getSqrtRefinementSteps	(	EVT	VT,
		MachineFunction &	MF
	)		const

Return the refinement step count for a square root of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2206 of file TargetLoweringBase.cpp.

References getOpRefinementSteps(), and getRecipEstimateForFunc().

◆ getSSPStackGuardCheck()

Function * TargetLoweringBase::getSSPStackGuardCheck ( const Module & M ) const

virtual

If the target has a standard stack protection check function that performs validation and error handling, returns the function.

Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 1991 of file TargetLoweringBase.cpp.

Referenced by llvm::AArch64TargetLowering::getSSPStackGuardCheck(), llvm::ARMTargetLowering::getSSPStackGuardCheck(), llvm::X86TargetLowering::getSSPStackGuardCheck(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getStackPointerRegisterToSaveRestore()

Register llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const

inline

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 1824 of file TargetLowering.h.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::calculateDbgEntityHistory(), TransferTracker::isEntryValueValue(), isRegOtherThanSPAndFP(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LegalizerHelper::lowerDynStackAlloc(), LiveDebugValues::MLocTracker::MLocTracker(), and llvm::FunctionLoweringInfo::set().

◆ getStackProbeSymbolName()

virtual StringRef llvm::TargetLoweringBase::getStackProbeSymbolName ( const MachineFunction & MF ) const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 1916 of file TargetLowering.h.

◆ getStoreMemOperandFlags()

MachineMemOperand::Flags TargetLoweringBase::getStoreMemOperandFlags	(	const StoreInst &	SI,
		const DataLayout &	DL
	)		const

Definition at line 2271 of file TargetLoweringBase.cpp.

References getTargetMMOFlags(), llvm::MachineMemOperand::MONonTemporal, llvm::MachineMemOperand::MOStore, llvm::MachineMemOperand::MOVolatile, and SI.

◆ getStrictFPOperationAction()

LegalizeAction llvm::TargetLoweringBase::getStrictFPOperationAction	(	unsigned	Op,
		EVT	VT
	)		const

inline

Definition at line 1163 of file TargetLowering.h.

References getOperationAction(), and llvm_unreachable.

◆ getTargetMachine()

const TargetMachine & llvm::TargetLoweringBase::getTargetMachine ( ) const

inline

Definition at line 350 of file TargetLowering.h.

◆ getTargetMMOFlags()

virtual MachineMemOperand::Flags llvm::TargetLoweringBase::getTargetMMOFlags ( const Instruction & I ) const

inlinevirtual

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.

The default implementation does nothing.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 424 of file TargetLowering.h.

References llvm::MachineMemOperand::MONone.

Referenced by getAtomicMemOperandFlags(), getLoadMemOperandFlags(), and getStoreMemOperandFlags().

◆ getTgtMemIntrinsic()

virtual bool llvm::TargetLoweringBase::getTgtMemIntrinsic	(	IntrinsicInfo &	,
		const CallInst &	,
		MachineFunction &	,
		unsigned
	)		const

inlinevirtual

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).

If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented in llvm::SITargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SPIRVTargetLowering, and llvm::X86TargetLowering.

Definition at line 1069 of file TargetLowering.h.

◆ getTruncStoreAction()

LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction	(	EVT	ValVT,
		EVT	MemVT
	)		const

inline

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1323 of file TargetLowering.h.

References assert(), Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::MVT::SimpleTy, and llvm::MVT::VALUETYPE_SIZE.

Referenced by isTruncStoreLegal(), and isTruncStoreLegalOrCustom().

◆ getTypeAction() [1/2]

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction	(	LLVMContext &	Context,
		EVT	VT
	)		const

inline

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').

'Custom' is not an option.

Definition at line 986 of file TargetLowering.h.

References Context, and getTypeConversion().

Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::X86TargetLowering::decomposeMulByConstant(), findMemType(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getCopyToPartsVector(), llvm::X86TargetLowering::getSetCCResultType(), getTypeToExpandTo(), getVectorTypeBreakdown(), LowerStore(), OptimizeNoopCopyExpression(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), shouldNormalizeToSelectSequence(), and widenAbs().

◆ getTypeAction() [2/2]

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT VT ) const

inline

Definition at line 989 of file TargetLowering.h.

References llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction().

◆ getTypeConversion()

TargetLoweringBase::LegalizeKind TargetLoweringBase::getTypeConversion	(	LLVMContext &	Context,
		EVT	VT
	)		const

Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it.

First: how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Second: for types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 958 of file TargetLoweringBase.cpp.

References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::coefficientNextPowerOf2(), Context, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::EVT::getIntegerVT(), llvm::EVT::getPow2VectorType(), llvm::EVT::getRoundIntegerType(), llvm::ElementCount::getScalable(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), getTypeConversion(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::EVT::isInteger(), llvm::EVT::isPow2VectorType(), llvm::isPowerOf2_32(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::ElementCount::isScalar(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm::MVT::SimpleTy, TypeExpandInteger, TypeLegal, TypePromoteInteger, TypeScalarizeScalableVector, TypeScalarizeVector, TypeSoftenFloat, TypeSoftPromoteHalf, TypeSplitVector, and TypeWidenVector.

Referenced by getTypeAction(), getTypeConversion(), llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(), getTypeToTransformTo(), and getVectorTypeBreakdown().

◆ getTypeToExpandTo()

EVT llvm::TargetLoweringBase::getTypeToExpandTo	(	LLVMContext &	Context,
		EVT	VT
	)		const

inline

For types supported by the target, this is an identity function.

For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 1007 of file TargetLowering.h.

References assert(), Context, getTypeAction(), getTypeToTransformTo(), llvm::EVT::isVector(), llvm_unreachable, TypeExpandInteger, and TypeLegal.

◆ getTypeToPromoteTo()

MVT llvm::TargetLoweringBase::getTypeToPromoteTo	(	unsigned	Op,
		MVT	VT
	)		const

inline

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 1462 of file TargetLowering.h.

References assert(), getOperationAction(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::isVoid, Promote, and llvm::MVT::SimpleTy.

Referenced by isLoadBitCastBeneficial().

◆ getTypeToTransformTo()

virtual EVT llvm::TargetLoweringBase::getTypeToTransformTo	(	LLVMContext &	Context,
		EVT	VT
	)		const

inlinevirtual

For types supported by the target, this is an identity function.

For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Reimplemented in llvm::X86TargetLowering.

Definition at line 999 of file TargetLowering.h.

References Context, and getTypeConversion().

Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineMinNumMaxNumImpl(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getConstant(), getMemcpyLoadsAndStores(), getPTest(), llvm::FastISel::getRegForValue(), getRegisterType(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::BasicTTIImplBase< T >::getStoreMinimumVF(), getTypeToExpandTo(), llvm::X86TargetLowering::getTypeToTransformTo(), getVectorTypeBreakdown(), LowerMSCATTER(), LowerStore(), llvm::VETargetLowering::lowerToVVP(), OptimizeNoopCopyExpression(), llvm::FastISel::selectBinaryOp(), and widenAbs().

◆ getVaListSizeInBits()

virtual unsigned llvm::TargetLoweringBase::getVaListSizeInBits ( const DataLayout & DL ) const

inlinevirtual

Returns the size of the platform's va_list object.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1664 of file TargetLowering.h.

References DL, getPointerTy(), and llvm::MVT::getSizeInBits().

◆ getValueType()

EVT llvm::TargetLoweringBase::getValueType	(	const DataLayout &	DL,
		Type *	Ty,
		bool	AllowUnknown = `false`
	)		const

inline

Return the EVT corresponding to this LLVM type.

This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 1494 of file TargetLowering.h.

References DL, llvm::Type::getContext(), llvm::EVT::getEVT(), getPointerTy(), and llvm::EVT::getVectorVT().

◆ getValueTypeActions()

const ValueTypeActionImpl & llvm::TargetLoweringBase::getValueTypeActions ( ) const

inline

Definition at line 962 of file TargetLowering.h.

◆ getVectorIdxTy()

virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( const DataLayout & DL ) const

inlinevirtual

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::SPIRVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 411 of file TargetLowering.h.

References DL, and getPointerTy().

Referenced by llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::SparcTargetLowering::LowerCall_32(), and llvm::SparcTargetLowering::LowerReturn_32().

◆ getVectorTypeBreakdown()

unsigned TargetLoweringBase::getVectorTypeBreakdown	(	LLVMContext &	Context,
		EVT	VT,
		EVT &	IntermediateVT,
		unsigned &	NumIntermediates,
		MVT &	RegisterVT
	)		const

Vector types are broken down into some number of legal first class types.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.

For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1549 of file TargetLoweringBase.cpp.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::coefficientNextPowerOf2(), Context, llvm::divideCeil(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::ElementCount::getFixed(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeConversion(), getTypeToTransformTo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::ElementCount::isScalar(), isTypeLegal(), llvm::EVT::isVector(), llvm::report_fatal_error(), TypeLegal, TypePromoteInteger, and TypeWidenVector.

Referenced by getCopyFromPartsVector(), getCopyToPartsVector(), getNumRegisters(), llvm::SelectionDAG::getReducedAlign(), getRegisterType(), and getVectorTypeBreakdownForCallingConv().

◆ getVectorTypeBreakdownForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getVectorTypeBreakdownForCallingConv	(	LLVMContext &	Context,
		CallingConv::ID	CC,
		EVT	VT,
		EVT &	IntermediateVT,
		unsigned &	NumIntermediates,
		MVT &	RegisterVT
	)		const

inlinevirtual

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.

This occurs even if the vector type is legal.

Reimplemented in llvm::SITargetLowering, llvm::MipsTargetLowering, and llvm::X86TargetLowering.

Definition at line 1038 of file TargetLowering.h.

References Context, and getVectorTypeBreakdown().

Referenced by getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), and llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv().

◆ getVPExplicitVectorLengthTy()

virtual MVT llvm::TargetLoweringBase::getVPExplicitVectorLengthTy ( ) const

inlinevirtual

Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.

It must be a legal scalar integer type, and must be at least as large as i32. The EVL is implicitly zero-extended to any larger type.

Definition at line 419 of file TargetLowering.h.

References llvm::MVT::i32.

◆ hasAndNot()

virtual bool llvm::TargetLoweringBase::hasAndNot ( SDValue X ) const

inlinevirtual

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.

Reimplemented in llvm::AArch64TargetLowering, llvm::LoongArchTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 706 of file TargetLowering.h.

References hasAndNotCompare(), and X.

Referenced by foldVSelectToSignBitSplatMask().

◆ hasAndNotCompare()

virtual bool llvm::TargetLoweringBase::hasAndNotCompare ( SDValue Y ) const

inlinevirtual

Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.

This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.

Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0

Reimplemented in llvm::AArch64TargetLowering, llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 699 of file TargetLowering.h.

Referenced by hasAndNot().

◆ hasBigEndianPartOrdering()

bool llvm::TargetLoweringBase::hasBigEndianPartOrdering	(	EVT	VT,
		const DataLayout &	DL
	)		const

inline

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 1648 of file TargetLowering.h.

References DL, and llvm::MVT::ppcf128.

Referenced by getCopyFromParts(), and llvm::CallLowering::handleAssignments().

◆ hasBitPreservingFPLogic()

virtual bool llvm::TargetLoweringBase::hasBitPreservingFPLogic ( EVT VT ) const

inlinevirtual

Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.

This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 645 of file TargetLowering.h.

Referenced by foldBitcastedFPLogic().

◆ hasBitTest()

virtual bool llvm::TargetLoweringBase::hasBitTest	(	SDValue	X,
		SDValue	Y
	)		const

inlinevirtual

Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.

Reimplemented in llvm::HexagonTargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 716 of file TargetLowering.h.

Referenced by combineShiftAnd1ToBitTest(), and shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().

◆ hasExtractBitsInsn()

bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const

inline

Return true if the target has BitExtract instructions.

Definition at line 461 of file TargetLowering.h.

◆ hasFastEqualityCompare()

virtual MVT llvm::TargetLoweringBase::hasFastEqualityCompare ( unsigned NumBits ) const

inlinevirtual

Return the preferred operand type if the target has a quick way to compare integer values of the given size.

Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.

Reimplemented in llvm::X86TargetLowering.

Definition at line 682 of file TargetLowering.h.

References llvm::MVT::getIntegerVT(), llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, and isTypeLegal().

◆ hasInlineStackProbe()

virtual bool llvm::TargetLoweringBase::hasInlineStackProbe ( const MachineFunction & MF ) const

inlinevirtual

Reimplemented in llvm::PPCTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 1914 of file TargetLowering.h.

Referenced by llvm::SystemZELFFrameLowering::emitPrologue().

◆ hasMultipleConditionRegisters()

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const

inline

Return true if multiple condition registers are available.

Definition at line 456 of file TargetLowering.h.

Referenced by shouldNormalizeToSelectSequence(), and sinkCmpExpression().

◆ hasPairedLoad()

virtual bool llvm::TargetLoweringBase::hasPairedLoad	(	EVT	,
		Align &
	)		const

inlinevirtual

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.

RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2884 of file TargetLowering.h.

◆ hasStackProbeSymbol()

virtual bool llvm::TargetLoweringBase::hasStackProbeSymbol ( const MachineFunction & MF ) const

inlinevirtual

Returns the name of the symbol used to emit stack probes or the empty string if not applicable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1912 of file TargetLowering.h.

◆ hasStandaloneRem()

virtual bool llvm::TargetLoweringBase::hasStandaloneRem ( EVT VT ) const

inlinevirtual

Return true if the target can handle a standalone remainder operation.

Reimplemented in llvm::ARMTargetLowering, and llvm::VETargetLowering.

Definition at line 504 of file TargetLowering.h.

◆ hasTargetDAGCombine()

bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType NT ) const

inline

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 1654 of file TargetLowering.h.

References assert().

◆ hasVectorBlend()

virtual bool llvm::TargetLoweringBase::hasVectorBlend ( ) const

inlinevirtual

Return true if the target has a vector blend instruction.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2890 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::getVectorShuffle().

◆ initActions()

void TargetLoweringBase::initActions ( )

protected

Initialize all of the actions to default values.

Definition at line 740 of file TargetLoweringBase.cpp.

Referenced by TargetLoweringBase().

◆ insertSSPDeclarations()

void TargetLoweringBase::insertSSPDeclarations ( Module & M ) const

virtual

Inserts necessary declarations for SSP (stack protection) purpose.

Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 1971 of file TargetLoweringBase.cpp.

References llvm::GlobalValue::ExternalLinkage, llvm::Type::getInt8PtrTy(), llvm::TargetMachine::getRelocationModel(), llvm::TargetMachine::getTargetTriple(), llvm::Triple::isOSFreeBSD(), llvm::Triple::isWindowsGNUEnvironment(), and llvm::Reloc::Static.

Referenced by getStackGuard(), llvm::AArch64TargetLowering::insertSSPDeclarations(), llvm::ARMTargetLowering::insertSSPDeclarations(), llvm::PPCTargetLowering::insertSSPDeclarations(), llvm::SparcTargetLowering::insertSSPDeclarations(), and llvm::X86TargetLowering::insertSSPDeclarations().

◆ InstructionOpcodeToISD()

int TargetLoweringBase::InstructionOpcodeToISD ( unsigned Opcode ) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1784 of file TargetLoweringBase.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::FAdd, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::FMul, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREEZE, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, llvm::Mul, llvm::ISD::MUL, llvm::Or, llvm::ISD::OR, PHI, llvm::ISD::SDIV, llvm::ISD::SELECT, Select, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, llvm::Xor, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::PPCTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getArithmeticReductionCostSVE(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::PPCTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< T >::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), llvm::PPCTTIImpl::getVectorInstrCost(), llvm::X86TTIImpl::getVectorInstrCost(), isPromotedInstructionLegal(), llvm::ARMTTIImpl::maybeLoweredToCall(), SinkShiftAndTruncate(), and llvm::PPCTTIImpl::vectorCostAdjustmentFactor().

◆ isBeneficialToExpandPowI()

bool llvm::TargetLoweringBase::isBeneficialToExpandPowI	(	int	Exponent,
		bool	OptForSize
	)		const

inline

Return true if it is beneficial to expand an @llvm.powi.

intrinsic. If not optimizing for size, expanding @llvm.powi.* intrinsics is always considered beneficial. If optimizing for size, expansion is only considered beneficial for upto 5 multiplies and a divide (if the exponent is negative).

Definition at line 2273 of file TargetLowering.h.

References llvm::Exponent, llvm::Log2_32(), and llvm::popcount().

Referenced by ExpandPowI(), and llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().

◆ isBinOp()

virtual bool llvm::TargetLoweringBase::isBinOp ( unsigned Opcode ) const

inlinevirtual

Return true if the node is a math/logic binary operator.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2705 of file TargetLowering.h.

References llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::FSUB, isCommutativeBinOp(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UDIV, llvm::ISD::UREM, and llvm::ISD::USUBSAT.

Referenced by canonicalizeShuffleWithBinOps(), getKnownUndefForVectorBinop(), llvm::X86TargetLowering::isBinOp(), narrowExtractedVectorBinOp(), narrowInsertExtractVectorBinOp(), and scalarizeExtractedBinop().

◆ isCheapToSpeculateCtlz()

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCtlz ( Type * Ty ) const

inlinevirtual

Return true if it is cheap to speculate a call to intrinsic ctlz.

Reimplemented in llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 618 of file TargetLowering.h.

Referenced by despeculateCountZeros(), and llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().

◆ isCheapToSpeculateCttz()

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCttz ( Type * Ty ) const

inlinevirtual

Return true if it is cheap to speculate a call to intrinsic cttz.

Reimplemented in llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 613 of file TargetLowering.h.

Referenced by despeculateCountZeros(), and llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().

◆ isCommutativeBinOp()

virtual bool llvm::TargetLoweringBase::isCommutativeBinOp ( unsigned Opcode ) const

inlinevirtual

Returns true if the opcode is a commutative binary operation.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2663 of file TargetLowering.h.

References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::FADD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, and llvm::ISD::XOR.

Referenced by llvm::SelectionDAG::canonicalizeCommutativeBinop(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getNode(), isBinOp(), llvm::X86TargetLowering::isCommutativeBinOp(), and llvm::TargetLowering::SimplifySetCC().

◆ isComplexDeinterleavingOperationSupported()

virtual bool llvm::TargetLoweringBase::isComplexDeinterleavingOperationSupported	(	ComplexDeinterleavingOperation	Operation,
		Type *	Ty
	)		const

inlinevirtual

Does this target support complex deinterleaving with the given operation and type.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3145 of file TargetLowering.h.

◆ isComplexDeinterleavingSupported()

virtual bool llvm::TargetLoweringBase::isComplexDeinterleavingSupported ( ) const

inlinevirtual

Does this target support complex deinterleaving.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3141 of file TargetLowering.h.

◆ isCondCodeLegal()

bool llvm::TargetLoweringBase::isCondCodeLegal	(	ISD::CondCode	CC,
		MVT	VT
	)		const

inline

Return true if the specified condition code is legal on this target.

Definition at line 1449 of file TargetLowering.h.

References CC, getCondCodeAction(), and Legal.

Referenced by llvm::SelectionDAG::FoldSetCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), llvm::R600TargetLowering::PerformDAGCombine(), and llvm::TargetLowering::SimplifySetCC().

◆ isCondCodeLegalOrCustom()

bool llvm::TargetLoweringBase::isCondCodeLegalOrCustom	(	ISD::CondCode	CC,
		MVT	VT
	)		const

inline

Return true if the specified condition code is legal or custom on this target.

Definition at line 1455 of file TargetLowering.h.

References CC, Custom, getCondCodeAction(), and Legal.

Referenced by llvm::TargetLowering::LegalizeSetCCCondCode().

◆ isConstantUnsignedBitfieldExtractLegal()

virtual bool llvm::TargetLoweringBase::isConstantUnsignedBitfieldExtractLegal	(	unsigned	Opc,
		LLT	Ty1,
		LLT	Ty2
	)		const

inlinevirtual

Returns: true if a constant G_UBFX is legal on the target.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1897 of file TargetLowering.h.

◆ isCtlzFast()

virtual bool llvm::TargetLoweringBase::isCtlzFast ( ) const

inlinevirtual

Return true if ctlz instruction is fast.

Reimplemented in llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 623 of file TargetLowering.h.

Referenced by llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl().

◆ isEqualityCmpFoldedWithSignedCmp()

virtual bool llvm::TargetLoweringBase::isEqualityCmpFoldedWithSignedCmp ( ) const

inlinevirtual

Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 635 of file TargetLowering.h.

Referenced by foldICmpWithDominatingICmp().

◆ isExtFree()

bool llvm::TargetLoweringBase::isExtFree ( const Instruction * I ) const

inline

Return true if the extension represented by I is free.

Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by I to decide whether or not I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.

Precondition: I must be a sign, zero, or fp extension.

Definition at line 2767 of file TargetLowering.h.

References llvm::EVT::getEVT(), I, isExtFreeImpl(), isFPExtFree(), isZExtFree(), and llvm_unreachable.

◆ isExtFreeImpl()

virtual bool llvm::TargetLoweringBase::isExtFreeImpl ( const Instruction * I ) const

inlineprotectedvirtual

Return true if the extension represented by I is free.

Precondition: I is a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.

Definition at line 3415 of file TargetLowering.h.

Referenced by isExtFree().

◆ isExtLoad()

bool llvm::TargetLoweringBase::isExtLoad	(	const LoadInst *	Load,
		const Instruction *	Ext,
		const DataLayout &	DL
	)		const

inline

Return true if Load and Ext can form an ExtLoad.

For example, in AArch64 L = load i8, i8* ptr E = zext i8 L to i32 can be lowered into one load instruction ldrb w0, [x0]

Definition at line 2792 of file TargetLowering.h.

References assert(), DL, getValueType(), isLoadExtLegal(), isTruncateFree(), isTypeLegal(), llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.

◆ isExtractSubvectorCheap()

virtual bool llvm::TargetLoweringBase::isExtractSubvectorCheap	(	EVT	ResVT,
		EVT	SrcVT,
		unsigned	Index
	)		const

inlinevirtual

Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.

This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3073 of file TargetLowering.h.

Referenced by foldExtractSubvectorFromShuffleVector(), llvm::SelectionDAG::matchBinOpReduction(), and narrowExtractedVectorBinOp().

◆ isExtractVecEltCheap()

virtual bool llvm::TargetLoweringBase::isExtractVecEltCheap	(	EVT	VT,
		unsigned	Index
	)		const

inlinevirtual

Return true if extraction of a scalar element from the given vector type at the given index is cheap.

For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3088 of file TargetLowering.h.

Referenced by scalarizeBinOpOfSplats().

◆ isFAbsFree()

virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT VT ) const

inlinevirtual

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 2968 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost().

◆ isFMADLegal() [1/2]

virtual bool llvm::TargetLoweringBase::isFMADLegal	(	const MachineInstr &	MI,
		LLT	Ty
	)		const

inlinevirtual

Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD.

N may be an TargetOpcode::G_FADD, TargetOpcode::G_FSUB, or an TargetOpcode::G_FMUL which will be distributed into an fadd/fsub.

Reimplemented in llvm::SITargetLowering.

Definition at line 3008 of file TargetLowering.h.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::LLT::getScalarSizeInBits(), isOperationLegal(), and MI.

◆ isFMADLegal() [2/2]

virtual bool llvm::TargetLoweringBase::isFMADLegal	(	const SelectionDAG &	DAG,
		const SDNode *	N
	)		const

inlinevirtual

Returns true if be combined with to form an ISD::FMAD.

N may be an ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an fadd/fsub.

Reimplemented in llvm::SITargetLowering.

Definition at line 3030 of file TargetLowering.h.

References assert(), llvm::ISD::FADD, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FSUB, isOperationLegal(), and N.

◆ isFMAFasterThanFMulAndFAdd() [1/3]

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd	(	const Function &	F,
		Type *
	)		const

inlinevirtual

IR version.

Reimplemented in llvm::AArch64TargetLowering, and llvm::PPCTargetLowering.

Definition at line 3000 of file TargetLowering.h.

◆ isFMAFasterThanFMulAndFAdd() [2/3]

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd	(	const MachineFunction &	MF,
		EVT
	)		const

inlinevirtual

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented in llvm::HexagonTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::NVPTXTargetLowering, and llvm::SPIRVTargetLowering.

Definition at line 2981 of file TargetLowering.h.

◆ isFMAFasterThanFMulAndFAdd() [3/3]

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd	(	const MachineFunction &	MF,
		LLT
	)		const

inlinevirtual

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented in llvm::SITargetLowering.

Definition at line 2994 of file TargetLowering.h.

◆ isFNegFree()

virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT VT ) const

inlinevirtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::ARMTargetLowering.

Definition at line 2961 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

◆ isFPExtFoldable() [1/2]

virtual bool llvm::TargetLoweringBase::isFPExtFoldable	(	const MachineInstr &	MI,
		unsigned	Opcode,
		LLT	DestTy,
		LLT	SrcTy
	)		const

inlinevirtual

Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

Reimplemented in llvm::SITargetLowering.

Definition at line 2940 of file TargetLowering.h.

◆ isFPExtFoldable() [2/2]

virtual bool llvm::TargetLoweringBase::isFPExtFoldable	(	const SelectionDAG &	DAG,
		unsigned	Opcode,
		EVT	DestVT,
		EVT	SrcVT
	)		const

inlinevirtual

Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

Reimplemented in llvm::SITargetLowering.

Definition at line 2948 of file TargetLowering.h.

References assert(), llvm::EVT::isFloatingPoint(), and isFPExtFree().

◆ isFPExtFree()

virtual bool llvm::TargetLoweringBase::isFPExtFree	(	EVT	DestVT,
		EVT	SrcVT
	)		const

inlinevirtual

Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

Reimplemented in llvm::PPCTargetLowering.

Definition at line 2931 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by llvm::TargetLowering::getNegatedExpression(), isExtFree(), and isFPExtFoldable().

◆ isFPImmLegal()

virtual bool llvm::TargetLoweringBase::isFPImmLegal	(	const APFloat &	,
		EVT	,
		bool	ForCodeSize = `false`
	)		const

inlinevirtual

Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented in llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 1078 of file TargetLowering.h.

Referenced by llvm::TargetLowering::getNegatedExpression().

◆ isFreeAddrSpaceCast()

bool TargetLoweringBase::isFreeAddrSpaceCast	(	unsigned	SrcAS,
		unsigned	DestAS
	)		const

virtual

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

we are happy to sink it into basic blocks. A cast may be free, but not necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.

Reimplemented in llvm::SITargetLowering.

Definition at line 946 of file TargetLoweringBase.cpp.

References llvm::TargetMachine::isNoopAddrSpaceCast().

Referenced by llvm::BasicTTIImplBase< T >::getCastInstrCost(), and OptimizeNoopCopyExpression().

◆ isFsqrtCheap()

virtual bool llvm::TargetLoweringBase::isFsqrtCheap	(	SDValue	X,
		SelectionDAG &	DAG
	)		const

inlinevirtual

Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 509 of file TargetLowering.h.

◆ isIndexedLoadLegal()

bool llvm::TargetLoweringBase::isIndexedLoadLegal	(	unsigned	IdxMode,
		EVT	VT
	)		const

inline

Return true if the specified indexed load is legal on this target.

Definition at line 1362 of file TargetLowering.h.

References Custom, getIndexedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts(), and llvm::BasicTTIImplBase< T >::isIndexedLoadLegal().

◆ isIndexedMaskedLoadLegal()

bool llvm::TargetLoweringBase::isIndexedMaskedLoadLegal	(	unsigned	IdxMode,
		EVT	VT
	)		const

inline

Return true if the specified indexed load is legal on this target.

Definition at line 1390 of file TargetLowering.h.

References Custom, getIndexedMaskedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts().

◆ isIndexedMaskedStoreLegal()

bool llvm::TargetLoweringBase::isIndexedMaskedStoreLegal	(	unsigned	IdxMode,
		EVT	VT
	)		const

inline

Return true if the specified indexed load is legal on this target.

Definition at line 1404 of file TargetLowering.h.

References Custom, getIndexedMaskedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts().

◆ isIndexedStoreLegal()

bool llvm::TargetLoweringBase::isIndexedStoreLegal	(	unsigned	IdxMode,
		EVT	VT
	)		const

inline

Return true if the specified indexed load is legal on this target.

Definition at line 1376 of file TargetLowering.h.

References Custom, getIndexedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts(), and llvm::BasicTTIImplBase< T >::isIndexedStoreLegal().

◆ isIntDivCheap()

virtual bool llvm::TargetLoweringBase::isIntDivCheap	(	EVT	VT,
		AttributeList	Attr
	)		const

inlinevirtual

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

The definition of "cheaper" may depend on whether we're optimizing for speed or for size.

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::VETargetLowering.

Definition at line 501 of file TargetLowering.h.

Referenced by llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSREMPow2(), and llvm::TargetLowering::SimplifySetCC().

◆ isJumpExpensive()

bool llvm::TargetLoweringBase::isJumpExpensive ( ) const

inline

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 559 of file TargetLowering.h.

◆ isJumpTableRelative()

bool TargetLoweringBase::isJumpTableRelative ( ) const

virtual

Reimplemented in llvm::MipsTargetLowering, and llvm::PPCTargetLowering.

Definition at line 2015 of file TargetLoweringBase.cpp.

References getTargetMachine(), and llvm::TargetMachine::isPositionIndependent().

Referenced by llvm::VETargetLowering::getMinimumJumpTableEntries(), and llvm::PPCTargetLowering::isJumpTableRelative().

◆ isLegalAddImmediate()

virtual bool llvm::TargetLoweringBase::isLegalAddImmediate ( int64_t ) const

inlinevirtual

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2624 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< T >::isLegalAddImmediate(), and performAddCSelIntoCSinc().

◆ isLegalAddressingMode()

bool TargetLoweringBase::isLegalAddressingMode	(	const DataLayout &	DL,
		const AddrMode &	AM,
		Type *	Ty,
		unsigned	AddrSpace,
		Instruction *	I = `nullptr`
	)		const

virtual

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.

If the address space cannot be determined, it will be -1.

TODO: Remove default argument

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARCTargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 1916 of file TargetLoweringBase.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.

Referenced by canFoldInAddressingMode(), and llvm::BasicTTIImplBase< T >::isLegalAddressingMode().

◆ isLegalICmpImmediate()

virtual bool llvm::TargetLoweringBase::isLegalICmpImmediate ( int64_t ) const

inlinevirtual

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::MSP430TargetLowering.

Definition at line 2617 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< T >::isLegalICmpImmediate(), llvm::MSP430TargetLowering::isLegalICmpImmediate(), and llvm::TargetLowering::SimplifySetCC().

◆ isLegalRC()

bool TargetLoweringBase::isLegalRC	(	const TargetRegisterInfo &	TRI,
		const TargetRegisterClass &	RC
	)		const

protected

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 1154 of file TargetLoweringBase.cpp.

References I, isTypeLegal(), llvm::MVT::Other, and TRI.

Referenced by findRepresentativeClass(), and llvm::TargetLowering::getRegForInlineAsmConstraint().

◆ isLegalScaleForGatherScatter()

virtual bool llvm::TargetLoweringBase::isLegalScaleForGatherScatter	(	uint64_t	Scale,
		uint64_t	ElemSize
	)		const

inlinevirtual

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 1423 of file TargetLowering.h.

Referenced by getUniformBase().

◆ isLegalStoreImmediate()

virtual bool llvm::TargetLoweringBase::isLegalStoreImmediate ( int64_t Value ) const

inlinevirtual

Return true if the specified immediate is legal for the value input of a store instruction.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2630 of file TargetLowering.h.

Referenced by getMemsetValue().

◆ isLoadBitCastBeneficial()

bool TargetLoweringBase::isLoadBitCastBeneficial	(	EVT	LoadVT,
		EVT	BitcastVT,
		const SelectionDAG &	DAG,
		const MachineMemOperand &	MMO
	)		const

virtual

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 2216 of file TargetLoweringBase.cpp.

References allowsMemoryAccess(), llvm::CallingConv::Fast, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), getOperationAction(), llvm::EVT::getSimpleVT(), getTypeToPromoteTo(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isSimple(), llvm::ISD::LOAD, and Promote.

Referenced by llvm::X86TargetLowering::isLoadBitCastBeneficial(), and isStoreBitCastBeneficial().

◆ isLoadExtLegal()

bool llvm::TargetLoweringBase::isLoadExtLegal	(	unsigned	ExtType,
		EVT	ValVT,
		EVT	MemVT
	)		const

inline

Return true if the specified load with extension is legal on this target.

Definition at line 1309 of file TargetLowering.h.

References getLoadExtAction(), and Legal.

Referenced by combineEXTEND_VECTOR_INREG(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), isExtLoad(), tryToFoldExtendSelectLoad(), tryToFoldExtOfExtload(), and tryToFoldExtOfLoad().

◆ isLoadExtLegalOrCustom()

bool llvm::TargetLoweringBase::isLoadExtLegalOrCustom	(	unsigned	ExtType,
		EVT	ValVT,
		EVT	MemVT
	)		const

inline

Return true if the specified load with extension is legal or custom on this target.

Definition at line 1315 of file TargetLowering.h.

References Custom, getLoadExtAction(), and Legal.

Referenced by tryToFoldExtOfMaskedLoad().

◆ isMaskAndCmp0FoldingBeneficial()

virtual bool llvm::TargetLoweringBase::isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const

inlinevirtual

Return if the target supports combining a chain like:

%andResult = and %val1, #mask

%icmpResult = icmp %andResult, 0

into a single machine instruction of a form like:

cc = test %register, #mask

test

modulo schedule test

Definition: ModuloSchedule.cpp:2143

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 665 of file TargetLowering.h.

Referenced by sinkAndCmp0Expression().

◆ isMulAddWithConstProfitable()

virtual bool llvm::TargetLoweringBase::isMulAddWithConstProfitable	(	SDValue	AddNode,
		SDValue	ConstNode
	)		const

inlinevirtual

Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).

This may not be true if c1 and c2 can be represented as immediates but c1*c2 cannot, for example. The target should check if c1, c2 and c1*c2 can be represented as immediates, or have to be materialized into registers. If it is not sure about some cases, a default true can be returned to let the DAGCombiner decide. AddNode is (add x, c1), and ConstNode is c2.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2253 of file TargetLowering.h.

◆ isMultiStoresCheaperThanBitsMerge()

virtual bool llvm::TargetLoweringBase::isMultiStoresCheaperThanBitsMerge	(	EVT	LTy,
		EVT	HTy
	)		const

inlinevirtual

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 651 of file TargetLowering.h.

Referenced by splitMergedValStore().

◆ isNarrowingProfitable()

virtual bool llvm::TargetLoweringBase::isNarrowingProfitable	(	EVT	,
		EVT
	)		const

inlinevirtual

Return true if it's profitable to narrow operations of type VT1 to VT2.

e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::X86TargetLowering.

Definition at line 3047 of file TargetLowering.h.

◆ isOperationCustom()

bool llvm::TargetLoweringBase::isOperationCustom	(	unsigned	Op,
		EVT	VT
	)		const

inline

Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

Definition at line 1222 of file TargetLowering.h.

References Custom, and getOperationAction().

Referenced by llvm::RISCVTTIImpl::getIntrinsicInstrCost(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isOperationExpand()

bool llvm::TargetLoweringBase::isOperationExpand	(	unsigned	Op,
		EVT	VT
	)		const

inline

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.

This is used to help guide high-level lowering decisions.

Definition at line 1284 of file TargetLowering.h.

References Expand, getOperationAction(), and isTypeLegal().

Referenced by combineFMA(), llvm::TargetLowering::expandCTTZ(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::BasicTTIImplBase< T >::getCmpSelInstrCost(), llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(), shouldFormOverflowOp(), llvm::X86TargetLowering::shouldFormOverflowOp(), llvm::PPCTTIImpl::vectorCostAdjustmentFactor(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isOperationLegal()

bool llvm::TargetLoweringBase::isOperationLegal	(	unsigned	Op,
		EVT	VT
	)		const

inline

Return true if the specified operation is legal on this target.

Definition at line 1289 of file TargetLowering.h.

References getOperationAction(), isTypeLegal(), Legal, and llvm::MVT::Other.

◆ isOperationLegalOrCustom()

bool llvm::TargetLoweringBase::isOperationLegalOrCustom	(	unsigned	Op,
		EVT	VT,
		bool	LegalOnly = `false`
	)		const

inline

Return true if the specified operation is legal on this target or can be made legal with custom lowering.

This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.

Definition at line 1181 of file TargetLowering.h.

References Custom, getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, and llvm::MVT::Other.

◆ isOperationLegalOrCustomOrPromote()

bool llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote	(	unsigned	Op,
		EVT	VT,
		bool	LegalOnly = `false`
	)		const

inline

Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.

This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.

Definition at line 1209 of file TargetLowering.h.

References Custom, getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, llvm::MVT::Other, and Promote.

Referenced by canExpandVectorCTPOP(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< T >::getFPOpCost(), narrowExtractedVectorBinOp(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), and llvm::X86TargetLowering::shouldScalarizeBinop().

◆ isOperationLegalOrPromote()

bool llvm::TargetLoweringBase::isOperationLegalOrPromote	(	unsigned	Op,
		EVT	VT,
		bool	LegalOnly = `false`
	)		const

inline

Return true if the specified operation is legal on this target or can be made legal using promotion.

This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.

Definition at line 1195 of file TargetLowering.h.

References getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, llvm::MVT::Other, and Promote.

Referenced by llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(), lowerBuildVectorToBitOp(), and PromoteMaskArithmetic().

◆ isPredictableSelectExpensive()

bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const

inline

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 563 of file TargetLowering.h.

References PredictableSelectIsExpensive.

Referenced by isFormingBranchFromSelectProfitable().

◆ isProfitableToCombineMinNumMaxNum()

virtual bool llvm::TargetLoweringBase::isProfitableToCombineMinNumMaxNum ( EVT VT ) const

inlinevirtual

Definition at line 2225 of file TargetLowering.h.

Referenced by isLegalToCombineMinNumMaxNum().

◆ isProfitableToHoist()

virtual bool llvm::TargetLoweringBase::isProfitableToHoist ( Instruction * I ) const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering, and llvm::PPCTargetLowering.

Definition at line 2756 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< T >::isProfitableToHoist().

◆ isSafeMemOpType()

virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT ) const

inlinevirtual

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1808 of file TargetLowering.h.

Referenced by llvm::TargetLowering::findOptimalMemOpLowering().

◆ isSelectSupported()

virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind ) const

inlinevirtual

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 437 of file TargetLowering.h.

◆ isSExtCheaperThanZExt()

virtual bool llvm::TargetLoweringBase::isSExtCheaperThanZExt	(	EVT	FromTy,
		EVT	ToTy
	)		const

inlinevirtual

Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 2838 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::getNode(), and llvm::TargetLowering::SimplifySetCC().

◆ isShuffleMaskLegal()

virtual bool llvm::TargetLoweringBase::isShuffleMaskLegal	(	ArrayRef< int >	,
		EVT
	)		const

inlinevirtual

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::HexagonTargetLowering, llvm::MipsSETargetLowering, llvm::X86TargetLowering, and llvm::SITargetLowering.

Definition at line 1087 of file TargetLowering.h.

Referenced by llvm::TargetLowering::buildLegalVectorShuffle(), combineConcatVectorOfShuffleAndItsOperands(), combineShuffleOfBitcast(), ExpandBVWithShuffles(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), and formSplatFromShuffles().

◆ isSlowDivBypassed()

bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const

inline

Returns true if target has indicated at least one type should be bypassed.

Definition at line 546 of file TargetLowering.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty().

◆ isStoreBitCastBeneficial()

virtual bool llvm::TargetLoweringBase::isStoreBitCastBeneficial	(	EVT	StoreVT,
		EVT	BitcastVT,
		const SelectionDAG &	DAG,
		const MachineMemOperand &	MMO
	)		const

inlinevirtual

Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))

Definition at line 583 of file TargetLowering.h.

References isLoadBitCastBeneficial().

◆ isStrictFPEnabled()

bool llvm::TargetLoweringBase::isStrictFPEnabled ( ) const

inline

Return true if the target support strict float operation.

Definition at line 341 of file TargetLowering.h.

References IsStrictFPEnabled.

◆ isSuitableForBitTests()

bool llvm::TargetLoweringBase::isSuitableForBitTests	(	unsigned	NumDests,
		unsigned	NumCmps,
		const APInt &	Low,
		const APInt &	High,
		const DataLayout &	DL
	)		const

inline

Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons.

Check if the number of destinations, comparison metric, and range are all suitable.

Definition at line 1259 of file TargetLowering.h.

References DL, High, llvm::Low, and rangeFitsInWord().

Referenced by llvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().

◆ isSuitableForJumpTable()

bool TargetLoweringBase::isSuitableForJumpTable	(	const SwitchInst *	SI,
		uint64_t	NumCases,
		uint64_t	Range,
		ProfileSummaryInfo *	PSI,
		BlockFrequencyInfo *	BFI
	)		const

virtual

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.

Definition at line 1639 of file TargetLoweringBase.cpp.

References getMaximumJumpTableSize(), getMinimumJumpTableDensity(), llvm::shouldOptimizeForSize(), and SI.

Referenced by llvm::SwitchCG::SwitchLowering::findJumpTables(), and llvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().

◆ isSupportedFixedPointOperation()

virtual bool llvm::TargetLoweringBase::isSupportedFixedPointOperation	(	unsigned	Op,
		EVT	VT,
		unsigned	Scale
	)		const

inlinevirtual

Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.

If not, the operation is illegal.

Definition at line 1125 of file TargetLowering.h.

Referenced by getFixedPointOperationAction().

◆ isTruncateFree() [1/3]

virtual bool llvm::TargetLoweringBase::isTruncateFree	(	EVT	FromVT,
		EVT	ToVT
	)		const

inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, llvm::PPCTargetLowering, llvm::X86TargetLowering, and llvm::SystemZTargetLowering.

Definition at line 2749 of file TargetLowering.h.

◆ isTruncateFree() [2/3]

virtual bool llvm::TargetLoweringBase::isTruncateFree	(	LLT	FromTy,
		LLT	ToTy,
		const DataLayout &	DL,
		LLVMContext &	Ctx
	)		const

inlinevirtual

Definition at line 2750 of file TargetLowering.h.

References DL, llvm::getApproximateEVTForLLT(), and isTruncateFree().

◆ isTruncateFree() [3/3]

virtual bool llvm::TargetLoweringBase::isTruncateFree	(	Type *	FromTy,
		Type *	ToTy
	)		const

inlinevirtual

Return true if it's free to truncate a value of type FromTy to type ToTy.

e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.

Reimplemented in llvm::SystemZTargetLowering, llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, llvm::NVPTXTargetLowering, llvm::RISCVTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 2736 of file TargetLowering.h.

Referenced by ExtendUsesToFormExtLoad(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), getMemsetStores(), isExtLoad(), isTruncateFree(), llvm::BasicTTIImplBase< T >::isTruncateFree(), and llvm::TargetLowering::ShrinkDemandedOp().

◆ isTruncStoreLegal()

bool llvm::TargetLoweringBase::isTruncStoreLegal	(	EVT	ValVT,
		EVT	MemVT
	)		const

inline

Return true if the specified store with truncation is legal on this target.

Definition at line 1334 of file TargetLowering.h.

References getTruncStoreAction(), isTypeLegal(), and Legal.

Referenced by canCombineTruncStore(), llvm::R600TargetLowering::canCombineTruncStore(), combineMaskedStore(), combineStore(), llvm::BasicTTIImplBase< T >::getStoreMinimumVF(), and ShrinkLoadReplaceStoreWithStore().

◆ isTruncStoreLegalOrCustom()

bool llvm::TargetLoweringBase::isTruncStoreLegalOrCustom	(	EVT	ValVT,
		EVT	MemVT
	)		const

inline

Return true if the specified store with truncation has solution on this target.

Definition at line 1340 of file TargetLowering.h.

References Custom, getTruncStoreAction(), isTypeLegal(), and Legal.

Referenced by canCombineTruncStore().

◆ isTypeLegal()

bool llvm::TargetLoweringBase::isTypeLegal ( EVT VT ) const

inline

Return true if the target has native support for the specified value type.

This means that it has a register that directly holds it without promotions or expansions.

Definition at line 936 of file TargetLowering.h.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

◆ isVectorClearMaskLegal()

virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal	(	ArrayRef< int >	,
		EVT
	)		const

inlinevirtual

Similar to isShuffleMaskLegal.

Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::AArch64TargetLowering, and llvm::X86TargetLowering.

Definition at line 1100 of file TargetLowering.h.

◆ isVectorLoadExtDesirable()

virtual bool llvm::TargetLoweringBase::isVectorLoadExtDesirable ( SDValue ExtVal ) const

inlinevirtual

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Reimplemented in llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 2957 of file TargetLowering.h.

Referenced by tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().

◆ isVectorShiftByScalarCheap()

virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type * Ty ) const

inlinevirtual

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.

On x86 before AVX2 for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors. This should also apply to lowering for vector funnel shifts (rotates).

Reimplemented in llvm::X86TargetLowering.

Definition at line 2641 of file TargetLowering.h.

◆ isVScaleKnownToBeAPowerOfTwo()

virtual bool llvm::TargetLoweringBase::isVScaleKnownToBeAPowerOfTwo ( ) const

inlinevirtual

Return true only if vscale must be a power of two.

Reimplemented in llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.

Definition at line 555 of file TargetLowering.h.

◆ isZExtFree() [1/4]

virtual bool llvm::TargetLoweringBase::isZExtFree	(	EVT	FromTy,
		EVT	ToTy
	)		const

inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::X86TargetLowering.

Definition at line 2829 of file TargetLowering.h.

◆ isZExtFree() [2/4]

virtual bool llvm::TargetLoweringBase::isZExtFree	(	LLT	FromTy,
		LLT	ToTy,
		const DataLayout &	DL,
		LLVMContext &	Ctx
	)		const

inlinevirtual

Definition at line 2830 of file TargetLowering.h.

References DL, llvm::getApproximateEVTForLLT(), and isZExtFree().

◆ isZExtFree() [3/4]

virtual bool llvm::TargetLoweringBase::isZExtFree	(	SDValue	Val,
		EVT	VT2
	)		const

inlinevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented in llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, llvm::MSP430TargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 2924 of file TargetLowering.h.

References llvm::SDValue::getValueType(), and isZExtFree().

◆ isZExtFree() [4/4]

virtual bool llvm::TargetLoweringBase::isZExtFree	(	Type *	FromTy,
		Type *	ToTy
	)		const

inlinevirtual

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.

The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::X86TargetLowering.

Definition at line 2825 of file TargetLowering.h.

Referenced by combineShuffleOfScalars(), foldCONCAT_VECTORS(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::RegsForValue::getCopyToRegs(), hasSameExtUse(), isExtFree(),

Classes

Public Types

Public Member Functions

Static Public Member Functions

Protected Member Functions

Protected Attributes

Detailed Description

Member Typedef Documentation

◆ ArgListTy

◆ LegalizeKind

Member Enumeration Documentation

◆ AtomicExpansionKind

◆ BooleanContent

◆ LegalizeAction

◆ LegalizeTypeAction

◆ MulExpansionKind

◆ NegatibleCost

◆ ReciprocalEstimate

◆ SelectSupportKind

◆ ShiftLegalizationStrategy

Constructor & Destructor Documentation

◆ TargetLoweringBase() [1/2]

◆ TargetLoweringBase() [2/2]

◆ ~TargetLoweringBase()

Member Function Documentation

◆ addBypassSlowDiv()

◆ AddPromotedToType()

◆ addRegisterClass()

◆ aggressivelyPreferBuildVectorSources()

◆ alignLoopsWithOptSize()

◆ allowsMemoryAccess() [1/3]

◆ allowsMemoryAccess() [2/3]

◆ allowsMemoryAccess() [3/3]

◆ allowsMemoryAccessForAlignment() [1/2]

◆ allowsMemoryAccessForAlignment() [2/2]

◆ allowsMisalignedMemoryAccesses() [1/2]

◆ allowsMisalignedMemoryAccesses() [2/2]

◆ allowTruncateForTailCall()

◆ areJTsAllowed()

◆ canCombineStoreAndExtract()

◆ canCombineTruncStore()

◆ canMergeStoresTo()

◆ canOpTrap()

◆ computeRegisterProperties()

◆ convertSelectOfConstantsToMath()

◆ convertSetCCLogicToBitwiseLogic()

◆ createComplexDeinterleavingIR()

◆ decomposeMulByConstant()

◆ emitAtomicCmpXchgNoStoreLLBalance()

◆ emitBitTestAtomicRMWIntrinsic()

◆ emitCmpArithAtomicRMWIntrinsic()

◆ emitExpandAtomicRMW()

◆ emitLeadingFence()

◆ emitLoadLinked()

◆ emitMaskedAtomicCmpXchgIntrinsic()

◆ emitMaskedAtomicRMWIntrinsic()

◆ emitPatchPoint()

◆ emitStoreConditional()

◆ emitTrailingFence()

◆ enableAggressiveFMAFusion() [1/2]

◆ enableAggressiveFMAFusion() [2/2]

◆ enableExtLdPromotion()

◆ fallBackToDAGISel()

◆ finalizeLowering()

◆ findRepresentativeClass()

◆ generateFMAsInMachineCombiner()

◆ getABIAlignmentForCallingConv()

◆ getAddrModeArguments()

◆ getAsmOperandValueType()

◆ getAtomicMemOperandFlags()

◆ getBooleanContents() [1/2]

◆ getBooleanContents() [2/2]

◆ getBypassSlowDivWidths()

◆ getByValTypeAlignment()

◆ getCmpLibcallCC()

◆ getCmpLibcallReturnType()

◆ getCondCodeAction()

◆ getCustomCtpopCost()

◆ getCustomOperationAction()

◆ getDefaultSafeStackPointerLocation()