This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen. More...
#include "llvm/CodeGen/TargetLowering.h"
Classes | |
| struct | AddrMode |
| This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null, there is no BaseGV. More... | |
| class | ArgListEntry |
| struct | IntrinsicInfo |
| class | ValueTypeActionImpl |
Public Member Functions | |
| virtual void | markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| TargetLoweringBase (const TargetLoweringBase &)=delete | |
| TargetLoweringBase & | operator= (const TargetLoweringBase &)=delete |
| virtual | ~TargetLoweringBase ()=default |
| bool | isStrictFPEnabled () const |
| Return true if the target support strict float operation. More... | |
| const TargetMachine & | getTargetMachine () const |
| virtual bool | useSoftFloat () const |
| virtual MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| virtual MVT | getPointerMemTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| MVT | getFrameIndexTy (const DataLayout &DL) const |
| Return the type for frame index, which is determined by the alloca address space specified through the data layout. More... | |
| MVT | getProgramPointerTy (const DataLayout &DL) const |
| Return the type for code pointers, which is determined by the program address space specified through the data layout. More... | |
| virtual MVT | getFenceOperandTy (const DataLayout &DL) const |
| Return the type for operands of fence. More... | |
| virtual MVT | getScalarShiftAmountTy (const DataLayout &, EVT) const |
| Return the type to use for a scalar shift opcode, given the shifted amount type. More... | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const |
| Returns the type for the shift amount of a shift opcode. More... | |
| virtual LLVM_READONLY LLT | getPreferredShiftAmountTy (LLT ShiftValueTy) const |
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy. More... | |
| virtual MVT | getVectorIdxTy (const DataLayout &DL) const |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More... | |
| virtual MVT | getVPExplicitVectorLengthTy () const |
| Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc. More... | |
| virtual MachineMemOperand::Flags | getTargetMMOFlags (const Instruction &I) const |
| This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. More... | |
| MachineMemOperand::Flags | getLoadMemOperandFlags (const LoadInst &LI, const DataLayout &DL) const |
| MachineMemOperand::Flags | getStoreMemOperandFlags (const StoreInst &SI, const DataLayout &DL) const |
| MachineMemOperand::Flags | getAtomicMemOperandFlags (const Instruction &AI, const DataLayout &DL) const |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| virtual bool | shouldExpandGetActiveLaneMask (EVT VT, EVT OpVT) const |
| Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder. More... | |
| virtual bool | reduceSelectOfFPConstantLoads (EVT CmpOpVT) const |
| Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. More... | |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (MVT VT) const |
| Return the preferred vector type legalization action. More... | |
| virtual bool | softPromoteHalfType () const |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| virtual bool | isIntDivCheap (EVT VT, AttributeList Attr) const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More... | |
| virtual bool | hasStandaloneRem (EVT VT) const |
| Return true if the target can handle a standalone remainder operation. More... | |
| virtual bool | isFsqrtCheap (SDValue X, SelectionDAG &DAG) const |
| Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More... | |
| int | getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More... | |
| int | getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More... | |
| int | getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a square root of the given type based on the function's attributes. More... | |
| int | getDivRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a division of the given type based on the function's attributes. More... | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. More... | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. More... | |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More... | |
| virtual bool | fallBackToDAGISel (const Instruction &Inst) const |
| virtual bool | isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const |
| Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More... | |
| virtual bool | isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const |
| Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) More... | |
| virtual bool | storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const |
| Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More... | |
| virtual bool | mergeStoresAfterLegalization (EVT MemVT) const |
| Allow store merging for the specified type after legalization in addition to before legalization. More... | |
| virtual bool | canMergeStoresTo (unsigned AS, EVT MemVT, const MachineFunction &MF) const |
| Returns if it's reasonable to merge stores to MemVT size. More... | |
| virtual bool | isCheapToSpeculateCttz () const |
| Return true if it is cheap to speculate a call to intrinsic cttz. More... | |
| virtual bool | isCheapToSpeculateCtlz () const |
| Return true if it is cheap to speculate a call to intrinsic ctlz. More... | |
| virtual bool | isCtlzFast () const |
| Return true if ctlz instruction is fast. More... | |
| virtual unsigned | getCustomCtpopCost (EVT VT, ISD::CondCode Cond) const |
| Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP. More... | |
| virtual bool | isEqualityCmpFoldedWithSignedCmp () const |
| Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison. More... | |
| virtual bool | preferZeroCompareBranch () const |
| Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare. More... | |
| virtual bool | hasBitPreservingFPLogic (EVT VT) const |
| Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More... | |
| virtual bool | isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const |
| Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More... | |
| virtual bool | isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const |
| Return if the target supports combining a chain like: More... | |
| virtual bool | convertSetCCLogicToBitwiseLogic (EVT VT) const |
| Use bitwise logic to make pairs of compares more efficient. More... | |
| virtual MVT | hasFastEqualityCompare (unsigned NumBits) const |
| Return the preferred operand type if the target has a quick way to compare integer values of the given size. More... | |
| virtual bool | hasAndNotCompare (SDValue Y) const |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More... | |
| virtual bool | hasAndNot (SDValue X) const |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More... | |
| virtual bool | hasBitTest (SDValue X, SDValue Y) const |
| Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized. More... | |
| virtual bool | shouldFoldMaskToVariableShiftPair (SDValue X) const |
| There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred. More... | |
| virtual bool | shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to fold a pair of shifts into a mask. More... | |
| virtual bool | shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. More... | |
| virtual bool | shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const |
| Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in. More... | |
| virtual bool | preferIncOfAddToSubOfNot (EVT VT) const |
| These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical. More... | |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More... | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy, Idx). More... | |
| virtual bool | shouldSplatInsEltVarIndex (EVT) const |
| Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. More... | |
| virtual bool | enableAggressiveFMAFusion (EVT VT) const |
| Return true if target always benefits from combining into FMA for a given value type. More... | |
| virtual bool | enableAggressiveFMAFusion (LLT Ty) const |
| Return true if target always benefits from combining into FMA for a given value type. More... | |
| virtual EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const |
| Return the ValueType of the result of SETCC operations. More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. More... | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More... | |
| BooleanContent | getBooleanContents (EVT Type) const |
| SDValue | promoteTargetBoolean (SelectionDAG &DAG, SDValue Bool, EVT ValVT) const |
| Promote the given target boolean to a target boolean of the given type. More... | |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT, bool isDivergent=false) const |
| Return the register class that should be used for the specified value type. More... | |
| virtual bool | requiresUniformRegister (MachineFunction &MF, const Value *) const |
| Allows target to decide about the register class of the specific value that is live outside the defining block. More... | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. More... | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. More... | |
| virtual bool | shouldExpandShift (SelectionDAG &DAG, SDNode *N) const |
| Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a library call is preferred (e.g for code-size reasons). More... | |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. More... | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More... | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. More... | |
| virtual unsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More... | |
| virtual bool | getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More... | |
| virtual bool | isFPImmLegal (const APFloat &, EVT, bool ForCodeSize=false) const |
| Returns true if the target can instruction select the specified FP immediate natively. More... | |
| virtual bool | isShuffleMaskLegal (ArrayRef< int >, EVT) const |
| Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More... | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. More... | |
| virtual bool | isVectorClearMaskLegal (ArrayRef< int >, EVT) const |
| Similar to isShuffleMaskLegal. More... | |
| virtual LegalizeAction | getCustomOperationAction (SDNode &Op) const |
| How to legalize this custom operation? More... | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| virtual bool | isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const |
| Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. More... | |
| LegalizeAction | getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const |
| Some fixed point operations may be natively supported by the target but only for specific scales. More... | |
| LegalizeAction | getStrictFPOperationAction (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT, bool LegalOnly=false) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. More... | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. More... | |
| bool | isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More... | |
| bool | isOperationCustom (unsigned Op, EVT VT) const |
| Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More... | |
| virtual bool | areJTsAllowed (const Function *Fn) const |
| Return true if lowering to a jump table is allowed. More... | |
| bool | rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const |
| Check whether the range [Low,High] fits in a machine word. More... | |
| virtual bool | isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. More... | |
| virtual MVT | getPreferredSwitchConditionType (LLVMContext &Context, EVT ConditionVT) const |
| Returns preferred type for switch condition. More... | |
| bool | isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. More... | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More... | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. More... | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. More... | |
| bool | isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation has solution on this target. More... | |
| virtual bool | canCombineTruncStore (EVT ValVT, EVT MemVT, bool LegalOnly) const |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedMaskedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedMaskedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedMaskedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedMaskedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| virtual bool | shouldExtendGSIndex (EVT VT, EVT &EltTy) const |
| Returns true if the index type for a masked gather/scatter requires extending. More... | |
| virtual bool | shouldRemoveExtendFromGSIndex (EVT VT) const |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| bool | isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal or custom on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. More... | |
| virtual EVT | getAsmOperandValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. More... | |
| EVT | getMemValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| virtual uint64_t | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const |
| Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| virtual unsigned | getNumRegisters (LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const |
| Return the number of registers that this ValueType will eventually require. More... | |
| virtual MVT | getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More... | |
| virtual unsigned | getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const |
| Certain targets require unusual breakdowns of certain types. More... | |
| virtual Align | getABIAlignmentForCallingConv (Type *ArgTy, const DataLayout &DL) const |
| Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type. More... | |
| virtual bool | ShouldShrinkFPConstant (EVT) const |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More... | |
| virtual bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const |
| Return true if it is profitable to reduce a load to a smaller type. More... | |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More... | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. More... | |
| unsigned | getGatherAllAliasesMaxDepth () const |
| virtual unsigned | getVaListSizeInBits (const DataLayout &DL) const |
| Returns the size of the platform's va_list object. More... | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| virtual unsigned | getMaxGluedStoresPerMemcpy () const |
| Get maximum # of store operations to be glued together. More... | |
| unsigned | getMaxExpandSizeMemcmp (bool OptSize) const |
| Get maximum # of load operations permitted for memcmp. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| virtual bool | allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const |
| Determine if the target supports unaligned memory accesses. More... | |
| virtual bool | allowsMisalignedMemoryAccesses (LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const |
| LLT handling variant. More... | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const |
| This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access. More... | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) const |
| Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand. More... | |
| virtual bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given address space and alignment. More... | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given MachineMemOperand. More... | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, bool *Fast=nullptr) const |
| LLT handling variant. More... | |
| virtual EVT | getOptimalMemOpType (const MemOp &Op, const AttributeList &) const |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More... | |
| virtual LLT | getOptimalMemOpLLT (const MemOp &Op, const AttributeList &) const |
| LLT returning variant. More... | |
| virtual bool | isSafeMemOpType (MVT) const |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More... | |
| virtual unsigned | getMinimumJumpTableEntries () const |
| Return lower limit for number of blocks in a jump table. More... | |
| unsigned | getMinimumJumpTableDensity (bool OptForSize) const |
| Return lower limit of the density in a jump table. More... | |
| unsigned | getMaximumJumpTableSize () const |
| Return upper limit for number of entries in a jump table. More... | |
| virtual bool | isJumpTableRelative () const |
| Register | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| virtual Register | getExceptionPointerRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. More... | |
| virtual Register | getExceptionSelectorRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More... | |
| virtual bool | needsFixedCatchObjects () const |
| Align | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| Align | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| Align | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| virtual Align | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. More... | |
| virtual unsigned | getMaxPermittedBytesForAlignment (MachineBasicBlock *MBB) const |
| Return the maximum amount of bytes allowed to be emitted when padding for alignment. More... | |
| virtual bool | alignLoopsWithOptSize () const |
| Should loops be aligned even when the function is marked OptSize (but not MinSize). More... | |
| virtual Value * | getIRStackGuard (IRBuilderBase &IRB) const |
| If the target has a standard location for the stack protector guard, returns the address of that location. More... | |
| virtual void | insertSSPDeclarations (Module &M) const |
| Inserts necessary declarations for SSP (stack protection) purpose. More... | |
| virtual Value * | getSDagStackGuard (const Module &M) const |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More... | |
| virtual bool | useStackGuardXorFP () const |
| If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. More... | |
| virtual Function * | getSSPStackGuardCheck (const Module &M) const |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. More... | |
| virtual bool | isConstantUnsignedBitfieldExtractLegal (unsigned Opc, LLT Ty1, LLT Ty2) const |
| virtual Value * | getSafeStackPointerLocation (IRBuilderBase &IRB) const |
| Returns the target-specific address of the unsafe stack pointer. More... | |
| virtual bool | hasStackProbeSymbol (MachineFunction &MF) const |
| Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More... | |
| virtual bool | hasInlineStackProbe (MachineFunction &MF) const |
| virtual StringRef | getStackProbeSymbolName (MachineFunction &MF) const |
| virtual bool | isFreeAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const |
| Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More... | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More... | |
| virtual void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder) const |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. More... | |
| virtual bool | shouldExtendTypeInLibCall (EVT Type) const |
| Returns true if arguments should be extended in lib calls. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicLoadInIR (LoadInst *LI) const |
| Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual AtomicExpansionKind | shouldCastAtomicLoadInIR (LoadInst *LI) const |
| Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicStoreInIR (StoreInst *SI) const |
| Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into. More... | |
| virtual AtomicExpansionKind | shouldCastAtomicStoreInIR (StoreInst *SI) const |
| Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW) const |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More... | |
| virtual AtomicExpansionKind | shouldCastAtomicRMWIInIR (AtomicRMWInst *RMWI) const |
| Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass. More... | |
| virtual LoadInst * | lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const |
| On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More... | |
| virtual ISD::NodeType | getExtendForAtomicOps () const |
| Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More... | |
| virtual ISD::NodeType | getExtendForAtomicCmpSwapArg () const |
| Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More... | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More... | |
| virtual bool | isProfitableToCombineMinNumMaxNum (EVT VT) const |
| virtual bool | convertSelectOfConstantsToMath (EVT VT) const |
| Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More... | |
| virtual bool | decomposeMulByConstant (LLVMContext &Context, EVT VT, SDValue C) const |
| Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. More... | |
| virtual bool | isMulAddWithConstProfitable (SDValue AddNode, SDValue ConstNode) const |
| Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). More... | |
| virtual bool | shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const |
| Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. More... | |
| virtual bool | getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More... | |
| virtual bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More... | |
| virtual InstructionCost | getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| virtual bool | isLegalICmpImmediate (int64_t) const |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More... | |
| virtual bool | isLegalAddImmediate (int64_t) const |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More... | |
| virtual bool | isLegalStoreImmediate (int64_t Value) const |
| Return true if the specified immediate is legal for the value input of a store instruction. More... | |
| virtual bool | isVectorShiftByScalarCheap (Type *Ty) const |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More... | |
| virtual Type * | shouldConvertSplatType (ShuffleVectorInst *SVI) const |
| Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable. More... | |
| virtual bool | shouldConvertPhiType (Type *From, Type *To) const |
| Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'. More... | |
| virtual bool | isCommutativeBinOp (unsigned Opcode) const |
| Returns true if the opcode is a commutative binary operation. More... | |
| virtual bool | isBinOp (unsigned Opcode) const |
| Return true if the node is a math/logic binary operator. More... | |
| virtual bool | isTruncateFree (Type *FromTy, Type *ToTy) const |
| Return true if it's free to truncate a value of type FromTy to type ToTy. More... | |
| virtual bool | allowTruncateForTailCall (Type *FromTy, Type *ToTy) const |
| Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More... | |
| virtual bool | isTruncateFree (EVT FromVT, EVT ToVT) const |
| virtual bool | isTruncateFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const |
| virtual bool | isProfitableToHoist (Instruction *I) const |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const |
Return true if Load and Ext can form an ExtLoad. More... | |
| virtual bool | isZExtFree (Type *FromTy, Type *ToTy) const |
| Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More... | |
| virtual bool | isZExtFree (EVT FromTy, EVT ToTy) const |
| virtual bool | isZExtFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const |
| virtual bool | isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const |
| Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. More... | |
| virtual bool | signExtendConstant (const ConstantInt *C) const |
| Return true if this constant should be sign extended when promoting to a larger type. More... | |
| virtual bool | shouldSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const |
| Return true if sinking I's operands to the same basic block as I is profitable, e.g. More... | |
| virtual bool | hasPairedLoad (EVT, Align &) const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More... | |
| virtual bool | hasVectorBlend () const |
| Return true if the target has a vector blend instruction. More... | |
| virtual unsigned | getMaxSupportedInterleaveFactor () const |
| Get the maximum supported factor for interleaved memory accesses. More... | |
| virtual bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const |
| Lower an interleaved load to target specific intrinsics. More... | |
| virtual bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const |
| Lower an interleaved store to target specific intrinsics. More... | |
| virtual bool | isZExtFree (SDValue Val, EVT VT2) const |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More... | |
| virtual bool | isFPExtFree (EVT DestVT, EVT SrcVT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More... | |
| virtual bool | isFPExtFoldable (const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More... | |
| virtual bool | isFPExtFoldable (const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More... | |
| virtual bool | isVectorLoadExtDesirable (SDValue ExtVal) const |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More... | |
| virtual bool | isFNegFree (EVT VT) const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFAbsFree (EVT VT) const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, EVT) const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| virtual bool | isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, LLT) const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| virtual bool | isFMAFasterThanFMulAndFAdd (const Function &F, Type *) const |
| IR version. More... | |
| virtual bool | isFMADLegal (const MachineInstr &MI, LLT Ty) const |
Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD. More... | |
| virtual bool | isFMADLegal (const SelectionDAG &DAG, const SDNode *N) const |
| Returns true if be combined with to form an ISD::FMAD. More... | |
| virtual bool | generateFMAsInMachineCombiner (EVT VT, CodeGenOpt::Level OptLevel) const |
| virtual bool | isNarrowingProfitable (EVT, EVT) const |
| Return true if it's profitable to narrow operations of type VT1 to VT2. More... | |
| virtual bool | shouldFoldSelectWithIdentityConstant (unsigned BinOpcode, EVT VT) const |
| Return true if pulling a binary operation into a select with an identity constant is profitable. More... | |
| virtual bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const |
| Return true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| virtual bool | isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const |
| Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. More... | |
| virtual bool | shouldScalarizeBinop (SDValue VecOp) const |
| Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. More... | |
| virtual bool | isExtractVecEltCheap (EVT VT, unsigned Index) const |
| Return true if extraction of a scalar element from the given vector type at the given index is cheap. More... | |
| virtual bool | shouldFormOverflowOp (unsigned Opcode, EVT VT, bool MathUsed) const |
| Try to convert math with an overflow comparison into the corresponding DAG node operation. More... | |
| virtual bool | aggressivelyPreferBuildVectorSources (EVT VecVT) const |
| virtual bool | shouldConsiderGEPOffsetSplit () const |
| virtual bool | shouldAvoidTransformToShift (EVT VT, unsigned Amount) const |
| Return true if creating a shift of the type by the given amount is not profitable. More... | |
| virtual bool | shouldKeepZExtForFP16Conv () const |
| Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function. More... | |
| virtual bool | shouldConvertFpToSat (unsigned Op, EVT FPVT, EVT VT) const |
| Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns. More... | |
| void | setLibcallName (ArrayRef< RTLIB::Libcall > Calls, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. More... | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. More... | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| virtual void | finalizeLowering (MachineFunction &MF) const |
| Execute target specific actions to finalize target lowering. More... | |
| virtual bool | shouldLocalize (const MachineInstr &MI, const TargetTransformInfo *TTI) const |
Check whether or not MI needs to be moved close to its uses. More... | |
Helpers for TargetTransformInfo implementations | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< InstructionCost, MVT > | getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
Helpers for atomic expansion. | |
| unsigned | getMaxAtomicSizeInBitsSupported () const |
| Returns the maximum atomic operation size (in bits) supported by the backend. More... | |
| unsigned | getMinCmpXchgSizeInBits () const |
| Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More... | |
| bool | supportsUnalignedAtomics () const |
| Whether the target supports unaligned atomic operations. More... | |
| virtual bool | shouldInsertFencesForAtomic (const Instruction *I) const |
| Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More... | |
| virtual Value * | emitLoadLinked (IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More... | |
| virtual Value * | emitStoreConditional (IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const |
| Perform a store-conditional operation to Addr. More... | |
| virtual Value * | emitMaskedAtomicRMWIntrinsic (IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const |
| Perform a masked atomicrmw using a target-specific intrinsic. More... | |
| virtual void | emitBitTestAtomicRMWIntrinsic (AtomicRMWInst *AI) const |
| Perform a bit test atomicrmw using a target-specific intrinsic. More... | |
| virtual Value * | emitMaskedAtomicCmpXchgIntrinsic (IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const |
| Perform a masked cmpxchg using a target-specific intrinsic. More... | |
| virtual Instruction * | emitLeadingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. More... | |
| virtual Instruction * | emitTrailingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const |
Static Public Member Functions | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
Protected Member Functions | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
| Value * | getDefaultSafeStackPointerLocation (IRBuilderBase &IRB, bool UseTLS) const |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More... | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setMinimumJumpTableEntries (unsigned Val) |
| Indicate the minimum number of blocks to generate jump tables. More... | |
| void | setMaximumJumpTableSize (unsigned) |
| Indicate the maximum number of entries in jump tables. More... | |
| void | setStackPointerRegisterToSaveRestore (Register R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More... | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. More... | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More... | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. More... | |
| virtual std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More... | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. More... | |
| void | setOperationAction (ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. More... | |
| void | setOperationAction (ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More... | |
| void | setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedLoadAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More... | |
| void | setIndexedLoadAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | setIndexedStoreAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedStoreAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | setIndexedMaskedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedMaskedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setCondCodeAction (ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More... | |
| void | setCondCodeAction (ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More... | |
| void | setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| Convenience method to set an operation to Promote and specify the type in a single call. More... | |
| void | setTargetDAGCombine (ArrayRef< ISD::NodeType > NTs) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More... | |
| void | setMinFunctionAlignment (Align Alignment) |
| Set the target's minimum function alignment. More... | |
| void | setPrefFunctionAlignment (Align Alignment) |
| Set the target's preferred function alignment. More... | |
| void | setPrefLoopAlignment (Align Alignment) |
| Set the target's preferred loop alignment. More... | |
| void | setMaxBytesForAlignment (unsigned MaxBytes) |
| void | setMinStackArgumentAlignment (Align Alignment) |
| Set the minimum stack alignment of an argument. More... | |
| void | setMaxAtomicSizeInBitsSupported (unsigned SizeInBits) |
| Set the maximum atomic operation size supported by the backend. More... | |
| void | setMinCmpXchgSizeInBits (unsigned SizeInBits) |
| Sets the minimum cmpxchg or ll/sc size supported by the backend. More... | |
| void | setSupportsUnalignedAtomics (bool UnalignedSupported) |
| Sets whether unaligned atomic operations are supported. More... | |
| virtual bool | isExtFreeImpl (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. More... | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More... | |
Protected Attributes | |
| unsigned | GatherAllAliasesMaxDepth |
| Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More... | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum number of store instructions per memcpy call. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| unsigned | MaxGluedStoresPerMemcpy = 0 |
| Specify max number of store instructions to glue in inlined memcpy. More... | |
| unsigned | MaxLoadsPerMemcmp |
| Specify maximum number of load instructions per memcmp call. More... | |
| unsigned | MaxLoadsPerMemcmpOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| unsigned | MaxStoresPerMemmove |
| Specify maximum number of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More... | |
| bool | EnableExtLdPromotion |
| bool | IsStrictFPEnabled |
Detailed Description
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.
Definition at line 191 of file TargetLowering.h.
Member Typedef Documentation
◆ ArgListTy
| using llvm::TargetLoweringBase::ArgListTy = std::vector<ArgListEntry> |
Definition at line 312 of file TargetLowering.h.
◆ LegalizeKind
| using llvm::TargetLoweringBase::LegalizeKind = std::pair<LegalizeTypeAction, EVT> |
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition at line 227 of file TargetLowering.h.
Member Enumeration Documentation
◆ AtomicExpansionKind
|
strong |
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Exists because different targets have different levels of support for these atomic instructions, and also have different options w.r.t. what they should expand to.
| Enumerator | |
|---|---|
| None | |
| CastToInteger | |
| LLSC | |
| LLOnly | |
| CmpXChg | |
| MaskedIntrinsic | |
| BitTestIntrinsic | |
| Expand | |
| NotAtomic | |
Definition at line 249 of file TargetLowering.h.
◆ BooleanContent
Enum that describes how the target represents true/false values.
| Enumerator | |
|---|---|
| UndefinedBooleanContent | |
| ZeroOrOneBooleanContent | |
| ZeroOrNegativeOneBooleanContent | |
Definition at line 230 of file TargetLowering.h.
◆ LegalizeAction
| enum llvm::TargetLoweringBase::LegalizeAction : uint8_t |
This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.
| Enumerator | |
|---|---|
| Legal | |
| Promote | |
| Expand | |
| LibCall | |
| Custom | |
Definition at line 195 of file TargetLowering.h.
◆ LegalizeTypeAction
| enum llvm::TargetLoweringBase::LegalizeTypeAction : uint8_t |
This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.
Definition at line 205 of file TargetLowering.h.
◆ MulExpansionKind
|
strong |
Enum that specifies when a multiplication should be expanded.
| Enumerator | |
|---|---|
| Always | |
| OnlyLegalOrCustom | |
Definition at line 269 of file TargetLowering.h.
◆ NegatibleCost
|
strong |
Enum that specifies when a float negation is beneficial.
| Enumerator | |
|---|---|
| Cheaper | |
| Neutral | |
| Expensive | |
Definition at line 276 of file TargetLowering.h.
◆ ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
| Enumerator | |
|---|---|
| Unspecified | |
| Disabled | |
| Enabled | |
Definition at line 510 of file TargetLowering.h.
◆ SelectSupportKind
Enum that describes what type of support for selects the target has.
| Enumerator | |
|---|---|
| ScalarValSelect | |
| ScalarCondVectorVal | |
| VectorMaskSelect | |
Definition at line 237 of file TargetLowering.h.
Constructor & Destructor Documentation
◆ TargetLoweringBase() [1/2]
|
explicit |
NOTE: The TargetMachine owns TLOF.
Definition at line 696 of file TargetLoweringBase.cpp.
References llvm::sys::path::begin(), DisableStrictNodeMutation, EnableExtLdPromotion, llvm::sys::path::end(), GatherAllAliasesMaxDepth, llvm::TargetMachine::getTargetTriple(), llvm::Sched::ILP, initActions(), InitCmpLibcallCCs(), IsStrictFPEnabled, JumpIsExpensiveOverride, MaxGluedStoresPerMemcpy, MaxLoadsPerMemcmp, MaxLoadsPerMemcmpOptSize, MaxStoresPerMemcpy, MaxStoresPerMemcpyOptSize, MaxStoresPerMemmove, MaxStoresPerMemmoveOptSize, MaxStoresPerMemset, MaxStoresPerMemsetOptSize, PredictableSelectIsExpensive, and UndefinedBooleanContent.
◆ TargetLoweringBase() [2/2]
|
delete |
◆ ~TargetLoweringBase()
|
virtualdefault |
Member Function Documentation
◆ addBypassSlowDiv()
|
inlineprotected |
Tells the code generator which bitwidths to bypass.
Definition at line 2262 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ AddPromotedToType()
|
inlineprotected |
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.
If that default is insufficient, this method can be used by the target to override the default.
Definition at line 2408 of file TargetLowering.h.
References llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), setOperationPromotedToType(), and llvm::SITargetLowering::SITargetLowering().
◆ addRegisterClass()
|
inlineprotected |
Add the specified register class as an available regclass for the specified value type.
This indicates the selector can handle values of that class natively.
Definition at line 2269 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ aggressivelyPreferBuildVectorSources()
|
inlinevirtual |
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 3024 of file TargetLowering.h.
◆ alignLoopsWithOptSize()
|
inlinevirtual |
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Reimplemented in llvm::ARMTargetLowering.
Definition at line 1829 of file TargetLowering.h.
◆ allowsMemoryAccess() [1/3]
| bool TargetLoweringBase::allowsMemoryAccess | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| EVT | VT, | ||
| const MachineMemOperand & | MMO, | ||
| bool * | Fast = nullptr |
||
| ) | const |
Return true if the target supports a memory access of this type for the given MachineMemOperand.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1707 of file TargetLoweringBase.cpp.
References allowsMemoryAccess(), Context, DL, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), and llvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccess() [2/3]
|
virtual |
Return true if the target supports a memory access of this type for the given address space and alignment.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Reimplemented in llvm::HexagonTargetLowering.
Definition at line 1698 of file TargetLoweringBase.cpp.
References allowsMemoryAccessForAlignment(), Context, and DL.
Referenced by llvm::HexagonTargetLowering::allowsMemoryAccess(), allowsMemoryAccess(), combineConcatVectorOps(), combineLoad(), combineStore(), isLoadBitCastBeneficial(), llvm::LegalizerHelper::lowerLoad(), llvm::LegalizerHelper::lowerStore(), llvm::CombinerHelper::matchTruncStoreMerge(), and ShrinkLoadReplaceStoreWithStore().
◆ allowsMemoryAccess() [3/3]
| bool TargetLoweringBase::allowsMemoryAccess | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| LLT | Ty, | ||
| const MachineMemOperand & | MMO, | ||
| bool * | Fast = nullptr |
||
| ) | const |
LLT handling variant.
Definition at line 1715 of file TargetLoweringBase.cpp.
References allowsMemoryAccess(), Context, DL, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::getApproximateEVTForLLT(), and llvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccessForAlignment() [1/2]
| bool TargetLoweringBase::allowsMemoryAccessForAlignment | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| EVT | VT, | ||
| const MachineMemOperand & | MMO, | ||
| bool * | Fast = nullptr |
||
| ) | const |
Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1691 of file TargetLoweringBase.cpp.
References allowsMemoryAccessForAlignment(), Context, DL, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), and llvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccessForAlignment() [2/2]
| bool TargetLoweringBase::allowsMemoryAccessForAlignment | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| EVT | VT, | ||
| unsigned | AddrSpace = 0, |
||
| Align | Alignment = Align(1), |
||
| MachineMemOperand::Flags | Flags = MachineMemOperand::MONone, |
||
| bool * | Fast = nullptr |
||
| ) | const |
This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1671 of file TargetLoweringBase.cpp.
References allowsMisalignedMemoryAccesses(), Context, DL, llvm::EVT::getTypeForEVT(), and llvm::EVT::isZeroSized().
Referenced by allowsMemoryAccess(), allowsMemoryAccessForAlignment(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), and llvm::HexagonTargetLowering::LowerUnalignedLoad().
◆ allowsMisalignedMemoryAccesses() [1/2]
|
inlinevirtual |
Determine if the target supports unaligned memory accesses.
This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.
Reimplemented in llvm::MipsSETargetLowering, llvm::SITargetLowering, llvm::R600TargetLowering, llvm::X86TargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::RISCVTargetLowering, llvm::AArch64TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::Mips16TargetLowering.
Definition at line 1689 of file TargetLowering.h.
Referenced by allowsMemoryAccessForAlignment(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::allowsMisalignedMemoryAccesses(), findGISelOptimalMemOpLowering(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::AMDGPUTargetLowering::performLoadCombine(), and llvm::AMDGPUTargetLowering::performStoreCombine().
◆ allowsMisalignedMemoryAccesses() [2/2]
|
inlinevirtual |
LLT handling variant.
Reimplemented in llvm::SITargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1697 of file TargetLowering.h.
◆ allowTruncateForTailCall()
|
inlinevirtual |
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.
Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::SystemZTargetLowering.
Definition at line 2661 of file TargetLowering.h.
Referenced by getNoopInput().
◆ areJTsAllowed()
Return true if lowering to a jump table is allowed.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1204 of file TargetLowering.h.
References llvm::ISD::BR_JT, llvm::ISD::BRIND, llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsBool(), isOperationLegalOrCustom(), and llvm::MVT::Other.
Referenced by llvm::X86TargetLowering::areJTsAllowed(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters().
◆ canCombineStoreAndExtract()
|
inlinevirtual |
Return true if the target can combine store(extractelement VectorTy, Idx).
Cost[out] gives the cost of that transformation when this is true.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 809 of file TargetLowering.h.
◆ canCombineTruncStore()
|
inlinevirtual |
Reimplemented in llvm::R600TargetLowering.
Definition at line 1323 of file TargetLowering.h.
References isTruncStoreLegal(), and isTruncStoreLegalOrCustom().
◆ canMergeStoresTo()
|
inlinevirtual |
Returns if it's reasonable to merge stores to MemVT size.
Reimplemented in llvm::SITargetLowering, llvm::R600TargetLowering, llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 616 of file TargetLowering.h.
◆ canOpTrap()
|
virtual |
Returns true if the operation can trap for the value type.
VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.
Definition at line 895 of file TargetLoweringBase.cpp.
References assert(), isTypeLegal(), llvm::ISD::SDIV, llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.
◆ computeRegisterProperties()
|
protected |
Once all of the register classes are added, this allows us to compute derived properties we expose.
computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition at line 1248 of file TargetLoweringBase.cpp.
References assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, findRepresentativeClass(), llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::MVT::getFixedSizeInBits(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), llvm::MVT::getPow2VectorType(), getPreferredVectorAction(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), getVectorTypeBreakdownMVT(), i, llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::isPowerOf2_32(), llvm::MVT::isScalableVector(), isTypeLegal(), llvm::MVT::isVoid, llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE, llvm::MVT::LAST_INTEGER_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, LLVM_FALLTHROUGH, llvm_unreachable, llvm::MVT::MAX_ALLOWED_VALUETYPE, llvm::MVT::Other, llvm::MVT::ppcf128, llvm::MSP430ISD::RRC, llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), softPromoteHalfType(), TRI, TypeExpandFloat, TypeExpandInteger, TypePromoteFloat, TypePromoteInteger, TypeScalarizeScalableVector, TypeScalarizeVector, TypeSoftenFloat, TypeSoftPromoteHalf, TypeSplitVector, TypeWidenVector, and llvm::MVT::VALUETYPE_SIZE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::VETargetLowering::VETargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ convertSelectOfConstantsToMath()
|
inlinevirtual |
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.
For example: select Cond, C1, C1-1 --> add (zext Cond), C1-1
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2158 of file TargetLowering.h.
◆ convertSetCCLogicToBitwiseLogic()
|
inlinevirtual |
Use bitwise logic to make pairs of compares more efficient.
For example: and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 683 of file TargetLowering.h.
◆ decomposeMulByConstant()
|
inlinevirtual |
Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.
This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2167 of file TargetLowering.h.
◆ emitAtomicCmpXchgNoStoreLLBalance()
|
inlinevirtual |
Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2032 of file TargetLowering.h.
◆ emitBitTestAtomicRMWIntrinsic()
|
inlinevirtual |
Perform a bit test atomicrmw using a target-specific intrinsic.
This represents the combined bit test intrinsic which will be lowered at a late stage by the backend.
Definition at line 1970 of file TargetLowering.h.
References llvm_unreachable.
◆ emitLeadingFence()
|
virtual |
Inserts in the IR a target-specific intrinsic specifying a fence.
It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.
Inst is the original atomic instruction, prior to other expansions that may be performed.
This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::VETargetLowering.
Definition at line 2254 of file TargetLoweringBase.cpp.
References Builder, llvm::Instruction::hasAtomicStore(), and llvm::isReleaseOrStronger().
◆ emitLoadLinked()
|
inlinevirtual |
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.
Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1944 of file TargetLowering.h.
References llvm_unreachable.
◆ emitMaskedAtomicCmpXchgIntrinsic()
|
inlinevirtual |
Perform a masked cmpxchg using a target-specific intrinsic.
This represents the core LL/SC loop which will be lowered at a late stage by the backend.
Reimplemented in llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1978 of file TargetLowering.h.
References llvm_unreachable.
◆ emitMaskedAtomicRMWIntrinsic()
|
inlinevirtual |
Perform a masked atomicrmw using a target-specific intrinsic.
This represents the core LL/SC loop which will be lowered at a late stage by the backend.
Reimplemented in llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1959 of file TargetLowering.h.
References llvm_unreachable.
◆ emitPatchPoint()
|
protected |
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.
Definition at line 1128 of file TargetLoweringBase.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addMemOperand(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineFunction::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineInstr::getNumOperands(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::DataLayout::getPointerSize(), i, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isReg(), llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex(), llvm::MachineOperand::isTied(), llvm::MachineInstr::mayLoad(), MBB, MI, llvm::MachineMemOperand::MOLoad, llvm::none_of(), and llvm::MachineInstr::tieOperands().
Referenced by llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), and llvm::X86TargetLowering::EmitInstrWithCustomInserter().
◆ emitStoreConditional()
|
inlinevirtual |
Perform a store-conditional operation to Addr.
Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1951 of file TargetLowering.h.
References llvm_unreachable.
◆ emitTrailingFence()
|
virtual |
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::VETargetLowering.
Definition at line 2263 of file TargetLoweringBase.cpp.
References Builder, and llvm::isAcquireOrStronger().
◆ enableAggressiveFMAFusion() [1/2]
|
inlinevirtual |
Return true if target always benefits from combining into FMA for a given value type.
This must typically return false on targets where FMA takes more cycles to execute than FADD.
Reimplemented in llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::NVPTXTargetLowering, and llvm::SITargetLowering.
Definition at line 823 of file TargetLowering.h.
◆ enableAggressiveFMAFusion() [2/2]
|
inlinevirtual |
Return true if target always benefits from combining into FMA for a given value type.
This must typically return false on targets where FMA takes more cycles to execute than FADD.
Reimplemented in llvm::SITargetLowering.
Definition at line 828 of file TargetLowering.h.
◆ enableExtLdPromotion()
|
inline |
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Definition at line 804 of file TargetLowering.h.
References EnableExtLdPromotion.
◆ fallBackToDAGISel()
|
inlinevirtual |
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 559 of file TargetLowering.h.
◆ finalizeLowering()
|
virtual |
Execute target specific actions to finalize target lowering.
This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.
Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.
Definition at line 2195 of file TargetLoweringBase.cpp.
References llvm::MachineRegisterInfo::freezeReservedRegs(), and llvm::MachineFunction::getRegInfo().
Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::ARMTargetLowering::finalizeLowering(), and INITIALIZE_PASS().
◆ findRepresentativeClass()
|
protectedvirtual |
Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.
Definition at line 1221 of file TargetLoweringBase.cpp.
References llvm::TargetRegisterInfo::getNumRegClasses(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getSpillSize(), i, isLegalRC(), llvm::SuperRegClassIterator::isValid(), llvm::BitVector::set_bits(), llvm::BitVector::setBitsInMask(), llvm::MVT::SimpleTy, and TRI.
Referenced by computeRegisterProperties(), llvm::ARMTargetLowering::findRepresentativeClass(), and llvm::X86TargetLowering::findRepresentativeClass().
◆ generateFMAsInMachineCombiner()
|
inlinevirtual |
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 2948 of file TargetLowering.h.
◆ getABIAlignmentForCallingConv()
|
inlinevirtual |
Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.
Reimplemented in llvm::ARMTargetLowering, and llvm::MipsTargetLowering.
Definition at line 1586 of file TargetLowering.h.
References DL.
◆ getAddrModeArguments()
|
inlinevirtual |
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.
This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.
Reimplemented in llvm::SITargetLowering.
Definition at line 2481 of file TargetLowering.h.
◆ getAsmOperandValueType()
|
inlinevirtual |
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1448 of file TargetLowering.h.
References DL, and getValueType().
Referenced by llvm::AArch64TargetLowering::getAsmOperandValueType(), llvm::InlineAsmLowering::lowerInlineAsm(), and llvm::TargetLowering::ParseConstraints().
◆ getAtomicMemOperandFlags()
| MachineMemOperand::Flags TargetLoweringBase::getAtomicMemOperandFlags | ( | const Instruction & | AI, |
| const DataLayout & | DL | ||
| ) | const |
Definition at line 2236 of file TargetLoweringBase.cpp.
References getTargetMMOFlags(), llvm_unreachable, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::MachineMemOperand::MOVolatile.
◆ getBooleanContents() [1/2]
|
inline |
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.
"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.
Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.
Definition at line 853 of file TargetLowering.h.
References llvm::HexagonMCInstrInfo::isFloat().
Referenced by llvm::SelectionDAG::computeKnownBits(), llvm::GISelKnownBits::computeKnownBitsImpl(), llvm::GISelKnownBits::computeNumSignBits(), llvm::SelectionDAG::ComputeNumSignBits(), extractBooleanFlip(), llvm::SelectionDAG::FoldConstantArithmetic(), getAsCarry(), llvm::SelectionDAG::getBoolConstant(), getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::getICmpTrueVal(), llvm::TargetLowering::isConstFalseVal(), llvm::isConstTrueVal(), llvm::TargetLowering::isConstTrueVal(), llvm::TargetLowering::isExtendedTrueVal(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), promoteTargetBoolean(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::TargetLowering::SimplifySetCC().
◆ getBooleanContents() [2/2]
|
inline |
Definition at line 859 of file TargetLowering.h.
References getBooleanContents().
◆ getBypassSlowDivWidths()
|
inline |
Returns map of slow types for division or remainder with corresponding fast types.
Definition at line 545 of file TargetLowering.h.
◆ getByValTypeAlignment()
|
virtual |
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
This is the actual alignment, not its logarithm.
Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 1666 of file TargetLoweringBase.cpp.
References DL.
◆ getCmpLibcallCC()
|
inline |
Get the CondCode that's to be used to test the result of the comparison libcall against zero.
Definition at line 3072 of file TargetLowering.h.
Referenced by llvm::TargetLowering::softenSetCCOperands().
◆ getCmpLibcallReturnType()
|
virtual |
Return the ValueType for comparison libcalls.
Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.
Reimplemented in llvm::AVRTargetLowering, and llvm::MSP430TargetLowering.
Definition at line 1481 of file TargetLoweringBase.cpp.
References llvm::MVT::i32.
Referenced by llvm::TargetLowering::softenSetCCOperands().
◆ getCondCodeAction()
|
inline |
Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1399 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), Promote, Shift, and llvm::MVT::SimpleTy.
Referenced by isCondCodeLegal(), isCondCodeLegalOrCustom(), and llvm::TargetLowering::LegalizeSetCCCondCode().
◆ getCustomCtpopCost()
|
inlinevirtual |
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.
Definition at line 638 of file TargetLowering.h.
Referenced by simplifySetCCWithCTPOP().
◆ getCustomOperationAction()
|
inlinevirtual |
How to legalize this custom operation?
Reimplemented in llvm::VETargetLowering.
Definition at line 1084 of file TargetLowering.h.
References Legal.
◆ getDefaultSafeStackPointerLocation()
|
protected |
Definition at line 1843 of file TargetLoweringBase.cpp.
References llvm::GlobalValue::ExternalLinkage, llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::GlobalValue::InitialExecTLSModel, M, llvm::GlobalValue::NotThreadLocal, and llvm::report_fatal_error().
Referenced by llvm::X86TargetLowering::getSafeStackPointerLocation(), and getSafeStackPointerLocation().
◆ getDivRefinementSteps()
| int TargetLoweringBase::getDivRefinementSteps | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return the refinement step count for a division of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 2190 of file TargetLoweringBase.cpp.
References getOpRefinementSteps(), and getRecipEstimateForFunc().
◆ getExceptionPointerRegister()
|
inlinevirtual |
If a physical register, this returns the register that receives the exception address on entry to an EH pad.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, llvm::HexagonTargetLowering, llvm::XCoreTargetLowering, and llvm::SparcTargetLowering.
Definition at line 1793 of file TargetLowering.h.
Referenced by GetEHSpillList(), and llvm::MachineBasicBlock::liveout_begin().
◆ getExceptionSelectorRegister()
|
inlinevirtual |
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, llvm::HexagonTargetLowering, llvm::XCoreTargetLowering, and llvm::SparcTargetLowering.
Definition at line 1800 of file TargetLowering.h.
Referenced by GetEHSpillList(), and llvm::MachineBasicBlock::liveout_begin().
◆ getExtendForAtomicCmpSwapArg()
|
inlinevirtual |
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is separate from getExtendForAtomicOps, which is concerned with the sign-extension of the instruction's output, whereas here we are concerned with the sign-extension of the input. For targets with compare-and-swap instructions (or sub-word comparisons in their LL/SC loop expansions), the input can be ANY_EXTEND, but the output will still have a specific extension.
Reimplemented in llvm::SystemZTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2129 of file TargetLowering.h.
References llvm::ISD::ANY_EXTEND.
◆ getExtendForAtomicOps()
|
inlinevirtual |
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
Reimplemented in llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, and llvm::VETargetLowering.
Definition at line 2117 of file TargetLowering.h.
References llvm::ISD::ZERO_EXTEND.
Referenced by llvm::SelectionDAG::computeKnownBits(), and llvm::SelectionDAG::ComputeNumSignBits().
◆ getExtendForContent()
|
inlinestatic |
Definition at line 317 of file TargetLowering.h.
References llvm::ISD::ANY_EXTEND, Content, llvm_unreachable, llvm::ISD::SIGN_EXTEND, UndefinedBooleanContent, llvm::ISD::ZERO_EXTEND, ZeroOrNegativeOneBooleanContent, and ZeroOrOneBooleanContent.
Referenced by llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), promoteTargetBoolean(), and llvm::TargetLowering::SimplifySetCC().
◆ getFenceOperandTy()
|
inlinevirtual |
Return the type for operands of fence.
TODO: Let fence operands be of i32 type and remove this.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 379 of file TargetLowering.h.
References DL, and getPointerTy().
◆ getFixedPointOperationAction()
|
inline |
Some fixed point operations may be natively supported by the target but only for specific scales.
This method allows for checking if the width is supported by the target for a given operation that may depend on scale.
Definition at line 1111 of file TargetLowering.h.
References Expand, getOperationAction(), isSupportedFixedPointOperation(), Legal, llvm_unreachable, llvm::ISD::SDIVFIX, llvm::ISD::SDIVFIXSAT, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::UDIVFIX, llvm::ISD::UDIVFIXSAT, llvm::ISD::UMULFIX, and llvm::ISD::UMULFIXSAT.
Referenced by expandDivFix().
◆ getFrameIndexTy()
|
inline |
Return the type for frame index, which is determined by the alloca address space specified through the data layout.
Definition at line 367 of file TargetLowering.h.
References DL, and getPointerTy().
Referenced by addStackMapLiveVars(), llvm::SelectionDAG::CreateStackTemporary(), getAddressForMemoryInput(), llvm::SelectionDAGBuilder::getFrameIndexTy(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::SelectionDAGBuilder::getValueImpl(), and llvm::TargetLowering::LowerCallTo().
◆ getGatherAllAliasesMaxDepth()
|
inline |
Definition at line 1622 of file TargetLowering.h.
References GatherAllAliasesMaxDepth.
◆ getIndexedLoadAction()
|
inline |
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1334 of file TargetLowering.h.
Referenced by isIndexedLoadLegal().
◆ getIndexedMaskedLoadAction()
|
inline |
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1362 of file TargetLowering.h.
Referenced by isIndexedMaskedLoadLegal().
◆ getIndexedMaskedStoreAction()
|
inline |
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1376 of file TargetLowering.h.
Referenced by isIndexedMaskedStoreLegal().
◆ getIndexedStoreAction()
|
inline |
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1348 of file TargetLowering.h.
Referenced by isIndexedStoreLegal().
◆ getIRStackGuard()
|
virtual |
If the target has a standard location for the stack protector guard, returns the address of that location.
Otherwise, returns nullptr. DEPRECATED: please override useLoadStackGuardNode and customize LOAD_STACK_GUARD, or customize @llvm.stackguard().
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1936 of file TargetLoweringBase.cpp.
References G, llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), getTargetMachine(), llvm::GlobalValue::HiddenVisibility, and M.
Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), llvm::X86TargetLowering::getIRStackGuard(), and getStackGuard().
◆ getLibcallCallingConv()
|
inline |
Get the CallingConv that should be used for the specified libcall.
Definition at line 3082 of file TargetLowering.h.
◆ getLibcallName()
|
inline |
Get the libcall routine name for the specified libcall.
Definition at line 3060 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), llvm::SparcTargetLowering::LowerOperation(), LowerSINT_TO_FP(), LowerUINT_TO_FP(), optimizeCall(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::returnTypeIsEligibleForTailCall(), and llvm::X86TargetLowering::X86TargetLowering().
◆ getLoadExtAction()
|
inline |
Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1274 of file TargetLowering.h.
References assert(), Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::ISD::LAST_LOADEXT_TYPE, Shift, llvm::MVT::SimpleTy, and llvm::MVT::VALUETYPE_SIZE.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), isLoadExtLegal(), and isLoadExtLegalOrCustom().
◆ getLoadMemOperandFlags()
| MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags | ( | const LoadInst & | LI, |
| const DataLayout & | DL | ||
| ) | const |
Definition at line 2200 of file TargetLoweringBase.cpp.
References DL, llvm::LoadInst::getPointerOperand(), getTargetMMOFlags(), llvm::Value::getType(), llvm::Instruction::hasMetadata(), llvm::isDereferenceablePointer(), llvm::LoadInst::isVolatile(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONonTemporal, and llvm::MachineMemOperand::MOVolatile.
◆ getMaxAtomicSizeInBitsSupported()
|
inline |
Returns the maximum atomic operation size (in bits) supported by the backend.
Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.
Definition at line 1917 of file TargetLowering.h.
Referenced by atomicSizeSupported().
◆ getMaxExpandSizeMemcmp()
|
inline |
Get maximum # of load operations permitted for memcmp.
This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1666 of file TargetLowering.h.
References MaxLoadsPerMemcmp, and MaxLoadsPerMemcmpOptSize.
Referenced by llvm::BPFTTIImpl::enableMemCmpExpansion(), llvm::PPCTTIImpl::enableMemCmpExpansion(), and llvm::X86TTIImpl::enableMemCmpExpansion().
◆ getMaxGluedStoresPerMemcpy()
|
inlinevirtual |
Get maximum # of store operations to be glued together.
This function returns the maximum number of store operations permitted to glue together during lowering of llvm.memcpy. The value is set by
Definition at line 1656 of file TargetLowering.h.
References MaxGluedStoresPerMemcpy.
Referenced by getMemcpyLoadsAndStores().
◆ getMaximumJumpTableSize()
| unsigned TargetLoweringBase::getMaximumJumpTableSize | ( | ) | const |
Return upper limit for number of entries in a jump table.
Zero if no limit.
Definition at line 1986 of file TargetLoweringBase.cpp.
References MaximumJumpTableSize.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), and isSuitableForJumpTable().
◆ getMaxPermittedBytesForAlignment()
|
virtual |
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
Definition at line 2004 of file TargetLoweringBase.cpp.
◆ getMaxStoresPerMemcpy()
|
inline |
Get maximum # of store operations permitted for llvm.memcpy.
This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1647 of file TargetLowering.h.
References MaxStoresPerMemcpy, and MaxStoresPerMemcpyOptSize.
Referenced by getMemcpyLoadsAndStores(), llvm::ARMTTIImpl::getNumMemOps(), and llvm::LegalizerHelper::lowerMemCpyFamily().
◆ getMaxStoresPerMemmove()
|
inline |
Get maximum # of store operations permitted for llvm.memmove.
This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1676 of file TargetLowering.h.
References MaxStoresPerMemmove, and MaxStoresPerMemmoveOptSize.
Referenced by getMemmoveLoadsAndStores(), and llvm::ARMTTIImpl::getNumMemOps().
◆ getMaxStoresPerMemset()
|
inline |
Get maximum # of store operations permitted for llvm.memset.
This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1637 of file TargetLowering.h.
References MaxStoresPerMemset, and MaxStoresPerMemsetOptSize.
Referenced by getMemsetStores(), and llvm::ARMTTIImpl::getNumMemOps().
◆ getMaxSupportedInterleaveFactor()
|
inlinevirtual |
Get the maximum supported factor for interleaved memory accesses.
Default to be the minimum interleave factor: 2.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2803 of file TargetLowering.h.
Referenced by llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().
◆ getMemValueType()
|
inline |
Definition at line 1477 of file TargetLowering.h.
References DL, llvm::Type::getContext(), llvm::EVT::getEVT(), getPointerMemTy(), getValueType(), and llvm::EVT::getVectorVT().
Referenced by llvm::ComputeValueVTs(), getAddressForMemoryInput(), setInfoSVEStN(), and llvm::SelectionDAGBuilder::visitSwitchCase().
◆ getMinCmpXchgSizeInBits()
|
inline |
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
Any smaller operations are widened in AtomicExpandPass.
Note that unlike operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.
Definition at line 1928 of file TargetLowering.h.
◆ getMinFunctionAlignment()
|
inline |
Return the minimum function alignment.
Definition at line 1814 of file TargetLowering.h.
◆ getMinimumJumpTableDensity()
| unsigned TargetLoweringBase::getMinimumJumpTableDensity | ( | bool | OptForSize | ) | const |
Return lower limit of the density in a jump table.
Definition at line 1982 of file TargetLoweringBase.cpp.
References JumpTableDensity, and OptsizeJumpTableDensity.
Referenced by isSuitableForJumpTable().
◆ getMinimumJumpTableEntries()
|
virtual |
Return lower limit for number of blocks in a jump table.
Reimplemented in llvm::VETargetLowering.
Definition at line 1974 of file TargetLoweringBase.cpp.
References MinimumJumpTableEntries.
Referenced by llvm::VETargetLowering::getMinimumJumpTableEntries().
◆ getMinStackArgumentAlignment()
|
inline |
Return the minimum stack alignment of an argument.
Definition at line 1809 of file TargetLowering.h.
◆ getNumRegisters()
|
inlinevirtual |
Return the number of registers that this ValueType will eventually require.
This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.
RegisterVT may be passed as a way to override the default settings, for instance with i128 inline assembly operands on SystemZ.
Reimplemented in llvm::SystemZTargetLowering.
Definition at line 1546 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::BitWidth, Context, getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::computeLegalValueVTs(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::SystemZTargetLowering::getNumRegisters(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), getNumRegistersForCallingConv(), getRegistersForValue(), llvm::FunctionLoweringInfo::getValueFromVirtualReg(), llvm::TargetLowering::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RegsForValue::RegsForValue(), and llvm::FunctionLoweringInfo::set().
◆ getNumRegistersForCallingConv()
|
inlinevirtual |
Certain targets require unusual breakdowns of certain types.
For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Reimplemented in llvm::X86TargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, llvm::SITargetLowering, and llvm::SPIRVTargetLowering.
Definition at line 1578 of file TargetLowering.h.
References Context, and getNumRegisters().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::CallLowering::determineAssignments(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::CallLowering::getReturnInfo(), llvm::GetReturnInfo(), llvm::SystemZTargetLowering::LowerCall(), llvm::AArch64CallLowering::lowerReturn(), and llvm::RegsForValue::RegsForValue().
◆ getOperationAction()
|
inline |
Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1091 of file TargetLowering.h.
References llvm::array_lengthof(), Custom, Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), and llvm::MVT::SimpleTy.
Referenced by getFixedPointOperationAction(), getStrictFPOperationAction(), getTypeToPromoteTo(), isLoadBitCastBeneficial(), isOperationCustom(), isOperationExpand(), isOperationLegal(), isOperationLegalOrCustom(), isOperationLegalOrCustomOrPromote(), isOperationLegalOrPromote(), llvm::ARMTTIImpl::maybeLoweredToCall(), and llvm::SystemZTargetLowering::SystemZTargetLowering().
◆ getOptimalMemOpLLT()
|
inlinevirtual |
LLT returning variant.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1758 of file TargetLowering.h.
Referenced by findGISelOptimalMemOpLowering().
◆ getOptimalMemOpType()
|
inlinevirtual |
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented in llvm::PPCTargetLowering, llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1751 of file TargetLowering.h.
References llvm::MVT::Other.
Referenced by llvm::TargetLowering::findOptimalMemOpLowering().
◆ getPointerMemTy()
|
inlinevirtual |
Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Reimplemented in llvm::WebAssemblyTargetLowering.
Definition at line 361 of file TargetLowering.h.
References DL, and llvm::MVT::getIntegerVT().
Referenced by getLoadStackGuard(), getMemValueType(), llvm::WebAssemblyTargetLowering::getPointerMemTy(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getPointerTy()
|
inlinevirtual |
Return the pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Reimplemented in llvm::AArch64TargetLowering, and llvm::WebAssemblyTargetLowering.
Definition at line 354 of file TargetLowering.h.
References DL, and llvm::MVT::getIntegerVT().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::X86TargetLowering::BuildFILD(), CheckType(), CheckValueType(), combineGatherScatter(), combineLoad(), combineStore(), combineTargetShuffle(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), createMMXBuildVector(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::RISCVTargetLowering::getAddr(), getAddressForMemoryInput(), getAVX2GatherNode(), getCopyFromParts(), getFenceOperandTy(), getFrameIndexTy(), getGatherNode(), llvm::SelectionDAG::getIntPtrConstant(), getLoadStackGuard(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::WebAssemblyTargetLowering::getPointerTy(), getPrefetchNode(), getProgramPointerTy(), llvm::NVPTXTargetLowering::getPrototype(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getScatterNode(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), getSetCCResultType(), getShiftAmountTy(), llvm::SelectionDAG::getSymbolFunctionGlobalAddress(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getUniformBase(), getVaListSizeInBits(), llvm::SelectionDAGBuilder::getValueImpl(), getValueType(), getVectorIdxTy(), isBLACompatibleAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCTPOP(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::VETargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::R600TargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerReturn_32(), LowerRETURNADDR(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::SparcTargetLowering::makeAddress(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformTruncatingStoreCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::SwiftErrorValueTracking::propagateVRegs(), recoverFramePointer(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), transformCallee(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getPreferredShiftAmountTy()
|
inlinevirtual |
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
Reimplemented in llvm::SITargetLowering.
Definition at line 401 of file TargetLowering.h.
Referenced by llvm::CombinerHelper::applyUMulHToLShr(), llvm::CombinerHelper::buildUDivUsingMul(), llvm::CombinerHelper::matchBitfieldExtractFromAnd(), llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg(), llvm::CombinerHelper::matchBitfieldExtractFromShr(), llvm::CombinerHelper::matchBitfieldExtractFromShrAnd(), llvm::CombinerHelper::matchCombineShlOfExtend(), llvm::CombinerHelper::matchCombineTruncOfShl(), and llvm::CombinerHelper::matchUMulHToLShr().
◆ getPreferredSwitchConditionType()
|
virtual |
Returns preferred type for switch condition.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1605 of file TargetLoweringBase.cpp.
References Context, and getRegisterType().
Referenced by llvm::X86TargetLowering::getPreferredSwitchConditionType().
◆ getPreferredVectorAction()
|
inlinevirtual |
Return the preferred vector type legalization action.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.
Definition at line 460 of file TargetLowering.h.
References llvm::MVT::getVectorElementCount(), llvm::MVT::isPow2VectorType(), llvm::ElementCount::isScalar(), TypePromoteInteger, TypeScalarizeVector, and TypeWidenVector.
Referenced by computeRegisterProperties(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::AArch64TargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), and llvm::X86TargetLowering::getPreferredVectorAction().
◆ getPrefFunctionAlignment()
|
inline |
Return the preferred function alignment.
Definition at line 1817 of file TargetLowering.h.
◆ getPrefLoopAlignment()
|
virtual |
Return the preferred loop alignment.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::SITargetLowering.
Definition at line 1998 of file TargetLoweringBase.cpp.
References Align, llvm::TargetOptions::LoopAlignment, and llvm::TargetMachine::Options.
Referenced by llvm::SITargetLowering::getPrefLoopAlignment(), llvm::PPCTargetLowering::getPrefLoopAlignment(), and llvm::X86TargetLowering::getPrefLoopAlignment().
◆ getProgramPointerTy()
|
inline |
Return the type for code pointers, which is determined by the program address space specified through the data layout.
Definition at line 373 of file TargetLowering.h.
References DL, and getPointerTy().
◆ getRecipEstimateDivEnabled()
| int TargetLoweringBase::getRecipEstimateDivEnabled | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 2180 of file TargetLoweringBase.cpp.
References getOpEnabled(), and getRecipEstimateForFunc().
◆ getRecipEstimateSqrtEnabled()
| int TargetLoweringBase::getRecipEstimateSqrtEnabled | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 2175 of file TargetLoweringBase.cpp.
References getOpEnabled(), and getRecipEstimateForFunc().
◆ getRegClassFor()
|
inlinevirtual |
Return the register class that should be used for the specified value type.
Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.
Definition at line 891 of file TargetLowering.h.
References assert(), and llvm::MVT::SimpleTy.
Referenced by allocateRVVReg(), llvm::CCState::analyzeMustTailForwardedRegisters(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), llvm::FunctionLoweringInfo::CreateReg(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), llvm::SITargetLowering::getRegClassFor(), llvm::ARMTargetLowering::getRegClassFor(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::SwiftErrorValueTracking::propagateVRegs(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::scheduledNode(), unpackFromRegLoc(), and llvm::X86TargetLowering::X86TargetLowering().
◆ getRegisterType() [1/2]
|
inline |
Return the type of registers that this ValueType will eventually require.
Definition at line 1514 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), Context, getRegisterType(), llvm::EVT::getSimpleVT(), getTypeToTransformTo(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.
◆ getRegisterType() [2/2]
Return the type of registers that this ValueType will eventually require.
Definition at line 1508 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.
Referenced by llvm::computeLegalValueVTs(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getNumRegisters(), getPreferredSwitchConditionType(), getRegisterType(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), getRegisterTypeForCallingConv(), llvm::GetReturnInfo(), llvm::MipsTargetLowering::getTypeForExtReturn(), llvm::TargetLowering::getTypeForExtReturn(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), llvm::TargetLowering::LowerCallTo(), and llvm::RegsForValue::RegsForValue().
◆ getRegisterTypeForCallingConv()
|
inlinevirtual |
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
For MIPS all vector types must be passed through the integer register set.
Reimplemented in llvm::X86TargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, llvm::SPIRVTargetLowering, and llvm::SITargetLowering.
Definition at line 1570 of file TargetLowering.h.
References Context, and getRegisterType().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::CallLowering::determineAssignments(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::CallLowering::getReturnInfo(), llvm::GetReturnInfo(), llvm::SystemZTargetLowering::LowerCall(), llvm::AArch64CallLowering::lowerReturn(), and llvm::RegsForValue::RegsForValue().
◆ getRepRegClassCostFor()
|
inlinevirtual |
Return the cost of the 'representative' register class for the specified value type.
Definition at line 920 of file TargetLowering.h.
References llvm::MVT::SimpleTy.
◆ getRepRegClassFor()
|
inlinevirtual |
Return the 'representative' register class for the specified value type.
The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.
Reimplemented in llvm::MipsSETargetLowering.
Definition at line 913 of file TargetLowering.h.
References llvm::MVT::SimpleTy.
Referenced by llvm::MipsSETargetLowering::getRepRegClassFor().
◆ getSafeStackPointerLocation()
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virtual |
Returns the target-specific address of the unsafe stack pointer.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1876 of file TargetLoweringBase.cpp.
References llvm::IRBuilderBase::CreateCall(), getDefaultSafeStackPointerLocation(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPointerTo(), llvm::TargetMachine::getTargetTriple(), llvm::Triple::isAndroid(), and M.
Referenced by llvm::AArch64TargetLowering::getSafeStackPointerLocation(), and llvm::X86TargetLowering::getSafeStackPointerLocation().
◆ getScalarShiftAmountTy()
|
virtual |
Return the type to use for a scalar shift opcode, given the shifted amount type.
Targets should return a legal type if the input type is legal. Targets can return a type that is too small if the input type is illegal.
Reimplemented in llvm::AArch64TargetLowering, llvm::XCoreTargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SITargetLowering, llvm::SystemZTargetLowering, llvm::MipsTargetLowering, llvm::M68kTargetLowering, llvm::SparcTargetLowering, llvm::MSP430TargetLowering, llvm::VETargetLowering, llvm::BPFTargetLowering, llvm::X86TargetLowering, and llvm::AVRTargetLowering.
Definition at line 874 of file TargetLoweringBase.cpp.
References DL, and llvm::MVT::getIntegerVT().
Referenced by getShiftAmountTy().
◆ getScalingFactorCost()
|
inlinevirtual |
Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.
If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well. TODO: Remove default argument
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2523 of file TargetLowering.h.
References DL, and isLegalAddressingMode().
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getScalingFactorCost().
◆ getSchedulingPreference() [1/2]
|
inline |
Return target scheduling preference.
Definition at line 878 of file TargetLowering.h.
Referenced by llvm::createDefaultScheduler(), llvm::PPCTargetLowering::getSchedulingPreference(), and llvm::ScheduleDAGSDNodes::newSUnit().
◆ getSchedulingPreference() [2/2]
|
inlinevirtual |
Some scheduler, e.g.
hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.
Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.
Definition at line 885 of file TargetLowering.h.
References llvm::Sched::None.
◆ getSDagStackGuard()
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 1966 of file TargetLoweringBase.cpp.
References M.
Referenced by getLoadStackGuard(), llvm::ARMTargetLowering::getSDagStackGuard(), llvm::AArch64TargetLowering::getSDagStackGuard(), llvm::PPCTargetLowering::getSDagStackGuard(), and llvm::X86TargetLowering::getSDagStackGuard().
◆ getSetCCResultType()
|
virtual |
Return the ValueType of the result of SETCC operations.
Reimplemented in llvm::NVPTXTargetLowering, llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, llvm::ARMTargetLowering, llvm::SITargetLowering, llvm::MipsTargetLowering, llvm::M68kTargetLowering, llvm::SparcTargetLowering, llvm::AVRTargetLowering, llvm::VETargetLowering, llvm::BPFTargetLowering, llvm::CSKYTargetLowering, llvm::SystemZTargetLowering, llvm::R600TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1475 of file TargetLoweringBase.cpp.
References assert(), DL, getPointerTy(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.
Referenced by llvm::TargetLowering::BuildUDIV(), combineFMinNumFMaxNum(), combinePredicateReduction(), combineShiftAnd1ToBitTest(), combineVSelectWithAllOnesOrZeros(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandMUL_LOHI(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::getSqrtInputTest(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerMULO(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), promoteTargetBoolean(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().
◆ getShiftAmountTy()
| EVT TargetLoweringBase::getShiftAmountTy | ( | EVT | LHSTy, |
| const DataLayout & | DL, | ||
| bool | LegalTypes = true |
||
| ) | const |
Returns the type for the shift amount of a shift opcode.
For vectors, returns the input type. For scalars, behavior depends on LegalTypes. If LegalTypes is true, calls getScalarShiftAmountTy, otherwise uses pointer type. If getScalarShiftAmountTy or pointer type cannot represent all possible shift amounts, returns MVT::i32. In general, LegalTypes should be set to true for calls during type legalization and after type legalization has been completed.
Definition at line 879 of file TargetLoweringBase.cpp.
References assert(), DL, getPointerTy(), getScalarShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::EVT::isVector(), and llvm::Log2_32_Ceil().
Referenced by BuildExactSDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), expandDivFix(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getCopyFromParts(), GetExponent(), getLimitedPrecisionExp2(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SelectionDAG::getShiftAmountOperand(), llvm::AMDGPUTargetLowering::performTruncateCombine(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifySetCC().
◆ getSimpleValueType()
|
inline |
Return the MVT corresponding to this LLVM type. See getValueType.
Definition at line 1497 of file TargetLowering.h.
References DL, llvm::EVT::getSimpleVT(), and getValueType().
Referenced by llvm::InlineAsmLowering::lowerInlineAsm(), and llvm::TargetLowering::ParseConstraints().
◆ getSqrtRefinementSteps()
| int TargetLoweringBase::getSqrtRefinementSteps | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return the refinement step count for a square root of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 2185 of file TargetLoweringBase.cpp.
References getOpRefinementSteps(), and getRecipEstimateForFunc().
◆ getSSPStackGuardCheck()
If the target has a standard stack protection check function that performs validation and error handling, returns the function.
Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 1970 of file TargetLoweringBase.cpp.
Referenced by llvm::ARMTargetLowering::getSSPStackGuardCheck(), llvm::AArch64TargetLowering::getSSPStackGuardCheck(), llvm::X86TargetLowering::getSSPStackGuardCheck(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getStackPointerRegisterToSaveRestore()
|
inline |
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 1786 of file TargetLowering.h.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::calculateDbgEntityHistory(), TransferTracker::isEntryValueValue(), isRegOtherThanSPAndFP(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LegalizerHelper::lowerDynStackAlloc(), LiveDebugValues::MLocTracker::MLocTracker(), and llvm::FunctionLoweringInfo::set().
◆ getStackProbeSymbolName()
|
inlinevirtual |
Reimplemented in llvm::X86TargetLowering.
Definition at line 1878 of file TargetLowering.h.
◆ getStoreMemOperandFlags()
| MachineMemOperand::Flags TargetLoweringBase::getStoreMemOperandFlags | ( | const StoreInst & | SI, |
| const DataLayout & | DL | ||
| ) | const |
Definition at line 2220 of file TargetLoweringBase.cpp.
References getTargetMMOFlags(), llvm::MachineMemOperand::MONonTemporal, llvm::MachineMemOperand::MOStore, llvm::MachineMemOperand::MOVolatile, and SI.
◆ getStrictFPOperationAction()
|
inline |
Definition at line 1140 of file TargetLowering.h.
References getOperationAction(), and llvm_unreachable.
◆ getTargetMachine()
|
inline |
Definition at line 347 of file TargetLowering.h.
Referenced by llvm::WebAssemblyTTIImpl::areInlineCompatible(), llvm::ARMTTIImpl::areInlineCompatible(), llvm::GCNTTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areTypesABICompatible(), llvm::ARMTargetLowering::ARMTargetLowering(), checkAddrSpaceIsValidForLibcall(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::finalizeLowering(), llvm::RISCVTargetLowering::getAddr(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getAssumedAddrSpace(), llvm::NVPTXTargetLowering::getDivF32Level(), llvm::AMDGPUTargetLowering::getImplicitParameterOffset(), getIRStackGuard(), llvm::RISCVTargetLowering::getJumpTableEncoding(), llvm::TargetLowering::getJumpTableEncoding(), llvm::PPCTargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getOptimalMemOpType(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getPredicatedAddrSpace(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::isAccessedAsGotIndirect(), llvm::SITargetLowering::isFreeAddrSpaceCast(), llvm::MipsTargetLowering::isJumpTableRelative(), isJumpTableRelative(), llvm::X86TargetLowering::isLegalAddressingMode(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isNoopAddrSpaceCast(), llvm::TargetLowering::isOffsetFoldingLegal(), llvm::SystemZSubtarget::isPC32DBLSymbol(), llvm::TargetLowering::isPositionIndependent(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::PPCTargetLowering::isProfitableToHoist(), IsSmallObject(), llvm::M68kCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(), llvm::SITargetLowering::PerformDAGCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::shouldBuildRelLookupTables(), llvm::SITargetLowering::shouldEmitFixup(), llvm::SITargetLowering::shouldEmitGOTReloc(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::AArch64TargetLowering::shouldExpandAtomicLoadInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), llvm::AArch64TargetLowering::shouldExpandAtomicRMWInIR(), llvm::HexagonTargetLowering::shouldReduceLoadWidth(), llvm::SITargetLowering::shouldUseLDSConstAddress(), llvm::CSKYSubtarget::useHardFloatABI(), llvm::NVPTXTargetLowering::usePrecSqrtF32(), and llvm::AArch64Subtarget::useSmallAddressing().
◆ getTargetMMOFlags()
|
inlinevirtual |
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.
The default implementation does nothing.
Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.
Definition at line 421 of file TargetLowering.h.
References llvm::MachineMemOperand::MONone.
Referenced by getAtomicMemOperandFlags(), getLoadMemOperandFlags(), and getStoreMemOperandFlags().
◆ getTgtMemIntrinsic()
|
inlinevirtual |
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).
If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::NVPTXTargetLowering, llvm::RISCVTargetLowering, llvm::HexagonTargetLowering, and llvm::SITargetLowering.
Definition at line 1047 of file TargetLowering.h.
◆ getTruncStoreAction()
|
inline |
Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1300 of file TargetLowering.h.
References assert(), Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::MVT::SimpleTy, and llvm::MVT::VALUETYPE_SIZE.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), isTruncStoreLegal(), and isTruncStoreLegalOrCustom().
◆ getTypeAction() [1/2]
|
inline |
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').
'Custom' is not an option.
Definition at line 968 of file TargetLowering.h.
References Context.
Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::X86TargetLowering::decomposeMulByConstant(), findMemType(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getCopyToPartsVector(), llvm::X86TargetLowering::getSetCCResultType(), getTypeToExpandTo(), getVectorTypeBreakdown(), LowerStore(), OptimizeNoopCopyExpression(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), and shouldNormalizeToSelectSequence().
◆ getTypeAction() [2/2]
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inline |
Definition at line 971 of file TargetLowering.h.
References llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction().
◆ getTypeLegalizationCost()
| std::pair< InstructionCost, MVT > TargetLoweringBase::getTypeLegalizationCost | ( | const DataLayout & | DL, |
| Type * | Ty | ||
| ) | const |
Estimate the cost of type-legalization and the legalized type.
Definition at line 1808 of file TargetLoweringBase.cpp.
References DL, llvm::Type::getContext(), llvm::InstructionCost::getInvalid(), llvm::EVT::getSimpleVT(), getValueType(), llvm::MVT::i64, llvm::EVT::isSimple(), TypeExpandInteger, TypeLegal, TypeScalarizeScalableVector, and TypeSplitVector.
Referenced by llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::HexagonTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::HexagonTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::HexagonTTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedAddReductionCost(), llvm::PPCTTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), llvm::HexagonTTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::PPCTTIImpl::getMemoryOpCost(), llvm::X86TTIImpl::getMemoryOpCost(), llvm::ARMTTIImpl::getMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), llvm::X86TTIImpl::getMinMaxCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getNumberOfParts(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getRegUsageForType(), llvm::X86TTIImpl::getReplicationShuffleCost(), llvm::X86TTIImpl::getScalarizationOverhead(), llvm::RISCVTTIImpl::getShuffleCost(), llvm::PPCTTIImpl::getShuffleCost(), llvm::X86TTIImpl::getShuffleCost(), llvm::ARMTTIImpl::getShuffleCost(), llvm::RISCVTTIImpl::getSpliceCost(), llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getTypeBasedIntrinsicInstrCost(), llvm::SITargetLowering::getTypeLegalizationCost(), llvm::PPCTTIImpl::getUserCost(), llvm::X86TTIImpl::getVectorInstrCost(), llvm::ARMTTIImpl::getVectorInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getVectorInstrCost(), llvm::PPCTTIImpl::getVPMemoryOpCost(), and llvm::PPCTTIImpl::vectorCostAdjustmentFactor().
◆ getTypeToExpandTo()
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inline |
For types supported by the target, this is an identity function.
For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.
Definition at line 989 of file TargetLowering.h.
References assert(), Context, getTypeAction(), getTypeToTransformTo(), llvm::EVT::isVector(), llvm_unreachable, TypeExpandInteger, and TypeLegal.
◆ getTypeToPromoteTo()
If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition at line 1425 of file TargetLowering.h.
References assert(), getOperationAction(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::isVoid, Promote, and llvm::MVT::SimpleTy.
Referenced by isLoadBitCastBeneficial().
◆ getTypeToTransformTo()
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inline |
For types supported by the target, this is an identity function.
For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.
Definition at line 981 of file TargetLowering.h.
References Context.
Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineMinNumMaxNum(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::X86TargetLowering::decomposeMulByConstant(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getConstant(), getMemcpyLoadsAndStores(), getPTest(), getRegisterType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getStoreMinimumVF(), getTypeToExpandTo(), getVectorTypeBreakdown(), LowerMSCATTER(), LowerStore(), llvm::VETargetLowering::lowerToVVP(), OptimizeNoopCopyExpression(), and llvm::X86TargetLowering::ReplaceNodeResults().
◆ getVaListSizeInBits()
|
inlinevirtual |
Returns the size of the platform's va_list object.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1627 of file TargetLowering.h.
References DL, getPointerTy(), and llvm::MVT::getSizeInBits().
◆ getValueType()
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inline |
Return the EVT corresponding to this LLVM type.
This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.
Definition at line 1457 of file TargetLowering.h.
References DL, llvm::Type::getContext(), llvm::EVT::getEVT(), getPointerTy(), and llvm::EVT::getVectorVT().
Referenced by analyzeCallOperands(), combineArithReduction(), combineConcatVectorOps(), combineMulToPMULDQ(), combineToHorizontalAddSub(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ComputeValueVTs(), detectAVGPattern(), detectPMADDUBSW(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), getAsmOperandValueType(), llvm::X86TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedAddReductionCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getFPOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::PPCTTIImpl::getMemoryOpCost(), llvm::X86TTIImpl::getMemoryOpCost(), llvm::ARMTTIImpl::getMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), getMemValueType(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::GCNTTIImpl::getMinMaxReductionCost(), llvm::NVPTXTargetLowering::getPrototype(), llvm::X86TTIImpl::getShuffleCost(), getSimpleValueType(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getStoreMinimumVF(), llvm::RISCVTargetLowering::getTgtMemIntrinsic(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getTypeLegalizationCost(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::PPCTTIImpl::getVPMemoryOpCost(), llvm::MipsTTIImpl::hasDivRemOp(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::X86TTIImpl::hasDivRemOp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), isExtLoad(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedLoadLegal(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedStoreLegal(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::PPCTargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), isSupportedType(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerFormalArguments(), matchPMADDWD(), matchPMADDWD_2(), llvm::ARMTTIImpl::maybeLoweredToCall(), narrowVectorSelect(), OptimizeExtractBits(), OptimizeNoopCopyExpression(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and SinkShiftAndTruncate().
◆ getValueTypeActions()
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inline |
Definition at line 960 of file TargetLowering.h.
◆ getVectorIdxTy()
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inlinevirtual |
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.
Reimplemented in llvm::SystemZTargetLowering, llvm::SPIRVTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 408 of file TargetLowering.h.
References DL, and getPointerTy().
Referenced by llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::SparcTargetLowering::LowerCall_32(), and llvm::SparcTargetLowering::LowerReturn_32().
◆ getVectorTypeBreakdown()
| unsigned TargetLoweringBase::getVectorTypeBreakdown | ( | LLVMContext & | Context, |
| EVT | VT, | ||
| EVT & | IntermediateVT, | ||
| unsigned & | NumIntermediates, | ||
| MVT & | RegisterVT | ||
| ) | const |
Vector types are broken down into some number of legal first class types.
getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.
For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
Definition at line 1493 of file TargetLoweringBase.cpp.
References llvm::LinearPolySize< LeafTy >::coefficientNextPowerOf2(), Context, llvm::divideCeil(), llvm::LinearPolySize< LeafTy >::divideCoefficientBy(), llvm::LinearPolySize< ElementCount >::getFixed(), llvm::TypeSize::getKnownMinSize(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeToTransformTo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), llvm::LinearPolySize< LeafTy >::isScalable(), llvm::ElementCount::isScalar(), isTypeLegal(), llvm::EVT::isVector(), llvm::report_fatal_error(), llvm::X86II::TA, TypeLegal, TypePromoteInteger, and TypeWidenVector.
Referenced by getCopyFromPartsVector(), getCopyToPartsVector(), getNumRegisters(), llvm::SelectionDAG::getReducedAlign(), getRegisterType(), and getVectorTypeBreakdownForCallingConv().
◆ getVectorTypeBreakdownForCallingConv()
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inlinevirtual |
Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.
This occurs even if the vector type is legal.
Reimplemented in llvm::X86TargetLowering, llvm::MipsTargetLowering, and llvm::SITargetLowering.
Definition at line 1020 of file TargetLowering.h.
References Context, and getVectorTypeBreakdown().
Referenced by getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), and llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv().
◆ getVPExplicitVectorLengthTy()
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inlinevirtual |
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.
It must be a legal scalar integer type, and must be at least as large as i32. The EVL is implicitly zero-extended to any larger type.
Definition at line 416 of file TargetLowering.h.
References llvm::MVT::i32.
◆ hasAndNot()
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inlinevirtual |
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::VETargetLowering.
Definition at line 715 of file TargetLowering.h.
References hasAndNotCompare(), and X.
Referenced by foldVSelectToSignBitSplatMask().
◆ hasAndNotCompare()
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inlinevirtual |
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.
This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.
Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0
Reimplemented in llvm::PPCTargetLowering, llvm::X86TargetLowering, llvm::RISCVTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 708 of file TargetLowering.h.
Referenced by hasAndNot().
◆ hasBigEndianPartOrdering()
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inline |
When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.
Definition at line 1611 of file TargetLowering.h.
References DL, and llvm::MVT::ppcf128.
Referenced by getCopyFromParts(), and llvm::CallLowering::handleAssignments().
◆ hasBitPreservingFPLogic()
|
inlinevirtual |
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.
This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, and llvm::RISCVTargetLowering.
Definition at line 654 of file TargetLowering.h.
Referenced by foldBitcastedFPLogic().
◆ hasBitTest()
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.
Reimplemented in llvm::X86TargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 725 of file TargetLowering.h.
Referenced by combineShiftAnd1ToBitTest(), and shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().
◆ hasExtractBitsInsn()
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inline |
Return true if the target has BitExtract instructions.
Definition at line 456 of file TargetLowering.h.
◆ hasFastEqualityCompare()
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inlinevirtual |
Return the preferred operand type if the target has a quick way to compare integer values of the given size.
Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.
Reimplemented in llvm::X86TargetLowering.
Definition at line 691 of file TargetLowering.h.
References llvm::MVT::getIntegerVT(), llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, and isTypeLegal().
◆ hasInlineStackProbe()
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inlinevirtual |
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::SystemZTargetLowering.
Definition at line 1876 of file TargetLowering.h.
Referenced by llvm::SystemZELFFrameLowering::emitPrologue().
◆ hasMultipleConditionRegisters()
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inline |
Return true if multiple condition registers are available.
Definition at line 451 of file TargetLowering.h.
Referenced by shouldNormalizeToSelectSequence(), and sinkCmpExpression().
◆ hasPairedLoad()
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.
RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.
This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).
In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 2793 of file TargetLowering.h.
◆ hasStackProbeSymbol()
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inlinevirtual |
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1874 of file TargetLowering.h.
◆ hasStandaloneRem()
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inlinevirtual |
Return true if the target can handle a standalone remainder operation.
Reimplemented in llvm::VETargetLowering, and llvm::ARMTargetLowering.
Definition at line 499 of file TargetLowering.h.
◆ hasTargetDAGCombine()
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inline |
If true, the target has custom DAG combine transformations that it can perform for the specified node.
Definition at line 1617 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), and llvm::AMDGPU::CPol::NT.
◆ hasVectorBlend()
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inlinevirtual |
Return true if the target has a vector blend instruction.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2799 of file TargetLowering.h.
Referenced by llvm::SelectionDAG::getVectorShuffle().
◆ initActions()
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protected |
Initialize all of the actions to default values.
Definition at line 731 of file TargetLoweringBase.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ABS, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, AddPromotedToType(), llvm::MVT::all_valuetypes(), llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::sys::path::begin(), llvm::ISD::BITREVERSE, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DEBUGTRAP, llvm::sys::path::end(), Expand, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FCBRT, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMAD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FNEARBYINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::MVT::fp_valuetypes(), llvm::ISD::FPOWI, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FTRUNC, llvm::ISD::GET_DYNAMIC_AREA_OFFSET, llvm::MVT::getIntegerVT(), llvm::MVT::i64, llvm::ISD::IS_FPCLASS, llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm::ISD::LRINT, llvm::ISD::LROUND, llvm::MVT::Other, llvm::ISD::PARITY, llvm::ISD::PRE_INC, llvm::ISD::PREFETCH, Promote, llvm::ISD::READCYCLECOUNTER, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SADDSAT, llvm::ISD::SDIVFIX, llvm::ISD::SDIVFIXSAT, llvm::ISD::SETCCCARRY, setIndexedLoadAction(), setIndexedMaskedLoadAction(), setIndexedMaskedStoreAction(), setIndexedStoreAction(), setOperationAction(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SSHLSAT, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::SSUBSAT, llvm::ISD::SUBC, llvm::ISD::SUBCARRY, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UBSANTRAP, llvm::ISD::UDIVFIX, llvm::ISD::UDIVFIXSAT, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULFIX, llvm::ISD::UMULFIXSAT, llvm::ISD::UMULO, llvm::ISD::USHLSAT, llvm::ISD::USUBO, llvm::ISD::USUBSAT, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SEQ_FADD, llvm::ISD::VECREDUCE_SEQ_FMUL, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, llvm::ISD::VECTOR_SPLICE, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by TargetLoweringBase().
◆ insertSSPDeclarations()
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virtual |
Inserts necessary declarations for SSP (stack protection) purpose.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::SparcTargetLowering.
Definition at line 1950 of file TargetLoweringBase.cpp.
References llvm::GlobalValue::ExternalLinkage, llvm::Type::getInt8PtrTy(), llvm::TargetMachine::getRelocationModel(), llvm::TargetMachine::getTargetTriple(), llvm::Triple::isOSFreeBSD(), llvm::Triple::isWindowsGNUEnvironment(), M, and llvm::Reloc::Static.
Referenced by getStackGuard(), llvm::SparcTargetLowering::insertSSPDeclarations(), llvm::ARMTargetLowering::insertSSPDeclarations(), llvm::AArch64TargetLowering::insertSSPDeclarations(), llvm::PPCTargetLowering::insertSSPDeclarations(), and llvm::X86TargetLowering::insertSSPDeclarations().
◆ InstructionOpcodeToISD()
| int TargetLoweringBase::InstructionOpcodeToISD | ( | unsigned | Opcode | ) | const |
Get the ISD node that corresponds to the Instruction class opcode.
Definition at line 1728 of file TargetLoweringBase.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::FAdd, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::FMul, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREEZE, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::SPII::Load, llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, Mul, llvm::ISD::MUL, llvm::Or, llvm::ISD::OR, llvm::MipsISD::Ret, llvm::ISD::SDIV, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, llvm::Xor, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::BPFTTIImpl::getArithmeticInstrCost(), llvm::LanaiTTIImpl::getArithmeticInstrCost(), llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::PPCTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::PPCTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::PPCTTIImpl::getVectorInstrCost(), llvm::X86TTIImpl::getVectorInstrCost(), isPromotedInstructionLegal(), llvm::ARMTTIImpl::maybeLoweredToCall(), SinkShiftAndTruncate(), and llvm::PPCTTIImpl::vectorCostAdjustmentFactor().
◆ isBinOp()
|
inlinevirtual |
Return true if the node is a math/logic binary operator.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2621 of file TargetLowering.h.
References llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::FSUB, isCommutativeBinOp(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UDIV, llvm::ISD::UREM, and llvm::ISD::USUBSAT.
Referenced by canonicalizeShuffleWithBinOps(), getKnownUndefForVectorBinop(), llvm::X86TargetLowering::isBinOp(), narrowExtractedVectorBinOp(), narrowInsertExtractVectorBinOp(), and scalarizeExtractedBinop().
◆ isCheapToSpeculateCtlz()
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inlinevirtual |
Return true if it is cheap to speculate a call to intrinsic ctlz.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, llvm::VETargetLowering, llvm::AMDGPUTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 627 of file TargetLowering.h.
Referenced by despeculateCountZeros(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost().
◆ isCheapToSpeculateCttz()
|
inlinevirtual |
Return true if it is cheap to speculate a call to intrinsic cttz.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::MipsTargetLowering, llvm::AMDGPUTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 622 of file TargetLowering.h.
Referenced by despeculateCountZeros(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost().
◆ isCommutativeBinOp()
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inlinevirtual |
Returns true if the opcode is a commutative binary operation.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2581 of file TargetLowering.h.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::FADD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, and llvm::ISD::XOR.
Referenced by llvm::SelectionDAG::canonicalizeCommutativeBinop(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getNode(), isBinOp(), llvm::X86TargetLowering::isCommutativeBinOp(), and llvm::TargetLowering::SimplifySetCC().
◆ isCondCodeLegal()
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inline |
Return true if the specified condition code is legal on this target.
Definition at line 1412 of file TargetLowering.h.
References getCondCodeAction(), and Legal.
Referenced by llvm::SelectionDAG::FoldSetCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), llvm::R600TargetLowering::PerformDAGCombine(), and llvm::TargetLowering::SimplifySetCC().
◆ isCondCodeLegalOrCustom()
|
inline |
Return true if the specified condition code is legal or custom on this target.
Definition at line 1418 of file TargetLowering.h.
References Custom, getCondCodeAction(), and Legal.
Referenced by llvm::TargetLowering::LegalizeSetCCCondCode().
◆ isConstantUnsignedBitfieldExtractLegal()
|
inlinevirtual |
- Returns
- true if a constant G_UBFX is legal on the target.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 1859 of file TargetLowering.h.
◆ isCtlzFast()
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inlinevirtual |
Return true if ctlz instruction is fast.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::VETargetLowering, and llvm::HexagonTargetLowering.
Definition at line 632 of file TargetLowering.h.
Referenced by llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl().
◆ isEqualityCmpFoldedWithSignedCmp()
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inlinevirtual |
Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.
Reimplemented in llvm::PPCTargetLowering.
Definition at line 644 of file TargetLowering.h.
Referenced by foldICmpWithDominatingICmp().
◆ isExtFree()
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inline |
Return true if the extension represented by I is free.
Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by I to decide whether or not I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.
- Precondition
Imust be a sign, zero, or fp extension.
Definition at line 2683 of file TargetLowering.h.
References llvm::EVT::getEVT(), I, isExtFreeImpl(), isFPExtFree(), isZExtFree(), and llvm_unreachable.
◆ isExtFreeImpl()
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inlineprotectedvirtual |
Return true if the extension represented by I is free.
- Precondition
Iis a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.
Definition at line 3295 of file TargetLowering.h.
Referenced by isExtFree().
◆ isExtLoad()
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inline |
Return true if Load and Ext can form an ExtLoad.
For example, in AArch64 L = load i8, i8* ptr E = zext i8 L to i32 can be lowered into one load instruction ldrb w0, [x0]
Definition at line 2708 of file TargetLowering.h.
References assert(), DL, llvm::MipsISD::Ext, getValueType(), isLoadExtLegal(), isTruncateFree(), isTypeLegal(), llvm::SPII::Load, llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.
◆ isExtractSubvectorCheap()
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inlinevirtual |
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.
This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2982 of file TargetLowering.h.
Referenced by foldExtractSubvectorFromShuffleVector(), llvm::SelectionDAG::matchBinOpReduction(), and narrowExtractedVectorBinOp().
◆ isExtractVecEltCheap()
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inlinevirtual |
Return true if extraction of a scalar element from the given vector type at the given index is cheap.
For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2997 of file TargetLowering.h.
Referenced by scalarizeBinOpOfSplats().
◆ isFAbsFree()
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inlinevirtual |
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 2877 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getTypeBasedIntrinsicInstrCost().
◆ isFMADLegal() [1/2]
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inlinevirtual |
Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD.
N may be an TargetOpcode::G_FADD, TargetOpcode::G_FSUB, or an TargetOpcode::G_FMUL which will be distributed into an fadd/fsub.
Reimplemented in llvm::SITargetLowering.
Definition at line 2917 of file TargetLowering.h.
References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::LLT::getScalarSizeInBits(), isOperationLegal(), and MI.
◆ isFMADLegal() [2/2]
|
inlinevirtual |
Returns true if be combined with to form an ISD::FMAD.
N may be an ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an fadd/fsub.
Reimplemented in llvm::SITargetLowering.
Definition at line 2939 of file TargetLowering.h.
References assert(), llvm::ISD::FADD, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FSUB, isOperationLegal(), and N.
◆ isFMAFasterThanFMulAndFAdd() [1/3]
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inlinevirtual |
IR version.
Reimplemented in llvm::PPCTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2909 of file TargetLowering.h.
◆ isFMAFasterThanFMulAndFAdd() [2/3]
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inlinevirtual |
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)
Reimplemented in llvm::NVPTXTargetLowering, llvm::SPIRVTargetLowering, llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.
Definition at line 2890 of file TargetLowering.h.
◆ isFMAFasterThanFMulAndFAdd() [3/3]
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inlinevirtual |
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)
Reimplemented in llvm::SITargetLowering.
Definition at line 2903 of file TargetLowering.h.
◆ isFNegFree()
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inlinevirtual |
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2870 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
◆ isFPExtFoldable() [1/2]
|
inlinevirtual |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
Reimplemented in llvm::SITargetLowering.
Definition at line 2849 of file TargetLowering.h.
◆ isFPExtFoldable() [2/2]
|
inlinevirtual |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
Reimplemented in llvm::SITargetLowering.
Definition at line 2857 of file TargetLowering.h.
References assert(), llvm::EVT::isFloatingPoint(), and isFPExtFree().
◆ isFPExtFree()
Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).
Reimplemented in llvm::PPCTargetLowering.
Definition at line 2840 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
Referenced by llvm::TargetLowering::getNegatedExpression(), isExtFree(), and isFPExtFoldable().
◆ isFPImmLegal()
|
inlinevirtual |
Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented in llvm::ARMTargetLowering, llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::HexagonTargetLowering, llvm::VETargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1056 of file TargetLowering.h.
Referenced by llvm::TargetLowering::getNegatedExpression().
◆ isFreeAddrSpaceCast()
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virtual |
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
we are happy to sink it into basic blocks. A cast may be free, but not necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
Reimplemented in llvm::SITargetLowering.
Definition at line 908 of file TargetLoweringBase.cpp.
References llvm::TargetMachine::isNoopAddrSpaceCast().
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), and OptimizeNoopCopyExpression().
◆ isFsqrtCheap()
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inlinevirtual |
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 504 of file TargetLowering.h.
◆ isIndexedLoadLegal()
|
inline |
Return true if the specified indexed load is legal on this target.
Definition at line 1339 of file TargetLowering.h.
References Custom, getIndexedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.
Referenced by getCombineLoadStoreParts(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedLoadLegal().
◆ isIndexedMaskedLoadLegal()
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inline |
Return true if the specified indexed load is legal on this target.
Definition at line 1367 of file TargetLowering.h.
References Custom, getIndexedMaskedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.
Referenced by getCombineLoadStoreParts().
◆ isIndexedMaskedStoreLegal()
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inline |
Return true if the specified indexed load is legal on this target.
Definition at line 1381 of file TargetLowering.h.
References Custom, getIndexedMaskedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.
Referenced by getCombineLoadStoreParts().
◆ isIndexedStoreLegal()
|
inline |
Return true if the specified indexed load is legal on this target.
Definition at line 1353 of file TargetLowering.h.
References Custom, getIndexedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.
Referenced by getCombineLoadStoreParts(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedStoreLegal().
◆ isIntDivCheap()
|
inlinevirtual |
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
The definition of "cheaper" may depend on whether we're optimizing for speed or for size.
Reimplemented in llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 496 of file TargetLowering.h.
Referenced by llvm::RISCVTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSREMPow2(), and llvm::TargetLowering::SimplifySetCC().
◆ isJumpExpensive()
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inline |
Return true if Flow Control is an expensive operation that should be avoided.
Definition at line 551 of file TargetLowering.h.
◆ isJumpTableRelative()
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virtual |
Reimplemented in llvm::PPCTargetLowering, and llvm::MipsTargetLowering.
Definition at line 1994 of file TargetLoweringBase.cpp.
References getTargetMachine(), and llvm::TargetMachine::isPositionIndependent().
Referenced by llvm::VETargetLowering::getMinimumJumpTableEntries(), and llvm::PPCTargetLowering::isJumpTableRelative().
◆ isLegalAddImmediate()
|
inlinevirtual |
Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.
Reimplemented in llvm::AArch64TargetLowering, llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2542 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddImmediate(), and performAddCSelIntoCSinc().
◆ isLegalAddressingMode()
|
virtual |
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.
If the address space cannot be determined, it will be -1.
TODO: Remove default argument
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, llvm::HexagonTargetLowering, llvm::SITargetLowering, llvm::XCoreTargetLowering, llvm::AVRTargetLowering, and llvm::ARCTargetLowering.
Definition at line 1895 of file TargetLoweringBase.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.
Referenced by canFoldInAddressingMode(), getScalingFactorCost(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddressingMode().
◆ isLegalICmpImmediate()
|
inlinevirtual |
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented in llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::RISCVTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 2535 of file TargetLowering.h.
Referenced by llvm::MSP430TargetLowering::isLegalICmpImmediate(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalICmpImmediate(), and llvm::TargetLowering::SimplifySetCC().
◆ isLegalRC()
|
protected |
Return true if the value types that can be represented by the specified register class are all legal.
isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.
Definition at line 1117 of file TargetLoweringBase.cpp.
References I, isTypeLegal(), llvm::TargetRegisterInfo::legalclasstypes_begin(), llvm::MVT::Other, and TRI.
Referenced by findRepresentativeClass(), and llvm::TargetLowering::getRegForInlineAsmConstraint().
◆ isLegalStoreImmediate()
|
inlinevirtual |
Return true if the specified immediate is legal for the value input of a store instruction.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2548 of file TargetLowering.h.
Referenced by getMemsetValue().
◆ isLoadBitCastBeneficial()
|
inlinevirtual |
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
Reimplemented in llvm::AMDGPUTargetLowering, and llvm::X86TargetLowering.
Definition at line 569 of file TargetLowering.h.
References allowsMemoryAccess(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), getOperationAction(), llvm::EVT::getSimpleVT(), getTypeToPromoteTo(), llvm::EVT::isSimple(), llvm::ISD::LOAD, and Promote.
Referenced by llvm::X86TargetLowering::isLoadBitCastBeneficial(), and isStoreBitCastBeneficial().
◆ isLoadExtLegal()
|
inline |
Return true if the specified load with extension is legal on this target.
Definition at line 1286 of file TargetLowering.h.
References getLoadExtAction(), and Legal.
Referenced by combineEXTEND_VECTOR_INREG(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), isExtLoad(), tryToFoldExtendSelectLoad(), tryToFoldExtOfExtload(), and tryToFoldExtOfLoad().
◆ isLoadExtLegalOrCustom()
|
inline |
Return true if the specified load with extension is legal or custom on this target.
Definition at line 1292 of file TargetLowering.h.
References Custom, getLoadExtAction(), and Legal.
Referenced by tryToFoldExtOfMaskedLoad().
◆ isMaskAndCmp0FoldingBeneficial()
|
inlinevirtual |
Return if the target supports combining a chain like:
into a single machine instruction of a form like:
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::SystemZTargetLowering.
Definition at line 674 of file TargetLowering.h.
Referenced by sinkAndCmp0Expression().
◆ isMulAddWithConstProfitable()
|
inlinevirtual |
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
This may not be true if c1 and c2 can be represented as immediates but c1*c2 cannot, for example. The target should check if c1, c2 and c1*c2 can be represented as immediates, or have to be materialized into registers. If it is not sure about some cases, a default true can be returned to let the DAGCombiner decide. AddNode is (add x, c1), and ConstNode is c2.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2181 of file TargetLowering.h.
◆ isMultiStoresCheaperThanBitsMerge()
|
inlinevirtual |
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
Reimplemented in llvm::X86TargetLowering.
Definition at line 660 of file TargetLowering.h.
Referenced by splitMergedValStore().
◆ isNarrowingProfitable()
Return true if it's profitable to narrow operations of type VT1 to VT2.
e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2956 of file TargetLowering.h.
◆ isOperationCustom()
|
inline |
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
Definition at line 1199 of file TargetLowering.h.
References Custom, and getOperationAction().
Referenced by llvm::X86TargetLowering::X86TargetLowering().
◆ isOperationExpand()
|
inline |
Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.
This is used to help guide high-level lowering decisions.
Definition at line 1261 of file TargetLowering.h.
References Expand, getOperationAction(), and isTypeLegal().
Referenced by combineFMA(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getTypeBasedIntrinsicInstrCost(), llvm::X86TargetLowering::shouldFormOverflowOp(), shouldFormOverflowOp(), llvm::PPCTTIImpl::vectorCostAdjustmentFactor(), and llvm::X86TargetLowering::X86TargetLowering().
◆ isOperationLegal()
|
inline |
Return true if the specified operation is legal on this target.
Definition at line 1266 of file TargetLowering.h.
References getOperationAction(), isTypeLegal(), Legal, and llvm::MVT::Other.
Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineLogicBlendIntoConditionalNegate(), combineTruncatedArithmetic(), llvm::X86TargetLowering::decomposeMulByConstant(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandABS(), foldFPToIntToFP(), llvm::PPCTargetLowering::getNegatedExpression(), llvm::X86TargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::X86TTIImpl::hasDivRemOp(), isFMADLegal(), isOperationLegalOrCustom(), isOperationLegalOrCustomOrPromote(), isOperationLegalOrPromote(), LowerADDSAT_SUBSAT(), LowerVSETCC(), PerformABSCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performXORCombine(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), stripModuloOnShift(), and tryFoldToZero().
◆ isOperationLegalOrCustom()
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inline |
Return true if the specified operation is legal on this target or can be made legal with custom lowering.
This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.
Definition at line 1158 of file TargetLowering.h.
References Custom, getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, and llvm::MVT::Other.
Referenced by areJTsAllowed(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canExpandVectorCTPOP(), combineABSToABD(), combineCarryDiamond(), combineConcatVectorOfCasts(), combineMinNumMaxNum(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleOfBitcast(), combineShuffleToVectorExtend(), combineVSelectToBLENDV(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::findOptimalMemOpLowering(), foldExtractSubvectorFromShuffleVector(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), getAsCarry(), llvm::TargetLowering::getNegatedExpression(), llvm::MipsTTIImpl::hasDivRemOp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), llvm::ARMTargetLowering::isExtractSubvectorCheap(), llvm::AArch64TargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::PPCTargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), matchBSwapHWordOrAndAnd(), narrowInsertExtractVectorBinOp(), scalarizeBinOpOfSplats(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::shouldBuildLookupTables(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::X86TargetLowering::shouldConvertFpToSat(), shouldConvertFpToSat(), llvm::TargetLowering::SimplifyDemandedBits(), simplifySetCCWithCTPOP(), SinkShiftAndTruncate(), and widenCtPop().
◆ isOperationLegalOrCustomOrPromote()
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inline |
Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.
This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.
Definition at line 1186 of file TargetLowering.h.
References Custom, getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, llvm::MVT::Other, and Promote.
Referenced by canExpandVectorCTPOP(), llvm::TargetLowering::expandABS(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getFPOpCost(), narrowExtractedVectorBinOp(), and llvm::X86TargetLowering::shouldScalarizeBinop().
◆ isOperationLegalOrPromote()
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inline |
Return true if the specified operation is legal on this target or can be made legal using promotion.
This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.
Definition at line 1172 of file TargetLowering.h.
References getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, llvm::MVT::Other, and Promote.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getTypeBasedIntrinsicInstrCost(), lowerBuildVectorToBitOp(), and PromoteMaskArithmetic().
◆ isPredictableSelectExpensive()
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inline |
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.
Definition at line 555 of file TargetLowering.h.
References PredictableSelectIsExpensive.
Referenced by isFormingBranchFromSelectProfitable().
◆ isProfitableToCombineMinNumMaxNum()
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inlinevirtual |
Definition at line 2153 of file TargetLowering.h.
Referenced by isLegalToCombineMinNumMaxNum().
◆ isProfitableToHoist()
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inlinevirtual |
Reimplemented in llvm::PPCTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2672 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isProfitableToHoist().
◆ isSafeMemOpType()
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inlinevirtual |
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1770 of file TargetLowering.h.
Referenced by llvm::TargetLowering::findOptimalMemOpLowering().
◆ isSelectSupported()
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inlinevirtual |
Reimplemented in llvm::AMDGPUTargetLowering, llvm::PPCTargetLowering, and llvm::ARMTargetLowering.
Definition at line 432 of file TargetLowering.h.
◆ isSExtCheaperThanZExt()
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inlinevirtual |
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Reimplemented in llvm::RISCVTargetLowering.
Definition at line 2754 of file TargetLowering.h.
Referenced by llvm::SelectionDAG::getNode(), and llvm::TargetLowering::SimplifySetCC().
◆ isShuffleMaskLegal()
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inlinevirtual |
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented in llvm::SITargetLowering, llvm::X86TargetLowering, llvm::HexagonTargetLowering, llvm::MipsSETargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1065 of file TargetLowering.h.
Referenced by llvm::TargetLowering::buildLegalVectorShuffle(), combineShuffleOfBitcast(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), and formSplatFromShuffles().
◆ isSlowDivBypassed()
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inline |
Returns true if target has indicated at least one type should be bypassed.
Definition at line 541 of file TargetLowering.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty().
◆ isStoreBitCastBeneficial()
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inlinevirtual |
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))
Definition at line 592 of file TargetLowering.h.
References isLoadBitCastBeneficial().
◆ isStrictFPEnabled()
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inline |
Return true if the target support strict float operation.
Definition at line 338 of file TargetLowering.h.
References IsStrictFPEnabled.
◆ isSuitableForBitTests()
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inline |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons.
Check if the number of destinations, comparison metric, and range are all suitable.
Definition at line 1236 of file TargetLowering.h.
References DL, High, llvm::Low, and rangeFitsInWord().
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters().
◆ isSuitableForJumpTable()
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virtual |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.
Definition at line 1583 of file TargetLoweringBase.cpp.
References llvm::AMDGPUISD::BFI, getMaximumJumpTableSize(), getMinimumJumpTableDensity(), llvm::shouldOptimizeForSize(), and SI.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters().
◆ isSupportedFixedPointOperation()
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inlinevirtual |
Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.
If not, the operation is illegal.
Definition at line 1102 of file TargetLowering.h.
Referenced by getFixedPointOperationAction().
◆ isTruncateFree() [1/3]
Reimplemented in llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2665 of file TargetLowering.h.
◆ isTruncateFree() [2/3]
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inlinevirtual |
Definition at line 2666 of file TargetLowering.h.
References DL, llvm::getApproximateEVTForLLT(), and isTruncateFree().
◆ isTruncateFree() [3/3]
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inlinevirtual |
Return true if it's free to truncate a value of type FromTy to type ToTy.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, llvm::NVPTXTargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::AMDGPUTargetLowering, and llvm::SystemZTargetLowering.
Definition at line 2652 of file TargetLowering.h.
Referenced by ExtendUsesToFormExtLoad(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), getMemsetStores(), isExtLoad(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTruncateFree(), isTruncateFree(), and llvm::TargetLowering::ShrinkDemandedOp().
◆ isTruncStoreLegal()
Return true if the specified store with truncation is legal on this target.
Definition at line 1311 of file TargetLowering.h.
References getTruncStoreAction(), isTypeLegal(), and Legal.
Referenced by llvm::R600TargetLowering::canCombineTruncStore(), canCombineTruncStore(), combineMaskedStore(), combineStore(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getStoreMinimumVF().
◆ isTruncStoreLegalOrCustom()
Return true if the specified store with truncation has solution on this target.
Definition at line 1317 of file TargetLowering.h.
References Custom, getTruncStoreAction(), isTypeLegal(), and Legal.
Referenced by canCombineTruncStore().
◆ isTypeLegal()
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inline |
Return true if the target has native support for the specified value type.
This means that it has a register that directly holds it without promotions or expansions.
Definition at line 934 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
Referenced by llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canOpTrap(), CollectOpsToWiden(), combineAdd(), combineAddOrSubToADCOrSBB(), combineAnd(), combineBitcast(), combineBitcastToBoolVector(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfScalars(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineFMA(), combineFMinNumFMaxNum(), combineFneg(), combineLoad(), combineOr(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineShiftAnd1ToBitTest(), combineShuffle(), combineShuffleToFMAddSub(), combineShuffleToVectorExtend(), combineStore(), combineTargetShuffle(), combineTruncateWithSat(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineXor(), computeRegisterProperties(), EltsFromConsecutiveLoads(), expandDivFix(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::findOptimalMemOpLowering(), getAVX512Node(), getAVX512TruncNode(), getBT(), getConstVector(), getContainerForFixedLengthVector(), getCopyFromPartsVector(), getCopyToParts(), llvm::PPCTargetLowering::getNegatedExpression(), llvm::X86TargetLowering::getNegatedExpression(), getPredicateForFixedLengthVector(), getPredicateForScalableVector(), getPromotedVectorElementType(), getPTest(), llvm::SelectionDAG::getReducedAlign(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::SelectionDAG::getSplatValue(), getTypeToPromoteTo(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), llvm::SITargetLowering::hasBitPreservingFPLogic(), llvm::SystemZTTIImpl::hasDivRemOp(), hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), isAddSubOrSubAdd(), isExtLoad(), isLegalRC(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), isNoopBitcast(), isOperationExpand(), isOperationLegal(), isOperationLegalOrCustom(), isOperationLegalOrCustomOrPromote(), isOperationLegalOrPromote(), isPackedVectorType(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), isTruncStoreLegal(), isTruncStoreLegalOrCustom(), llvm::X86TargetLowering::isTypeDesirableForOp(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), LowerADDSUBCARRY(), lowerCTLZ_CTTZ_ZERO_UNDEF(), LowerFABSorFNEG(), lowerFCMPIntrinsic(), LowerFCOPYSIGN(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), lowerICMPIntrinsic(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleAsElementInsertion(), lowerShuffleAsShift(), LowerSINT_TO_FP(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP(), lowerVECTOR_SHUFFLE(), LowerVectorAllZero(), LowerXALUO(), OptimizeExtractBits(), PerformANDCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformExtendCombine(), PerformExtractEltToVMOVRRD(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performFpToIntCombine(), performInsertSubvectorCombine(), PerformInsertSubvectorCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), PerformORCombine(), performORCombine(), performSelectCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), PerformTruncatingStoreCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVSetCCToVCTPCombine(), PerformXORCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::X86TargetLowering::shouldSplatInsEltVarIndex(), llvm::TargetLowering::SimplifySetCC(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), tryToFoldExtendOfConstant(), tryWidenMaskForShuffle(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::X86TargetLowering::X86TargetLowering().
◆ isVectorClearMaskLegal()
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inlinevirtual |
Similar to isShuffleMaskLegal.
Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1078 of file TargetLowering.h.
◆ isVectorLoadExtDesirable()
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inlinevirtual |
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2866 of file TargetLowering.h.
Referenced by tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().
◆ isVectorShiftByScalarCheap()
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inlinevirtual |
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.
On x86 before AVX2 for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors. This should also apply to lowering for vector funnel shifts (rotates).
Reimplemented in llvm::X86TargetLowering.
Definition at line 2559 of file TargetLowering.h.
◆ isZExtFree() [1/4]
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2745 of file TargetLowering.h.
◆ isZExtFree() [2/4]
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inlinevirtual |
Definition at line 2746 of file TargetLowering.h.
References DL, llvm::getApproximateEVTForLLT(), and isZExtFree().
◆ isZExtFree() [3/4]
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::AMDGPUTargetLowering, llvm::MSP430TargetLowering, and llvm::XCoreTargetLowering.
Definition at line 2833 of file TargetLowering.h.
References llvm::SDValue::getValueType(), and isZExtFree().
◆ isZExtFree() [4/4]
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inlinevirtual |
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.
The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2741 of file TargetLowering.h.
Referenced by combineShuffleOfScalars(), foldCONCAT_VECTORS(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::RegsForValue::getCopyToRegs(), hasSameExtUse(), isExtFree(), llvm::RISCVTargetLowering::isZExtFree(), llvm::PPCTargetLowering::isZExtFree(), isZExtFree(), llvm::TargetLowering::ShrinkDemandedOp(), and tryToFoldExtendOfConstant().
◆ lowerIdempotentRMWIntoFencedLoad()
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inlinevirtual |
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.
This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.
Definition at line 2111 of file TargetLowering.h.
◆ lowerInterleavedLoad()
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inlinevirtual |
Lower an interleaved load to target specific intrinsics.
Return true on success.
LI is the vector load instruction. Shuffles is the shufflevector list to DE-interleave the loaded vector. Indices is the corresponding indices for each shufflevector. Factor is the interleave factor.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2812 of file TargetLowering.h.
◆ lowerInterleavedStore()
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inlinevirtual |
Lower an interleaved store to target specific intrinsics.
Return true on success.
SI is the vector store instruction. SVI is the shufflevector to RE-interleave the stored vector. Factor is the interleave factor.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2825 of file TargetLowering.h.
◆ markLibCallAttributes()
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inlinevirtual |
Reimplemented in llvm::X86TargetLowering.
Definition at line 314 of file TargetLowering.h.
Referenced by llvm::TargetLowering::CallLoweringInfo::setLibCallee().
◆ mergeStoresAfterLegalization()
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inlinevirtual |
Allow store merging for the specified type after legalization in addition to before legalization.
This may transform stores that do not exist earlier (for example, stores created from intrinsics).
Reimplemented in llvm::AMDGPUTargetLowering, llvm::AArch64TargetLowering, and llvm::X86TargetLowering.
Definition at line 611 of file TargetLowering.h.
◆ needsFixedCatchObjects()
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inlinevirtual |
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1804 of file TargetLowering.h.
References llvm::report_fatal_error().
Referenced by llvm::FunctionLoweringInfo::set().
◆ operator=()
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delete |
◆ preferIncOfAddToSubOfNot()
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inlinevirtual |
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.
Some targets may prefer one to the other.
Reimplemented in llvm::PPCTargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 796 of file TargetLowering.h.
◆ preferZeroCompareBranch()
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inlinevirtual |
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Reimplemented in llvm::ARMTargetLowering, and llvm::SystemZTargetLowering.
Definition at line 648 of file TargetLowering.h.
Referenced by optimizeBranch().
◆ promoteTargetBoolean()
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inline |
Promote the given target boolean to a target boolean of the given type.
A target boolean is an integer value, not necessarily of type i1, the bits of which conform to getBooleanContents.
ValVT is the type of values that produced the boolean.
Definition at line 868 of file TargetLowering.h.
References getBooleanContents(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), getExtendForContent(), llvm::SelectionDAG::getNode(), and getSetCCResultType().
◆ rangeFitsInWord()
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inline |
Check whether the range [Low,High] fits in a machine word.
Definition at line 1213 of file TargetLowering.h.
References DL, High, llvm::Low, and UINT64_MAX.
Referenced by isSuitableForBitTests().
◆ reduceSelectOfFPConstantLoads()
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inlinevirtual |
Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.
The parameter may be used to differentiate a select with FP compare from integer compare.
Reimplemented in llvm::X86TargetLowering.
Definition at line 446 of file TargetLowering.h.
◆ requiresUniformRegister()
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inlinevirtual |
Allows target to decide about the register class of the specific value that is live outside the defining block.
Returns true if the value needs uniform register class.
Reimplemented in llvm::SITargetLowering.
Definition at line 901 of file TargetLowering.h.
Referenced by llvm::FunctionLoweringInfo::CreateRegs().
◆ setBooleanContents() [1/2]
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inlineprotected |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
See getBooleanContents.
Definition at line 2210 of file TargetLowering.h.
◆ setBooleanContents() [2/2]
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inlineprotected |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
See getBooleanContents.
Definition at line 2203 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::VETargetLowering::VETargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setBooleanVectorContents()
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inlineprotected |
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type.
See getBooleanContents.
Definition at line 2217 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::VETargetLowering::VETargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setCmpLibcallCC()
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inline |
Override the default CondCode to be used to test the result of the comparison libcall against zero.
Definition at line 3066 of file TargetLowering.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::MSP430TargetLowering::MSP430TargetLowering().
◆ setCondCodeAction() [1/2]
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Definition at line 2398 of file TargetLowering.h.
References setCondCodeAction().
◆ setCondCodeAction() [2/2]
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Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.
The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit value and the upper 29 bits index into the second dimension of the array to select what 32-bit value to use.
Definition at line 2384 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::MVT::isValid(), Shift, and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), setCondCodeAction(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setHasExtractBitsInsn()
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Tells the code generator that the target has BitExtract instructions.
The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.
Definition at line 2252 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), and llvm::SITargetLowering::SITargetLowering().
◆ setHasMultipleConditionRegisters()
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Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.
With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.
Definition at line 2244 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().
◆ setIndexedLoadAction() [1/2]
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Definition at line 2339 of file TargetLowering.h.
References setIndexedLoadAction().
◆ setIndexedLoadAction() [2/2]
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Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.
NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp
Definition at line 2333 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and setIndexedLoadAction().
◆ setIndexedMaskedLoadAction()
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Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.
NOTE: All indexed mode masked loads are initialized to Expand in TargetLowering.cpp
Definition at line 2367 of file TargetLowering.h.
Referenced by initActions().
◆ setIndexedMaskedStoreAction()
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Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it. <