This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen. More...
#include "llvm/CodeGen/TargetLowering.h"
Classes | |
| struct | AddrMode |
| This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null, there is no BaseGV. More... | |
| class | ArgListEntry |
| struct | IntrinsicInfo |
| class | ValueTypeActionImpl |
Public Types | |
| enum | LegalizeAction : uint8_t { Legal, Promote, Expand, LibCall, Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More... | |
| enum | LegalizeTypeAction : uint8_t { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More... | |
| enum | BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values. More... | |
| enum | SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect } |
| Enum that describes what type of support for selects the target has. More... | |
| enum | AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg, AtomicExpansionKind::MaskedIntrinsic } |
| Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More... | |
| enum | MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom } |
| Enum that specifies when a multiplication should be expanded. More... | |
| enum | ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 } |
| Reciprocal estimate status values used by the functions below. More... | |
| using | LegalizeKind = std::pair< LegalizeTypeAction, EVT > |
| LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More... | |
| using | ArgListTy = std::vector< ArgListEntry > |
Public Member Functions | |
| virtual void | markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| TargetLoweringBase (const TargetLoweringBase &)=delete | |
| TargetLoweringBase & | operator= (const TargetLoweringBase &)=delete |
| virtual | ~TargetLoweringBase ()=default |
| const TargetMachine & | getTargetMachine () const |
| virtual bool | useSoftFloat () const |
| virtual MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| MVT | getPointerMemTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| MVT | getFrameIndexTy (const DataLayout &DL) const |
| Return the type for frame index, which is determined by the alloca address space specified through the data layout. More... | |
| virtual MVT | getFenceOperandTy (const DataLayout &DL) const |
| Return the type for operands of fence. More... | |
| virtual MVT | getScalarShiftAmountTy (const DataLayout &, EVT) const |
| EVT is not used in-tree, but is used by out-of-tree target. More... | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const |
| virtual MVT | getVectorIdxTy (const DataLayout &DL) const |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More... | |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| virtual bool | reduceSelectOfFPConstantLoads (EVT CmpOpVT) const |
| Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. More... | |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (MVT VT) const |
| Return the preferred vector type legalization action. More... | |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| virtual bool | isIntDivCheap (EVT VT, AttributeList Attr) const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More... | |
| virtual bool | hasStandaloneRem (EVT VT) const |
| Return true if the target can handle a standalone remainder operation. More... | |
| virtual bool | isFsqrtCheap (SDValue X, SelectionDAG &DAG) const |
| Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More... | |
| int | getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More... | |
| int | getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More... | |
| int | getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a square root of the given type based on the function's attributes. More... | |
| int | getDivRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a division of the given type based on the function's attributes. More... | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. More... | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. More... | |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More... | |
| virtual BranchProbability | getPredictableBranchThreshold () const |
| If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More... | |
| virtual bool | isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const |
| Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More... | |
| virtual bool | isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const |
| Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) More... | |
| virtual bool | storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const |
| Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More... | |
| virtual bool | mergeStoresAfterLegalization (EVT MemVT) const |
| Allow store merging for the specified type after legalization in addition to before legalization. More... | |
| virtual bool | canMergeStoresTo (unsigned AS, EVT MemVT, const SelectionDAG &DAG) const |
| Returns if it's reasonable to merge stores to MemVT size. More... | |
| virtual bool | isCheapToSpeculateCttz () const |
| Return true if it is cheap to speculate a call to intrinsic cttz. More... | |
| virtual bool | isCheapToSpeculateCtlz () const |
| Return true if it is cheap to speculate a call to intrinsic ctlz. More... | |
| virtual bool | isCtlzFast () const |
| Return true if ctlz instruction is fast. More... | |
| virtual bool | hasBitPreservingFPLogic (EVT VT) const |
| Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More... | |
| virtual bool | isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const |
| Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More... | |
| virtual bool | isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const |
| Return if the target supports combining a chain like: More... | |
| virtual bool | convertSetCCLogicToBitwiseLogic (EVT VT) const |
| Use bitwise logic to make pairs of compares more efficient. More... | |
| virtual MVT | hasFastEqualityCompare (unsigned NumBits) const |
| Return the preferred operand type if the target has a quick way to compare integer values of the given size. More... | |
| virtual bool | hasAndNotCompare (SDValue Y) const |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More... | |
| virtual bool | hasAndNot (SDValue X) const |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More... | |
| virtual bool | hasBitTest (SDValue X, SDValue Y) const |
| Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized. More... | |
| virtual bool | shouldFoldMaskToVariableShiftPair (SDValue X) const |
| There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred. More... | |
| virtual bool | shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to fold a pair of shifts into a mask. More... | |
| virtual bool | shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. More... | |
| virtual bool | shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const |
| Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in. More... | |
| virtual bool | preferIncOfAddToSubOfNot (EVT VT) const |
| These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical. More... | |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More... | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy, Idx). More... | |
| virtual bool | shouldSplatInsEltVarIndex (EVT) const |
| Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. More... | |
| virtual bool | enableAggressiveFMAFusion (EVT VT) const |
| Return true if target always beneficiates from combining into FMA for a given value type. More... | |
| virtual EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const |
| Return the ValueType of the result of SETCC operations. More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. More... | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More... | |
| BooleanContent | getBooleanContents (EVT Type) const |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT, bool isDivergent=false) const |
| Return the register class that should be used for the specified value type. More... | |
| virtual bool | requiresUniformRegister (MachineFunction &MF, const Value *) const |
| Allows target to decide about the register class of the specific value that is live outside the defining block. More... | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. More... | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. More... | |
| virtual bool | shouldExpandShift (SelectionDAG &DAG, SDNode *N) const |
| Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a library call is preferred (e.g for code-size reasons). More... | |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. More... | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More... | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. More... | |
| virtual unsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More... | |
| virtual bool | getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More... | |
| virtual bool | isFPImmLegal (const APFloat &, EVT, bool ForCodeSize=false) const |
| Returns true if the target can instruction select the specified FP immediate natively. More... | |
| virtual bool | isShuffleMaskLegal (ArrayRef< int >, EVT) const |
| Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More... | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. More... | |
| virtual bool | isVectorClearMaskLegal (ArrayRef< int >, EVT) const |
| Similar to isShuffleMaskLegal. More... | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| virtual bool | isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const |
| Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. More... | |
| LegalizeAction | getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const |
| Some fixed point operations may be natively supported by the target but only for specific scales. More... | |
| LegalizeAction | getStrictFPOperationAction (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. More... | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. More... | |
| bool | isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More... | |
| bool | isOperationCustom (unsigned Op, EVT VT) const |
| Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More... | |
| virtual bool | areJTsAllowed (const Function *Fn) const |
| Return true if lowering to a jump table is allowed. More... | |
| bool | rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const |
| Check whether the range [Low,High] fits in a machine word. More... | |
| virtual bool | isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. More... | |
| bool | isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. More... | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More... | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. More... | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. More... | |
| bool | isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation has solution on this target. More... | |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| bool | isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal or custom on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. More... | |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. More... | |
| EVT | getMemValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| virtual unsigned | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const |
| Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| unsigned | getNumRegisters (LLVMContext &Context, EVT VT) const |
| Return the number of registers that this ValueType will eventually require. More... | |
| virtual MVT | getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More... | |
| virtual unsigned | getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const |
| Certain targets require unusual breakdowns of certain types. More... | |
| virtual unsigned | getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const |
| Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type. More... | |
| virtual bool | ShouldShrinkFPConstant (EVT) const |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More... | |
| virtual bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const |
| Return true if it is profitable to reduce a load to a smaller type. More... | |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More... | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. More... | |
| unsigned | getGatherAllAliasesMaxDepth () const |
| virtual unsigned | getVaListSizeInBits (const DataLayout &DL) const |
| Returns the size of the platform's va_list object. More... | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| virtual unsigned | getMaxGluedStoresPerMemcpy () const |
| Get maximum # of store operations to be glued together. More... | |
| unsigned | getMaxExpandSizeMemcmp (bool OptSize) const |
| Get maximum # of load operations permitted for memcmp. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| virtual bool | allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const |
| Determine if the target supports unaligned memory accesses. More... | |
| virtual bool | allowsMisalignedMemoryAccesses (LLT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const |
| LLT handling variant. More... | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const |
| This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access. More... | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) const |
| Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand. More... | |
| virtual bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given address space and alignment. More... | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given MachineMemOperand. More... | |
| virtual EVT | getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More... | |
| virtual LLT | getOptimalMemOpLLT (uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const |
| LLT returning variant. More... | |
| virtual bool | isSafeMemOpType (MVT) const |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More... | |
| bool | usesUnderscoreSetJmp () const |
| Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More... | |
| bool | usesUnderscoreLongJmp () const |
| Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More... | |
| virtual unsigned | getMinimumJumpTableEntries () const |
| Return lower limit for number of blocks in a jump table. More... | |
| unsigned | getMinimumJumpTableDensity (bool OptForSize) const |
| Return lower limit of the density in a jump table. More... | |
| unsigned | getMaximumJumpTableSize () const |
| Return upper limit for number of entries in a jump table. More... | |
| virtual bool | isJumpTableRelative () const |
| unsigned | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| virtual unsigned | getExceptionPointerRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. More... | |
| virtual unsigned | getExceptionSelectorRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More... | |
| virtual bool | needsFixedCatchObjects () const |
| Align | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| Align | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| Align | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| virtual Align | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. More... | |
| virtual bool | alignLoopsWithOptSize () const |
| Should loops be aligned even when the function is marked OptSize (but not MinSize). More... | |
| virtual Value * | getIRStackGuard (IRBuilder<> &IRB) const |
| If the target has a standard location for the stack protector guard, returns the address of that location. More... | |
| virtual void | insertSSPDeclarations (Module &M) const |
| Inserts necessary declarations for SSP (stack protection) purpose. More... | |
| virtual Value * | getSDagStackGuard (const Module &M) const |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More... | |
| virtual bool | useStackGuardXorFP () const |
| If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. More... | |
| virtual Function * | getSSPStackGuardCheck (const Module &M) const |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. More... | |
| virtual Value * | getSafeStackPointerLocation (IRBuilder<> &IRB) const |
| Returns the target-specific address of the unsafe stack pointer. More... | |
| virtual StringRef | getStackProbeSymbolName (MachineFunction &MF) const |
| Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More... | |
| virtual bool | isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const |
| Returns true if a cast between SrcAS and DestAS is a noop. More... | |
| virtual bool | isFreeAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const |
| Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More... | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More... | |
| virtual void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const |
| virtual bool | shouldExpandAtomicStoreInIR (StoreInst *SI) const |
| Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More... | |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. More... | |
| virtual bool | shouldExtendTypeInLibCall (EVT Type) const |
| Returns true if arguments should be extended in lib calls. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicLoadInIR (LoadInst *LI) const |
| Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW) const |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More... | |
| virtual LoadInst * | lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const |
| On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More... | |
| virtual ISD::NodeType | getExtendForAtomicOps () const |
| Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More... | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More... | |
| virtual bool | isProfitableToCombineMinNumMaxNum (EVT VT) const |
| virtual bool | convertSelectOfConstantsToMath (EVT VT) const |
| Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More... | |
| virtual bool | decomposeMulByConstant (LLVMContext &Context, EVT VT, SDValue C) const |
| Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. More... | |
| virtual bool | shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const |
| Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. More... | |
| virtual bool | getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More... | |
| virtual bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More... | |
| virtual int | getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| virtual bool | isLegalICmpImmediate (int64_t) const |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More... | |
| virtual bool | isLegalAddImmediate (int64_t) const |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More... | |
| virtual bool | isLegalStoreImmediate (int64_t Value) const |
| Return true if the specified immediate is legal for the value input of a store instruction. More... | |
| virtual bool | isVectorShiftByScalarCheap (Type *Ty) const |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More... | |
| virtual bool | isCommutativeBinOp (unsigned Opcode) const |
| Returns true if the opcode is a commutative binary operation. More... | |
| virtual bool | isBinOp (unsigned Opcode) const |
| Return true if the node is a math/logic binary operator. More... | |
| virtual bool | isTruncateFree (Type *FromTy, Type *ToTy) const |
| Return true if it's free to truncate a value of type FromTy to type ToTy. More... | |
| virtual bool | allowTruncateForTailCall (Type *FromTy, Type *ToTy) const |
| Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More... | |
| virtual bool | isTruncateFree (EVT FromVT, EVT ToVT) const |
| virtual bool | isProfitableToHoist (Instruction *I) const |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const |
Return true if Load and Ext can form an ExtLoad. More... | |
| virtual bool | isZExtFree (Type *FromTy, Type *ToTy) const |
| Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More... | |
| virtual bool | isZExtFree (EVT FromTy, EVT ToTy) const |
| virtual bool | isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const |
| Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. More... | |
| virtual bool | shouldSinkOperands (Instruction *I, SmallVectorImpl< Use *> &Ops) const |
| Return true if sinking I's operands to the same basic block as I is profitable, e.g. More... | |
| virtual bool | hasPairedLoad (EVT, unsigned &) const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More... | |
| virtual bool | hasVectorBlend () const |
| Return true if the target has a vector blend instruction. More... | |
| virtual unsigned | getMaxSupportedInterleaveFactor () const |
| Get the maximum supported factor for interleaved memory accesses. More... | |
| virtual bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const |
| Lower an interleaved load to target specific intrinsics. More... | |
| virtual bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const |
| Lower an interleaved store to target specific intrinsics. More... | |
| virtual bool | isZExtFree (SDValue Val, EVT VT2) const |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More... | |
| virtual bool | isFPExtFree (EVT DestVT, EVT SrcVT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More... | |
| virtual bool | isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More... | |
| virtual bool | isVectorLoadExtDesirable (SDValue ExtVal) const |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More... | |
| virtual bool | isFNegFree (EVT VT) const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFAbsFree (EVT VT) const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFMAFasterThanFMulAndFAdd (EVT) const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| virtual bool | isNarrowingProfitable (EVT, EVT) const |
| Return true if it's profitable to narrow operations of type VT1 to VT2. More... | |
| virtual bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const |
| Return true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| virtual bool | isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const |
| Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. More... | |
| virtual bool | shouldScalarizeBinop (SDValue VecOp) const |
| Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. More... | |
| virtual bool | isExtractVecEltCheap (EVT VT, unsigned Index) const |
| Return true if extraction of a scalar element from the given vector type at the given index is cheap. More... | |
| virtual bool | shouldFormOverflowOp (unsigned Opcode, EVT VT) const |
| Try to convert math with an overflow comparison into the corresponding DAG node operation. More... | |
| virtual bool | aggressivelyPreferBuildVectorSources (EVT VecVT) const |
| virtual bool | shouldConsiderGEPOffsetSplit () const |
| virtual unsigned | getShiftAmountThreshold (EVT VT) const |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. More... | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. More... | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| virtual void | finalizeLowering (MachineFunction &MF) const |
| Execute target specific actions to finalize target lowering. More... | |
Helpers for TargetTransformInfo implementations | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< int, MVT > | getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
Helpers for atomic expansion. | |
| unsigned | getMaxAtomicSizeInBitsSupported () const |
| Returns the maximum atomic operation size (in bits) supported by the backend. More... | |
| unsigned | getMinCmpXchgSizeInBits () const |
| Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More... | |
| bool | supportsUnalignedAtomics () const |
| Whether the target supports unaligned atomic operations. More... | |
| virtual bool | shouldInsertFencesForAtomic (const Instruction *I) const |
| Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More... | |
| virtual Value * | emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More... | |
| virtual Value * | emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const |
| Perform a store-conditional operation to Addr. More... | |
| virtual Value * | emitMaskedAtomicRMWIntrinsic (IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const |
| Perform a masked atomicrmw using a target-specific intrinsic. More... | |
| virtual Value * | emitMaskedAtomicCmpXchgIntrinsic (IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const |
| Perform a masked cmpxchg using a target-specific intrinsic. More... | |
| virtual Instruction * | emitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. More... | |
| virtual Instruction * | emitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const |
Static Public Member Functions | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
Protected Member Functions | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
| Value * | getDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More... | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setUseUnderscoreSetJmp (bool Val) |
| Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More... | |
| void | setUseUnderscoreLongJmp (bool Val) |
| Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More... | |
| void | setMinimumJumpTableEntries (unsigned Val) |
| Indicate the minimum number of blocks to generate jump tables. More... | |
| void | setMaximumJumpTableSize (unsigned) |
| Indicate the maximum number of entries in jump tables. More... | |
| void | setStackPointerRegisterToSaveRestore (unsigned R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More... | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. More... | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More... | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. More... | |
| virtual std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More... | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. More... | |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. More... | |
| void | setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More... | |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More... | |
| void | setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More... | |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More... | |
| void | setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| Convenience method to set an operation to Promote and specify the type in a single call. More... | |
| void | setTargetDAGCombine (ISD::NodeType NT) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More... | |
| void | setMinFunctionAlignment (Align Alignment) |
| Set the target's minimum function alignment. More... | |
| void | setPrefFunctionAlignment (Align Alignment) |
| Set the target's preferred function alignment. More... | |
| void | setPrefLoopAlignment (Align Alignment) |
| Set the target's preferred loop alignment. More... | |
| void | setMinStackArgumentAlignment (Align Alignment) |
| Set the minimum stack alignment of an argument. More... | |
| void | setMaxAtomicSizeInBitsSupported (unsigned SizeInBits) |
| Set the maximum atomic operation size supported by the backend. More... | |
| void | setMinCmpXchgSizeInBits (unsigned SizeInBits) |
| Sets the minimum cmpxchg or ll/sc size supported by the backend. More... | |
| void | setSupportsUnalignedAtomics (bool UnalignedSupported) |
| Sets whether unaligned atomic operations are supported. More... | |
| virtual bool | isExtFreeImpl (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. More... | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More... | |
| MachineBasicBlock * | emitXRayCustomEvent (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify the XRay custom event operands with target-dependent details. More... | |
| MachineBasicBlock * | emitXRayTypedEvent (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify the XRay typed event operands with target-dependent details. More... | |
Protected Attributes | |
| unsigned | GatherAllAliasesMaxDepth |
| Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More... | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum number of store instructions per memcpy call. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| unsigned | MaxGluedStoresPerMemcpy = 0 |
| Specify max number of store instructions to glue in inlined memcpy. More... | |
| unsigned | MaxLoadsPerMemcmp |
| Specify maximum number of load instructions per memcmp call. More... | |
| unsigned | MaxLoadsPerMemcmpOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| unsigned | MaxStoresPerMemmove |
| Specify maximum number of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Likewise for functions with the OptSize attribute. More... | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More... | |
| bool | EnableExtLdPromotion |
Detailed Description
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.
Definition at line 109 of file TargetLowering.h.
Member Typedef Documentation
◆ ArgListTy
| using llvm::TargetLoweringBase::ArgListTy = std::vector<ArgListEntry> |
Definition at line 205 of file TargetLowering.h.
◆ LegalizeKind
| using llvm::TargetLoweringBase::LegalizeKind = std::pair<LegalizeTypeAction, EVT> |
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition at line 137 of file TargetLowering.h.
Member Enumeration Documentation
◆ AtomicExpansionKind
|
strong |
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Exists because different targets have different levels of support for these atomic instructions, and also have different options w.r.t. what they should expand to.
| Enumerator | |
|---|---|
| None | |
| LLSC | |
| LLOnly | |
| CmpXChg | |
| MaskedIntrinsic | |
Definition at line 159 of file TargetLowering.h.
◆ BooleanContent
Enum that describes how the target represents true/false values.
| Enumerator | |
|---|---|
| UndefinedBooleanContent | |
| ZeroOrOneBooleanContent | |
| ZeroOrNegativeOneBooleanContent | |
Definition at line 140 of file TargetLowering.h.
◆ LegalizeAction
| enum llvm::TargetLoweringBase::LegalizeAction : uint8_t |
This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.
| Enumerator | |
|---|---|
| Legal | |
| Promote | |
| Expand | |
| LibCall | |
| Custom | |
Definition at line 113 of file TargetLowering.h.
◆ LegalizeTypeAction
| enum llvm::TargetLoweringBase::LegalizeTypeAction : uint8_t |
This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.
| Enumerator | |
|---|---|
| TypeLegal | |
| TypePromoteInteger | |
| TypeExpandInteger | |
| TypeSoftenFloat | |
| TypeExpandFloat | |
| TypeScalarizeVector | |
| TypeSplitVector | |
| TypeWidenVector | |
| TypePromoteFloat | |
Definition at line 123 of file TargetLowering.h.
◆ MulExpansionKind
|
strong |
Enum that specifies when a multiplication should be expanded.
| Enumerator | |
|---|---|
| Always | |
| OnlyLegalOrCustom | |
Definition at line 170 of file TargetLowering.h.
◆ ReciprocalEstimate
| enum llvm::TargetLoweringBase::ReciprocalEstimate : int |
Reciprocal estimate status values used by the functions below.
| Enumerator | |
|---|---|
| Unspecified | |
| Disabled | |
| Enabled | |
Definition at line 346 of file TargetLowering.h.
◆ SelectSupportKind
Enum that describes what type of support for selects the target has.
| Enumerator | |
|---|---|
| ScalarValSelect | |
| ScalarCondVectorVal | |
| VectorMaskSelect | |
Definition at line 147 of file TargetLowering.h.
Constructor & Destructor Documentation
◆ TargetLoweringBase() [1/2]
|
explicit |
NOTE: The TargetMachine owns TLOF.
Definition at line 566 of file TargetLoweringBase.cpp.
References llvm::sys::path::begin(), EnableExtLdPromotion, llvm::sys::path::end(), GatherAllAliasesMaxDepth, llvm::TargetMachine::getTargetTriple(), llvm::Sched::ILP, initActions(), InitCmpLibcallCCs(), JumpIsExpensiveOverride, MaxGluedStoresPerMemcpy, MaxLoadsPerMemcmp, MaxLoadsPerMemcmpOptSize, MaxStoresPerMemcpy, MaxStoresPerMemcpyOptSize, MaxStoresPerMemmove, MaxStoresPerMemmoveOptSize, MaxStoresPerMemset, MaxStoresPerMemsetOptSize, PredictableSelectIsExpensive, and UndefinedBooleanContent.
◆ TargetLoweringBase() [2/2]
|
delete |
◆ ~TargetLoweringBase()
|
virtualdefault |
Member Function Documentation
◆ addBypassSlowDiv()
|
inlineprotected |
Tells the code generator which bitwidths to bypass.
Definition at line 2011 of file TargetLowering.h.
Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ AddPromotedToType()
|
inlineprotected |
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.
If that default is insufficient, this method can be used by the target to override the default.
Definition at line 2108 of file TargetLowering.h.
References llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::SITargetLowering::SITargetLowering().
◆ addRegisterClass()
|
inlineprotected |
Add the specified register class as an available regclass for the specified value type.
This indicates the selector can handle values of that class natively.
Definition at line 2018 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::MVT::SimpleTy, and TRI.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ aggressivelyPreferBuildVectorSources()
|
inlinevirtual |
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 2602 of file TargetLowering.h.
Referenced by scalarizeExtractedBinop().
◆ alignLoopsWithOptSize()
|
inlinevirtual |
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Reimplemented in llvm::ARMTargetLowering.
Definition at line 1621 of file TargetLowering.h.
◆ allowsMemoryAccess() [1/2]
|
virtual |
Return true if the target supports a memory access of this type for the given address space and alignment.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1548 of file TargetLoweringBase.cpp.
References allowsMemoryAccessForAlignment().
Referenced by allowsMemoryAccess(), combineConcatVectorOps(), combineLoad(), combineStore(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), and stripTruncAndExt().
◆ allowsMemoryAccess() [2/2]
| bool TargetLoweringBase::allowsMemoryAccess | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| EVT | VT, | ||
| const MachineMemOperand & | MMO, | ||
| bool * | Fast = nullptr |
||
| ) | const |
Return true if the target supports a memory access of this type for the given MachineMemOperand.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1555 of file TargetLoweringBase.cpp.
References allowsMemoryAccess(), llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlignment(), and llvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccessForAlignment() [1/2]
| bool TargetLoweringBase::allowsMemoryAccessForAlignment | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| EVT | VT, | ||
| unsigned | AddrSpace = 0, |
||
| unsigned | Alignment = 1, |
||
| MachineMemOperand::Flags | Flags = MachineMemOperand::MONone, |
||
| bool * | Fast = nullptr |
||
| ) | const |
This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1520 of file TargetLoweringBase.cpp.
References allowsMisalignedMemoryAccesses(), llvm::DataLayout::getABITypeAlignment(), and llvm::EVT::getTypeForEVT().
Referenced by allowsMemoryAccess(), allowsMemoryAccessForAlignment(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), getLoadExtOrTrunc(), getSPDenormModeValue(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), isWordAligned(), llvm::NVPTXTargetLowering::LowerOperation(), and llvm::HexagonTargetLowering::LowerUnalignedLoad().
◆ allowsMemoryAccessForAlignment() [2/2]
| bool TargetLoweringBase::allowsMemoryAccessForAlignment | ( | LLVMContext & | Context, |
| const DataLayout & | DL, | ||
| EVT | VT, | ||
| const MachineMemOperand & | MMO, | ||
| bool * | Fast = nullptr |
||
| ) | const |
Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.
If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).
Definition at line 1540 of file TargetLoweringBase.cpp.
References allowsMemoryAccessForAlignment(), llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlignment(), and llvm::MachineMemOperand::getFlags().
◆ allowsMisalignedMemoryAccesses() [1/2]
|
inlinevirtual |
Determine if the target supports unaligned memory accesses.
This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.
Reimplemented in llvm::PPCTargetLowering, llvm::X86TargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::R600TargetLowering, llvm::MipsSETargetLowering, and llvm::Mips16TargetLowering.
Definition at line 1463 of file TargetLowering.h.
Referenced by allowsMemoryAccessForAlignment(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::allowsMisalignedMemoryAccesses(), findGISelOptimalMemOpLowering(), llvm::TargetLowering::findOptimalMemOpLowering(), getMemCmpLoad(), llvm::AMDGPUTargetLowering::performLoadCombine(), and llvm::AMDGPUTargetLowering::performStoreCombine().
◆ allowsMisalignedMemoryAccesses() [2/2]
|
inlinevirtual |
LLT handling variant.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1471 of file TargetLowering.h.
References llvm::CallingConv::Fast, and llvm::MachineMemOperand::MONone.
◆ allowTruncateForTailCall()
|
inlinevirtual |
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.
Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.
Reimplemented in llvm::X86TargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 2329 of file TargetLowering.h.
Referenced by getNoopInput().
◆ areJTsAllowed()
Return true if lowering to a jump table is allowed.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1012 of file TargetLowering.h.
References llvm::ISD::BR_JT, llvm::ISD::BRIND, llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), and llvm::MVT::Other.
Referenced by llvm::X86TargetLowering::areJTsAllowed(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters().
◆ canCombineStoreAndExtract()
|
inlinevirtual |
Return true if the target can combine store(extractelement VectorTy, Idx).
Cost[out] gives the cost of that transformation when this is true.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 631 of file TargetLowering.h.
◆ canMergeStoresTo()
|
inlinevirtual |
Returns if it's reasonable to merge stores to MemVT size.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::R600TargetLowering.
Definition at line 452 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore().
◆ canOpTrap()
Returns true if the operation can trap for the value type.
VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.
Definition at line 806 of file TargetLoweringBase.cpp.
References assert(), isTypeLegal(), llvm::ISD::SDIV, llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by CollectOpsToWiden().
◆ computeRegisterProperties()
|
protected |
Once all of the register classes are added, this allows us to compute derived properties we expose.
computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition at line 1163 of file TargetLoweringBase.cpp.
References assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, findRepresentativeClass(), llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::MVT::getPow2VectorType(), getPreferredVectorAction(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), getVectorTypeBreakdownMVT(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::isPowerOf2_32(), llvm::MVT::isScalableVector(), isTypeLegal(), llvm::MVT::isVoid, llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE, llvm::MVT::LAST_INTEGER_VALUETYPE, llvm::MVT::LAST_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, LLVM_FALLTHROUGH, llvm_unreachable, llvm::MVT::MAX_ALLOWED_VALUETYPE, llvm::MVT::Other, llvm::MVT::ppcf128, llvm::MSP430ISD::RRC, llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), TypeExpandFloat, TypeExpandInteger, TypePromoteFloat, TypePromoteInteger, TypeScalarizeVector, TypeSoftenFloat, TypeSplitVector, and TypeWidenVector.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ convertSelectOfConstantsToMath()
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.
For example: select Cond, C1, C1-1 –> add (zext Cond), C1-1
Reimplemented in llvm::X86TargetLowering, and llvm::PPCTargetLowering.
Definition at line 1909 of file TargetLowering.h.
Referenced by foldExtendedSignBitTest().
◆ convertSetCCLogicToBitwiseLogic()
|
inlinevirtual |
Use bitwise logic to make pairs of compares more efficient.
For example: and (seteq A, B), (seteq C, D) –> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 505 of file TargetLowering.h.
Referenced by simplifyDivRem().
◆ decomposeMulByConstant()
|
inlinevirtual |
Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.
This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1918 of file TargetLowering.h.
Referenced by tryFoldToZero().
◆ emitAtomicCmpXchgNoStoreLLBalance()
|
inlinevirtual |
Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1824 of file TargetLowering.h.
◆ emitLeadingFence()
|
inlinevirtual |
Inserts in the IR a target-specific intrinsic specifying a fence.
It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.
Inst is the original atomic instruction, prior to other expansions that may be performed.
This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1800 of file TargetLowering.h.
References llvm::IRBuilder< T, Inserter >::CreateFence(), llvm::Instruction::hasAtomicStore(), and llvm::isReleaseOrStronger().
◆ emitLoadLinked()
|
inlinevirtual |
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1735 of file TargetLowering.h.
References llvm_unreachable.
◆ emitMaskedAtomicCmpXchgIntrinsic()
|
inlinevirtual |
Perform a masked cmpxchg using a target-specific intrinsic.
This represents the core LL/SC loop which will be lowered at a late stage by the backend.
Definition at line 1761 of file TargetLowering.h.
References llvm_unreachable.
◆ emitMaskedAtomicRMWIntrinsic()
|
inlinevirtual |
Perform a masked atomicrmw using a target-specific intrinsic.
This represents the core LL/SC loop which will be lowered at a late stage by the backend.
Definition at line 1750 of file TargetLowering.h.
References llvm_unreachable.
◆ emitPatchPoint()
|
protected |
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.
Definition at line 1019 of file TargetLoweringBase.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addMemOperand(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineInstr::eraseFromParent(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getNumOperands(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::DataLayout::getPointerSize(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isFI(), llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex(), llvm::MachineInstr::mayLoad(), MI, and llvm::MachineMemOperand::MOLoad.
Referenced by llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), and llvm::X86TargetLowering::EmitInstrWithCustomInserter().
◆ emitStoreConditional()
|
inlinevirtual |
Perform a store-conditional operation to Addr.
Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1742 of file TargetLowering.h.
References llvm_unreachable.
◆ emitTrailingFence()
|
inlinevirtual |
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1808 of file TargetLowering.h.
References llvm::IRBuilder< T, Inserter >::CreateFence(), and llvm::isAcquireOrStronger().
◆ emitXRayCustomEvent()
|
protected |
Replace/modify the XRay custom event operands with target-dependent details.
Definition at line 1100 of file TargetLoweringBase.cpp.
References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineBasicBlock::insert().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter().
◆ emitXRayTypedEvent()
|
protected |
Replace/modify the XRay typed event operands with target-dependent details.
Definition at line 1115 of file TargetLoweringBase.cpp.
References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineBasicBlock::insert().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter().
◆ enableAggressiveFMAFusion()
Return true if target always beneficiates from combining into FMA for a given value type.
This must typically return false on targets where FMA takes more cycles to execute than FADD.
Reimplemented in llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::NVPTXTargetLowering, and llvm::SITargetLowering.
Definition at line 645 of file TargetLowering.h.
References Context.
Referenced by isContractable().
◆ enableExtLdPromotion()
|
inline |
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Definition at line 626 of file TargetLowering.h.
Referenced by hasSameExtUse().
◆ finalizeLowering()
|
virtual |
Execute target specific actions to finalize target lowering.
This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.
Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.
Definition at line 2001 of file TargetLoweringBase.cpp.
References llvm::MachineRegisterInfo::freezeReservedRegs(), and llvm::MachineFunction::getRegInfo().
Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::ARMTargetLowering::finalizeLowering(), llvm::AArch64TargetLowering::getVaListSizeInBits(), INITIALIZE_PASS(), and llvm::SelectionDAGISel::runOnMachineFunction().
◆ findRepresentativeClass()
|
protectedvirtual |
Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.
Definition at line 1136 of file TargetLoweringBase.cpp.
References llvm::TargetRegisterInfo::getNumRegClasses(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getSpillSize(), isLegalRC(), llvm::SuperRegClassIterator::isValid(), llvm::BitVector::setBitsInMask(), and llvm::MVT::SimpleTy.
Referenced by llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(), computeRegisterProperties(), llvm::ARMTargetLowering::findRepresentativeClass(), and llvm::X86TargetLowering::findRepresentativeClass().
◆ getABIAlignmentForCallingConv()
|
inlinevirtual |
Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type.
Reimplemented in llvm::ARMTargetLowering, and llvm::MipsTargetLowering.
Definition at line 1360 of file TargetLowering.h.
References llvm::DataLayout::getABITypeAlignment().
◆ getAddrModeArguments()
|
inlinevirtual |
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.
This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.
Reimplemented in llvm::SITargetLowering.
Definition at line 2176 of file TargetLowering.h.
◆ getBooleanContents() [1/2]
|
inline |
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.
"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.
Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.
Definition at line 672 of file TargetLowering.h.
Referenced by combineShiftOfShiftedLogic(), llvm::SelectionDAG::computeKnownBits(), llvm::GISelKnownBits::computeKnownBitsImpl(), llvm::SelectionDAG::ComputeNumSignBits(), extractBooleanFlip(), flipBoolean(), foldAddSubMasked1(), foldExtendedSignBitTest(), getAsCarry(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getBoolExtOrTrunc(), getExpandedMinMaxOps(), llvm::TargetLowering::isConstFalseVal(), llvm::TargetLowering::isConstTrueVal(), llvm::TargetLowering::isExtendedTrueVal(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::SimplifyDemandedBits(), tryFoldToZero(), and zeroExtendToMatch().
◆ getBooleanContents() [2/2]
|
inline |
Definition at line 678 of file TargetLowering.h.
References llvm::EVT::isFloatingPoint(), and llvm::EVT::isVector().
◆ getBypassSlowDivWidths()
|
inline |
Returns map of slow types for division or remainder with corresponding fast types.
Definition at line 381 of file TargetLowering.h.
◆ getByValTypeAlignment()
|
virtual |
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
This is the actual alignment, not its logarithm.
Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 1515 of file TargetLoweringBase.cpp.
References llvm::DataLayout::getABITypeAlignment().
Referenced by llvm::CallLowering::setArgFlags().
◆ getCmpLibcallCC()
|
inline |
Get the CondCode that's to be used to test the result of the comparison libcall against zero.
Definition at line 2639 of file TargetLowering.h.
Referenced by llvm::TargetLowering::softenSetCCOperands().
◆ getCmpLibcallReturnType()
|
virtual |
Return the ValueType for comparison libcalls.
Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.
Reimplemented in llvm::AVRTargetLowering.
Definition at line 1382 of file TargetLoweringBase.cpp.
References llvm::MVT::i32.
Referenced by llvm::TargetLowering::softenSetCCOperands().
◆ getCondCodeAction()
|
inline |
Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1183 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.
◆ getDefaultSafeStackPointerLocation()
|
protected |
Definition at line 1677 of file TargetLoweringBase.cpp.
References llvm::GlobalValue::ExternalLinkage, llvm::Module::getContext(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::Module::getNamedValue(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::GlobalValue::InitialExecTLSModel, llvm::GlobalValue::NotThreadLocal, and llvm::report_fatal_error().
Referenced by llvm::X86TargetLowering::getSafeStackPointerLocation(), and getSafeStackPointerLocation().
◆ getDivRefinementSteps()
| int TargetLoweringBase::getDivRefinementSteps | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return the refinement step count for a division of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 1996 of file TargetLoweringBase.cpp.
References getOpRefinementSteps(), and getRecipEstimateForFunc().
◆ getExceptionPointerRegister()
|
inlinevirtual |
If a physical register, this returns the register that receives the exception address on entry to an EH pad.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::MipsTargetLowering, llvm::HexagonTargetLowering, llvm::RISCVTargetLowering, llvm::XCoreTargetLowering, and llvm::SparcTargetLowering.
Definition at line 1586 of file TargetLowering.h.
Referenced by llvm::rdf::DataFlowGraph::DefStack::clear_block(), GetEHSpillList(), and mapWasmLandingPadIndex().
◆ getExceptionSelectorRegister()
|
inlinevirtual |
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::MipsTargetLowering, llvm::HexagonTargetLowering, llvm::RISCVTargetLowering, llvm::XCoreTargetLowering, and llvm::SparcTargetLowering.
Definition at line 1594 of file TargetLowering.h.
Referenced by llvm::rdf::DataFlowGraph::DefStack::clear_block(), GetEHSpillList(), and mapWasmLandingPadIndex().
◆ getExtendForAtomicOps()
|
inlinevirtual |
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
Reimplemented in llvm::SystemZTargetLowering, llvm::MipsTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1880 of file TargetLowering.h.
References llvm::ISD::ZERO_EXTEND.
◆ getExtendForContent()
|
inlinestatic |
Definition at line 210 of file TargetLowering.h.
References llvm::ISD::ANY_EXTEND, llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::SystemZISD::TM, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), and llvm::TargetLowering::LowerAsmOperandForConstraint().
◆ getFenceOperandTy()
|
inlinevirtual |
Return the type for operands of fence.
TODO: Let fence operands be of i32 type and remove this.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 262 of file TargetLowering.h.
Referenced by getUniformBase().
◆ getFixedPointOperationAction()
|
inline |
Some fixed point operations may be natively supported by the target but only for specific scales.
This method allows for checking if the width is supported by the target for a given operation that may depend on scale.
Definition at line 911 of file TargetLowering.h.
References llvm::LegalizeActions::Legal, llvm_unreachable, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::UMULFIX, and llvm::ISD::UMULFIXSAT.
◆ getFrameIndexTy()
|
inline |
Return the type for frame index, which is determined by the alloca address space specified through the data layout.
Definition at line 256 of file TargetLowering.h.
References llvm::DataLayout::getAllocaAddrSpace().
Referenced by addStackMapLiveVars(), llvm::SelectionDAG::CreateStackTemporary(), FixedPointIntrinsicToOpcode(), getAddressForMemoryInput(), llvm::SelectionDAGBuilder::getFrameIndexTy(), and llvm::SelectionDAGBuilder::getValueImpl().
◆ getGatherAllAliasesMaxDepth()
|
inline |
Definition at line 1396 of file TargetLowering.h.
◆ getIndexedLoadAction()
|
inline |
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1147 of file TargetLowering.h.
References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.
◆ getIndexedStoreAction()
|
inline |
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1165 of file TargetLowering.h.
References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.
◆ getIRStackGuard()
If the target has a standard location for the stack protector guard, returns the address of that location.
Otherwise, returns nullptr. DEPRECATED: please override useLoadStackGuardNode and customize LOAD_STACK_GUARD, or customize @llvm.stackguard().
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1769 of file TargetLoweringBase.cpp.
References llvm::Module::getContext(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::Module::getOrInsertGlobal(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), and getTargetMachine().
Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), llvm::X86TargetLowering::getIRStackGuard(), and getStackGuard().
◆ getLibcallCallingConv()
|
inline |
Get the CallingConv that should be used for the specified libcall.
Definition at line 2649 of file TargetLowering.h.
References llvm::ISD::BUILTIN_OP_END, llvm::ISD::LAST_INDEXED_MODE, llvm::MVT::LAST_VALUETYPE, LibcallRoutineNames, llvm::ISD::SETCC_INVALID, llvm::SystemZISD::TM, and TT.
Referenced by getComparePred().
◆ getLibcallName()
|
inline |
Get the libcall routine name for the specified libcall.
Definition at line 2627 of file TargetLowering.h.
References LibcallRoutineNames.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), getComparePred(), isSinCosLibcallAvailable(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), llvm::SparcTargetLowering::LowerOperation(), LowerSINT_TO_FP(), LowerUINT_TO_FP(), optimizeCall(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::returnTypeIsEligibleForTailCall(), and llvm::X86TargetLowering::X86TargetLowering().
◆ getLoadExtAction()
|
inline |
Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1094 of file TargetLowering.h.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::ISD::LAST_LOADEXT_TYPE, llvm::MVT::LAST_VALUETYPE, and llvm::MVT::SimpleTy.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost().
◆ getMaxAtomicSizeInBitsSupported()
|
inline |
Returns the maximum atomic operation size (in bits) supported by the backend.
Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.
Definition at line 1708 of file TargetLowering.h.
Referenced by atomicSizeSupported().
◆ getMaxExpandSizeMemcmp()
Get maximum # of load operations permitted for memcmp.
This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1440 of file TargetLowering.h.
References MaxLoadsPerMemcmp, and MaxLoadsPerMemcmpOptSize.
Referenced by llvm::PPCTTIImpl::enableMemCmpExpansion(), llvm::AArch64TTIImpl::enableMemCmpExpansion(), and llvm::X86TTIImpl::enableMemCmpExpansion().
◆ getMaxGluedStoresPerMemcpy()
|
inlinevirtual |
Get maximum # of store operations to be glued together.
This function returns the maximum number of store operations permitted to glue together during lowering of llvm.memcpy. The value is set by
Definition at line 1430 of file TargetLowering.h.
Referenced by getMemcpyLoadsAndStores().
◆ getMaximumJumpTableSize()
| unsigned TargetLoweringBase::getMaximumJumpTableSize | ( | ) | const |
Return upper limit for number of entries in a jump table.
Zero if no limit.
Definition at line 1809 of file TargetLoweringBase.cpp.
References MaximumJumpTableSize.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().
◆ getMaxStoresPerMemcpy()
Get maximum # of store operations permitted for llvm.memcpy.
This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1421 of file TargetLowering.h.
Referenced by getMemcpyLoadsAndStores().
◆ getMaxStoresPerMemmove()
Get maximum # of store operations permitted for llvm.memmove.
This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1450 of file TargetLowering.h.
Referenced by llvm::ARMTTIImpl::getMemcpyCost(), and getMemmoveLoadsAndStores().
◆ getMaxStoresPerMemset()
Get maximum # of store operations permitted for llvm.memset.
This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 1411 of file TargetLowering.h.
Referenced by getMemsetStores().
◆ getMaxSupportedInterleaveFactor()
|
inlinevirtual |
Get the maximum supported factor for interleaved memory accesses.
Default to be the minimum interleave factor: 2.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2461 of file TargetLowering.h.
Referenced by llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().
◆ getMemValueType()
|
inline |
Definition at line 1256 of file TargetLowering.h.
References llvm::Type::getContext(), llvm::EVT::getEVT(), llvm::EVT::getTypeForEVT(), and llvm::EVT::getVectorVT().
Referenced by llvm::ComputeValueVTs(), findMatchingInlineAsmOperand(), getAddressForMemoryInput(), and getUniformBase().
◆ getMinCmpXchgSizeInBits()
|
inline |
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
Any smaller operations are widened in AtomicExpandPass.
Note that unlike operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.
Definition at line 1719 of file TargetLowering.h.
◆ getMinFunctionAlignment()
|
inline |
Return the minimum function alignment.
Definition at line 1609 of file TargetLowering.h.
Referenced by llvm::MachineFunction::MachineFunction().
◆ getMinimumJumpTableDensity()
Return lower limit of the density in a jump table.
Definition at line 1805 of file TargetLoweringBase.cpp.
References JumpTableDensity, and OptsizeJumpTableDensity.
◆ getMinimumJumpTableEntries()
|
virtual |
Return lower limit for number of blocks in a jump table.
Definition at line 1797 of file TargetLoweringBase.cpp.
References MinimumJumpTableEntries.
Referenced by llvm::PPCTTIImpl::getUserCost().
◆ getMinStackArgumentAlignment()
|
inline |
Return the minimum stack alignment of an argument.
Definition at line 1604 of file TargetLowering.h.
◆ getNumRegisters()
|
inline |
Return the number of registers that this ValueType will eventually require.
This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.
Definition at line 1321 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), GetRegistersForValue(), getShiftAmountTyForConstant(), llvm::FunctionLoweringInfo::getValueFromVirtualReg(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RegsForValue::RegsForValue(), tryToElideArgumentCopy(), and llvm::X86CallLowering::X86CallLowering().
◆ getNumRegistersForCallingConv()
|
inlinevirtual |
Certain targets require unusual breakdowns of certain types.
For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Reimplemented in llvm::X86TargetLowering, llvm::MipsTargetLowering, and llvm::SITargetLowering.
Definition at line 1352 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), findUnwindDestinations(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::GetReturnInfo(), llvm::CallLowering::handleAssignments(), llvm::AArch64CallLowering::lowerReturn(), and llvm::RegsForValue::RegsForValue().
◆ getOperationAction()
|
inline |
Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 891 of file TargetLowering.h.
References llvm::array_lengthof(), llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), and llvm::MVT::SimpleTy.
Referenced by FoldIntToFPToInt(), llvm::ARMTTIImpl::isHardwareLoopProfitable(), reduceBuildVecToShuffleWithZero(), scalarizeBinOpOfSplats(), and llvm::SystemZTargetLowering::SystemZTargetLowering().
◆ getOptimalMemOpLLT()
|
inlinevirtual |
LLT returning variant.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1537 of file TargetLowering.h.
Referenced by findGISelOptimalMemOpLowering().
◆ getOptimalMemOpType()
|
inlinevirtual |
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented in llvm::PPCTargetLowering, llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::SITargetLowering.
Definition at line 1527 of file TargetLowering.h.
References llvm::MVT::Other.
Referenced by llvm::TargetLowering::findOptimalMemOpLowering().
◆ getPointerMemTy()
|
inline |
Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Definition at line 250 of file TargetLowering.h.
References llvm::MVT::getIntegerVT(), and llvm::DataLayout::getPointerSizeInBits().
Referenced by getLoadStackGuard(), mayTailCallThisCC(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getPointerTy()
|
inlinevirtual |
Return the pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 243 of file TargetLowering.h.
References llvm::MVT::getIntegerVT(), and llvm::DataLayout::getPointerSizeInBits().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), callingConvSupported(), CC_Lanai32_VarArg(), CC_RISCV_FastCC(), llvm::ARMTargetLowering::CCAssignFnForReturn(), CheckType(), CheckValueType(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), createPHIsForCMOVsInSinkBB(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), findMatchingInlineAsmOperand(), findUnwindDestinations(), FixedPointIntrinsicToOpcode(), GeneratePerfectShuffle(), getAddressForMemoryInput(), getAVX2GatherNode(), getCopyFromParts(), GetExponent(), getGatherNode(), getIntOperandFromRegisterString(), llvm::SelectionDAG::getIntPtrConstant(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemCmpLoad(), getMOVL(), getNextIntArgReg(), getNormalLoadInput(), getOpenCLAlignment(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPrefetchNode(), llvm::NVPTXTargetLowering::getPrototype(), getRetpolineSymbol(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getScatterNode(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), getSetCCResultType(), getShiftAmountTy(), getShiftAmountTyForConstant(), getTargetNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::intCCToAVRCC(), isBLACompatibleAddress(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), isWorthFoldingADDlow(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), llvm::MSP430TargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), LowerCTPOP(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::MSP430TargetLowering::LowerExternalSymbol(), LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), lowerFABS64(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerMemOpCallTo(), lowerMSABitClearImm(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), llvm::SparcTargetLowering::makeAddress(), mapWasmLandingPadIndex(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformTruncatingStoreCombine(), PrepareCall(), llvm::SwiftErrorValueTracking::propagateVRegs(), recoverFramePointer(), llvm::R600TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), selectI64Imm(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), shouldGuaranteeTCO(), UnpackFromArgumentSlot(), vectorizeExtractedCast(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), VisitGlobalVariableForEmission(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getPredictableBranchThreshold()
|
virtual |
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Definition at line 1563 of file TargetLoweringBase.cpp.
Referenced by isFormingBranchFromSelectProfitable().
◆ getPreferredVectorAction()
|
inlinevirtual |
Return the preferred vector type legalization action.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.
Definition at line 302 of file TargetLowering.h.
References llvm::MVT::getVectorNumElements(), and llvm::MVT::isPow2VectorType().
Referenced by computeRegisterProperties(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), llvm::AArch64TargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), and llvm::X86TargetLowering::getPreferredVectorAction().
◆ getPrefFunctionAlignment()
|
inline |
Return the preferred function alignment.
Definition at line 1612 of file TargetLowering.h.
Referenced by llvm::MachineFunction::MachineFunction().
◆ getPrefLoopAlignment()
|
inlinevirtual |
Return the preferred loop alignment.
Reimplemented in llvm::PPCTargetLowering, and llvm::SITargetLowering.
Definition at line 1615 of file TargetLowering.h.
Referenced by llvm::SITargetLowering::getPrefLoopAlignment(), and llvm::PPCTargetLowering::getPrefLoopAlignment().
◆ getRecipEstimateDivEnabled()
| int TargetLoweringBase::getRecipEstimateDivEnabled | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 1986 of file TargetLoweringBase.cpp.
References getOpEnabled(), and getRecipEstimateForFunc().
◆ getRecipEstimateSqrtEnabled()
| int TargetLoweringBase::getRecipEstimateSqrtEnabled | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 1981 of file TargetLoweringBase.cpp.
References getOpEnabled(), and getRecipEstimateForFunc().
◆ getRegClassFor()
|
inlinevirtual |
Return the register class that should be used for the specified value type.
Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.
Definition at line 696 of file TargetLowering.h.
References assert(), and llvm::MVT::SimpleTy.
Referenced by llvm::CCState::analyzeMustTailForwardedRegisters(), AnalyzeReturnValues(), callingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), createPHIsForCMOVsInSinkBB(), llvm::FunctionLoweringInfo::CreateReg(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitXBegin(), llvm::FastISel::fastEmitInst_extractsubreg(), findMatchingInlineAsmOperand(), FixedPointIntrinsicToOpcode(), getComparePred(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), llvm::SITargetLowering::getRegClassFor(), llvm::ARMTargetLowering::getRegClassFor(), getRetpolineSymbol(), llvm::BPFTargetLowering::getTargetNodeName(), isSortedByValueNo(), lowerFABS64(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), mapWasmLandingPadIndex(), numVectorEltsOrZero(), llvm::SwiftErrorValueTracking::propagateVRegs(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::ResourcePriorityQueue::scheduledNode(), UnpackFromArgumentSlot(), and llvm::X86TargetLowering::X86TargetLowering().
◆ getRegisterType() [1/2]
Return the type of registers that this ValueType will eventually require.
Definition at line 1287 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.
Referenced by llvm::FunctionLoweringInfo::CreateRegs(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::GetReturnInfo(), getShiftAmountTyForConstant(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), Passv64i1ArgInRegs(), llvm::RegsForValue::RegsForValue(), and llvm::X86CallLowering::X86CallLowering().
◆ getRegisterType() [2/2]
|
inline |
Return the type of registers that this ValueType will eventually require.
Definition at line 1293 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.
◆ getRegisterTypeForCallingConv()
|
inlinevirtual |
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
For MIPS all vector types must be passed through the integer register set.
Reimplemented in llvm::X86TargetLowering, llvm::MipsTargetLowering, and llvm::SITargetLowering.
Definition at line 1344 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), findUnwindDestinations(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::GetReturnInfo(), llvm::CallLowering::handleAssignments(), llvm::AArch64CallLowering::lowerReturn(), and llvm::RegsForValue::RegsForValue().
◆ getRepRegClassCostFor()
|
inlinevirtual |
Return the cost of the 'representative' register class for the specified value type.
Definition at line 725 of file TargetLowering.h.
References llvm::MVT::SimpleTy.
◆ getRepRegClassFor()
|
inlinevirtual |
Return the 'representative' register class for the specified value type.
The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.
Reimplemented in llvm::MipsSETargetLowering.
Definition at line 718 of file TargetLowering.h.
References llvm::MVT::SimpleTy.
Referenced by llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), and llvm::MipsSETargetLowering::getRepRegClassFor().
◆ getSafeStackPointerLocation()
Returns the target-specific address of the unsafe stack pointer.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1709 of file TargetLoweringBase.cpp.
References llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::Module::getContext(), getDefaultSafeStackPointerLocation(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::Module::getOrInsertFunction(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPointerTo(), llvm::TargetMachine::getTargetTriple(), and llvm::Triple::isAndroid().
Referenced by llvm::AArch64TargetLowering::getSafeStackPointerLocation(), and llvm::X86TargetLowering::getSafeStackPointerLocation().
◆ getScalarShiftAmountTy()
|
virtual |
EVT is not used in-tree, but is used by out-of-tree target.
A documentation for this function would be nice...
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, llvm::AArch64TargetLowering, llvm::MipsTargetLowering, llvm::XCoreTargetLowering, llvm::SparcTargetLowering, llvm::MSP430TargetLowering, llvm::AVRTargetLowering, and llvm::BPFTargetLowering.
Definition at line 792 of file TargetLoweringBase.cpp.
References llvm::MVT::getIntegerVT(), and llvm::DataLayout::getPointerSizeInBits().
Referenced by getShiftAmountTy(), and isTargetConstant().
◆ getScalingFactorCost()
|
inlinevirtual |
Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.
If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well. TODO: Remove default argument
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2218 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getScalingFactorCost().
◆ getSchedulingPreference() [1/2]
|
inline |
Return target scheduling preference.
Definition at line 683 of file TargetLowering.h.
Referenced by llvm::createDefaultScheduler(), llvm::PPCTargetLowering::getSchedulingPreference(), and llvm::ScheduleDAGSDNodes::newSUnit().
◆ getSchedulingPreference() [2/2]
|
inlinevirtual |
Some scheduler, e.g.
hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.
Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.
Definition at line 690 of file TargetLowering.h.
References llvm::Sched::None.
◆ getSDagStackGuard()
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1789 of file TargetLoweringBase.cpp.
References llvm::Module::getNamedValue().
Referenced by FixedPointIntrinsicToOpcode(), getLoadStackGuard(), llvm::AArch64TargetLowering::getSDagStackGuard(), llvm::ARMTargetLowering::getSDagStackGuard(), and llvm::X86TargetLowering::getSDagStackGuard().
◆ getSetCCResultType()
|
virtual |
Return the ValueType of the result of SETCC operations.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::SITargetLowering, llvm::MipsTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::SparcTargetLowering, llvm::RISCVTargetLowering, llvm::AVRTargetLowering, llvm::BPFTargetLowering, and llvm::R600TargetLowering.
Definition at line 1376 of file TargetLoweringBase.cpp.
References assert(), getPointerTy(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.
Referenced by combineFMinNumFMaxNum(), combineHorizontalPredicateResult(), combineShiftAnd1ToBitTest(), llvm::TargetLowering::expandMUL_LOHI(), foldXorTruncShiftIntoCmp(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFPToInt(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::TargetLowering::softenSetCCOperands(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().
◆ getShiftAmountThreshold()
Reimplemented in llvm::MSP430TargetLowering.
Definition at line 2613 of file TargetLowering.h.
References llvm::EVT::getScalarSizeInBits().
◆ getShiftAmountTy()
| EVT TargetLoweringBase::getShiftAmountTy | ( | EVT | LHSTy, |
| const DataLayout & | DL, | ||
| bool | LegalTypes = true |
||
| ) | const |
Definition at line 797 of file TargetLoweringBase.cpp.
References assert(), getPointerTy(), getScalarShiftAmountTy(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
Referenced by BuildExactSDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), generateEquivalentSub(), GetFPLibCall(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SelectionDAG::getShiftAmountOperand(), getShiftAmountTyForConstant(), isVectorReductionOp(), llvm::AMDGPUTargetLowering::performTruncateCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), and simplifyDivRem().
◆ getSimpleValueType()
|
inline |
Return the MVT corresponding to this LLVM type. See getValueType.
Definition at line 1276 of file TargetLowering.h.
Referenced by findMatchingInlineAsmOperand(), LowerFPToInt(), and llvm::TargetLowering::ParseConstraints().
◆ getSqrtRefinementSteps()
| int TargetLoweringBase::getSqrtRefinementSteps | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return the refinement step count for a square root of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line 1991 of file TargetLoweringBase.cpp.
References getOpRefinementSteps(), and getRecipEstimateForFunc().
◆ getSSPStackGuardCheck()
If the target has a standard stack protection check function that performs validation and error handling, returns the function.
Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1793 of file TargetLoweringBase.cpp.
Referenced by CreatePrologue(), llvm::AArch64TargetLowering::getSSPStackGuardCheck(), llvm::ARMTargetLowering::getSSPStackGuardCheck(), llvm::X86TargetLowering::getSSPStackGuardCheck(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getStackPointerRegisterToSaveRestore()
|
inline |
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 1579 of file TargetLowering.h.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::calculateDbgEntityHistory(), llvm::WinException::endFunclet(), INITIALIZE_PASS(), llvm::TargetInstrInfo::isSchedulingBoundary(), and llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC().
◆ getStackProbeSymbolName()
|
inlinevirtual |
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1662 of file TargetLowering.h.
◆ getStrictFPOperationAction()
|
inline |
Definition at line 936 of file TargetLowering.h.
References llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMA, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSIN, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm_unreachable, llvm::ISD::LRINT, llvm::ISD::LROUND, llvm::ISD::STRICT_FADD, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FCOS, llvm::ISD::STRICT_FDIV, llvm::ISD::STRICT_FEXP, llvm::ISD::STRICT_FEXP2, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FLOG, llvm::ISD::STRICT_FLOG10, llvm::ISD::STRICT_FLOG2, llvm::ISD::STRICT_FMA, llvm::ISD::STRICT_FMAXNUM, llvm::ISD::STRICT_FMINNUM, llvm::ISD::STRICT_FMUL, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FP_EXTEND, llvm::ISD::STRICT_FP_ROUND, llvm::ISD::STRICT_FP_TO_SINT, llvm::ISD::STRICT_FP_TO_UINT, llvm::ISD::STRICT_FPOW, llvm::ISD::STRICT_FPOWI, llvm::ISD::STRICT_FREM, llvm::ISD::STRICT_FRINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FSIN, llvm::ISD::STRICT_FSQRT, llvm::ISD::STRICT_FSUB, llvm::ISD::STRICT_FTRUNC, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, and llvm::ISD::STRICT_LROUND.
◆ getTargetMachine()
|
inline |
Definition at line 236 of file TargetLowering.h.
References llvm::SystemZISD::TM.
Referenced by areCallingConvEligibleForTCO_64SVR4(), llvm::X86TTIImpl::areFunctionArgsABICompatible(), llvm::AArch64TTIImpl::areInlineCompatible(), llvm::ARMTTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areInlineCompatible(), llvm::GCNTTIImpl::areInlineCompatible(), buildPCRelGlobalAddress(), callingConvSupported(), CC_RISCV_FastCC(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineADDToADDZE(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), emitPostSt(), EmitVectorComparison(), EnsureStackAlignment(), llvm::SITargetLowering::finalizeLowering(), llvm::X86TargetLowering::findRepresentativeClass(), FPCCToARMCC(), llvm::NVPTXTargetLowering::getDivF32Level(), llvm::AMDGPUTargetLowering::getImplicitParameterOffset(), getIRStackGuard(), llvm::ARMTargetLowering::getJumpTableEncoding(), llvm::TargetLowering::getJumpTableEncoding(), getMOVL(), llvm::PPCTargetLowering::getOptimalMemOpType(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getTargetNode(), llvm::PPCTargetLowering::isAccessedAsGotIndirect(), llvm::X86TargetLowering::isLegalAddressingMode(), llvm::TargetLowering::isOffsetFoldingLegal(), llvm::SystemZSubtarget::isPC32DBLSymbol(), llvm::TargetLowering::isPositionIndependent(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerEXTRACT_SUBVECTOR(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::SparcTargetLowering::makeAddress(), MatchingStackOffset(), llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(), mayTailCallThisCC(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), PerformSETCCCombine(), PrepareCall(), llvm::SITargetLowering::shouldEmitFixup(), llvm::SITargetLowering::shouldEmitGOTReloc(), llvm::SITargetLowering::shouldEmitPCReloc(), llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::HexagonTargetLowering::shouldReduceLoadWidth(), llvm::NVPTXTargetLowering::usePrecSqrtF32(), and llvm::AArch64Subtarget::useSmallAddressing().
◆ getTgtMemIntrinsic()
|
inlinevirtual |
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).
If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 852 of file TargetLowering.h.
Referenced by getOffsetFromIndices(), and getUniformBase().
◆ getTruncStoreAction()
|
inline |
Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 1120 of file TargetLowering.h.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::MVT::LAST_VALUETYPE, and llvm::MVT::SimpleTy.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost().
◆ getTypeAction() [1/2]
|
inline |
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').
'Custom' is not an option.
Definition at line 773 of file TargetLowering.h.
Referenced by llvm::X86TargetLowering::decomposeMulByConstant(), FindMemType(), llvm::X86TTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::SelectionDAG::getConstant(), llvm::X86TargetLowering::getSetCCResultType(), getShiftAmountTyForConstant(), getVectorTypeBreakdown(), LowerINSERT_VECTOR_ELT_i1(), LowerStore(), OptimizeNoopCopyExpression(), llvm::X86TargetLowering::ReplaceNodeResults(), ShrinkLoadReplaceStoreWithStore(), and tryUnmergingGEPsAcrossIndirectBr().
◆ getTypeAction() [2/2]
|
inline |
Definition at line 776 of file TargetLowering.h.
◆ getTypeLegalizationCost()
| std::pair< int, MVT > TargetLoweringBase::getTypeLegalizationCost | ( | const DataLayout & | DL, |
| Type * | Ty | ||
| ) | const |
Estimate the cost of type-legalization and the legalized type.
Definition at line 1650 of file TargetLoweringBase.cpp.
References C, llvm::Type::getContext(), llvm::EVT::getSimpleVT(), getValueType(), TypeExpandInteger, TypeLegal, and TypeSplitVector.
Referenced by llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::HexagonTTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::HexagonTTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::HexagonTTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), llvm::PPCTTIImpl::getInterleavedMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX2(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::HexagonTTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::PPCTTIImpl::getMemoryOpCost(), llvm::X86TTIImpl::getMemoryOpCost(), llvm::AArch64TTIImpl::getMemoryOpCost(), llvm::ARMTTIImpl::getMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::GCNTTIImpl::getMinMaxReductionCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getNumberOfParts(), llvm::AArch64TTIImpl::getPopcntSupport(), llvm::PPCTTIImpl::getShuffleCost(), llvm::X86TTIImpl::getShuffleCost(), llvm::ARMTTIImpl::getShuffleCost(), llvm::AArch64TTIImpl::getShuffleCost(), llvm::PPCTTIImpl::getUserCost(), llvm::X86TTIImpl::getUserCost(), llvm::AArch64TTIImpl::getVectorInstrCost(), llvm::X86TTIImpl::getVectorInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getVectorInstrCost(), and llvm::PPCTTIImpl::vectorCostAdjustment().
◆ getTypeToExpandTo()
|
inline |
For types supported by the target, this is an identity function.
For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.
Definition at line 794 of file TargetLowering.h.
References assert(), llvm::EVT::isVector(), and llvm_unreachable.
Referenced by getExpandedMinMaxOps().
◆ getTypeToPromoteTo()
If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition at line 1209 of file TargetLowering.h.
References assert(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::MVT::isVoid, and llvm::MVT::SimpleTy.
◆ getTypeToTransformTo()
|
inline |
For types supported by the target, this is an identity function.
For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.
Definition at line 786 of file TargetLowering.h.
Referenced by CollectOpsToWiden(), combineMinNumMaxNum(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::X86TargetLowering::decomposeMulByConstant(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), llvm::SelectionDAG::getConstant(), GetFPLibCall(), getMemcpyLoadsAndStores(), GetPromotionOpcode(), llvm::X86TargetLowering::getSetCCResultType(), getShiftAmountTyForConstant(), getVectorTypeBreakdown(), isNegativeOne(), LowerMSCATTER(), LowerStore(), OptimizeNoopCopyExpression(), llvm::X86TargetLowering::ReplaceNodeResults(), and ShrinkLoadReplaceStoreWithStore().
◆ getVaListSizeInBits()
|
inlinevirtual |
Returns the size of the platform's va_list object.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1401 of file TargetLowering.h.
◆ getValueType()
|
inline |
Return the EVT corresponding to this LLVM type.
This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.
Definition at line 1236 of file TargetLowering.h.
References llvm::Type::getContext(), llvm::EVT::getEVT(), llvm::EVT::getTypeForEVT(), and llvm::EVT::getVectorVT().
Referenced by addStackMapLiveVars(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), combineAdd(), combineMulToPMULDQ(), combineSub(), CompactSwizzlableVector(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ComputeValueVTs(), detectAVGPattern(), detectPMADDUBSW(), llvm::FastISel::fastEmitZExtFromI1(), findMatchingInlineAsmOperand(), FixedPointIntrinsicToOpcode(), generateEquivalentSub(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), getComparePred(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getFPOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX2(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), getMemCmpLoad(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), llvm::GCNTTIImpl::getMinMaxReductionCost(), getOffsetFromIndices(), llvm::NVPTXTargetLowering::getPrototype(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getTypeLegalizationCost(), getUniformBase(), llvm::PPCTTIImpl::getUserCost(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::MipsCallLowering::MipsHandler::handle(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::X86TTIImpl::hasDivRemOp(), hasSameExtUse(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), llvm::ARMTTIImpl::isHardwareLoopProfitable(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedLoadLegal(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedStoreLegal(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::AArch64TargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), isSupportedType(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), isVectorReductionOp(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerInterruptReturn(), makeBitReverse(), matchPMADDWD(), matchPMADDWD_2(), mayTailCallThisCC(), OptimizeExtractBits(), OptimizeNoopCopyExpression(), Passv64i1ArgInRegs(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SinkShiftAndTruncate(), and tryUnmergingGEPsAcrossIndirectBr().
◆ getValueTypeActions()
|
inline |
Definition at line 765 of file TargetLowering.h.
◆ getVectorIdxTy()
|
inlinevirtual |
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.
Reimplemented in llvm::SystemZTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 276 of file TargetLowering.h.
Referenced by CollectOpsToWiden(), createBSWAPShuffleMask(), getCopyFromPartsVector(), getShiftAmountTyForConstant(), getVectorCompareInfo(), isSETCCorConvertedSETCC(), isTruncateOf(), LowerBUILD_VECTORAsVariablePermute(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerReturn_32(), reduceBuildVecToShuffleWithZero(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorStore(), and simplifyShuffleOfShuffle().
◆ getVectorTypeBreakdown()
| unsigned TargetLoweringBase::getVectorTypeBreakdown | ( | LLVMContext & | Context, |
| EVT | VT, | ||
| EVT & | IntermediateVT, | ||
| unsigned & | NumIntermediates, | ||
| MVT & | RegisterVT | ||
| ) | const |
Vector types are broken down into some number of legal first class types.
getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.
For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
Definition at line 1394 of file TargetLoweringBase.cpp.
References getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeToTransformTo(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), isTypeLegal(), llvm::NextPowerOf2(), llvm::X86II::TA, TypePromoteInteger, and TypeWidenVector.
Referenced by getCopyFromPartsVector().
◆ getVectorTypeBreakdownForCallingConv()
|
inlinevirtual |
Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.
This occurs even if the vector type is legal.
Reimplemented in llvm::X86TargetLowering, llvm::MipsTargetLowering, and llvm::SITargetLowering.
Definition at line 825 of file TargetLowering.h.
Referenced by getCopyFromPartsVector(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), and llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv().
◆ hasAndNot()
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 537 of file TargetLowering.h.
Referenced by scalarizeBinOpOfSplats(), and stripTruncAndExt().
◆ hasAndNotCompare()
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.
This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.
Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 530 of file TargetLowering.h.
◆ hasBigEndianPartOrdering()
|
inline |
When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.
Definition at line 1385 of file TargetLowering.h.
References llvm::DataLayout::isBigEndian(), and llvm::MVT::ppcf128.
Referenced by foldBitcastedFPLogic(), and getCopyFromParts().
◆ hasBitPreservingFPLogic()
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.
This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::RISCVTargetLowering.
Definition at line 476 of file TargetLowering.h.
Referenced by foldBitcastedFPLogic().
◆ hasBitTest()
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.
Reimplemented in llvm::X86TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 547 of file TargetLowering.h.
Referenced by combineShiftAnd1ToBitTest().
◆ hasExtractBitsInsn()
|
inline |
Return true if the target has BitExtract instructions.
Definition at line 298 of file TargetLowering.h.
Referenced by tryUnmergingGEPsAcrossIndirectBr().
◆ hasFastEqualityCompare()
|
inlinevirtual |
Return the preferred operand type if the target has a quick way to compare integer values of the given size.
Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.
Reimplemented in llvm::X86TargetLowering.
Definition at line 513 of file TargetLowering.h.
References llvm::MVT::getIntegerVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.
Referenced by getMemCmpLoad().
◆ hasMultipleConditionRegisters()
|
inline |
Return true if multiple condition registers are available.
Definition at line 293 of file TargetLowering.h.
Referenced by sinkCmpExpression().
◆ hasPairedLoad()
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.
RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.
This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).
In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 2451 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore().
◆ hasStandaloneRem()
Return true if the target can handle a standalone remainder operation.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 335 of file TargetLowering.h.
Referenced by getComparePred().
◆ hasTargetDAGCombine()
|
inline |
If true, the target has custom DAG combine transformations that it can perform for the specified node.
Definition at line 1391 of file TargetLowering.h.
References llvm::array_lengthof(), and assert().
◆ hasVectorBlend()
|
inlinevirtual |
Return true if the target has a vector blend instruction.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2457 of file TargetLowering.h.
Referenced by llvm::SelectionDAG::getVectorShuffle().
◆ initActions()
|
protected |
Initialize all of the actions to default values.
Definition at line 601 of file TargetLoweringBase.cpp.
References llvm::ISD::ABS, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, AddPromotedToType(), llvm::MVT::all_valuetypes(), llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_SWAP, llvm::sys::path::begin(), llvm::ISD::BITREVERSE, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DEBUGTRAP, llvm::sys::path::end(), Expand, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FCBRT, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMAD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FNEARBYINT, llvm::MVT::fp_valuetypes(), llvm::ISD::FPOWI, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FTRUNC, llvm::ISD::GET_DYNAMIC_AREA_OFFSET, llvm::MVT::getIntegerVT(), llvm::MVT::i64, llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm::ISD::LRINT, llvm::ISD::LROUND, llvm::MVT::Other, llvm::ISD::PRE_INC, llvm::ISD::PREFETCH, Promote, llvm::ISD::READCYCLECOUNTER, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SETCCCARRY, setIndexedLoadAction(), setIndexedStoreAction(), setOperationAction(), llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SSUBO, llvm::ISD::SSUBSAT, llvm::ISD::STRICT_FADD, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FCOS, llvm::ISD::STRICT_FDIV, llvm::ISD::STRICT_FEXP, llvm::ISD::STRICT_FEXP2, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FLOG, llvm::ISD::STRICT_FLOG10, llvm::ISD::STRICT_FLOG2, llvm::ISD::STRICT_FMA, llvm::ISD::STRICT_FMAXNUM, llvm::ISD::STRICT_FMINNUM, llvm::ISD::STRICT_FMUL, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FP_EXTEND, llvm::ISD::STRICT_FP_ROUND, llvm::ISD::STRICT_FP_TO_SINT, llvm::ISD::STRICT_FP_TO_UINT, llvm::ISD::STRICT_FPOW, llvm::ISD::STRICT_FPOWI, llvm::ISD::STRICT_FREM, llvm::ISD::STRICT_FRINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FSIN, llvm::ISD::STRICT_FSQRT, llvm::ISD::STRICT_FSUB, llvm::ISD::STRICT_FTRUNC, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, llvm::ISD::STRICT_LROUND, llvm::ISD::SUBC, llvm::ISD::SUBCARRY, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULFIX, llvm::ISD::UMULFIXSAT, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::USUBSAT, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by TargetLoweringBase().
◆ insertSSPDeclarations()
|
virtual |
Inserts necessary declarations for SSP (stack protection) purpose.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, and llvm::SparcTargetLowering.
Definition at line 1780 of file TargetLoweringBase.cpp.
References llvm::GlobalValue::ExternalLinkage, llvm::Module::getContext(), llvm::Type::getInt8PtrTy(), and llvm::Module::getNamedValue().
Referenced by getStackGuard(), llvm::SparcTargetLowering::insertSSPDeclarations(), llvm::AArch64TargetLowering::insertSSPDeclarations(), llvm::ARMTargetLowering::insertSSPDeclarations(), llvm::PPCTargetLowering::insertSSPDeclarations(), and llvm::X86TargetLowering::insertSSPDeclarations().
◆ InstructionOpcodeToISD()
| int TargetLoweringBase::InstructionOpcodeToISD | ( | unsigned | Opcode | ) | const |
Get the ISD node that corresponds to the Instruction class opcode.
Definition at line 1571 of file TargetLoweringBase.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::SPII::Load, llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::ISD::OR, llvm::MipsISD::Ret, llvm::ISD::SDIV, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::LanaiTTIImpl::getArithmeticInstrCost(), llvm::PPCTTIImpl::getArithmeticInstrCost(), llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::PPCTTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::PPCTTIImpl::getVectorInstrCost(), llvm::ARMTTIImpl::isHardwareLoopProfitable(), isPromotedInstructionLegal(), SinkShiftAndTruncate(), and llvm::PPCTTIImpl::vectorCostAdjustment().
◆ isBinOp()
Return true if the node is a math/logic binary operator.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2293 of file TargetLowering.h.
References llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by getAsNonOpaqueConstant(), getKnownUndefForVectorBinop(), llvm::X86TargetLowering::isBinOp(), narrowExtractedVectorBinOp(), narrowInsertExtractVectorBinOp(), scalarizeExtractedBinop(), and simplifyShuffleOfShuffle().
◆ isCheapToSpeculateCtlz()
|
inlinevirtual |
Return true if it is cheap to speculate a call to intrinsic ctlz.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::MipsTargetLowering, llvm::AMDGPUTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 463 of file TargetLowering.h.
Referenced by despeculateCountZeros().
◆ isCheapToSpeculateCttz()
|
inlinevirtual |
Return true if it is cheap to speculate a call to intrinsic cttz.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::MipsTargetLowering, llvm::AMDGPUTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 458 of file TargetLowering.h.
Referenced by despeculateCountZeros().
◆ isCommutativeBinOp()
Returns true if the opcode is a commutative binary operation.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2257 of file TargetLowering.h.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::FADD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, and llvm::ISD::XOR.
Referenced by llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getNode(), and llvm::X86TargetLowering::isCommutativeBinOp().
◆ isCondCodeLegal()
|
inline |
Return true if the specified condition code is legal on this target.
Definition at line 1196 of file TargetLowering.h.
References llvm::LegalizeActions::Legal.
Referenced by llvm::R600TargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::ReplaceNodeResults(), simplifyDivRem(), and stripTruncAndExt().
◆ isCondCodeLegalOrCustom()
|
inline |
Return true if the specified condition code is legal or custom on this target.
Definition at line 1202 of file TargetLowering.h.
References llvm::LegalizeActions::Legal.
◆ isCtlzFast()
|
inlinevirtual |
Return true if ctlz instruction is fast.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 468 of file TargetLowering.h.
Referenced by llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl().
◆ isExtFree()
|
inline |
Return true if the extension represented by I is free.
Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by I to decide whether or not I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.
- Precondition
Imust be a sign, zero, or fp extension.
Definition at line 2348 of file TargetLowering.h.
References llvm::EVT::getEVT(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::Value::getType(), and llvm_unreachable.
Referenced by hasSameExtUse(), and isPromotedInstructionLegal().
◆ isExtFreeImpl()
|
inlineprotectedvirtual |
Return true if the extension represented by I is free.
- Precondition
Iis a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.
Definition at line 2837 of file TargetLowering.h.
◆ isExtLoad()
|
inline |
Return true if Load and Ext can form an ExtLoad.
For example, in AArch64 L = load i8, i8* ptr E = zext i8 L to i32 can be lowered into one load instruction ldrb w0, [x0]
Definition at line 2373 of file TargetLowering.h.
References assert(), llvm::Value::getType(), llvm::Value::hasOneUse(), llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.
Referenced by hasSameExtUse().
◆ isExtractSubvectorCheap()
|
inlinevirtual |
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.
This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2564 of file TargetLowering.h.
Referenced by narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), and scalarizeExtractedBinop().
◆ isExtractVecEltCheap()
|
inlinevirtual |
Return true if extraction of a scalar element from the given vector type at the given index is cheap.
For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2579 of file TargetLowering.h.
Referenced by scalarizeBinOpOfSplats(), and simplifyShuffleOfShuffle().
◆ isFAbsFree()
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 2526 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
Referenced by foldBitcastedFPLogic(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), and visitFMinMax().
◆ isFMAFasterThanFMulAndFAdd()
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.
Definition at line 2539 of file TargetLowering.h.
Referenced by FixedPointIntrinsicToOpcode(), getOffsetFromIndices(), and isContractable().
◆ isFNegFree()
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2519 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
Referenced by foldBitcastedFPLogic(), and FoldIntToFPToInt().
◆ isFPExtFoldable()
|
inlinevirtual |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
Reimplemented in llvm::SITargetLowering.
Definition at line 2507 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
Referenced by isContractable().
◆ isFPExtFree()
Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).
Reimplemented in llvm::PPCTargetLowering.
Definition at line 2498 of file TargetLowering.h.
References assert(), and llvm::EVT::isFloatingPoint().
Referenced by llvm::TargetLowering::isNegatibleForFree().
◆ isFPImmLegal()
|
inlinevirtual |
Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 861 of file TargetLowering.h.
Referenced by FoldIntToFPToInt(), llvm::TargetLowering::isNegatibleForFree(), and scalarizeBinOpOfSplats().
◆ isFreeAddrSpaceCast()
|
inlinevirtual |
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
we are happy to sink it into basic blocks. A cast may be free, but not necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
Reimplemented in llvm::SITargetLowering.
Definition at line 1674 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getOperationCost(), and OptimizeNoopCopyExpression().
◆ isFsqrtCheap()
|
inlinevirtual |
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 340 of file TargetLowering.h.
◆ isIndexedLoadLegal()
Return true if the specified indexed load is legal on this target.
Definition at line 1155 of file TargetLowering.h.
References llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::LegalizeActions::Legal.
Referenced by canFoldInAddressingMode(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedLoadLegal().
◆ isIndexedStoreLegal()
Return true if the specified indexed load is legal on this target.
Definition at line 1173 of file TargetLowering.h.
References llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::LegalizeActions::Legal.
Referenced by canFoldInAddressingMode(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isIndexedStoreLegal().
◆ isIntDivCheap()
|
inlinevirtual |
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
The definition of "cheaper" may depend on whether we're optimizing for speed or for size.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 332 of file TargetLowering.h.
Referenced by llvm::TargetLowering::BuildSDIVPow2(), and simplifyDivRem().
◆ isJumpExpensive()
|
inline |
Return true if Flow Control is an expensive operation that should be avoided.
Definition at line 387 of file TargetLowering.h.
Referenced by scaleWeights(), and llvm::SelectionDAGBuilder::ShouldEmitAsBranches().
◆ isJumpTableRelative()
|
inlinevirtual |
Reimplemented in llvm::PPCTargetLowering, and llvm::MipsTargetLowering.
Definition at line 1573 of file TargetLowering.h.
References llvm::TargetMachine::isPositionIndependent().
Referenced by llvm::PPCTargetLowering::isJumpTableRelative().
◆ isLegalAddImmediate()
|
inlinevirtual |
Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2236 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddImmediate(), numVectorEltsOrZero(), and simplifyDivRem().
◆ isLegalAddressingMode()
|
virtual |
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.
If the address space cannot be determined, it will be -1.
TODO: Remove default argument
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::SITargetLowering, llvm::XCoreTargetLowering, llvm::AVRTargetLowering, llvm::ARCTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1728 of file TargetLoweringBase.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.
Referenced by canFoldInAddressingMode(), hasSameExtUse(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddressingMode(), and isPromotedInstructionLegal().
◆ isLegalICmpImmediate()
|
inlinevirtual |
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2229 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalICmpImmediate().
◆ isLegalRC()
|
protected |
Return true if the value types that can be represented by the specified register class are all legal.
isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.
Definition at line 1008 of file TargetLoweringBase.cpp.
References I, isTypeLegal(), llvm::TargetRegisterInfo::legalclasstypes_begin(), and llvm::MVT::Other.
Referenced by findRepresentativeClass(), and llvm::TargetLowering::getRegForInlineAsmConstraint().
◆ isLegalStoreImmediate()
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inlinevirtual |
Return true if the specified immediate is legal for the value input of a store instruction.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2242 of file TargetLowering.h.
Referenced by getMemsetValue().
◆ isLoadBitCastBeneficial()
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inlinevirtual |
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 405 of file TargetLowering.h.
References llvm::CallingConv::Fast, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::ISD::LOAD.
Referenced by foldBitcastedFPLogic(), and llvm::X86TargetLowering::isLoadBitCastBeneficial().
◆ isLoadExtLegal()
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inline |
Return true if the specified load with extension is legal on this target.
Definition at line 1106 of file TargetLowering.h.
References llvm::LegalizeActions::Legal.
Referenced by combineExtInVec(), combineShiftAnd1ToBitTest(), ExtendUsesToFormExtLoad(), foldExtendedSignBitTest(), FoldIntToFPToInt(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), hasSameExtUse(), isTruncateOf(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().
◆ isLoadExtLegalOrCustom()
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inline |
Return true if the specified load with extension is legal or custom on this target.
Definition at line 1112 of file TargetLowering.h.
References llvm::LegalizeActions::Legal.
Referenced by ExtendUsesToFormExtLoad().
◆ isMaskAndCmp0FoldingBeneficial()
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inlinevirtual |
Return if the target supports combining a chain like:
into a single machine instruction of a form like:
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 496 of file TargetLowering.h.
Referenced by sinkAndCmp0Expression().
◆ isMultiStoresCheaperThanBitsMerge()
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inlinevirtual |
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
Reimplemented in llvm::X86TargetLowering.
Definition at line 482 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore(), and splitMergedValStore().
◆ isNarrowingProfitable()
Return true if it's profitable to narrow operations of type VT1 to VT2.
e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 2546 of file TargetLowering.h.
Referenced by isTruncateOf(), ShrinkLoadReplaceStoreWithStore(), and simplifyDivRem().
◆ isNoopAddrSpaceCast()
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inlinevirtual |
Returns true if a cast between SrcAS and DestAS is a noop.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.
Definition at line 1667 of file TargetLowering.h.
Referenced by checkAddrSpaceIsValidForLibcall(), and isPromotedInstructionLegal().
◆ isOperationCustom()
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
Definition at line 1007 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::ReplaceNodeResults(), widenVec(), and llvm::X86TargetLowering::X86TargetLowering().
◆ isOperationExpand()
Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.
This is used to help guide high-level lowering decisions.
Definition at line 1081 of file TargetLowering.h.
Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), scalarizeExtractedBinop(), llvm::X86TargetLowering::shouldFormOverflowOp(), llvm::PPCTTIImpl::vectorCostAdjustment(), and llvm::X86TargetLowering::X86TargetLowering().
◆ isOperationLegal()
Return true if the specified operation is legal on this target.
Definition at line 1086 of file TargetLowering.h.
References llvm::LegalizeActions::Legal, and llvm::MVT::Other.
Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), CanCombineFCOPYSIGN_EXTEND_ROUND(), combineADDToADDZE(), combineLogicBlendIntoConditionalNegate(), combineParity(), combineShiftOfShiftedLogic(), combineTruncatedArithmetic(), llvm::X86TargetLowering::decomposeMulByConstant(), EltsFromConsecutiveLoads(), ExtendUsesToFormExtLoad(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), getBuildPairElt(), getShiftAmountTyForConstant(), llvm::X86TTIImpl::hasDivRemOp(), isClampZeroToOne(), isContractable(), llvm::TargetLowering::isNegatibleForFree(), isTruncateOf(), LowerADDSAT_SUBSAT(), narrowExtractedVectorLoad(), numVectorEltsOrZero(), PerformABSCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), reduceBuildVecToShuffleWithZero(), scalarizeExtractedBinop(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), stripModuloOnShift(), stripTruncAndExt(), tryFoldToZero(), and visitORCommutative().
◆ isOperationLegalOrCustom()
Return true if the specified operation is legal on this target or can be made legal with custom lowering.
This is used to help guide high-level lowering decisions.
Definition at line 980 of file TargetLowering.h.
References llvm::LegalizeActions::Legal, and llvm::MVT::Other.
Referenced by buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), CanCombineFCOPYSIGN_EXTEND_ROUND(), combineExtractSubvector(), combineMinNumMaxNum(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineShuffleToVectorExtend(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), ExtendUsesToFormExtLoad(), extractBooleanFlip(), llvm::TargetLowering::findOptimalMemOpLowering(), FixedPointIntrinsicToOpcode(), foldAddSubMasked1(), foldExtendedSignBitTest(), foldFPToIntToFP(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), getAsCarry(), getExpandedMinMaxOps(), getShiftAmountTyForConstant(), llvm::PPCTTIImpl::getUserCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), isBSwapHWordPair(), isContractable(), llvm::AArch64TargetLowering::isExtractSubvectorCheap(), llvm::ARMTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::TargetLowering::isNegatibleForFree(), llvm::AArch64TargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), LowerBUILD_VECTORAsVariablePermute(), makeBitReverse(), matchRotateSub(), narrowExtractedVectorLoad(), narrowInsertExtractVectorBinOp(), PrepareCall(), scalarizeBinOpOfSplats(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::shouldBuildLookupTables(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), simplifyShuffleOfShuffle(), SinkShiftAndTruncate(), stripTruncAndExt(), tryFoldToZero(), visitFMinMax(), and XFormVExtractWithShuffleIntoLoad().
◆ isOperationLegalOrCustomOrPromote()
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inline |
Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.
This is used to help guide high-level lowering decisions.
Definition at line 998 of file TargetLowering.h.
References llvm::LegalizeActions::Legal, and llvm::MVT::Other.
Referenced by llvm::TargetLowering::expandABS(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getFPOpCost(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), scalarizeBinOpOfSplats(), and llvm::X86TargetLowering::shouldScalarizeBinop().
◆ isOperationLegalOrPromote()
Return true if the specified operation is legal on this target or can be made legal using promotion.
This is used to help guide high-level lowering decisions.
Definition at line 989 of file TargetLowering.h.
References llvm::LegalizeActions::Legal, and llvm::MVT::Other.
Referenced by combineTruncatedArithmetic(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), lowerBuildVectorToBitOp(), and PromoteMaskArithmetic().
◆ isPredictableSelectExpensive()
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inline |
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.
Definition at line 391 of file TargetLowering.h.
Referenced by isFormingBranchFromSelectProfitable().
◆ isProfitableToCombineMinNumMaxNum()
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inlinevirtual |
Definition at line 1904 of file TargetLowering.h.
Referenced by isLegalToCombineMinNumMaxNum().
◆ isProfitableToHoist()
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inlinevirtual |
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 2337 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isProfitableToHoist().
◆ isSafeMemOpType()
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1551 of file TargetLowering.h.
Referenced by llvm::TargetLowering::findOptimalMemOpLowering().
◆ isSelectSupported()
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inlinevirtual |
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 280 of file TargetLowering.h.
◆ isSExtCheaperThanZExt()
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inlinevirtual |
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Reimplemented in llvm::RISCVTargetLowering.
Definition at line 2416 of file TargetLowering.h.
◆ isShuffleMaskLegal()
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inlinevirtual |
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, and llvm::MipsSETargetLowering.
Definition at line 870 of file TargetLowering.h.
Referenced by llvm::TargetLowering::buildLegalVectorShuffle(), ExpandBVWithShuffles(), foldShuffleOfConcatUndefs(), ShrinkLoadReplaceStoreWithStore(), and simplifyShuffleOfShuffle().
◆ isSlowDivBypassed()
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inline |
Returns true if target has indicated at least one type should be bypassed.
Definition at line 377 of file TargetLowering.h.
◆ isStoreBitCastBeneficial()
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inlinevirtual |
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))
Definition at line 428 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore().
◆ isSuitableForBitTests()
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inline |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons.
Check if the number of destinations, comparison metric, and range are all suitable.
Definition at line 1056 of file TargetLowering.h.
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters().
◆ isSuitableForJumpTable()
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inlinevirtual |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.
Definition at line 1031 of file TargetLowering.h.
References llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), and llvm::Function::hasOptSize().
Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters().
◆ isSupportedFixedPointOperation()
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inlinevirtual |
Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.
If not, the operation is illegal.
Definition at line 902 of file TargetLowering.h.
◆ isTruncateFree() [1/2]
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inlinevirtual |
Return true if it's free to truncate a value of type FromTy to type ToTy.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::AMDGPUTargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2320 of file TargetLowering.h.
Referenced by combineShiftOfShiftedLogic(), ExtendUsesToFormExtLoad(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), getMemsetStores(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getOperationCost(), hasSameExtUse(), isPromotedInstructionLegal(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTruncateFree(), isTruncateOf(), numVectorEltsOrZero(), scalarizeExtractedBinop(), llvm::TargetLowering::ShrinkDemandedOp(), and simplifyDivRem().
◆ isTruncateFree() [2/2]
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::AMDGPUTargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2333 of file TargetLowering.h.
◆ isTruncStoreLegal()
Return true if the specified store with truncation is legal on this target.
Definition at line 1131 of file TargetLowering.h.
References llvm::LegalizeActions::Legal.
Referenced by combineMaskedStore(), combineStore(), ShrinkLoadReplaceStoreWithStore(), and simplifyDivRem().
◆ isTruncStoreLegalOrCustom()
Return true if the specified store with truncation has solution on this target.
Definition at line 1137 of file TargetLowering.h.
References llvm::LegalizeActions::Legal.
◆ isTypeLegal()
Return true if the target has native support for the specified value type.
This means that it has a register that directly holds it without promotions or expansions.
Definition at line 739 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), adjustLoadValueTypeImpl(), llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canOpTrap(), CollectOpsToWiden(), combineAdd(), combineCCMask(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectors(), combineExtInVec(), combineExtractSubvector(), combineFMA(), combineFMinNumFMaxNum(), combineFneg(), combineHorizontalPredicateResult(), combineLoad(), combineMulToPMADDWD(), combineParity(), combineShiftAnd1ToBitTest(), combineShuffle(), combineShuffleToFMAddSub(), combineShuffleToVectorExtend(), combineStore(), combineTruncateWithSat(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), computeRegisterProperties(), ConvertCarryFlagToBooleanCarry(), EltsFromConsecutiveLoads(), ExpandBITCAST(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXStoreForLE(), llvm::FastISel::fastEmitZExtFromI1(), llvm::TargetLowering::findOptimalMemOpLowering(), foldBitcastedFPLogic(), getBufferOffsetForMMO(), getConstVector(), getCopyFromPartsVector(), getCopyToParts(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), getLoadExtOrTrunc(), getMemCmpLoad(), llvm::X86TargetLowering::getNegatedExpression(), getPromotedVectorElementType(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), llvm::SITargetLowering::hasBitPreservingFPLogic(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), isAddSubOrSubAdd(), isFloatingPointZero(), isLegalRC(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), llvm::X86TargetLowering::isNegatibleForFree(), isNoopBitcast(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSubBorrowChain(), llvm::X86TargetLowering::isTypeDesirableForOp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerBITCAST(), lowerFCMPIntrinsic(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), lowerICMPIntrinsic(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), LowerMUL(), lowerShuffleAsElementInsertion(), lowerShuffleAsShift(), LowerSINT_TO_FP(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP(), lowerVectorShuffle(), LowerXALUO(), LowerXOR(), matchRotateSub(), mayTailCallThisCC(), narrowExtractedVectorLoad(), numVectorEltsOrZero(), OptimizeExtractBits(), parseTexFail(), performANDCombine(), PerformANDCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), performORCombine(), PerformORCombine(), performSelectCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), PerformTruncatingStoreCombine(), PerformVECTOR_SHUFFLECombine(), PerformXORCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), reduceBuildVecToShuffleWithZero(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::X86TargetLowering::shouldSplatInsEltVarIndex(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), simplifyShuffleOfShuffle(), llvm::SystemZTargetLowering::SystemZTargetLowering(), tryToFoldExtendOfConstant(), vectorEltWillFoldAway(), llvm::SelectionDAGBuilder::visitBitTestHeader(), visitORCommutative(), and llvm::X86TargetLowering::X86TargetLowering().
◆ isVectorClearMaskLegal()
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inlinevirtual |
Similar to isShuffleMaskLegal.
Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented in llvm::X86TargetLowering.
Definition at line 883 of file TargetLowering.h.
Referenced by simplifyShuffleOfShuffle().
◆ isVectorLoadExtDesirable()
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inlinevirtual |
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2515 of file TargetLowering.h.
Referenced by ExtendUsesToFormExtLoad(), tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().
◆ isVectorShiftByScalarCheap()
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.
On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2252 of file TargetLowering.h.
Referenced by getTrueOrFalseValue(), and isBroadcastShuffle().
◆ isZExtFree() [1/3]
|
inlinevirtual |
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.
The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, and llvm::MSP430TargetLowering.
Definition at line 2406 of file TargetLowering.h.
Referenced by combineShuffleOfScalars(), ExtendUsesToFormExtLoad(), foldCONCAT_VECTORS(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::RegsForValue::getCopyToRegs(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getOperationCost(), hasSameExtUse(), isTruncateOf(), llvm::RISCVTargetLowering::isZExtFree(), llvm::PPCTargetLowering::isZExtFree(), llvm::TargetLowering::ShrinkDemandedOp(), simplifyDivRem(), and tryToFoldExtendOfConstant().
◆ isZExtFree() [2/3]
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, and llvm::MSP430TargetLowering.
Definition at line 2410 of file TargetLowering.h.
◆ isZExtFree() [3/3]
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::AMDGPUTargetLowering, llvm::MSP430TargetLowering, llvm::XCoreTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 2491 of file TargetLowering.h.
References llvm::SDValue::getValueType().
◆ lowerIdempotentRMWIntoFencedLoad()
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inlinevirtual |
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.
This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.
Definition at line 1874 of file TargetLowering.h.
◆ lowerInterleavedLoad()
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inlinevirtual |
Lower an interleaved load to target specific intrinsics.
Return true on success.
LI is the vector load instruction. Shuffles is the shufflevector list to DE-interleave the loaded vector. Indices is the corresponding indices for each shufflevector. Factor is the interleave factor.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2470 of file TargetLowering.h.
◆ lowerInterleavedStore()
|
inlinevirtual |
Lower an interleaved store to target specific intrinsics.
Return true on success.
SI is the vector store instruction. SVI is the shufflevector to RE-interleave the stored vector. Factor is the interleave factor.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2483 of file TargetLowering.h.
◆ markLibCallAttributes()
|
inlinevirtual |
Reimplemented in llvm::X86TargetLowering.
Definition at line 207 of file TargetLowering.h.
Referenced by llvm::TargetLowering::CallLoweringInfo::setLibCallee().
◆ mergeStoresAfterLegalization()
|
inlinevirtual |
Allow store merging for the specified type after legalization in addition to before legalization.
This may transform stores that do not exist earlier (for example, stores created from intrinsics).
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 447 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore().
◆ needsFixedCatchObjects()
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inlinevirtual |
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1599 of file TargetLowering.h.
References llvm::report_fatal_error().
◆ operator=()
|
delete |
◆ preferIncOfAddToSubOfNot()
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.
Some targets may prefer one to the other.
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 618 of file TargetLowering.h.
Referenced by foldAddSubMasked1(), foldAddSubOfSignBit(), and tryFoldToZero().
◆ rangeFitsInWord()
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inline |
Check whether the range [Low,High] fits in a machine word.
Definition at line 1021 of file TargetLowering.h.
References llvm::DataLayout::getIndexSizeInBits(), and UINT64_MAX.
◆ reduceSelectOfFPConstantLoads()
|
inlinevirtual |
Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.
The parameter may be used to differentiate a select with FP compare from integer compare.
Reimplemented in llvm::X86TargetLowering.
Definition at line 288 of file TargetLowering.h.
Referenced by scalarizeBinOpOfSplats().
◆ requiresUniformRegister()
|
inlinevirtual |
Allows target to decide about the register class of the specific value that is live outside the defining block.
Returns true if the value needs uniform register class.
Reimplemented in llvm::SITargetLowering.
Definition at line 706 of file TargetLowering.h.
Referenced by llvm::FunctionLoweringInfo::CreateRegs().
◆ setBooleanContents() [1/2]
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inlineprotected |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
See getBooleanContents.
Definition at line 1940 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setBooleanContents() [2/2]
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inlineprotected |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
See getBooleanContents.
Definition at line 1947 of file TargetLowering.h.
◆ setBooleanVectorContents()
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inlineprotected |
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type.
See getBooleanContents.
Definition at line 1954 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setCmpLibcallCC()
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inline |
Override the default CondCode to be used to test the result of the comparison libcall against zero.
Definition at line 2633 of file TargetLowering.h.
◆ setCondCodeAction()
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inlineprotected |
Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.
The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit value and the upper 29 bits index into the second dimension of the array to select what 32-bit value to use.
Definition at line 2091 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), llvm::MVT::isValid(), and llvm::MVT::SimpleTy.
Referenced by llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setHasExtractBitsInsn()
Tells the code generator that the target has BitExtract instructions.
The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.
Definition at line 2001 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), and llvm::SITargetLowering::SITargetLowering().
◆ setHasMultipleConditionRegisters()
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inlineprotected |
Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.
With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.
Definition at line 1993 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().
◆ setIndexedLoadAction()
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inlineprotected |
Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.
NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp
Definition at line 2066 of file TargetLowering.h.
References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MSP430TargetLowering::MSP430TargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().
◆ setIndexedStoreAction()
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inlineprotected |
Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.
NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp
Definition at line 2080 of file TargetLowering.h.
References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), and llvm::PPCTargetLowering::PPCTargetLowering().
◆ setJumpIsExpensive()
Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.
Definition at line 819 of file TargetLoweringBase.cpp.
References llvm::array_lengthof(), assert(), Context, llvm::EVT::getIntegerVT(), llvm::EVT::getPow2VectorType(), llvm::EVT::getRoundIntegerType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::EVT::isInteger(), llvm::EVT::isPow2VectorType(), llvm::isPowerOf2_32(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::MVT::isVector(), JumpIsExpensiveOverride, llvm::NextPowerOf2(), llvm::MVT::SimpleTy, TypeExpandInteger, TypeLegal, TypePromoteInteger, TypeScalarizeVector, TypeSoftenFloat, TypeSplitVector, and TypeWidenVector.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().
◆ setLibcallCallingConv()
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inline |
Set the CallingConv that should be used for the specified libcall.
Definition at line 2644 of file TargetLowering.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), darwinHasSinCos(), llvm::LanaiTargetLowering::LanaiTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setLibcallName()
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inline |
Rename the default libcall routine name for the specified libcall.
Definition at line 2622 of file TargetLowering.h.
References LibcallRoutineNames, and Name.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), darwinHasSinCos(), llvm::Mips16TargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setLoadExtAction()
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inlineprotected |
Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.
Definition at line 2043 of file TargetLowering.h.
References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_LOADEXT_TYPE, and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setMaxAtomicSizeInBitsSupported()
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Set the maximum atomic operation size supported by the backend.
Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.
Definition at line 2152 of file TargetLowering.h.
Referenced by llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setMaximumJumpTableSize()
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protected |
Indicate the maximum number of entries in jump tables.
Set to zero to generate unlimited jump tables.
Definition at line 1813 of file TargetLoweringBase.cpp.
References MaximumJumpTableSize.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().
◆ setMinCmpXchgSizeInBits()
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inlineprotected |
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition at line 2157 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::SparcTargetLowering::SparcTargetLowering().
◆ setMinFunctionAlignment()
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inlineprotected |
Set the target's minimum function alignment.
Definition at line 2128 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setMinimumJumpTableEntries()
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Indicate the minimum number of blocks to generate jump tables.
Definition at line 1801 of file TargetLoweringBase.cpp.
References MinimumJumpTableEntries.
Referenced by llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().
◆ setMinStackArgumentAlignment()
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inlineprotected |
Set the minimum stack alignment of an argument.
Definition at line 2144 of file TargetLowering.h.
Referenced by llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().
◆ setOperationAction()
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inlineprotected |
Indicate that the specified operation does not work with the specified type and indicate what to do about it.
Note that VT may refer to either the type of a result or that of an operand of Op.
Definition at line 2035 of file TargetLowering.h.
References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setOperationPromotedToType()
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inlineprotected |
Convenience method to set an operation to Promote and specify the type in a single call.
Definition at line 2114 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setPrefFunctionAlignment()
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inlineprotected |
Set the target's preferred function alignment.
This should be set if there is a performance benefit to higher-than-minimum alignment
Definition at line 2134 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setPrefLoopAlignment()
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inlineprotected |
Set the target's preferred loop alignment.
Default alignment is one, it means the target does not care about loop alignment. The target may also override getPrefLoopAlignment to provide per-loop values.
Definition at line 2141 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setSchedulingPreference()
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inlineprotected |
Specify the target scheduling preference.
Definition at line 1959 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setStackPointerRegisterToSaveRestore()
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If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 1984 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setSupportsUnalignedAtomics()
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inlineprotected |
Sets whether unaligned atomic operations are supported.
Definition at line 2162 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::AVRTargetLowering::AVRTargetLowering().
◆ setTargetDAGCombine()
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inlineprotected |
Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.
Definition at line 2122 of file TargetLowering.h.
References llvm::array_lengthof(), and assert().
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setTruncStoreAction()
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inlineprotected |
Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.
Definition at line 2055 of file TargetLowering.h.
References assert(), llvm::MVT::isValid(), and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setUseUnderscoreLongJmp()
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inlineprotected |
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _.
Defaults to false.
Definition at line 1971 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ setUseUnderscoreSetJmp()
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inlineprotected |
Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _.
Defaults to false.
Definition at line 1965 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ shouldAlignPointerArgs()
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inlinevirtual |
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.
If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 1682 of file TargetLowering.h.
◆ shouldConsiderGEPOffsetSplit()
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inlinevirtual |
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 2609 of file TargetLowering.h.
Referenced by isPromotedInstructionLegal().
◆ shouldConvertConstantLoadToIntImm()
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inlinevirtual |
Return true if it is beneficial to convert a load of a constant to just the constant itself.
On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.
Definition at line 2555 of file TargetLowering.h.
Referenced by getMemsetStringVal().
◆ shouldExpandAtomicCmpXchgInIR()
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inlinevirtual |
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1851 of file TargetLowering.h.
References llvm::None.
◆ shouldExpandAtomicLoadInIR()
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inlinevirtual |
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1844 of file TargetLowering.h.
References llvm::None.
◆ shouldExpandAtomicRMWInIR()
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inlinevirtual |
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Default is to never expand.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::AMDGPUTargetLowering, and llvm::SparcTargetLowering.
Definition at line 1857 of file TargetLowering.h.
References llvm::AtomicRMWInst::isFloatingPointOperation(), and llvm::None.
◆ shouldExpandAtomicStoreInIR()
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inlinevirtual |
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1828 of file TargetLowering.h.
◆ shouldExpandBuildVectorWithShuffles()
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inlinevirtual |
Reimplemented in llvm::PPCTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 323 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::shouldExpandBuildVectorWithShuffles().
◆ shouldExpandShift()
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inlinevirtual |
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a library call is preferred (e.g for code-size reasons).
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.
Definition at line 732 of file TargetLowering.h.
◆ shouldExtendTypeInLibCall()
Returns true if arguments should be extended in lib calls.
Reimplemented in llvm::RISCVTargetLowering.
Definition at line 1838 of file TargetLowering.h.
◆ shouldFoldConstantShiftPairToMask()
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inlinevirtual |
Return true if it is profitable to fold a pair of shifts into a mask.
This is usually true on most targets. But some targets, like Thumb1, have immediate shift instructions, but no immediate "and" instruction; this makes the fold unprofitable.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::MipsTargetLowering.
Definition at line 563 of file TargetLowering.h.
Referenced by combineShiftOfShiftedLogic(), and llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask().
◆ shouldFoldMaskToVariableShiftPair()
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inlinevirtual |
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred.
Return false if there is no preference.
Reimplemented in llvm::X86TargetLowering.
Definition at line 554 of file TargetLowering.h.
Referenced by simplifyDivRem().
◆ shouldFormOverflowOp()
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inlinevirtual |
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Targets may want to override this independently of whether the operation is legal/custom for the given type because it may obscure matching of other patterns.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2587 of file TargetLowering.h.
References llvm::EVT::isSimple(), llvm::EVT::isVector(), and llvm::ISD::UADDO.
◆ shouldInsertFencesForAtomic()
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inlinevirtual |
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
This should be true for most architectures with weak memory ordering. Defaults to false.
Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SparcTargetLowering, and llvm::RISCVTargetLowering.
Definition at line 1727 of file TargetLowering.h.
◆ shouldNormalizeToSelectSequence()
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inlinevirtual |
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
Targets that are able to perform and/or on flags should return false here.
Definition at line 1891 of file TargetLowering.h.
◆ shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
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inlinevirtual |
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 588 of file TargetLowering.h.
References llvm::ConstantSDNode::isOne(), llvm::ISD::SHL, and llvm::SystemZISD::XC.
Referenced by llvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), and llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().
◆ shouldReduceLoadWidth()
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inlinevirtual |
Return true if it is profitable to reduce a load to a smaller type.
Example: (i16 (trunc (i32 (load x))) -> i16 load x
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1372 of file TargetLowering.h.
References llvm::SDNode::hasOneUse(), and llvm::EVT::isVector().
Referenced by narrowExtractedVectorLoad(), llvm::AMDGPUTargetLowering::shouldReduceLoadWidth(), llvm::HexagonTargetLowering::shouldReduceLoadWidth(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), ShrinkLoadReplaceStoreWithStore(), and simplifyDivRem().
◆ shouldScalarizeBinop()
Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2571 of file TargetLowering.h.
Referenced by scalarizeExtractedBinop().
◆ ShouldShrinkFPConstant()
If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1368 of file TargetLowering.h.
◆ shouldSignExtendTypeInLibCall()
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inlinevirtual |
Returns true if arguments should be sign-extended in lib calls.
Definition at line 1833 of file TargetLowering.h.
◆ shouldSinkOperands()
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inlinevirtual |
Return true if sinking I's operands to the same basic block as I is profitable, e.g.
because the operands can be folded into a target instruction during instruction selection. After calling the function Ops contains the Uses to sink ordered by dominance (dominating users come first).
Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2425 of file TargetLowering.h.
Referenced by isBroadcastShuffle().
◆ shouldSplatInsEltVarIndex()
Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.
Reimplemented in llvm::X86TargetLowering.
Definition at line 638 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore().
◆ shouldTransformSignedTruncationCheck()
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inlinevirtual |
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.
Return false if there is no preference.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 575 of file TargetLowering.h.
◆ shouldUseStrictFP_TO_INT()
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inlinevirtual |
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.
This may be true if the target throws exceptions for out of bounds conversions or has fast FP CMOV.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1928 of file TargetLowering.h.
◆ storeOfVectorConstantIsCheap()
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inlinevirtual |
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 438 of file TargetLowering.h.
Referenced by ShrinkLoadReplaceStoreWithStore().
◆ supportsUnalignedAtomics()
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inline |
Whether the target supports unaligned atomic operations.
Definition at line 1722 of file TargetLowering.h.
Referenced by getUniformBase().
◆ useSoftFloat()
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inlinevirtual |
Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::SparcTargetLowering.
Definition at line 238 of file TargetLowering.h.
Referenced by sinkCmpExpression().
◆ useStackGuardXorFP()
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inlinevirtual |
If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.
getIRStackGuard must return nullptr if this returns true.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1644 of file TargetLowering.h.
Referenced by CreatePrologue(), FixedPointIntrinsicToOpcode(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ usesUnderscoreLongJmp()
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inline |
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
Definition at line 1559 of file TargetLowering.h.
Referenced by FixedPointIntrinsicToOpcode().
◆ usesUnderscoreSetJmp()
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inline |
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
Definition at line 1554 of file TargetLowering.h.
Referenced by FixedPointIntrinsicToOpcode().
Member Data Documentation
◆ EnableExtLdPromotion
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protected |
- See also
- enableExtLdPromotion.
Definition at line 2914 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), TargetLoweringBase(), and llvm::X86TargetLowering::X86TargetLowering().
◆ GatherAllAliasesMaxDepth
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protected |
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain.
As an approximation, this should be more than the number of consecutive stores expected to be merged.
Definition at line 2843 of file TargetLowering.h.
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and TargetLoweringBase().
◆ MaxGluedStoresPerMemcpy
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protected |
Specify max number of store instructions to glue in inlined memcpy.
When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number of store instructions to keep together. This helps in pairing and
Definition at line 2878 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), and TargetLoweringBase().
◆ MaxLoadsPerMemcmp
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protected |
Specify maximum number of load instructions per memcmp call.
When lowering @llvm.memcmp this field specifies the maximum number of pairs of load operations that may be substituted for a call to memcmp. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcmp will be done using as many of the largest load operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, loading 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte load, a one 2-byte load and one 1-byte load. This only applies to copying a constant array of constant size.
Definition at line 2891 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), and llvm::X86TargetLowering::X86TargetLowering().
◆ MaxLoadsPerMemcmpOptSize
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protected |
Likewise for functions with the OptSize attribute.
Definition at line 2893 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), and llvm::X86TargetLowering::X86TargetLowering().
◆ MaxStoresPerMemcpy
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protected |
Specify maximum number of store instructions per memcpy call.
When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.
Definition at line 2870 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemcpyOptSize
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protected |
Likewise for functions with the OptSize attribute.
Definition at line 2872 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemmove
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protected |
Specify maximum number of store instructions per memmove call.
When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.
Definition at line 2905 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemmoveOptSize
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protected |
Likewise for functions with the OptSize attribute.
Definition at line 2907 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemset
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protected |
Specify maximum number of store instructions per memset call.
When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.
Definition at line 2855 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemsetOptSize
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protected |
Likewise for functions with the OptSize attribute.
Definition at line 2857 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ PredictableSelectIsExpensive
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protected |
Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.
Definition at line 2911 of file TargetLowering.h.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), TargetLoweringBase(), and llvm::X86TargetLowering::X86TargetLowering().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetLowering.h
- lib/CodeGen/TargetLoweringBase.cpp
