LLVM  14.0.0git
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
79  };
80 
81 protected:
82  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
84 
85  bool HasV8_1aOps = false;
86  bool HasV8_2aOps = false;
87  bool HasV8_3aOps = false;
88  bool HasV8_4aOps = false;
89  bool HasV8_5aOps = false;
90  bool HasV8_6aOps = false;
91  bool HasV8_7aOps = false;
92 
93  bool HasV8_0rOps = false;
94  bool HasCONTEXTIDREL2 = false;
95 
96  bool HasFPARMv8 = false;
97  bool HasNEON = false;
98  bool HasCrypto = false;
99  bool HasDotProd = false;
100  bool HasCRC = false;
101  bool HasLSE = false;
102  bool HasLSE2 = false;
103  bool HasRAS = false;
104  bool HasRDM = false;
105  bool HasPerfMon = false;
106  bool HasFullFP16 = false;
107  bool HasFP16FML = false;
108  bool HasSPE = false;
109 
110  // ARMv8.1 extensions
111  bool HasVH = false;
112  bool HasPAN = false;
113  bool HasLOR = false;
114 
115  // ARMv8.2 extensions
116  bool HasPsUAO = false;
117  bool HasPAN_RWV = false;
118  bool HasCCPP = false;
119 
120  // SVE extensions
121  bool HasSVE = false;
123 
124  // Armv8.2 Crypto extensions
125  bool HasSM4 = false;
126  bool HasSHA3 = false;
127  bool HasSHA2 = false;
128  bool HasAES = false;
129 
130  // ARMv8.3 extensions
131  bool HasPAuth = false;
132  bool HasJS = false;
133  bool HasCCIDX = false;
134  bool HasComplxNum = false;
135 
136  // ARMv8.4 extensions
137  bool HasNV = false;
138  bool HasMPAM = false;
139  bool HasDIT = false;
140  bool HasTRACEV8_4 = false;
141  bool HasAM = false;
142  bool HasSEL2 = false;
143  bool HasTLB_RMI = false;
144  bool HasFlagM = false;
145  bool HasRCPC_IMMO = false;
146 
147  bool HasLSLFast = false;
148  bool HasRCPC = false;
149  bool HasAggressiveFMA = false;
150 
151  // Armv8.5-A Extensions
152  bool HasAlternativeNZCV = false;
153  bool HasFRInt3264 = false;
154  bool HasSpecRestrict = false;
155  bool HasSSBS = false;
156  bool HasSB = false;
157  bool HasPredRes = false;
158  bool HasCCDP = false;
159  bool HasBTI = false;
160  bool HasRandGen = false;
161  bool HasMTE = false;
162  bool HasTME = false;
163 
164  // Armv8.6-A Extensions
165  bool HasBF16 = false;
166  bool HasMatMulInt8 = false;
167  bool HasMatMulFP32 = false;
168  bool HasMatMulFP64 = false;
169  bool HasAMVS = false;
170  bool HasFineGrainedTraps = false;
172 
173  // Armv8.7-A Extensions
174  bool HasXS = false;
175  bool HasWFxT = false;
176  bool HasHCX = false;
177  bool HasLS64 = false;
178 
179  // Arm SVE2 extensions
180  bool HasSVE2 = false;
181  bool HasSVE2AES = false;
182  bool HasSVE2SM4 = false;
183  bool HasSVE2SHA3 = false;
184  bool HasSVE2BitPerm = false;
185 
186  // Armv9-A Extensions
187  bool HasRME = false;
188 
189  // Arm Scalable Matrix Extension (SME)
190  bool HasSME = false;
191  bool HasSMEF64 = false;
192  bool HasSMEI64 = false;
193  bool HasStreamingSVE = false;
194 
195  // Future architecture extensions.
196  bool HasETE = false;
197  bool HasTRBE = false;
198  bool HasBRBE = false;
199  bool HasPAUTH = false;
200  bool HasSPE_EEF = false;
201 
202  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
203  bool HasZeroCycleRegMove = false;
204 
205  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
206  bool HasZeroCycleZeroing = false;
207  bool HasZeroCycleZeroingGP = false;
209 
210  // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
211  // as movi is more efficient across all cores. Newer cores can eliminate
212  // fmovs early and there is no difference with movi, but this not true for
213  // all implementations.
215 
216  // StrictAlign - Disallow unaligned memory accesses.
217  bool StrictAlign = false;
218 
219  // NegativeImmediates - transform instructions with negative immediates
220  bool NegativeImmediates = true;
221 
222  // Enable 64-bit vectorization in SLP.
224 
225  bool OutlineAtomics = false;
227  bool BalanceFPOps = false;
228  bool CustomAsCheapAsMove = false;
229  bool ExynosAsCheapAsMove = false;
230  bool UsePostRAScheduler = false;
232  bool Paired128IsSlow = false;
233  bool STRQroIsSlow = false;
237  bool HasCmpBccFusion = false;
238  bool HasFuseAddress = false;
239  bool HasFuseAES = false;
241  bool HasFuseCCSelect = false;
242  bool HasFuseCryptoEOR = false;
243  bool HasFuseLiterals = false;
245  bool UseRSqrt = false;
246  bool Force32BitJumpTables = false;
247  bool UseEL1ForTP = false;
248  bool UseEL2ForTP = false;
249  bool UseEL3ForTP = false;
250  bool AllowTaggedGlobals = false;
251  bool HardenSlsRetBr = false;
252  bool HardenSlsBlr = false;
253  bool HardenSlsNoComdat = false;
254  uint8_t MaxInterleaveFactor = 2;
259  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
261  unsigned PrefLoopLogAlignment = 0;
262  unsigned MaxJumpTableSize = 0;
263  unsigned WideningBaseCost = 0;
264 
265  // ReserveXRegister[i] - X#i is not available as a general purpose register.
267 
268  // CustomCallUsedXRegister[i] - X#i call saved.
270 
271  bool IsLittle;
272 
275 
276  /// TargetTriple - What processor and OS we're targeting.
278 
283 
284  /// GlobalISel related APIs.
285  std::unique_ptr<CallLowering> CallLoweringInfo;
286  std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
287  std::unique_ptr<InstructionSelector> InstSelector;
288  std::unique_ptr<LegalizerInfo> Legalizer;
289  std::unique_ptr<RegisterBankInfo> RegBankInfo;
290 
291 private:
292  /// initializeSubtargetDependencies - Initializes using CPUString and the
293  /// passed in feature string so that we can use initializer lists for
294  /// subtarget initialization.
295  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
296  StringRef CPUString);
297 
298  /// Initialize properties based on the selected processor family.
299  void initializeProperties();
300 
301 public:
302  /// This constructor initializes the data members to match that
303  /// of the specified triple.
304  AArch64Subtarget(const Triple &TT, const std::string &CPU,
305  const std::string &FS, const TargetMachine &TM,
306  bool LittleEndian,
307  unsigned MinSVEVectorSizeInBitsOverride = 0,
308  unsigned MaxSVEVectorSizeInBitsOverride = 0);
309 
311  return &TSInfo;
312  }
313  const AArch64FrameLowering *getFrameLowering() const override {
314  return &FrameLowering;
315  }
316  const AArch64TargetLowering *getTargetLowering() const override {
317  return &TLInfo;
318  }
319  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
320  const AArch64RegisterInfo *getRegisterInfo() const override {
321  return &getInstrInfo()->getRegisterInfo();
322  }
323  const CallLowering *getCallLowering() const override;
324  const InlineAsmLowering *getInlineAsmLowering() const override;
326  const LegalizerInfo *getLegalizerInfo() const override;
327  const RegisterBankInfo *getRegBankInfo() const override;
328  const Triple &getTargetTriple() const { return TargetTriple; }
329  bool enableMachineScheduler() const override { return true; }
330  bool enablePostRAScheduler() const override {
331  return UsePostRAScheduler;
332  }
333 
334  /// Returns ARM processor family.
335  /// Avoid this function! CPU specifics should be kept local to this class
336  /// and preferably modeled with SubtargetFeatures or properties in
337  /// initializeProperties().
339  return ARMProcFamily;
340  }
341 
342  bool hasV8_1aOps() const { return HasV8_1aOps; }
343  bool hasV8_2aOps() const { return HasV8_2aOps; }
344  bool hasV8_3aOps() const { return HasV8_3aOps; }
345  bool hasV8_4aOps() const { return HasV8_4aOps; }
346  bool hasV8_5aOps() const { return HasV8_5aOps; }
347  bool hasV8_0rOps() const { return HasV8_0rOps; }
348 
349  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
350 
352 
354 
357  }
358 
359  bool requiresStrictAlign() const { return StrictAlign; }
360 
361  bool isXRaySupported() const override { return true; }
362 
363  unsigned getMinVectorRegisterBitWidth() const {
365  }
366 
367  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
368  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
369  bool isXRegCustomCalleeSaved(size_t i) const {
370  return CustomCallSavedXRegs[i];
371  }
372  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
373  bool hasFPARMv8() const { return HasFPARMv8; }
374  bool hasNEON() const { return HasNEON; }
375  bool hasCrypto() const { return HasCrypto; }
376  bool hasDotProd() const { return HasDotProd; }
377  bool hasCRC() const { return HasCRC; }
378  bool hasLSE() const { return HasLSE; }
379  bool hasLSE2() const { return HasLSE2; }
380  bool hasRAS() const { return HasRAS; }
381  bool hasRDM() const { return HasRDM; }
382  bool hasSM4() const { return HasSM4; }
383  bool hasSHA3() const { return HasSHA3; }
384  bool hasSHA2() const { return HasSHA2; }
385  bool hasAES() const { return HasAES; }
386  bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
387  bool balanceFPOps() const { return BalanceFPOps; }
390  }
394  bool isPaired128Slow() const { return Paired128IsSlow; }
395  bool isSTRQroSlow() const { return STRQroIsSlow; }
398  }
401  bool hasCmpBccFusion() const { return HasCmpBccFusion; }
402  bool hasFuseAddress() const { return HasFuseAddress; }
403  bool hasFuseAES() const { return HasFuseAES; }
405  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
406  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
407  bool hasFuseLiterals() const { return HasFuseLiterals; }
408 
409  /// Return true if the CPU supports any kind of instruction fusion.
410  bool hasFusion() const {
414  }
415 
416  bool hardenSlsRetBr() const { return HardenSlsRetBr; }
417  bool hardenSlsBlr() const { return HardenSlsBlr; }
418  bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
419 
420  bool useEL1ForTP() const { return UseEL1ForTP; }
421  bool useEL2ForTP() const { return UseEL2ForTP; }
422  bool useEL3ForTP() const { return UseEL3ForTP; }
423 
424  bool useRSqrt() const { return UseRSqrt; }
426  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
429  }
430  unsigned getCacheLineSize() const override { return CacheLineSize; }
431  unsigned getPrefetchDistance() const override { return PrefetchDistance; }
432  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
433  unsigned NumStridedMemAccesses,
434  unsigned NumPrefetches,
435  bool HasCall) const override {
436  return MinPrefetchStride;
437  }
438  unsigned getMaxPrefetchIterationsAhead() const override {
440  }
441  unsigned getPrefFunctionLogAlignment() const {
443  }
444  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
445 
446  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
447 
448  unsigned getWideningBaseCost() const { return WideningBaseCost; }
449 
452  }
453 
454  /// CPU has TBI (top byte of addresses is ignored during HW address
455  /// translation) and OS enables it.
456  bool supportsAddressTopByteIgnored() const;
457 
458  bool hasPerfMon() const { return HasPerfMon; }
459  bool hasFullFP16() const { return HasFullFP16; }
460  bool hasFP16FML() const { return HasFP16FML; }
461  bool hasSPE() const { return HasSPE; }
462  bool hasLSLFast() const { return HasLSLFast; }
463  bool hasSVE() const { return HasSVE; }
464  bool hasSVE2() const { return HasSVE2; }
465  bool hasRCPC() const { return HasRCPC; }
466  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
467  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
468  bool hasFRInt3264() const { return HasFRInt3264; }
469  bool hasSpecRestrict() const { return HasSpecRestrict; }
470  bool hasSSBS() const { return HasSSBS; }
471  bool hasSB() const { return HasSB; }
472  bool hasPredRes() const { return HasPredRes; }
473  bool hasCCDP() const { return HasCCDP; }
474  bool hasBTI() const { return HasBTI; }
475  bool hasRandGen() const { return HasRandGen; }
476  bool hasMTE() const { return HasMTE; }
477  bool hasTME() const { return HasTME; }
478  bool hasPAUTH() const { return HasPAUTH; }
479  // Arm SVE2 extensions
480  bool hasSVE2AES() const { return HasSVE2AES; }
481  bool hasSVE2SM4() const { return HasSVE2SM4; }
482  bool hasSVE2SHA3() const { return HasSVE2SHA3; }
483  bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
484  bool hasMatMulInt8() const { return HasMatMulInt8; }
485  bool hasMatMulFP32() const { return HasMatMulFP32; }
486  bool hasMatMulFP64() const { return HasMatMulFP64; }
487 
488  // Armv8.6-A Extensions
489  bool hasBF16() const { return HasBF16; }
490  bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
493  }
494 
495  // Arm Scalable Matrix Extension (SME)
496  bool hasSME() const { return HasSME; }
497  bool hasSMEF64() const { return HasSMEF64; }
498  bool hasSMEI64() const { return HasSMEI64; }
499  bool hasStreamingSVE() const { return HasStreamingSVE; }
500 
501  bool isLittleEndian() const { return IsLittle; }
502 
503  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
504  bool isTargetIOS() const { return TargetTriple.isiOS(); }
505  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
506  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
507  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
508  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
509 
510  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
511  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
512  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
513 
514  bool isTargetILP32() const {
515  return TargetTriple.isArch32Bit() ||
517  }
518 
519  bool useAA() const override;
520 
521  bool outlineAtomics() const { return OutlineAtomics; }
522 
523  bool hasVH() const { return HasVH; }
524  bool hasPAN() const { return HasPAN; }
525  bool hasLOR() const { return HasLOR; }
526 
527  bool hasPsUAO() const { return HasPsUAO; }
528  bool hasPAN_RWV() const { return HasPAN_RWV; }
529  bool hasCCPP() const { return HasCCPP; }
530 
531  bool hasPAuth() const { return HasPAuth; }
532  bool hasJS() const { return HasJS; }
533  bool hasCCIDX() const { return HasCCIDX; }
534  bool hasComplxNum() const { return HasComplxNum; }
535 
536  bool hasNV() const { return HasNV; }
537  bool hasMPAM() const { return HasMPAM; }
538  bool hasDIT() const { return HasDIT; }
539  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
540  bool hasAM() const { return HasAM; }
541  bool hasAMVS() const { return HasAMVS; }
542  bool hasXS() const { return HasXS; }
543  bool hasWFxT() const { return HasWFxT; }
544  bool hasHCX() const { return HasHCX; }
545  bool hasLS64() const { return HasLS64; }
546  bool hasSEL2() const { return HasSEL2; }
547  bool hasTLB_RMI() const { return HasTLB_RMI; }
548  bool hasFlagM() const { return HasFlagM; }
549  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
550 
551  bool addrSinkUsingGEPs() const override {
552  // Keeping GEPs inbounds is important for exploiting AArch64
553  // addressing-modes in ILP32 mode.
554  return useAA() || isTargetILP32();
555  }
556 
557  bool useSmallAddressing() const {
558  switch (TLInfo.getTargetMachine().getCodeModel()) {
559  case CodeModel::Kernel:
560  // Kernel is currently allowed only for Fuchsia targets,
561  // where it is the same as Small for almost all purposes.
562  case CodeModel::Small:
563  return true;
564  default:
565  return false;
566  }
567  }
568 
569  /// ParseSubtargetFeatures - Parses features string setting specified
570  /// subtarget options. Definition of function is auto generated by tblgen.
572 
573  /// ClassifyGlobalReference - Find the target operand flags that describe
574  /// how a global value should be referenced for the current subtarget.
575  unsigned ClassifyGlobalReference(const GlobalValue *GV,
576  const TargetMachine &TM) const;
577 
578  unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
579  const TargetMachine &TM) const;
580 
582  unsigned NumRegionInstrs) const override;
583 
584  bool enableEarlyIfConversion() const override;
585 
586  bool enableAdvancedRASplitCost() const override { return false; }
587 
588  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
589 
591  switch (CC) {
592  case CallingConv::C:
593  case CallingConv::Fast:
594  case CallingConv::Swift:
595  return isTargetWindows();
596  case CallingConv::Win64:
597  return true;
598  default:
599  return false;
600  }
601  }
602 
603  /// Return whether FrameLowering should always set the "extended frame
604  /// present" bit in FP, or set it based on a symbol in the runtime.
606  // Older OS versions (particularly system unwinders) are confused by the
607  // Swift extended frame, so when building code that might be run on them we
608  // must dynamically query the concurrency library to determine whether
609  // extended frames should be flagged as present.
610  const Triple &TT = getTargetTriple();
611 
612  unsigned Major, Minor, Micro;
613  TT.getOSVersion(Major, Minor, Micro);
614  switch(TT.getOS()) {
615  default:
616  return false;
617  case Triple::IOS:
618  case Triple::TvOS:
619  return Major < 15;
620  case Triple::WatchOS:
621  return Major < 8;
622  case Triple::MacOSX:
623  case Triple::Darwin:
624  return Major < 12;
625  }
626  }
627 
628  void mirFileLoaded(MachineFunction &MF) const override;
629 
630  // Return the known range for the bit length of SVE data registers. A value
631  // of 0 means nothing is known about that particular limit beyong what's
632  // implied by the architecture.
633  unsigned getMaxSVEVectorSizeInBits() const {
634  assert(HasSVE && "Tried to get SVE vector length without SVE support!");
635  return MaxSVEVectorSizeInBits;
636  }
637 
638  unsigned getMinSVEVectorSizeInBits() const {
639  assert(HasSVE && "Tried to get SVE vector length without SVE support!");
640  return MinSVEVectorSizeInBits;
641  }
642 
643  bool useSVEForFixedLengthVectors() const;
644 };
645 } // End llvm namespace
646 
647 #endif
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::AArch64Subtarget::NegativeImmediates
bool NegativeImmediates
Definition: AArch64Subtarget.h:220
i
i
Definition: README.txt:29
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:51
llvm::AArch64Subtarget::hasRandGen
bool hasRandGen() const
Definition: AArch64Subtarget.h:475
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:45
llvm::AArch64Subtarget::isTargetWindows
bool isTargetWindows() const
Definition: AArch64Subtarget.h:506
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
AArch64RegisterInfo.h
llvm::AArch64Subtarget::hasFuseLiterals
bool hasFuseLiterals() const
Definition: AArch64Subtarget.h:407
llvm::AArch64Subtarget::hasFPARMv8
bool hasFPARMv8() const
Definition: AArch64Subtarget.h:373
llvm::AArch64Subtarget::hasPAUTH
bool hasPAUTH() const
Definition: AArch64Subtarget.h:478
llvm::AArch64Subtarget::hasTRACEV8_4
bool hasTRACEV8_4() const
Definition: AArch64Subtarget.h:539
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:322
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::AArch64Subtarget::hasSVE2BitPerm
bool hasSVE2BitPerm() const
Definition: AArch64Subtarget.h:483
llvm::AArch64Subtarget::HasLSE
bool HasLSE
Definition: AArch64Subtarget.h:101
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:83
llvm::AArch64Subtarget::HasHCX
bool HasHCX
Definition: AArch64Subtarget.h:176
llvm::AArch64Subtarget::HasDotProd
bool HasDotProd
Definition: AArch64Subtarget.h:99
llvm::AArch64Subtarget::hasMatMulFP32
bool hasMatMulFP32() const
Definition: AArch64Subtarget.h:485
llvm::AArch64Subtarget::swiftAsyncContextIsDynamicallySet
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: AArch64Subtarget.h:605
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:72
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:213
llvm::AArch64Subtarget::hasFRInt3264
bool hasFRInt3264() const
Definition: AArch64Subtarget.h:468
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:262
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:53
llvm::AArch64Subtarget::predictableSelectIsExpensive
bool predictableSelectIsExpensive() const
Definition: AArch64Subtarget.h:388
llvm::AArch64Subtarget::hasSPE
bool hasSPE() const
Definition: AArch64Subtarget.h:461
CallLowering.h
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::isTargetIOS
bool isTargetIOS() const
Definition: AArch64Subtarget.h:504
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:74
llvm::AArch64Subtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: AArch64Subtarget.h:510
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:77
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:637
llvm::AArch64Subtarget::HasLS64
bool HasLS64
Definition: AArch64Subtarget.h:177
llvm::AArch64Subtarget::hasCONTEXTIDREL2
bool hasCONTEXTIDREL2() const
Definition: AArch64Subtarget.h:386
llvm::AArch64Subtarget::OutlineAtomics
bool OutlineAtomics
Definition: AArch64Subtarget.h:225
llvm::AArch64Subtarget::hasSB
bool hasSB() const
Definition: AArch64Subtarget.h:471
llvm::AArch64Subtarget::getPrefFunctionLogAlignment
unsigned getPrefFunctionLogAlignment() const
Definition: AArch64Subtarget.h:441
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:59
llvm::Triple::Darwin
@ Darwin
Definition: Triple.h:169
llvm::AArch64Subtarget::HasFP16FML
bool HasFP16FML
Definition: AArch64Subtarget.h:107
llvm::AArch64Subtarget::getMinSVEVectorSizeInBits
unsigned getMinSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:638
llvm::AArch64Subtarget::hasSM4
bool hasSM4() const
Definition: AArch64Subtarget.h:382
llvm::AArch64Subtarget::hasFlagM
bool hasFlagM() const
Definition: AArch64Subtarget.h:548
llvm::AArch64Subtarget::HasRandGen
bool HasRandGen
Definition: AArch64Subtarget.h:160
llvm::AArch64Subtarget::HasCCIDX
bool HasCCIDX
Definition: AArch64Subtarget.h:133
llvm::AArch64Subtarget::hasMPAM
bool hasMPAM() const
Definition: AArch64Subtarget.h:537
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:289
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:55
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:285
llvm::AArch64Subtarget::useEL3ForTP
bool useEL3ForTP() const
Definition: AArch64Subtarget.h:422
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:69
llvm::AArch64Subtarget::DisableLatencySchedHeuristic
bool DisableLatencySchedHeuristic
Definition: AArch64Subtarget.h:244
llvm::AArch64Subtarget::hasSVE
bool hasSVE() const
Definition: AArch64Subtarget.h:463
llvm::AArch64Subtarget::UseEL1ForTP
bool UseEL1ForTP
Definition: AArch64Subtarget.h:247
llvm::AArch64Subtarget::HasAggressiveFMA
bool HasAggressiveFMA
Definition: AArch64Subtarget.h:149
llvm::AArch64Subtarget::HasTRACEV8_4
bool HasTRACEV8_4
Definition: AArch64Subtarget.h:140
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:58
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:254
llvm::AArch64Subtarget::hasZeroCycleZeroingFP
bool hasZeroCycleZeroingFP() const
Definition: AArch64Subtarget.h:353
RegisterBankInfo.h
llvm::AArch64Subtarget::HasV8_3aOps
bool HasV8_3aOps
Definition: AArch64Subtarget.h:87
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:287
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:503
llvm::AArch64Subtarget::isTargetELF
bool isTargetELF() const
Definition: AArch64Subtarget.h:511
llvm::AArch64Subtarget::hasTME
bool hasTME() const
Definition: AArch64Subtarget.h:477
llvm::Triple::IOS
@ IOS
Definition: Triple.h:173
llvm::AArch64Subtarget::getVectorInsertExtractBaseCost
unsigned getVectorInsertExtractBaseCost() const
Definition: AArch64Subtarget.h:427
llvm::AArch64Subtarget::HasZeroCycleZeroing
bool HasZeroCycleZeroing
Definition: AArch64Subtarget.h:206
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AArch64Subtarget::hasRAS
bool hasRAS() const
Definition: AArch64Subtarget.h:380
llvm::AArch64Subtarget::HasMPAM
bool HasMPAM
Definition: AArch64Subtarget.h:138
llvm::AArch64Subtarget::TLInfo
AArch64TargetLowering TLInfo
Definition: AArch64Subtarget.h:282
llvm::AArch64Subtarget::getInstrInfo
const AArch64InstrInfo * getInstrInfo() const override
Definition: AArch64Subtarget.h:319
llvm::AArch64Subtarget::HasStreamingSVE
bool HasStreamingSVE
Definition: AArch64Subtarget.h:193
llvm::AArch64Subtarget::isMisaligned128StoreSlow
bool isMisaligned128StoreSlow() const
Definition: AArch64Subtarget.h:393
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:258
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:255
llvm::AArch64Subtarget::HasCmpBccFusion
bool HasCmpBccFusion
Definition: AArch64Subtarget.h:237
llvm::AArch64Subtarget::HasFuseCryptoEOR
bool HasFuseCryptoEOR
Definition: AArch64Subtarget.h:242
llvm::AArch64Subtarget::hasCRC
bool hasCRC() const
Definition: AArch64Subtarget.h:377
llvm::AArch64Subtarget::HasSME
bool HasSME
Definition: AArch64Subtarget.h:190
llvm::AArch64Subtarget::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Definition: AArch64Subtarget.h:226
llvm::AArch64Subtarget::HasCCPP
bool HasCCPP
Definition: AArch64Subtarget.h:118
llvm::AArch64Subtarget::Force32BitJumpTables
bool Force32BitJumpTables
Definition: AArch64Subtarget.h:246
llvm::AArch64Subtarget::HasSVE2SHA3
bool HasSVE2SHA3
Definition: AArch64Subtarget.h:183
llvm::AArch64Subtarget::hasPAN
bool hasPAN() const
Definition: AArch64Subtarget.h:524
llvm::AArch64Subtarget::isSTRQroSlow
bool isSTRQroSlow() const
Definition: AArch64Subtarget.h:395
llvm::AArch64Subtarget::HasV8_5aOps
bool HasV8_5aOps
Definition: AArch64Subtarget.h:89
llvm::AArch64Subtarget::useSVEForFixedLengthVectors
bool useSVEForFixedLengthVectors() const
Definition: AArch64Subtarget.cpp:350
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:595
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:49
llvm::AArch64Subtarget::isXRegCustomCalleeSaved
bool isXRegCustomCalleeSaved(size_t i) const
Definition: AArch64Subtarget.h:369
llvm::AArch64Subtarget::HardenSlsNoComdat
bool HardenSlsNoComdat
Definition: AArch64Subtarget.h:253
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:73
llvm::AArch64Subtarget::hasVH
bool hasVH() const
Definition: AArch64Subtarget.h:523
llvm::AArch64Subtarget::HasSHA3
bool HasSHA3
Definition: AArch64Subtarget.h:126
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:78
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:46
llvm::AArch64Subtarget::HasEnhancedCounterVirtualization
bool HasEnhancedCounterVirtualization
Definition: AArch64Subtarget.h:171
llvm::AArch64Subtarget::hasRCPC
bool hasRCPC() const
Definition: AArch64Subtarget.h:465
AArch64SelectionDAGInfo.h
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::AArch64Subtarget::UseEL3ForTP
bool UseEL3ForTP
Definition: AArch64Subtarget.h:249
llvm::AArch64Subtarget::getPrefetchDistance
unsigned getPrefetchDistance() const override
Definition: AArch64Subtarget.h:431
llvm::AArch64Subtarget::hardenSlsRetBr
bool hardenSlsRetBr() const
Definition: AArch64Subtarget.h:416
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:261
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:60
llvm::AArch64Subtarget::HasRDM
bool HasRDM
Definition: AArch64Subtarget.h:104
LegalizerInfo.h
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:68
llvm::AArch64Subtarget::hasSMEF64
bool hasSMEF64() const
Definition: AArch64Subtarget.h:497
llvm::AArch64Subtarget::HasCRC
bool HasCRC
Definition: AArch64Subtarget.h:100
llvm::Triple::WatchOS
@ WatchOS
Definition: Triple.h:194
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:316
llvm::AArch64Subtarget::HasSVE2BitPerm
bool HasSVE2BitPerm
Definition: AArch64Subtarget.h:184
llvm::AArch64Subtarget::hasAM
bool hasAM() const
Definition: AArch64Subtarget.h:540
llvm::AArch64Subtarget::hasSpecRestrict
bool hasSpecRestrict() const
Definition: AArch64Subtarget.h:469
llvm::AArch64Subtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
Definition: AArch64Subtarget.h:330
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:70
llvm::AArch64Subtarget::getWideningBaseCost
unsigned getWideningBaseCost() const
Definition: AArch64Subtarget.h:448
llvm::AArch64Subtarget::addrSinkUsingGEPs
bool addrSinkUsingGEPs() const override
Definition: AArch64Subtarget.h:551
llvm::AArch64Subtarget::HasMatMulFP32
bool HasMatMulFP32
Definition: AArch64Subtarget.h:167
llvm::AArch64Subtarget::HasFlagM
bool HasFlagM
Definition: AArch64Subtarget.h:144
llvm::AArch64Subtarget::HasFPARMv8
bool HasFPARMv8
Definition: AArch64Subtarget.h:96
llvm::AArch64FrameLowering
Definition: AArch64FrameLowering.h:23
llvm::AArch64Subtarget::HasCONTEXTIDREL2
bool HasCONTEXTIDREL2
Definition: AArch64Subtarget.h:94
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:169
llvm::AArch64Subtarget::UseRSqrt
bool UseRSqrt
Definition: AArch64Subtarget.h:245
llvm::AArch64Subtarget::hasAlternativeNZCV
bool hasAlternativeNZCV() const
Definition: AArch64Subtarget.h:467
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:199
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:336
llvm::AArch64Subtarget::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AArch64Subtarget.h:363
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:673
llvm::AArch64SelectionDAGInfo
Definition: AArch64SelectionDAGInfo.h:20
llvm::AArch64Subtarget::hasV8_2aOps
bool hasV8_2aOps() const
Definition: AArch64Subtarget.h:343
llvm::AArch64Subtarget::HasSPE
bool HasSPE
Definition: AArch64Subtarget.h:108
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:632
llvm::AArch64Subtarget::useAlternateSExtLoadCVTF32Pattern
bool useAlternateSExtLoadCVTF32Pattern() const
Definition: AArch64Subtarget.h:396
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:234
AArch64InstrInfo.h
llvm::AArch64Subtarget::HasSHA2
bool HasSHA2
Definition: AArch64Subtarget.h:127
llvm::AArch64Subtarget::MinSVEVectorSizeInBits
unsigned MinSVEVectorSizeInBits
Definition: AArch64Subtarget.h:273
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:238
InlineAsmLowering.h
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::AArch64Subtarget::HasSVE2SM4
bool HasSVE2SM4
Definition: AArch64Subtarget.h:182
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:38
llvm::AArch64Subtarget::hasLS64
bool hasLS64() const
Definition: AArch64Subtarget.h:545
llvm::AArch64Subtarget::hasDotProd
bool hasDotProd() const
Definition: AArch64Subtarget.h:376
llvm::Triple::TvOS
@ TvOS
Definition: Triple.h:193
llvm::AArch64Subtarget::isLittleEndian
bool isLittleEndian() const
Definition: AArch64Subtarget.h:501
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:484
llvm::AArch64Subtarget::HasComplxNum
bool HasComplxNum
Definition: AArch64Subtarget.h:134
llvm::AArch64Subtarget::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Definition: AArch64Subtarget.h:446
llvm::AArch64Subtarget::HasLSLFast
bool HasLSLFast
Definition: AArch64Subtarget.h:147
llvm::AArch64Subtarget::isTargetILP32
bool isTargetILP32() const
Definition: AArch64Subtarget.h:514
llvm::BitVector::count
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:154
llvm::AArch64Subtarget::hasMatMulInt8
bool hasMatMulInt8() const
Definition: AArch64Subtarget.h:484
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:256
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:318
llvm::AArch64Subtarget::HasPAN
bool HasPAN
Definition: AArch64Subtarget.h:112
llvm::AArch64Subtarget::HasFuseLiterals
bool HasFuseLiterals
Definition: AArch64Subtarget.h:243
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::HasAMVS
bool HasAMVS
Definition: AArch64Subtarget.h:169
llvm::AArch64Subtarget::HasV8_0rOps
bool HasV8_0rOps
Definition: AArch64Subtarget.h:93
llvm::AArch64Subtarget::HasV8_4aOps
bool HasV8_4aOps
Definition: AArch64Subtarget.h:88
llvm::AArch64Subtarget::HasETE
bool HasETE
Definition: AArch64Subtarget.h:196
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:340
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::AArch64Subtarget::hasSVE2SHA3
bool hasSVE2SHA3() const
Definition: AArch64Subtarget.h:482
llvm::AArch64Subtarget::HasRAS
bool HasRAS
Definition: AArch64Subtarget.h:103
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:645
llvm::AArch64Subtarget::hardenSlsBlr
bool hardenSlsBlr() const
Definition: AArch64Subtarget.h:417
AArch64GenSubtargetInfo
llvm::AArch64Subtarget::HasZeroCycleZeroingGP
bool HasZeroCycleZeroingGP
Definition: AArch64Subtarget.h:207
llvm::AArch64Subtarget::HasWFxT
bool HasWFxT
Definition: AArch64Subtarget.h:175
llvm::AArch64Subtarget::isXRaySupported
bool isXRaySupported() const override
Definition: AArch64Subtarget.h:361
llvm::AArch64Subtarget::balanceFPOps
bool balanceFPOps() const
Definition: AArch64Subtarget.h:387
llvm::AArch64Subtarget::hasCrypto
bool hasCrypto() const
Definition: AArch64Subtarget.h:375
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:61
llvm::AArch64Subtarget::BalanceFPOps
bool BalanceFPOps
Definition: AArch64Subtarget.h:227
llvm::AArch64Subtarget::HasAlternativeNZCV
bool HasAlternativeNZCV
Definition: AArch64Subtarget.h:152
llvm::BitVector
Definition: BitVector.h:74
llvm::AArch64Subtarget::HasSVE2AES
bool HasSVE2AES
Definition: AArch64Subtarget.h:181
llvm::AArch64Subtarget::getProcFamily
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
Definition: AArch64Subtarget.h:338
llvm::AArch64Subtarget::HasPredRes
bool HasPredRes
Definition: AArch64Subtarget.h:157
llvm::AArch64Subtarget::hasZeroCycleRegMove
bool hasZeroCycleRegMove() const
Definition: AArch64Subtarget.h:349
llvm::AArch64Subtarget::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: AArch64Subtarget.h:430
llvm::AArch64Subtarget::HasSMEI64
bool HasSMEI64
Definition: AArch64Subtarget.h:192
llvm::AArch64Subtarget::UseExperimentalZeroingPseudos
bool UseExperimentalZeroingPseudos
Definition: AArch64Subtarget.h:122
llvm::AArch64Subtarget::IsLittle
bool IsLittle
Definition: AArch64Subtarget.h:271
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AArch64Subtarget::HasAES
bool HasAES
Definition: AArch64Subtarget.h:128
llvm::AArch64Subtarget::hasRCPC_IMMO
bool hasRCPC_IMMO() const
Definition: AArch64Subtarget.h:549
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:260
llvm::AArch64Subtarget::HasPAUTH
bool HasPAUTH
Definition: AArch64Subtarget.h:199
llvm::AArch64Subtarget::STRQroIsSlow
bool STRQroIsSlow
Definition: AArch64Subtarget.h:233
llvm::AArch64Subtarget::HasTME
bool HasTME
Definition: AArch64Subtarget.h:162
llvm::AArch64Subtarget::HasBRBE
bool HasBRBE
Definition: AArch64Subtarget.h:198
llvm::Triple::isOSFuchsia
bool isOSFuchsia() const
Definition: Triple.h:514
llvm::AArch64Subtarget::CustomAsCheapAsMove
bool CustomAsCheapAsMove
Definition: AArch64Subtarget.h:228
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:63
llvm::AArch64Subtarget::MaxSVEVectorSizeInBits
unsigned MaxSVEVectorSizeInBits
Definition: AArch64Subtarget.h:274
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:76
InstructionSelector.h
llvm::AArch64Subtarget::HasVH
bool HasVH
Definition: AArch64Subtarget.h:111
llvm::AArch64Subtarget::HasMTE
bool HasMTE
Definition: AArch64Subtarget.h:161
llvm::AArch64Subtarget::getSelectionDAGInfo
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: AArch64Subtarget.h:310
llvm::AArch64Subtarget::hasNV
bool hasNV() const
Definition: AArch64Subtarget.h:536
llvm::AArch64Subtarget::hasArithmeticBccFusion
bool hasArithmeticBccFusion() const
Definition: AArch64Subtarget.h:399
llvm::AArch64Subtarget::HasBF16
bool HasBF16
Definition: AArch64Subtarget.h:165
llvm::AArch64Subtarget::HasFuseArithmeticLogic
bool HasFuseArithmeticLogic
Definition: AArch64Subtarget.h:240
llvm::Triple::MacOSX
@ MacOSX
Definition: Triple.h:177
llvm::AArch64Subtarget::HasSPE_EEF
bool HasSPE_EEF
Definition: AArch64Subtarget.h:200
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:230
llvm::AArch64Subtarget::hasJS
bool hasJS() const
Definition: AArch64Subtarget.h:532
llvm::AArch64Subtarget::useExperimentalZeroingPseudos
bool useExperimentalZeroingPseudos() const
Definition: AArch64Subtarget.h:450
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::AArch64Subtarget::HasPsUAO
bool HasPsUAO
Definition: AArch64Subtarget.h:116
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:266
llvm::AArch64Subtarget::hasLOR
bool hasLOR() const
Definition: AArch64Subtarget.h:525
llvm::AArch64Subtarget::HasXS
bool HasXS
Definition: AArch64Subtarget.h:174
llvm::AArch64Subtarget::hasLSLFast
bool hasLSLFast() const
Definition: AArch64Subtarget.h:462
llvm::AArch64Subtarget::hasCmpBccFusion
bool hasCmpBccFusion() const
Definition: AArch64Subtarget.h:401
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:57
AArch64FrameLowering.h
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:162
llvm::AArch64Subtarget::hasZeroCycleZeroingFPWorkaround
bool hasZeroCycleZeroingFPWorkaround() const
Definition: AArch64Subtarget.h:355
llvm::AArch64Subtarget::hardenSlsNoComdat
bool hardenSlsNoComdat() const
Definition: AArch64Subtarget.h:418
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:557
llvm::AArch64Subtarget::UseEL2ForTP
bool UseEL2ForTP
Definition: AArch64Subtarget.h:248
llvm::Triple::isArch32Bit
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1340
llvm::AArch64Subtarget::hasWFxT
bool hasWFxT() const
Definition: AArch64Subtarget.h:543
llvm::AArch64Subtarget::hasFuseCryptoEOR
bool hasFuseCryptoEOR() const
Definition: AArch64Subtarget.h:406
llvm::AArch64Subtarget::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
Definition: AArch64Subtarget.h:432
llvm::AArch64Subtarget::hasMTE
bool hasMTE() const
Definition: AArch64Subtarget.h:476
llvm::AArch64Subtarget::HasSM4
bool HasSM4
Definition: AArch64Subtarget.h:125
llvm::AArch64Subtarget::useEL2ForTP
bool useEL2ForTP() const
Definition: AArch64Subtarget.h:421
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:48
llvm::AArch64Subtarget::hasAMVS
bool hasAMVS() const
Definition: AArch64Subtarget.h:541
llvm::AArch64Subtarget::StrictAlign
bool StrictAlign
Definition: AArch64Subtarget.h:217
llvm::AArch64Subtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: AArch64Subtarget.h:329
llvm::AArch64Subtarget::AllowTaggedGlobals
bool AllowTaggedGlobals
Definition: AArch64Subtarget.h:250
llvm::AArch64Subtarget::hasFineGrainedTraps
bool hasFineGrainedTraps() const
Definition: AArch64Subtarget.h:490
llvm::AArch64Subtarget::HasPAuth
bool HasPAuth
Definition: AArch64Subtarget.h:131
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:67
llvm::AArch64Subtarget::UseAlternateSExtLoadCVTF32Pattern
bool UseAlternateSExtLoadCVTF32Pattern
Definition: AArch64Subtarget.h:234
llvm::AArch64Subtarget::hasSSBS
bool hasSSBS() const
Definition: AArch64Subtarget.h:470
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::AArch64Subtarget::HasNV
bool HasNV
Definition: AArch64Subtarget.h:137
llvm::AArch64Subtarget::hasV8_4aOps
bool hasV8_4aOps() const
Definition: AArch64Subtarget.h:345
llvm::AArch64Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: AArch64Subtarget.h:505
llvm::AArch64Subtarget::hasComplxNum
bool hasComplxNum() const
Definition: AArch64Subtarget.h:534
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:223
llvm::AArch64Subtarget::UsePostRAScheduler
bool UsePostRAScheduler
Definition: AArch64Subtarget.h:230
llvm::AArch64Subtarget::hasBTI
bool hasBTI() const
Definition: AArch64Subtarget.h:474
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:590
llvm::AArch64Subtarget::HasV8_2aOps
bool HasV8_2aOps
Definition: AArch64Subtarget.h:86
llvm::AArch64Subtarget::hasNEON
bool hasNEON() const
Definition: AArch64Subtarget.h:374
llvm::AArch64Subtarget::HasRCPC
bool HasRCPC
Definition: AArch64Subtarget.h:148
llvm::AArch64Subtarget::hasFuseAES
bool hasFuseAES() const
Definition: AArch64Subtarget.h:403
llvm::AArch64Subtarget::TSInfo
AArch64SelectionDAGInfo TSInfo
Definition: AArch64Subtarget.h:281
llvm::AArch64Subtarget::HasDIT
bool HasDIT
Definition: AArch64Subtarget.h:139
llvm::AArch64Subtarget::hasEnhancedCounterVirtualization
bool hasEnhancedCounterVirtualization() const
Definition: AArch64Subtarget.h:491
llvm::AArch64Subtarget::hasCCDP
bool hasCCDP() const
Definition: AArch64Subtarget.h:473
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AArch64Subtarget::hasFuseArithmeticLogic
bool hasFuseArithmeticLogic() const
Definition: AArch64Subtarget.h:404
llvm::AArch64Subtarget::hasArithmeticCbzFusion
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Definition: AArch64Subtarget.h:400
llvm::AArch64Subtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: AArch64Subtarget.h:426
llvm::AArch64Subtarget::hasCCIDX
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Definition: AArch64Subtarget.h:533
llvm::AArch64Subtarget::classifyGlobalFunctionReference
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Definition: AArch64Subtarget.cpp:285
llvm::AArch64Subtarget::HasFullFP16
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Definition: AArch64Subtarget.h:106
llvm::AArch64Subtarget::HasFRInt3264
bool HasFRInt3264
Definition: AArch64Subtarget.h:153
llvm::AArch64Subtarget::HasBTI
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Definition: AArch64Subtarget.h:159
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:372
llvm::AArch64Subtarget::outlineAtomics
bool outlineAtomics() const
Definition: AArch64Subtarget.h:521
llvm::AArch64Subtarget::isXRegisterReserved
bool isXRegisterReserved(size_t i) const
Definition: AArch64Subtarget.h:367
llvm::AArch64Subtarget::hasAES
bool hasAES() const
Definition: AArch64Subtarget.h:385
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AArch64Subtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: AArch64Subtarget.h:288
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:328
llvm::AArch64Subtarget::hasFuseCCSelect
bool hasFuseCCSelect() const
Definition: AArch64Subtarget.h:405
llvm::AArch64Subtarget::hasDIT
bool hasDIT() const
Definition: AArch64Subtarget.h:538
llvm::AArch64Subtarget::getFrameLowering
const AArch64FrameLowering * getFrameLowering() const override
Definition: AArch64Subtarget.h:313
TargetSubtargetInfo.h
llvm::AArch64Subtarget::HasSVE
bool HasSVE
Definition: AArch64Subtarget.h:121
llvm::AArch64Subtarget::HasFineGrainedTraps
bool HasFineGrainedTraps
Definition: AArch64Subtarget.h:170
llvm::AArch64Subtarget::hasPAuth
bool hasPAuth() const
Definition: AArch64Subtarget.h:531
llvm::AArch64Subtarget::HasFuseAES
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Definition: AArch64Subtarget.h:239
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:463
llvm::AArch64Subtarget::WideningBaseCost
unsigned WideningBaseCost
Definition: AArch64Subtarget.h:263
llvm::AArch64Subtarget::HasSB
bool HasSB
Definition: AArch64Subtarget.h:156
llvm::AArch64Subtarget::hasV8_0rOps
bool hasV8_0rOps() const
Definition: AArch64Subtarget.h:347
llvm::AArch64Subtarget::HasSpecRestrict
bool HasSpecRestrict
Definition: AArch64Subtarget.h:154
llvm::AArch64Subtarget::ExynosAsCheapAsMove
bool ExynosAsCheapAsMove
Definition: AArch64Subtarget.h:229
llvm::AArch64Subtarget::useEL1ForTP
bool useEL1ForTP() const
Definition: AArch64Subtarget.h:420
llvm::AArch64Subtarget::hasPsUAO
bool hasPsUAO() const
Definition: AArch64Subtarget.h:527
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:43
llvm::AArch64Subtarget::HasV8_6aOps
bool HasV8_6aOps
Definition: AArch64Subtarget.h:90
AArch64ISelLowering.h
llvm::AArch64Subtarget::HasCrypto
bool HasCrypto
Definition: AArch64Subtarget.h:98
llvm::AArch64Subtarget::hasSVE2
bool hasSVE2() const
Definition: AArch64Subtarget.h:464
llvm::AArch64Subtarget::hasSVE2AES
bool hasSVE2AES() const
Definition: AArch64Subtarget.h:480
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:75
llvm::AArch64Subtarget::force32BitJumpTables
bool force32BitJumpTables() const
Definition: AArch64Subtarget.h:425
llvm::AArch64Subtarget::HasZeroCycleZeroingFP
bool HasZeroCycleZeroingFP
Definition: AArch64Subtarget.h:214
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:50
llvm::AArch64Subtarget::hasTLB_RMI
bool hasTLB_RMI() const
Definition: AArch64Subtarget.h:547
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:547
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:52
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:320
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:339
llvm::AArch64Subtarget::HardenSlsRetBr
bool HardenSlsRetBr
Definition: AArch64Subtarget.h:251
llvm::AArch64Subtarget::isPaired128Slow
bool isPaired128Slow() const
Definition: AArch64Subtarget.h:394
llvm::AArch64Subtarget::hasV8_3aOps
bool hasV8_3aOps() const
Definition: AArch64Subtarget.h:344
llvm::AArch64Subtarget::hasPerfMon
bool hasPerfMon() const
Definition: AArch64Subtarget.h:458
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:48
llvm::AArch64Subtarget::HasArithmeticCbzFusion
bool HasArithmeticCbzFusion
Definition: AArch64Subtarget.h:236
llvm::AArch64Subtarget::hasSME
bool hasSME() const
Definition: AArch64Subtarget.h:496
llvm::AArch64Subtarget::HasZeroCycleZeroingFPWorkaround
bool HasZeroCycleZeroingFPWorkaround
Definition: AArch64Subtarget.h:208
llvm::AArch64Subtarget::useRSqrt
bool useRSqrt() const
Definition: AArch64Subtarget.h:424
llvm::AArch64Subtarget::HasTLB_RMI
bool HasTLB_RMI
Definition: AArch64Subtarget.h:143
llvm::AArch64Subtarget::hasPAN_RWV
bool hasPAN_RWV() const
Definition: AArch64Subtarget.h:528
llvm::AArch64Subtarget::hasRDM
bool hasRDM() const
Definition: AArch64Subtarget.h:381
llvm::AArch64Subtarget::getNumXRegisterReserved
unsigned getNumXRegisterReserved() const
Definition: AArch64Subtarget.h:368
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:246
llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits
unsigned getMaxSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:633
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:64
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:253
uint16_t
llvm::AArch64Subtarget::HasLSE2
bool HasLSE2
Definition: AArch64Subtarget.h:102
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:286
llvm::AArch64Subtarget::HasLOR
bool HasLOR
Definition: AArch64Subtarget.h:113
llvm::AArch64Subtarget::HasV8_1aOps
bool HasV8_1aOps
Definition: AArch64Subtarget.h:85
llvm::AArch64Subtarget::hasLSE2
bool hasLSE2() const
Definition: AArch64Subtarget.h:379
llvm::AArch64Subtarget::HasNEON
bool HasNEON
Definition: AArch64Subtarget.h:97
llvm::AArch64Subtarget::hasSEL2
bool hasSEL2() const
Definition: AArch64Subtarget.h:546
llvm::AArch64Subtarget::hasFullFP16
bool hasFullFP16() const
Definition: AArch64Subtarget.h:459
llvm::AArch64Subtarget::HasSMEF64
bool HasSMEF64
Definition: AArch64Subtarget.h:191
llvm::AArch64Subtarget::HasTRBE
bool HasTRBE
Definition: AArch64Subtarget.h:197
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AArch64Subtarget::hasCCPP
bool hasCCPP() const
Definition: AArch64Subtarget.h:529
llvm::AArch64Subtarget::enableAdvancedRASplitCost
bool enableAdvancedRASplitCost() const override
Definition: AArch64Subtarget.h:586
llvm::AArch64Subtarget::hasFuseAddress
bool hasFuseAddress() const
Definition: AArch64Subtarget.h:402
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:66
llvm::AArch64Subtarget::HasMatMulFP64
bool HasMatMulFP64
Definition: AArch64Subtarget.h:168
llvm::AArch64Subtarget::Misaligned128StoreIsSlow
bool Misaligned128StoreIsSlow
Definition: AArch64Subtarget.h:231
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:257
llvm::AArch64Subtarget::HasArithmeticBccFusion
bool HasArithmeticBccFusion
Definition: AArch64Subtarget.h:235
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:259
llvm::AArch64Subtarget::hasLSE
bool hasLSE() const
Definition: AArch64Subtarget.h:378
llvm::AArch64Subtarget::HasPerfMon
bool HasPerfMon
Definition: AArch64Subtarget.h:105
llvm::AArch64Subtarget::isTargetFuchsia
bool isTargetFuchsia() const
Definition: AArch64Subtarget.h:508
llvm::AArch64Subtarget::InstrInfo
AArch64InstrInfo InstrInfo
Definition: AArch64Subtarget.h:280
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:512
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::AArch64Subtarget::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const override
Definition: AArch64Subtarget.h:438
llvm::AArch64Subtarget::hasXS
bool hasXS() const
Definition: AArch64Subtarget.h:542
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:56
llvm::AArch64Subtarget::hasV8_5aOps
bool hasV8_5aOps() const
Definition: AArch64Subtarget.h:346
llvm::AArch64Subtarget::HasZeroCycleRegMove
bool HasZeroCycleRegMove
Definition: AArch64Subtarget.h:203
llvm::AArch64Subtarget::hasMatMulFP64
bool hasMatMulFP64() const
Definition: AArch64Subtarget.h:486
llvm::AArch64Subtarget::hasExynosCheapAsMoveHandling
bool hasExynosCheapAsMoveHandling() const
Definition: AArch64Subtarget.h:392
llvm::AArch64Subtarget::hasFP16FML
bool hasFP16FML() const
Definition: AArch64Subtarget.h:460
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::hasPredRes
bool hasPredRes() const
Definition: AArch64Subtarget.h:472
llvm::AArch64Subtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: AArch64Subtarget.h:444
llvm::AArch64Subtarget::HasRCPC_IMMO
bool HasRCPC_IMMO
Definition: AArch64Subtarget.h:145
llvm::AArch64Subtarget::Paired128IsSlow
bool Paired128IsSlow
Definition: AArch64Subtarget.h:232
llvm::AArch64Subtarget::HasV8_7aOps
bool HasV8_7aOps
Definition: AArch64Subtarget.h:91
llvm::AArch64Subtarget::HasSEL2
bool HasSEL2
Definition: AArch64Subtarget.h:142
llvm::AArch64Subtarget::HasRME
bool HasRME
Definition: AArch64Subtarget.h:187
llvm::AArch64Subtarget::hasZeroCycleZeroingGP
bool hasZeroCycleZeroingGP() const
Definition: AArch64Subtarget.h:351
llvm::AArch64Subtarget::HasFuseCCSelect
bool HasFuseCCSelect
Definition: AArch64Subtarget.h:241
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:277
llvm::AArch64Subtarget::requiresStrictAlign
bool requiresStrictAlign() const
Definition: AArch64Subtarget.h:359
llvm::AArch64Subtarget::HasAM
bool HasAM
Definition: AArch64Subtarget.h:141
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:325
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:242
llvm::AArch64Subtarget::HasFuseAddress
bool HasFuseAddress
Definition: AArch64Subtarget.h:238
llvm::AArch64Subtarget::hasSMEI64
bool hasSMEI64() const
Definition: AArch64Subtarget.h:498
llvm::AArch64Subtarget::HasCCDP
bool HasCCDP
Definition: AArch64Subtarget.h:158
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::AArch64Subtarget::HasPAN_RWV
bool HasPAN_RWV
Definition: AArch64Subtarget.h:117
llvm::AArch64Subtarget::hasSHA2
bool hasSHA2() const
Definition: AArch64Subtarget.h:384
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1110
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::HasJS
bool HasJS
Definition: AArch64Subtarget.h:132
llvm::AArch64Subtarget::hasHCX
bool hasHCX() const
Definition: AArch64Subtarget.h:544
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:62
llvm::AArch64Subtarget::CustomCallSavedXRegs
BitVector CustomCallSavedXRegs
Definition: AArch64Subtarget.h:269
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:174
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:484
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:355
llvm::AArch64Subtarget::hasStreamingSVE
bool hasStreamingSVE() const
Definition: AArch64Subtarget.h:499
llvm::AArch64Subtarget::hasAggressiveFMA
bool hasAggressiveFMA() const
Definition: AArch64Subtarget.h:466
llvm::CallLowering
Definition: CallLowering.h:43
llvm::AArch64Subtarget::hasBF16
bool hasBF16() const
Definition: AArch64Subtarget.h:489
llvm::AArch64Subtarget::HardenSlsBlr
bool HardenSlsBlr
Definition: AArch64Subtarget.h:252
llvm::AArch64Subtarget::HasMatMulInt8
bool HasMatMulInt8
Definition: AArch64Subtarget.h:166
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:65
llvm::AArch64Subtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: AArch64Subtarget.h:410
llvm::AArch64Subtarget::hasV8_1aOps
bool hasV8_1aOps() const
Definition: AArch64Subtarget.h:342
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:306
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:44
llvm::AArch64Subtarget::FrameLowering
AArch64FrameLowering FrameLowering
Definition: AArch64Subtarget.h:279
llvm::AArch64Subtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: AArch64Subtarget.h:507
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:47
llvm::AArch64Subtarget::HasSVE2
bool HasSVE2
Definition: AArch64Subtarget.h:180
llvm::AArch64Subtarget::hasSVE2SM4
bool hasSVE2SM4() const
Definition: AArch64Subtarget.h:481
llvm::AArch64Subtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: AArch64Subtarget.h:40
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:54
llvm::AArch64Subtarget::hasSHA3
bool hasSHA3() const
Definition: AArch64Subtarget.h:383
llvm::AArch64Subtarget::HasSSBS
bool HasSSBS
Definition: AArch64Subtarget.h:155
llvm::AArch64Subtarget::hasCustomCheapAsMoveHandling
bool hasCustomCheapAsMoveHandling() const
Definition: AArch64Subtarget.h:391