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AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
83  };
84 
85 protected:
86  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
88 
89  bool HasV8_0aOps = false;
90  bool HasV8_1aOps = false;
91  bool HasV8_2aOps = false;
92  bool HasV8_3aOps = false;
93  bool HasV8_4aOps = false;
94  bool HasV8_5aOps = false;
95  bool HasV8_6aOps = false;
96  bool HasV8_7aOps = false;
97  bool HasV8_8aOps = false;
98  bool HasV9_0aOps = false;
99  bool HasV9_1aOps = false;
100  bool HasV9_2aOps = false;
101  bool HasV9_3aOps = false;
102  bool HasV8_0rOps = false;
103 
104  bool HasCONTEXTIDREL2 = false;
105  bool HasEL2VMSA = false;
106  bool HasEL3 = false;
107  bool HasFPARMv8 = false;
108  bool HasNEON = false;
109  bool HasCrypto = false;
110  bool HasDotProd = false;
111  bool HasCRC = false;
112  bool HasLSE = false;
113  bool HasLSE2 = false;
114  bool HasRAS = false;
115  bool HasRDM = false;
116  bool HasPerfMon = false;
117  bool HasFullFP16 = false;
118  bool HasFP16FML = false;
119  bool HasSPE = false;
120 
121  bool FixCortexA53_835769 = false;
122 
123  // ARMv8.1 extensions
124  bool HasVH = false;
125  bool HasPAN = false;
126  bool HasLOR = false;
127 
128  // ARMv8.2 extensions
129  bool HasPsUAO = false;
130  bool HasPAN_RWV = false;
131  bool HasCCPP = false;
132 
133  // SVE extensions
134  bool HasSVE = false;
136  bool UseScalarIncVL = false;
137 
138  // Armv8.2 Crypto extensions
139  bool HasSM4 = false;
140  bool HasSHA3 = false;
141  bool HasSHA2 = false;
142  bool HasAES = false;
143 
144  // ARMv8.3 extensions
145  bool HasPAuth = false;
146  bool HasJS = false;
147  bool HasCCIDX = false;
148  bool HasComplxNum = false;
149 
150  // ARMv8.4 extensions
151  bool HasNV = false;
152  bool HasMPAM = false;
153  bool HasDIT = false;
154  bool HasTRACEV8_4 = false;
155  bool HasAM = false;
156  bool HasSEL2 = false;
157  bool HasTLB_RMI = false;
158  bool HasFlagM = false;
159  bool HasRCPC_IMMO = false;
160 
161  bool HasLSLFast = false;
162  bool HasRCPC = false;
163  bool HasAggressiveFMA = false;
164 
165  // Armv8.5-A Extensions
166  bool HasAlternativeNZCV = false;
167  bool HasFRInt3264 = false;
168  bool HasSpecRestrict = false;
169  bool HasSSBS = false;
170  bool HasSB = false;
171  bool HasPredRes = false;
172  bool HasCCDP = false;
173  bool HasBTI = false;
174  bool HasRandGen = false;
175  bool HasMTE = false;
176  bool HasTME = false;
177 
178  // Armv8.6-A Extensions
179  bool HasBF16 = false;
180  bool HasMatMulInt8 = false;
181  bool HasMatMulFP32 = false;
182  bool HasMatMulFP64 = false;
183  bool HasAMVS = false;
184  bool HasFineGrainedTraps = false;
186 
187  // Armv8.7-A Extensions
188  bool HasXS = false;
189  bool HasWFxT = false;
190  bool HasHCX = false;
191  bool HasLS64 = false;
192 
193  // Armv8.8-A Extensions
194  bool HasHBC = false;
195  bool HasMOPS = false;
196 
197  // Arm SVE2 extensions
198  bool HasSVE2 = false;
199  bool HasSVE2AES = false;
200  bool HasSVE2SM4 = false;
201  bool HasSVE2SHA3 = false;
202  bool HasSVE2BitPerm = false;
203 
204  // Armv9-A Extensions
205  bool HasRME = false;
206 
207  // Arm Scalable Matrix Extension (SME)
208  bool HasSME = false;
209  bool HasSMEF64 = false;
210  bool HasSMEI64 = false;
211  bool HasStreamingSVE = false;
212 
213  // AppleA7 system register.
214  bool HasAppleA7SysReg = false;
215 
216  // Future architecture extensions.
217  bool HasETE = false;
218  bool HasTRBE = false;
219  bool HasBRBE = false;
220  bool HasPAUTH = false;
221  bool HasSPE_EEF = false;
222 
223  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
224  bool HasZeroCycleRegMove = false;
225 
226  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
227  bool HasZeroCycleZeroing = false;
228  bool HasZeroCycleZeroingGP = false;
230 
231  // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
232  // as movi is more efficient across all cores. Newer cores can eliminate
233  // fmovs early and there is no difference with movi, but this not true for
234  // all implementations.
236 
237  // StrictAlign - Disallow unaligned memory accesses.
238  bool StrictAlign = false;
239 
240  // NegativeImmediates - transform instructions with negative immediates
241  bool NegativeImmediates = true;
242 
243  // Enable 64-bit vectorization in SLP.
245 
246  bool OutlineAtomics = false;
248  bool BalanceFPOps = false;
249  bool CustomAsCheapAsMove = false;
250  bool ExynosAsCheapAsMove = false;
251  bool UsePostRAScheduler = false;
253  bool Paired128IsSlow = false;
254  bool STRQroIsSlow = false;
258  bool HasCmpBccFusion = false;
259  bool HasFuseAddress = false;
260  bool HasFuseAES = false;
262  bool HasFuseCCSelect = false;
263  bool HasFuseCryptoEOR = false;
264  bool HasFuseLiterals = false;
266  bool UseRSqrt = false;
267  bool Force32BitJumpTables = false;
268  bool UseEL1ForTP = false;
269  bool UseEL2ForTP = false;
270  bool UseEL3ForTP = false;
271  bool AllowTaggedGlobals = false;
272  bool HardenSlsRetBr = false;
273  bool HardenSlsBlr = false;
274  bool HardenSlsNoComdat = false;
275  uint8_t MaxInterleaveFactor = 2;
280  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
282  unsigned PrefLoopLogAlignment = 0;
284  unsigned MaxJumpTableSize = 0;
285  unsigned WideningBaseCost = 0;
286 
287  // ReserveXRegister[i] - X#i is not available as a general purpose register.
289 
290  // CustomCallUsedXRegister[i] - X#i call saved.
292 
293  bool IsLittle;
294 
297  unsigned VScaleForTuning = 2;
298 
299  /// TargetTriple - What processor and OS we're targeting.
301 
306 
307  /// GlobalISel related APIs.
308  std::unique_ptr<CallLowering> CallLoweringInfo;
309  std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
310  std::unique_ptr<InstructionSelector> InstSelector;
311  std::unique_ptr<LegalizerInfo> Legalizer;
312  std::unique_ptr<RegisterBankInfo> RegBankInfo;
313 
314 private:
315  /// initializeSubtargetDependencies - Initializes using CPUString and the
316  /// passed in feature string so that we can use initializer lists for
317  /// subtarget initialization.
318  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
319  StringRef CPUString,
320  StringRef TuneCPUString);
321 
322  /// Initialize properties based on the selected processor family.
323  void initializeProperties();
324 
325 public:
326  /// This constructor initializes the data members to match that
327  /// of the specified triple.
328  AArch64Subtarget(const Triple &TT, const std::string &CPU,
329  const std::string &TuneCPU, const std::string &FS,
330  const TargetMachine &TM, bool LittleEndian,
331  unsigned MinSVEVectorSizeInBitsOverride = 0,
332  unsigned MaxSVEVectorSizeInBitsOverride = 0);
333 
335  return &TSInfo;
336  }
337  const AArch64FrameLowering *getFrameLowering() const override {
338  return &FrameLowering;
339  }
340  const AArch64TargetLowering *getTargetLowering() const override {
341  return &TLInfo;
342  }
343  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
344  const AArch64RegisterInfo *getRegisterInfo() const override {
345  return &getInstrInfo()->getRegisterInfo();
346  }
347  const CallLowering *getCallLowering() const override;
348  const InlineAsmLowering *getInlineAsmLowering() const override;
350  const LegalizerInfo *getLegalizerInfo() const override;
351  const RegisterBankInfo *getRegBankInfo() const override;
352  const Triple &getTargetTriple() const { return TargetTriple; }
353  bool enableMachineScheduler() const override { return true; }
354  bool enablePostRAScheduler() const override {
355  return UsePostRAScheduler;
356  }
357 
358  /// Returns ARM processor family.
359  /// Avoid this function! CPU specifics should be kept local to this class
360  /// and preferably modeled with SubtargetFeatures or properties in
361  /// initializeProperties().
363  return ARMProcFamily;
364  }
365 
366  bool hasV8_0aOps() const { return HasV8_0aOps; }
367  bool hasV8_1aOps() const { return HasV8_1aOps; }
368  bool hasV8_2aOps() const { return HasV8_2aOps; }
369  bool hasV8_3aOps() const { return HasV8_3aOps; }
370  bool hasV8_4aOps() const { return HasV8_4aOps; }
371  bool hasV8_5aOps() const { return HasV8_5aOps; }
372  bool hasV9_0aOps() const { return HasV9_0aOps; }
373  bool hasV9_1aOps() const { return HasV9_1aOps; }
374  bool hasV9_2aOps() const { return HasV9_2aOps; }
375  bool hasV9_3aOps() const { return HasV9_3aOps; }
376  bool hasV8_0rOps() const { return HasV8_0rOps; }
377 
378  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
379 
381 
383 
386  }
387 
388  bool requiresStrictAlign() const { return StrictAlign; }
389 
390  bool isXRaySupported() const override { return true; }
391 
392  unsigned getMinVectorRegisterBitWidth() const {
394  }
395 
396  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
397  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
398  bool isXRegCustomCalleeSaved(size_t i) const {
399  return CustomCallSavedXRegs[i];
400  }
401  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
402  bool hasFPARMv8() const { return HasFPARMv8; }
403  bool hasNEON() const { return HasNEON; }
404  bool hasCrypto() const { return HasCrypto; }
405  bool hasDotProd() const { return HasDotProd; }
406  bool hasCRC() const { return HasCRC; }
407  bool hasLSE() const { return HasLSE; }
408  bool hasLSE2() const { return HasLSE2; }
409  bool hasRAS() const { return HasRAS; }
410  bool hasRDM() const { return HasRDM; }
411  bool hasSM4() const { return HasSM4; }
412  bool hasSHA3() const { return HasSHA3; }
413  bool hasSHA2() const { return HasSHA2; }
414  bool hasAES() const { return HasAES; }
415  bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
416  bool balanceFPOps() const { return BalanceFPOps; }
419  }
423  bool isPaired128Slow() const { return Paired128IsSlow; }
424  bool isSTRQroSlow() const { return STRQroIsSlow; }
427  }
430  bool hasCmpBccFusion() const { return HasCmpBccFusion; }
431  bool hasFuseAddress() const { return HasFuseAddress; }
432  bool hasFuseAES() const { return HasFuseAES; }
434  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
435  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
436  bool hasFuseLiterals() const { return HasFuseLiterals; }
437 
438  /// Return true if the CPU supports any kind of instruction fusion.
439  bool hasFusion() const {
443  }
444 
445  bool hardenSlsRetBr() const { return HardenSlsRetBr; }
446  bool hardenSlsBlr() const { return HardenSlsBlr; }
447  bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
448 
449  bool useEL1ForTP() const { return UseEL1ForTP; }
450  bool useEL2ForTP() const { return UseEL2ForTP; }
451  bool useEL3ForTP() const { return UseEL3ForTP; }
452 
453  bool useRSqrt() const { return UseRSqrt; }
455  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
458  }
459  unsigned getCacheLineSize() const override { return CacheLineSize; }
460  unsigned getPrefetchDistance() const override { return PrefetchDistance; }
461  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
462  unsigned NumStridedMemAccesses,
463  unsigned NumPrefetches,
464  bool HasCall) const override {
465  return MinPrefetchStride;
466  }
467  unsigned getMaxPrefetchIterationsAhead() const override {
469  }
470  unsigned getPrefFunctionLogAlignment() const {
472  }
473  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
474 
475  unsigned getMaxBytesForLoopAlignment() const {
477  }
478 
479  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
480 
481  unsigned getWideningBaseCost() const { return WideningBaseCost; }
482 
485  }
486 
487  bool useScalarIncVL() const { return UseScalarIncVL; }
488 
489  /// CPU has TBI (top byte of addresses is ignored during HW address
490  /// translation) and OS enables it.
491  bool supportsAddressTopByteIgnored() const;
492 
493  bool hasPerfMon() const { return HasPerfMon; }
494  bool hasFullFP16() const { return HasFullFP16; }
495  bool hasFP16FML() const { return HasFP16FML; }
496  bool hasSPE() const { return HasSPE; }
497  bool hasLSLFast() const { return HasLSLFast; }
498  bool hasSVE() const { return HasSVE; }
499  bool hasSVE2() const { return HasSVE2; }
500  bool hasRCPC() const { return HasRCPC; }
501  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
502  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
503  bool hasFRInt3264() const { return HasFRInt3264; }
504  bool hasSpecRestrict() const { return HasSpecRestrict; }
505  bool hasSSBS() const { return HasSSBS; }
506  bool hasSB() const { return HasSB; }
507  bool hasPredRes() const { return HasPredRes; }
508  bool hasCCDP() const { return HasCCDP; }
509  bool hasBTI() const { return HasBTI; }
510  bool hasRandGen() const { return HasRandGen; }
511  bool hasMTE() const { return HasMTE; }
512  bool hasTME() const { return HasTME; }
513  bool hasPAUTH() const { return HasPAUTH; }
514  // Arm SVE2 extensions
515  bool hasSVE2AES() const { return HasSVE2AES; }
516  bool hasSVE2SM4() const { return HasSVE2SM4; }
517  bool hasSVE2SHA3() const { return HasSVE2SHA3; }
518  bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
519  bool hasMatMulInt8() const { return HasMatMulInt8; }
520  bool hasMatMulFP32() const { return HasMatMulFP32; }
521  bool hasMatMulFP64() const { return HasMatMulFP64; }
522 
523  // Armv8.6-A Extensions
524  bool hasBF16() const { return HasBF16; }
525  bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
528  }
529 
530  // Arm Scalable Matrix Extension (SME)
531  bool hasSME() const { return HasSME; }
532  bool hasSMEF64() const { return HasSMEF64; }
533  bool hasSMEI64() const { return HasSMEI64; }
534  bool hasStreamingSVE() const { return HasStreamingSVE; }
535 
536  bool isLittleEndian() const { return IsLittle; }
537 
538  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
539  bool isTargetIOS() const { return TargetTriple.isiOS(); }
540  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
541  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
542  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
543  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
544 
545  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
546  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
547  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
548 
549  bool isTargetILP32() const {
550  return TargetTriple.isArch32Bit() ||
552  }
553 
554  bool useAA() const override;
555 
556  bool outlineAtomics() const { return OutlineAtomics; }
557 
558  bool hasVH() const { return HasVH; }
559  bool hasPAN() const { return HasPAN; }
560  bool hasLOR() const { return HasLOR; }
561 
562  bool hasPsUAO() const { return HasPsUAO; }
563  bool hasPAN_RWV() const { return HasPAN_RWV; }
564  bool hasCCPP() const { return HasCCPP; }
565 
566  bool hasPAuth() const { return HasPAuth; }
567  bool hasJS() const { return HasJS; }
568  bool hasCCIDX() const { return HasCCIDX; }
569  bool hasComplxNum() const { return HasComplxNum; }
570 
571  bool hasNV() const { return HasNV; }
572  bool hasMPAM() const { return HasMPAM; }
573  bool hasDIT() const { return HasDIT; }
574  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
575  bool hasAM() const { return HasAM; }
576  bool hasAMVS() const { return HasAMVS; }
577  bool hasXS() const { return HasXS; }
578  bool hasWFxT() const { return HasWFxT; }
579  bool hasHCX() const { return HasHCX; }
580  bool hasLS64() const { return HasLS64; }
581  bool hasSEL2() const { return HasSEL2; }
582  bool hasTLB_RMI() const { return HasTLB_RMI; }
583  bool hasFlagM() const { return HasFlagM; }
584  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
585  bool hasEL2VMSA() const { return HasEL2VMSA; }
586  bool hasEL3() const { return HasEL3; }
587  bool hasHBC() const { return HasHBC; }
588  bool hasMOPS() const { return HasMOPS; }
589 
590  bool fixCortexA53_835769() const { return FixCortexA53_835769; }
591 
592  bool addrSinkUsingGEPs() const override {
593  // Keeping GEPs inbounds is important for exploiting AArch64
594  // addressing-modes in ILP32 mode.
595  return useAA() || isTargetILP32();
596  }
597 
598  bool useSmallAddressing() const {
599  switch (TLInfo.getTargetMachine().getCodeModel()) {
600  case CodeModel::Kernel:
601  // Kernel is currently allowed only for Fuchsia targets,
602  // where it is the same as Small for almost all purposes.
603  case CodeModel::Small:
604  return true;
605  default:
606  return false;
607  }
608  }
609 
610  /// ParseSubtargetFeatures - Parses features string setting specified
611  /// subtarget options. Definition of function is auto generated by tblgen.
613 
614  /// ClassifyGlobalReference - Find the target operand flags that describe
615  /// how a global value should be referenced for the current subtarget.
616  unsigned ClassifyGlobalReference(const GlobalValue *GV,
617  const TargetMachine &TM) const;
618 
619  unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
620  const TargetMachine &TM) const;
621 
623  unsigned NumRegionInstrs) const override;
624 
625  bool enableEarlyIfConversion() const override;
626 
627  bool enableAdvancedRASplitCost() const override { return false; }
628 
629  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
630 
632  switch (CC) {
633  case CallingConv::C:
634  case CallingConv::Fast:
635  case CallingConv::Swift:
636  return isTargetWindows();
637  case CallingConv::Win64:
638  return true;
639  default:
640  return false;
641  }
642  }
643 
644  /// Return whether FrameLowering should always set the "extended frame
645  /// present" bit in FP, or set it based on a symbol in the runtime.
647  // Older OS versions (particularly system unwinders) are confused by the
648  // Swift extended frame, so when building code that might be run on them we
649  // must dynamically query the concurrency library to determine whether
650  // extended frames should be flagged as present.
651  const Triple &TT = getTargetTriple();
652 
653  unsigned Major = TT.getOSVersion().getMajor();
654  switch(TT.getOS()) {
655  default:
656  return false;
657  case Triple::IOS:
658  case Triple::TvOS:
659  return Major < 15;
660  case Triple::WatchOS:
661  return Major < 8;
662  case Triple::MacOSX:
663  case Triple::Darwin:
664  return Major < 12;
665  }
666  }
667 
668  void mirFileLoaded(MachineFunction &MF) const override;
669 
670  // Return the known range for the bit length of SVE data registers. A value
671  // of 0 means nothing is known about that particular limit beyong what's
672  // implied by the architecture.
673  unsigned getMaxSVEVectorSizeInBits() const {
674  assert(HasSVE && "Tried to get SVE vector length without SVE support!");
675  return MaxSVEVectorSizeInBits;
676  }
677 
678  unsigned getMinSVEVectorSizeInBits() const {
679  assert(HasSVE && "Tried to get SVE vector length without SVE support!");
680  return MinSVEVectorSizeInBits;
681  }
682 
683  bool useSVEForFixedLengthVectors() const;
684 
685  unsigned getVScaleForTuning() const { return VScaleForTuning; }
686 };
687 } // End llvm namespace
688 
689 #endif
llvm::AArch64Subtarget::NegativeImmediates
bool NegativeImmediates
Definition: AArch64Subtarget.h:241
i
i
Definition: README.txt:29
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:51
llvm::AArch64Subtarget::hasRandGen
bool hasRandGen() const
Definition: AArch64Subtarget.h:510
llvm::AArch64Subtarget::fixCortexA53_835769
bool fixCortexA53_835769() const
Definition: AArch64Subtarget.h:590
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:45
llvm::AArch64Subtarget::isTargetWindows
bool isTargetWindows() const
Definition: AArch64Subtarget.h:541
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
AArch64RegisterInfo.h
llvm::AArch64Subtarget::hasFuseLiterals
bool hasFuseLiterals() const
Definition: AArch64Subtarget.h:436
llvm::AArch64Subtarget::hasFPARMv8
bool hasFPARMv8() const
Definition: AArch64Subtarget.h:402
llvm::AArch64Subtarget::hasPAUTH
bool hasPAUTH() const
Definition: AArch64Subtarget.h:513
llvm::AArch64Subtarget::hasTRACEV8_4
bool hasTRACEV8_4() const
Definition: AArch64Subtarget.h:574
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:349
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::AArch64Subtarget::hasSVE2BitPerm
bool hasSVE2BitPerm() const
Definition: AArch64Subtarget.h:518
llvm::AArch64Subtarget::HasLSE
bool HasLSE
Definition: AArch64Subtarget.h:112
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:169
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:87
llvm::AArch64Subtarget::HasHCX
bool HasHCX
Definition: AArch64Subtarget.h:190
llvm::AArch64Subtarget::HasDotProd
bool HasDotProd
Definition: AArch64Subtarget.h:110
llvm::AArch64Subtarget::hasMatMulFP32
bool hasMatMulFP32() const
Definition: AArch64Subtarget.h:520
llvm::AArch64Subtarget::swiftAsyncContextIsDynamicallySet
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: AArch64Subtarget.h:646
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:76
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:219
llvm::AArch64Subtarget::hasFRInt3264
bool hasFRInt3264() const
Definition: AArch64Subtarget.h:503
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:284
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:54
llvm::AArch64Subtarget::predictableSelectIsExpensive
bool predictableSelectIsExpensive() const
Definition: AArch64Subtarget.h:417
llvm::AArch64Subtarget::hasSPE
bool hasSPE() const
Definition: AArch64Subtarget.h:496
CallLowering.h
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::isTargetIOS
bool isTargetIOS() const
Definition: AArch64Subtarget.h:539
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:78
llvm::AArch64Subtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: AArch64Subtarget.h:545
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:81
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:621
llvm::AArch64Subtarget::HasLS64
bool HasLS64
Definition: AArch64Subtarget.h:191
llvm::AArch64Subtarget::hasCONTEXTIDREL2
bool hasCONTEXTIDREL2() const
Definition: AArch64Subtarget.h:415
llvm::AArch64Subtarget::OutlineAtomics
bool OutlineAtomics
Definition: AArch64Subtarget.h:246
llvm::AArch64Subtarget::hasSB
bool hasSB() const
Definition: AArch64Subtarget.h:506
llvm::AArch64Subtarget::getPrefFunctionLogAlignment
unsigned getPrefFunctionLogAlignment() const
Definition: AArch64Subtarget.h:470
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:60
llvm::Triple::Darwin
@ Darwin
Definition: Triple.h:175
llvm::AArch64Subtarget::HasFP16FML
bool HasFP16FML
Definition: AArch64Subtarget.h:118
llvm::AArch64Subtarget::getMinSVEVectorSizeInBits
unsigned getMinSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:678
llvm::AArch64Subtarget::hasSM4
bool hasSM4() const
Definition: AArch64Subtarget.h:411
llvm::AArch64Subtarget::hasFlagM
bool hasFlagM() const
Definition: AArch64Subtarget.h:583
llvm::AArch64Subtarget::HasRandGen
bool HasRandGen
Definition: AArch64Subtarget.h:174
llvm::AArch64Subtarget::HasCCIDX
bool HasCCIDX
Definition: AArch64Subtarget.h:147
llvm::AArch64Subtarget::hasMPAM
bool hasMPAM() const
Definition: AArch64Subtarget.h:572
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:312
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:56
llvm::AArch64Subtarget::hasV9_2aOps
bool hasV9_2aOps() const
Definition: AArch64Subtarget.h:374
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:308
llvm::AArch64Subtarget::useEL3ForTP
bool useEL3ForTP() const
Definition: AArch64Subtarget.h:451
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:72
llvm::AArch64Subtarget::DisableLatencySchedHeuristic
bool DisableLatencySchedHeuristic
Definition: AArch64Subtarget.h:265
llvm::AArch64Subtarget::hasSVE
bool hasSVE() const
Definition: AArch64Subtarget.h:498
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:225
llvm::AArch64Subtarget::UseEL1ForTP
bool UseEL1ForTP
Definition: AArch64Subtarget.h:268
llvm::AArch64Subtarget::HasV9_2aOps
bool HasV9_2aOps
Definition: AArch64Subtarget.h:100
llvm::AArch64Subtarget::HasAggressiveFMA
bool HasAggressiveFMA
Definition: AArch64Subtarget.h:163
llvm::AArch64Subtarget::HasTRACEV8_4
bool HasTRACEV8_4
Definition: AArch64Subtarget.h:154
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:59
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:275
llvm::AArch64Subtarget::hasZeroCycleZeroingFP
bool hasZeroCycleZeroingFP() const
Definition: AArch64Subtarget.h:382
RegisterBankInfo.h
llvm::AArch64Subtarget::HasV8_3aOps
bool HasV8_3aOps
Definition: AArch64Subtarget.h:92
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:310
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:538
llvm::AArch64Subtarget::isTargetELF
bool isTargetELF() const
Definition: AArch64Subtarget.h:546
llvm::AArch64Subtarget::hasTME
bool hasTME() const
Definition: AArch64Subtarget.h:512
llvm::Triple::IOS
@ IOS
Definition: Triple.h:179
llvm::AArch64Subtarget::getVectorInsertExtractBaseCost
unsigned getVectorInsertExtractBaseCost() const
Definition: AArch64Subtarget.h:456
llvm::AArch64Subtarget::HasZeroCycleZeroing
bool HasZeroCycleZeroing
Definition: AArch64Subtarget.h:227
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AArch64Subtarget::hasRAS
bool hasRAS() const
Definition: AArch64Subtarget.h:409
llvm::AArch64Subtarget::HasMPAM
bool HasMPAM
Definition: AArch64Subtarget.h:152
llvm::AArch64Subtarget::TLInfo
AArch64TargetLowering TLInfo
Definition: AArch64Subtarget.h:305
llvm::AArch64Subtarget::getInstrInfo
const AArch64InstrInfo * getInstrInfo() const override
Definition: AArch64Subtarget.h:343
llvm::AArch64Subtarget::HasStreamingSVE
bool HasStreamingSVE
Definition: AArch64Subtarget.h:211
llvm::AArch64Subtarget::isMisaligned128StoreSlow
bool isMisaligned128StoreSlow() const
Definition: AArch64Subtarget.h:422
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:279
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:276
llvm::AArch64Subtarget::HasCmpBccFusion
bool HasCmpBccFusion
Definition: AArch64Subtarget.h:258
llvm::AArch64Subtarget::HasFuseCryptoEOR
bool HasFuseCryptoEOR
Definition: AArch64Subtarget.h:263
llvm::AArch64Subtarget::hasCRC
bool hasCRC() const
Definition: AArch64Subtarget.h:406
llvm::AArch64Subtarget::HasSME
bool HasSME
Definition: AArch64Subtarget.h:208
llvm::AArch64Subtarget::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Definition: AArch64Subtarget.h:247
llvm::AArch64Subtarget::HasCCPP
bool HasCCPP
Definition: AArch64Subtarget.h:131
llvm::AArch64Subtarget::Force32BitJumpTables
bool Force32BitJumpTables
Definition: AArch64Subtarget.h:267
llvm::AArch64Subtarget::HasSVE2SHA3
bool HasSVE2SHA3
Definition: AArch64Subtarget.h:201
llvm::AArch64Subtarget::hasPAN
bool hasPAN() const
Definition: AArch64Subtarget.h:559
llvm::AArch64Subtarget::isSTRQroSlow
bool isSTRQroSlow() const
Definition: AArch64Subtarget.h:424
llvm::AArch64Subtarget::HasV8_5aOps
bool HasV8_5aOps
Definition: AArch64Subtarget.h:94
llvm::AArch64Subtarget::useSVEForFixedLengthVectors
bool useSVEForFixedLengthVectors() const
Definition: AArch64Subtarget.cpp:375
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:579
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:49
llvm::AArch64Subtarget::isXRegCustomCalleeSaved
bool isXRegCustomCalleeSaved(size_t i) const
Definition: AArch64Subtarget.h:398
llvm::AArch64Subtarget::HardenSlsNoComdat
bool HardenSlsNoComdat
Definition: AArch64Subtarget.h:274
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:77
llvm::AArch64Subtarget::hasVH
bool hasVH() const
Definition: AArch64Subtarget.h:558
llvm::AArch64Subtarget::HasSHA3
bool HasSHA3
Definition: AArch64Subtarget.h:140
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:82
llvm::AArch64Subtarget::CortexX2
@ CortexX2
Definition: AArch64Subtarget.h:66
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:46
llvm::AArch64Subtarget::HasEnhancedCounterVirtualization
bool HasEnhancedCounterVirtualization
Definition: AArch64Subtarget.h:185
llvm::AArch64Subtarget::MaxBytesForLoopAlignment
unsigned MaxBytesForLoopAlignment
Definition: AArch64Subtarget.h:283
llvm::AArch64Subtarget::hasRCPC
bool hasRCPC() const
Definition: AArch64Subtarget.h:500
AArch64SelectionDAGInfo.h
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::AArch64Subtarget::UseEL3ForTP
bool UseEL3ForTP
Definition: AArch64Subtarget.h:270
llvm::AArch64Subtarget::getPrefetchDistance
unsigned getPrefetchDistance() const override
Definition: AArch64Subtarget.h:460
llvm::AArch64Subtarget::HasV8_8aOps
bool HasV8_8aOps
Definition: AArch64Subtarget.h:97
llvm::AArch64Subtarget::hardenSlsRetBr
bool hardenSlsRetBr() const
Definition: AArch64Subtarget.h:445
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:282
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:61
llvm::AArch64Subtarget::HasRDM
bool HasRDM
Definition: AArch64Subtarget.h:115
LegalizerInfo.h
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::hasSMEF64
bool hasSMEF64() const
Definition: AArch64Subtarget.h:532
llvm::AArch64Subtarget::HasCRC
bool HasCRC
Definition: AArch64Subtarget.h:111
llvm::Triple::WatchOS
@ WatchOS
Definition: Triple.h:200
llvm::AArch64Subtarget::hasEL3
bool hasEL3() const
Definition: AArch64Subtarget.h:586
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:340
llvm::AArch64Subtarget::HasSVE2BitPerm
bool HasSVE2BitPerm
Definition: AArch64Subtarget.h:202
llvm::AArch64Subtarget::hasAM
bool hasAM() const
Definition: AArch64Subtarget.h:575
llvm::AArch64Subtarget::hasSpecRestrict
bool hasSpecRestrict() const
Definition: AArch64Subtarget.h:504
llvm::AArch64Subtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
Definition: AArch64Subtarget.h:354
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:74
llvm::AArch64Subtarget::getWideningBaseCost
unsigned getWideningBaseCost() const
Definition: AArch64Subtarget.h:481
llvm::AArch64Subtarget::addrSinkUsingGEPs
bool addrSinkUsingGEPs() const override
Definition: AArch64Subtarget.h:592
llvm::AArch64Subtarget::HasMatMulFP32
bool HasMatMulFP32
Definition: AArch64Subtarget.h:181
llvm::AArch64Subtarget::HasFlagM
bool HasFlagM
Definition: AArch64Subtarget.h:158
llvm::AArch64Subtarget::HasFPARMv8
bool HasFPARMv8
Definition: AArch64Subtarget.h:107
llvm::AArch64FrameLowering
Definition: AArch64FrameLowering.h:23
llvm::AArch64Subtarget::HasCONTEXTIDREL2
bool HasCONTEXTIDREL2
Definition: AArch64Subtarget.h:104
llvm::AArch64Subtarget::UseRSqrt
bool UseRSqrt
Definition: AArch64Subtarget.h:266
llvm::AArch64Subtarget::hasAlternativeNZCV
bool hasAlternativeNZCV() const
Definition: AArch64Subtarget.h:502
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:361
llvm::AArch64Subtarget::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AArch64Subtarget.h:392
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:657
llvm::AArch64SelectionDAGInfo
Definition: AArch64SelectionDAGInfo.h:20
llvm::AArch64Subtarget::hasV8_2aOps
bool hasV8_2aOps() const
Definition: AArch64Subtarget.h:368
llvm::AArch64Subtarget::HasSPE
bool HasSPE
Definition: AArch64Subtarget.h:119
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:616
llvm::AArch64Subtarget::useAlternateSExtLoadCVTF32Pattern
bool useAlternateSExtLoadCVTF32Pattern() const
Definition: AArch64Subtarget.h:425
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:261
AArch64InstrInfo.h
llvm::AArch64Subtarget::HasSHA2
bool HasSHA2
Definition: AArch64Subtarget.h:141
llvm::AArch64Subtarget::MinSVEVectorSizeInBits
unsigned MinSVEVectorSizeInBits
Definition: AArch64Subtarget.h:295
llvm::AArch64Subtarget::UseScalarIncVL
bool UseScalarIncVL
Definition: AArch64Subtarget.h:136
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:265
InlineAsmLowering.h
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::AArch64Subtarget::HasSVE2SM4
bool HasSVE2SM4
Definition: AArch64Subtarget.h:200
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:37
llvm::AArch64Subtarget::hasLS64
bool hasLS64() const
Definition: AArch64Subtarget.h:580
llvm::AArch64Subtarget::hasDotProd
bool hasDotProd() const
Definition: AArch64Subtarget.h:405
llvm::Triple::TvOS
@ TvOS
Definition: Triple.h:199
llvm::AArch64Subtarget::isLittleEndian
bool isLittleEndian() const
Definition: AArch64Subtarget.h:536
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:468
llvm::AArch64Subtarget::HasComplxNum
bool HasComplxNum
Definition: AArch64Subtarget.h:148
llvm::AArch64Subtarget::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Definition: AArch64Subtarget.h:479
llvm::AArch64Subtarget::HasLSLFast
bool HasLSLFast
Definition: AArch64Subtarget.h:161
llvm::AArch64Subtarget::isTargetILP32
bool isTargetILP32() const
Definition: AArch64Subtarget.h:549
llvm::BitVector::count
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:154
llvm::AArch64Subtarget::hasMatMulInt8
bool hasMatMulInt8() const
Definition: AArch64Subtarget.h:519
llvm::AArch64Subtarget::HasV9_1aOps
bool HasV9_1aOps
Definition: AArch64Subtarget.h:99
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:277
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:345
llvm::AArch64Subtarget::HasPAN
bool HasPAN
Definition: AArch64Subtarget.h:125
llvm::AArch64Subtarget::HasFuseLiterals
bool HasFuseLiterals
Definition: AArch64Subtarget.h:264
llvm::AArch64Subtarget::Neoverse512TVB
@ Neoverse512TVB
Definition: AArch64Subtarget.h:73
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::HasAMVS
bool HasAMVS
Definition: AArch64Subtarget.h:183
llvm::AArch64Subtarget::HasV8_0rOps
bool HasV8_0rOps
Definition: AArch64Subtarget.h:102
llvm::AArch64Subtarget::HasV8_4aOps
bool HasV8_4aOps
Definition: AArch64Subtarget.h:93
llvm::AArch64Subtarget::HasETE
bool HasETE
Definition: AArch64Subtarget.h:217
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:365
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::AArch64Subtarget::hasSVE2SHA3
bool hasSVE2SHA3() const
Definition: AArch64Subtarget.h:517
llvm::AArch64Subtarget::HasRAS
bool HasRAS
Definition: AArch64Subtarget.h:114
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:629
llvm::AArch64Subtarget::hardenSlsBlr
bool hardenSlsBlr() const
Definition: AArch64Subtarget.h:446
AArch64GenSubtargetInfo
llvm::AArch64Subtarget::HasZeroCycleZeroingGP
bool HasZeroCycleZeroingGP
Definition: AArch64Subtarget.h:228
llvm::AArch64Subtarget::HasWFxT
bool HasWFxT
Definition: AArch64Subtarget.h:189
llvm::AArch64Subtarget::isXRaySupported
bool isXRaySupported() const override
Definition: AArch64Subtarget.h:390
llvm::AArch64Subtarget::balanceFPOps
bool balanceFPOps() const
Definition: AArch64Subtarget.h:416
llvm::AArch64Subtarget::VScaleForTuning
unsigned VScaleForTuning
Definition: AArch64Subtarget.h:297
llvm::AArch64Subtarget::hasCrypto
bool hasCrypto() const
Definition: AArch64Subtarget.h:404
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:62
llvm::AArch64Subtarget::BalanceFPOps
bool BalanceFPOps
Definition: AArch64Subtarget.h:248
llvm::AArch64Subtarget::HasAlternativeNZCV
bool HasAlternativeNZCV
Definition: AArch64Subtarget.h:166
llvm::AArch64Subtarget::hasV9_1aOps
bool hasV9_1aOps() const
Definition: AArch64Subtarget.h:373
llvm::BitVector
Definition: BitVector.h:74
llvm::AArch64Subtarget::HasSVE2AES
bool HasSVE2AES
Definition: AArch64Subtarget.h:199
llvm::AArch64Subtarget::getProcFamily
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
Definition: AArch64Subtarget.h:362
llvm::AArch64Subtarget::HasPredRes
bool HasPredRes
Definition: AArch64Subtarget.h:171
llvm::AArch64Subtarget::hasZeroCycleRegMove
bool hasZeroCycleRegMove() const
Definition: AArch64Subtarget.h:378
llvm::AArch64Subtarget::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: AArch64Subtarget.h:459
llvm::AArch64Subtarget::HasSMEI64
bool HasSMEI64
Definition: AArch64Subtarget.h:210
llvm::AArch64Subtarget::UseExperimentalZeroingPseudos
bool UseExperimentalZeroingPseudos
Definition: AArch64Subtarget.h:135
llvm::AArch64Subtarget::IsLittle
bool IsLittle
Definition: AArch64Subtarget.h:293
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AArch64Subtarget::HasAES
bool HasAES
Definition: AArch64Subtarget.h:142
llvm::AArch64Subtarget::hasRCPC_IMMO
bool hasRCPC_IMMO() const
Definition: AArch64Subtarget.h:584
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:281
llvm::AArch64Subtarget::HasPAUTH
bool HasPAUTH
Definition: AArch64Subtarget.h:220
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AArch64Subtarget::STRQroIsSlow
bool STRQroIsSlow
Definition: AArch64Subtarget.h:254
llvm::AArch64Subtarget::HasTME
bool HasTME
Definition: AArch64Subtarget.h:176
llvm::AArch64Subtarget::HasBRBE
bool HasBRBE
Definition: AArch64Subtarget.h:219
llvm::Triple::isOSFuchsia
bool isOSFuchsia() const
Definition: Triple.h:498
llvm::AArch64Subtarget::CustomAsCheapAsMove
bool CustomAsCheapAsMove
Definition: AArch64Subtarget.h:249
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:65
llvm::AArch64Subtarget::MaxSVEVectorSizeInBits
unsigned MaxSVEVectorSizeInBits
Definition: AArch64Subtarget.h:296
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:80
InstructionSelector.h
llvm::AArch64Subtarget::HasVH
bool HasVH
Definition: AArch64Subtarget.h:124
llvm::AArch64Subtarget::HasMTE
bool HasMTE
Definition: AArch64Subtarget.h:175
llvm::AArch64Subtarget::getSelectionDAGInfo
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: AArch64Subtarget.h:334
llvm::AArch64Subtarget::hasNV
bool hasNV() const
Definition: AArch64Subtarget.h:571
llvm::AArch64Subtarget::hasArithmeticBccFusion
bool hasArithmeticBccFusion() const
Definition: AArch64Subtarget.h:428
llvm::AArch64Subtarget::HasBF16
bool HasBF16
Definition: AArch64Subtarget.h:179
llvm::AArch64Subtarget::HasFuseArithmeticLogic
bool HasFuseArithmeticLogic
Definition: AArch64Subtarget.h:261
llvm::Triple::MacOSX
@ MacOSX
Definition: Triple.h:183
llvm::AArch64Subtarget::HasSPE_EEF
bool HasSPE_EEF
Definition: AArch64Subtarget.h:221
llvm::AArch64Subtarget::hasV8_0aOps
bool hasV8_0aOps() const
Definition: AArch64Subtarget.h:366
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:257
llvm::AArch64Subtarget::hasJS
bool hasJS() const
Definition: AArch64Subtarget.h:567
llvm::AArch64Subtarget::useExperimentalZeroingPseudos
bool useExperimentalZeroingPseudos() const
Definition: AArch64Subtarget.h:483
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::AArch64Subtarget::HasPsUAO
bool HasPsUAO
Definition: AArch64Subtarget.h:129
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:288
llvm::AArch64Subtarget::hasLOR
bool hasLOR() const
Definition: AArch64Subtarget.h:560
llvm::AArch64Subtarget::HasXS
bool HasXS
Definition: AArch64Subtarget.h:188
llvm::AArch64Subtarget::hasLSLFast
bool hasLSLFast() const
Definition: AArch64Subtarget.h:497
llvm::AArch64Subtarget::hasCmpBccFusion
bool hasCmpBccFusion() const
Definition: AArch64Subtarget.h:430
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:58
AArch64FrameLowering.h
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:162
llvm::AArch64Subtarget::hasZeroCycleZeroingFPWorkaround
bool hasZeroCycleZeroingFPWorkaround() const
Definition: AArch64Subtarget.h:384
llvm::AArch64Subtarget::hardenSlsNoComdat
bool hardenSlsNoComdat() const
Definition: AArch64Subtarget.h:447
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:598
llvm::AArch64Subtarget::UseEL2ForTP
bool UseEL2ForTP
Definition: AArch64Subtarget.h:269
llvm::Triple::isArch32Bit
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1347
llvm::AArch64Subtarget::hasWFxT
bool hasWFxT() const
Definition: AArch64Subtarget.h:578
llvm::AArch64Subtarget::hasFuseCryptoEOR
bool hasFuseCryptoEOR() const
Definition: AArch64Subtarget.h:435
llvm::AArch64Subtarget::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
Definition: AArch64Subtarget.h:461
llvm::AArch64Subtarget::hasMTE
bool hasMTE() const
Definition: AArch64Subtarget.h:511
llvm::AArch64Subtarget::FixCortexA53_835769
bool FixCortexA53_835769
Definition: AArch64Subtarget.h:121
llvm::AArch64Subtarget::HasSM4
bool HasSM4
Definition: AArch64Subtarget.h:139
llvm::AArch64Subtarget::useEL2ForTP
bool useEL2ForTP() const
Definition: AArch64Subtarget.h:450
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:48
llvm::AArch64Subtarget::hasAMVS
bool hasAMVS() const
Definition: AArch64Subtarget.h:576
llvm::AArch64Subtarget::StrictAlign
bool StrictAlign
Definition: AArch64Subtarget.h:238
llvm::AArch64Subtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: AArch64Subtarget.h:353
llvm::AArch64Subtarget::AllowTaggedGlobals
bool AllowTaggedGlobals
Definition: AArch64Subtarget.h:271
llvm::AArch64Subtarget::hasFineGrainedTraps
bool hasFineGrainedTraps() const
Definition: AArch64Subtarget.h:525
llvm::AArch64Subtarget::HasPAuth
bool HasPAuth
Definition: AArch64Subtarget.h:145
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:70
llvm::AArch64Subtarget::UseAlternateSExtLoadCVTF32Pattern
bool UseAlternateSExtLoadCVTF32Pattern
Definition: AArch64Subtarget.h:255
llvm::AArch64Subtarget::hasSSBS
bool hasSSBS() const
Definition: AArch64Subtarget.h:505
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::AArch64Subtarget::HasNV
bool HasNV
Definition: AArch64Subtarget.h:151
llvm::AArch64Subtarget::hasV8_4aOps
bool hasV8_4aOps() const
Definition: AArch64Subtarget.h:370
llvm::AArch64Subtarget::HasV8_0aOps
bool HasV8_0aOps
Definition: AArch64Subtarget.h:89
llvm::AArch64Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: AArch64Subtarget.h:540
llvm::AArch64Subtarget::hasComplxNum
bool hasComplxNum() const
Definition: AArch64Subtarget.h:569
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:244
llvm::AArch64Subtarget::UsePostRAScheduler
bool UsePostRAScheduler
Definition: AArch64Subtarget.h:251
llvm::AArch64Subtarget::hasBTI
bool hasBTI() const
Definition: AArch64Subtarget.h:509
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:631
llvm::AArch64Subtarget::HasV8_2aOps
bool HasV8_2aOps
Definition: AArch64Subtarget.h:91
llvm::AArch64Subtarget::hasNEON
bool hasNEON() const
Definition: AArch64Subtarget.h:403
llvm::AArch64Subtarget::HasRCPC
bool HasRCPC
Definition: AArch64Subtarget.h:162
llvm::AArch64Subtarget::hasFuseAES
bool hasFuseAES() const
Definition: AArch64Subtarget.h:432
llvm::AArch64Subtarget::TSInfo
AArch64SelectionDAGInfo TSInfo
Definition: AArch64Subtarget.h:304
llvm::AArch64Subtarget::HasDIT
bool HasDIT
Definition: AArch64Subtarget.h:153
llvm::AArch64Subtarget::hasEnhancedCounterVirtualization
bool hasEnhancedCounterVirtualization() const
Definition: AArch64Subtarget.h:526
llvm::AArch64Subtarget::hasCCDP
bool hasCCDP() const
Definition: AArch64Subtarget.h:508
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::AArch64Subtarget::hasFuseArithmeticLogic
bool hasFuseArithmeticLogic() const
Definition: AArch64Subtarget.h:433
llvm::AArch64Subtarget::hasArithmeticCbzFusion
bool hasArithmeticCbzFusion() const
Definition: AArch64Subtarget.h:429
llvm::AArch64Subtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: AArch64Subtarget.h:455
llvm::AArch64Subtarget::hasCCIDX
bool hasCCIDX() const
Definition: AArch64Subtarget.h:568
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: AArch64Subtarget.cpp:312
llvm::AArch64Subtarget::HasFullFP16
bool HasFullFP16
Definition: AArch64Subtarget.h:117
llvm::AArch64Subtarget::HasFRInt3264
bool HasFRInt3264
Definition: AArch64Subtarget.h:167
llvm::AArch64Subtarget::HasBTI
bool HasBTI
Definition: AArch64Subtarget.h:173
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:401
llvm::AArch64Subtarget::HasEL2VMSA
bool HasEL2VMSA
Definition: AArch64Subtarget.h:105
llvm::AArch64Subtarget::outlineAtomics
bool outlineAtomics() const
Definition: AArch64Subtarget.h:556
llvm::AArch64Subtarget::CortexA710
@ CortexA710
Definition: AArch64Subtarget.h:63
llvm::AArch64Subtarget::isXRegisterReserved
bool isXRegisterReserved(size_t i) const
Definition: AArch64Subtarget.h:396
llvm::AArch64Subtarget::hasAES
bool hasAES() const
Definition: AArch64Subtarget.h:414
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AArch64Subtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: AArch64Subtarget.h:311
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:352
llvm::AArch64Subtarget::hasFuseCCSelect
bool hasFuseCCSelect() const
Definition: AArch64Subtarget.h:434
llvm::AArch64Subtarget::hasDIT
bool hasDIT() const
Definition: AArch64Subtarget.h:573
llvm::AArch64Subtarget::getFrameLowering
const AArch64FrameLowering * getFrameLowering() const override
Definition: AArch64Subtarget.h:337
TargetSubtargetInfo.h
llvm::AArch64Subtarget::HasSVE
bool HasSVE
Definition: AArch64Subtarget.h:134
llvm::AArch64Subtarget::getVScaleForTuning
unsigned getVScaleForTuning() const
Definition: AArch64Subtarget.h:685
llvm::AArch64Subtarget::getMaxBytesForLoopAlignment
unsigned getMaxBytesForLoopAlignment() const
Definition: AArch64Subtarget.h:475
llvm::AArch64Subtarget::HasFineGrainedTraps
bool HasFineGrainedTraps
Definition: AArch64Subtarget.h:184
llvm::AArch64Subtarget::hasPAuth
bool hasPAuth() const
Definition: AArch64Subtarget.h:566
llvm::AArch64Subtarget::HasFuseAES
bool HasFuseAES
Definition: AArch64Subtarget.h:260
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:447
llvm::AArch64Subtarget::WideningBaseCost
unsigned WideningBaseCost
Definition: AArch64Subtarget.h:285
llvm::AArch64Subtarget::HasAppleA7SysReg
bool HasAppleA7SysReg
Definition: AArch64Subtarget.h:214
llvm::AArch64Subtarget::HasSB
bool HasSB
Definition: AArch64Subtarget.h:170
llvm::AArch64Subtarget::hasV8_0rOps
bool hasV8_0rOps() const
Definition: AArch64Subtarget.h:376
llvm::AArch64Subtarget::HasSpecRestrict
bool HasSpecRestrict
Definition: AArch64Subtarget.h:168
llvm::AArch64Subtarget::ExynosAsCheapAsMove
bool ExynosAsCheapAsMove
Definition: AArch64Subtarget.h:250
llvm::AArch64Subtarget::useEL1ForTP
bool useEL1ForTP() const
Definition: AArch64Subtarget.h:449
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::AArch64Subtarget::hasPsUAO
bool hasPsUAO() const
Definition: AArch64Subtarget.h:562
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:43
llvm::AArch64Subtarget::HasV8_6aOps
bool HasV8_6aOps
Definition: AArch64Subtarget.h:95
AArch64ISelLowering.h
llvm::AArch64Subtarget::HasCrypto
bool HasCrypto
Definition: AArch64Subtarget.h:109
llvm::AArch64Subtarget::hasSVE2
bool hasSVE2() const
Definition: AArch64Subtarget.h:499
llvm::AArch64Subtarget::hasSVE2AES
bool hasSVE2AES() const
Definition: AArch64Subtarget.h:515
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:79
llvm::AArch64Subtarget::force32BitJumpTables
bool force32BitJumpTables() const
Definition: AArch64Subtarget.h:454
llvm::AArch64Subtarget::HasZeroCycleZeroingFP
bool HasZeroCycleZeroingFP
Definition: AArch64Subtarget.h:235
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:50
llvm::AArch64Subtarget::hasTLB_RMI
bool hasTLB_RMI() const
Definition: AArch64Subtarget.h:582
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:531
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:52
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:344
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:338
llvm::AArch64Subtarget::HardenSlsRetBr
bool HardenSlsRetBr
Definition: AArch64Subtarget.h:272
llvm::AArch64Subtarget::isPaired128Slow
bool isPaired128Slow() const
Definition: AArch64Subtarget.h:423
llvm::AArch64Subtarget::hasV8_3aOps
bool hasV8_3aOps() const
Definition: AArch64Subtarget.h:369
llvm::AArch64Subtarget::hasPerfMon
bool hasPerfMon() const
Definition: AArch64Subtarget.h:493
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:47
llvm::AArch64Subtarget::HasArithmeticCbzFusion
bool HasArithmeticCbzFusion
Definition: AArch64Subtarget.h:257
llvm::AArch64Subtarget::hasSME
bool hasSME() const
Definition: AArch64Subtarget.h:531
llvm::AArch64Subtarget::HasZeroCycleZeroingFPWorkaround
bool HasZeroCycleZeroingFPWorkaround
Definition: AArch64Subtarget.h:229
llvm::AArch64Subtarget::useRSqrt
bool useRSqrt() const
Definition: AArch64Subtarget.h:453
llvm::AArch64Subtarget::HasTLB_RMI
bool HasTLB_RMI
Definition: AArch64Subtarget.h:157
llvm::AArch64Subtarget::hasPAN_RWV
bool hasPAN_RWV() const
Definition: AArch64Subtarget.h:563
llvm::AArch64Subtarget::hasRDM
bool hasRDM() const
Definition: AArch64Subtarget.h:410
llvm::AArch64Subtarget::getNumXRegisterReserved
unsigned getNumXRegisterReserved() const
Definition: AArch64Subtarget.h:397
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:273
llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits
unsigned getMaxSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:673
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:67
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:280
uint16_t
llvm::AArch64Subtarget::HasLSE2
bool HasLSE2
Definition: AArch64Subtarget.h:113
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:309
llvm::AArch64Subtarget::HasLOR
bool HasLOR
Definition: AArch64Subtarget.h:126
llvm::AArch64Subtarget::HasV8_1aOps
bool HasV8_1aOps
Definition: AArch64Subtarget.h:90
llvm::AArch64Subtarget::hasLSE2
bool hasLSE2() const
Definition: AArch64Subtarget.h:408
llvm::AArch64Subtarget::HasNEON
bool HasNEON
Definition: AArch64Subtarget.h:108
llvm::AArch64Subtarget::HasV9_3aOps
bool HasV9_3aOps
Definition: AArch64Subtarget.h:101
llvm::AArch64Subtarget::hasSEL2
bool hasSEL2() const
Definition: AArch64Subtarget.h:581
llvm::AArch64Subtarget::hasFullFP16
bool hasFullFP16() const
Definition: AArch64Subtarget.h:494
llvm::AArch64Subtarget::HasSMEF64
bool HasSMEF64
Definition: AArch64Subtarget.h:209
llvm::AArch64Subtarget::HasTRBE
bool HasTRBE
Definition: AArch64Subtarget.h:218
llvm::AArch64Subtarget::hasCCPP
bool hasCCPP() const
Definition: AArch64Subtarget.h:564
llvm::AArch64Subtarget::enableAdvancedRASplitCost
bool enableAdvancedRASplitCost() const override
Definition: AArch64Subtarget.h:627
llvm::AArch64Subtarget::hasFuseAddress
bool hasFuseAddress() const
Definition: AArch64Subtarget.h:431
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:69
llvm::AArch64Subtarget::HasMatMulFP64
bool HasMatMulFP64
Definition: AArch64Subtarget.h:182
llvm::AArch64Subtarget::hasHBC
bool hasHBC() const
Definition: AArch64Subtarget.h:587
llvm::AArch64Subtarget::HasMOPS
bool HasMOPS
Definition: AArch64Subtarget.h:195
llvm::AArch64Subtarget::Misaligned128StoreIsSlow
bool Misaligned128StoreIsSlow
Definition: AArch64Subtarget.h:252
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:278
llvm::AArch64Subtarget::HasArithmeticBccFusion
bool HasArithmeticBccFusion
Definition: AArch64Subtarget.h:256
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:280
llvm::AArch64Subtarget::hasLSE
bool hasLSE() const
Definition: AArch64Subtarget.h:407
llvm::AArch64Subtarget::HasPerfMon
bool HasPerfMon
Definition: AArch64Subtarget.h:116
llvm::AArch64Subtarget::isTargetFuchsia
bool isTargetFuchsia() const
Definition: AArch64Subtarget.h:543
llvm::AArch64Subtarget::InstrInfo
AArch64InstrInfo InstrInfo
Definition: AArch64Subtarget.h:303
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:547
llvm::AArch64Subtarget::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const override
Definition: AArch64Subtarget.h:467
llvm::AArch64Subtarget::hasMOPS
bool hasMOPS() const
Definition: AArch64Subtarget.h:588
llvm::AArch64Subtarget::hasXS
bool hasXS() const
Definition: AArch64Subtarget.h:577
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:57
llvm::AArch64Subtarget::hasV8_5aOps
bool hasV8_5aOps() const
Definition: AArch64Subtarget.h:371
llvm::AArch64Subtarget::HasZeroCycleRegMove
bool HasZeroCycleRegMove
Definition: AArch64Subtarget.h:224
llvm::AArch64Subtarget::hasMatMulFP64
bool hasMatMulFP64() const
Definition: AArch64Subtarget.h:521
llvm::AArch64Subtarget::hasExynosCheapAsMoveHandling
bool hasExynosCheapAsMoveHandling() const
Definition: AArch64Subtarget.h:421
llvm::AArch64Subtarget::hasFP16FML
bool hasFP16FML() const
Definition: AArch64Subtarget.h:495
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:75
llvm::AArch64Subtarget::hasPredRes
bool hasPredRes() const
Definition: AArch64Subtarget.h:507
llvm::AArch64Subtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: AArch64Subtarget.h:473
llvm::AArch64Subtarget::HasRCPC_IMMO
bool HasRCPC_IMMO
Definition: AArch64Subtarget.h:159
llvm::AArch64Subtarget::Paired128IsSlow
bool Paired128IsSlow
Definition: AArch64Subtarget.h:253
llvm::AArch64Subtarget::HasV8_7aOps
bool HasV8_7aOps
Definition: AArch64Subtarget.h:96
llvm::AArch64Subtarget::hasEL2VMSA
bool hasEL2VMSA() const
Definition: AArch64Subtarget.h:585
llvm::AArch64Subtarget::HasSEL2
bool HasSEL2
Definition: AArch64Subtarget.h:156
llvm::AArch64Subtarget::HasRME
bool HasRME
Definition: AArch64Subtarget.h:205
llvm::AArch64Subtarget::hasZeroCycleZeroingGP
bool hasZeroCycleZeroingGP() const
Definition: AArch64Subtarget.h:380
llvm::AArch64Subtarget::HasFuseCCSelect
bool HasFuseCCSelect
Definition: AArch64Subtarget.h:262
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:300
llvm::AArch64Subtarget::requiresStrictAlign
bool requiresStrictAlign() const
Definition: AArch64Subtarget.h:388
llvm::AArch64Subtarget::HasAM
bool HasAM
Definition: AArch64Subtarget.h:155
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:328
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:269
llvm::AArch64Subtarget::HasFuseAddress
bool HasFuseAddress
Definition: AArch64Subtarget.h:259
llvm::AArch64Subtarget::hasSMEI64
bool hasSMEI64() const
Definition: AArch64Subtarget.h:533
llvm::AArch64Subtarget::HasCCDP
bool HasCCDP
Definition: AArch64Subtarget.h:172
llvm::AArch64Subtarget::HasPAN_RWV
bool HasPAN_RWV
Definition: AArch64Subtarget.h:130
llvm::AArch64Subtarget::hasSHA2
bool hasSHA2() const
Definition: AArch64Subtarget.h:413
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1143
llvm::AArch64Subtarget::useScalarIncVL
bool useScalarIncVL() const
Definition: AArch64Subtarget.h:487
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::CortexA510
@ CortexA510
Definition: AArch64Subtarget.h:53
llvm::AArch64Subtarget::HasJS
bool HasJS
Definition: AArch64Subtarget.h:146
llvm::AArch64Subtarget::hasHCX
bool hasHCX() const
Definition: AArch64Subtarget.h:579
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:64
llvm::AArch64Subtarget::CustomCallSavedXRegs
BitVector CustomCallSavedXRegs
Definition: AArch64Subtarget.h:291
llvm::AArch64Subtarget::HasHBC
bool HasHBC
Definition: AArch64Subtarget.h:194
llvm::AArch64Subtarget::hasV9_3aOps
bool hasV9_3aOps() const
Definition: AArch64Subtarget.h:375
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:179
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:491
llvm::AArch64Subtarget::hasV9_0aOps
bool hasV9_0aOps() const
Definition: AArch64Subtarget.h:372
llvm::AArch64Subtarget::HasV9_0aOps
bool HasV9_0aOps
Definition: AArch64Subtarget.h:98
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:380
llvm::AArch64Subtarget::hasStreamingSVE
bool hasStreamingSVE() const
Definition: AArch64Subtarget.h:534
llvm::AArch64Subtarget::hasAggressiveFMA
bool hasAggressiveFMA() const
Definition: AArch64Subtarget.h:501
llvm::CallLowering
Definition: CallLowering.h:43
llvm::AArch64Subtarget::hasBF16
bool hasBF16() const
Definition: AArch64Subtarget.h:524
llvm::AArch64Subtarget::HardenSlsBlr
bool HardenSlsBlr
Definition: AArch64Subtarget.h:273
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::AArch64Subtarget::HasMatMulInt8
bool HasMatMulInt8
Definition: AArch64Subtarget.h:180
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:68
llvm::AArch64Subtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: AArch64Subtarget.h:439
llvm::AArch64Subtarget::hasV8_1aOps
bool hasV8_1aOps() const
Definition: AArch64Subtarget.h:367
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:333
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:44
llvm::AArch64Subtarget::FrameLowering
AArch64FrameLowering FrameLowering
Definition: AArch64Subtarget.h:302
llvm::AArch64Subtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: AArch64Subtarget.h:542
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:47
llvm::AArch64Subtarget::HasSVE2
bool HasSVE2
Definition: AArch64Subtarget.h:198
llvm::AArch64Subtarget::hasSVE2SM4
bool hasSVE2SM4() const
Definition: AArch64Subtarget.h:516
llvm::AArch64Subtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: AArch64Subtarget.h:40
llvm::AArch64Subtarget::HasEL3
bool HasEL3
Definition: AArch64Subtarget.h:106
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:55
llvm::AArch64Subtarget::hasSHA3
bool hasSHA3() const
Definition: AArch64Subtarget.h:412
llvm::AArch64Subtarget::HasSSBS
bool HasSSBS
Definition: AArch64Subtarget.h:169
llvm::AArch64Subtarget::hasCustomCheapAsMoveHandling
bool hasCustomCheapAsMoveHandling() const
Definition: AArch64Subtarget.h:420