LLVM  10.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AArch64GenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class GlobalValue;
34 class StringRef;
35 class Triple;
36 
38 public:
39  enum ARMProcFamilyEnum : uint8_t {
64  };
65 
66 protected:
67  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
69 
70  bool HasV8_1aOps = false;
71  bool HasV8_2aOps = false;
72  bool HasV8_3aOps = false;
73  bool HasV8_4aOps = false;
74  bool HasV8_5aOps = false;
75 
76  bool HasFPARMv8 = false;
77  bool HasNEON = false;
78  bool HasCrypto = false;
79  bool HasDotProd = false;
80  bool HasCRC = false;
81  bool HasLSE = false;
82  bool HasRAS = false;
83  bool HasRDM = false;
84  bool HasPerfMon = false;
85  bool HasFullFP16 = false;
86  bool HasFP16FML = false;
87  bool HasSPE = false;
88 
89  // ARMv8.1 extensions
90  bool HasVH = false;
91  bool HasPAN = false;
92  bool HasLOR = false;
93 
94  // ARMv8.2 extensions
95  bool HasPsUAO = false;
96  bool HasPAN_RWV = false;
97  bool HasCCPP = false;
98 
99  // Armv8.2 Crypto extensions
100  bool HasSM4 = false;
101  bool HasSHA3 = false;
102  bool HasSHA2 = false;
103  bool HasAES = false;
104 
105  // ARMv8.3 extensions
106  bool HasPA = false;
107  bool HasJS = false;
108  bool HasCCIDX = false;
109  bool HasComplxNum = false;
110 
111  // ARMv8.4 extensions
112  bool HasNV = false;
113  bool HasRASv8_4 = false;
114  bool HasMPAM = false;
115  bool HasDIT = false;
116  bool HasTRACEV8_4 = false;
117  bool HasAM = false;
118  bool HasSEL2 = false;
119  bool HasTLB_RMI = false;
120  bool HasFMI = false;
121  bool HasRCPC_IMMO = false;
122 
123  bool HasLSLFast = false;
124  bool HasSVE = false;
125  bool HasSVE2 = false;
126  bool HasRCPC = false;
127  bool HasAggressiveFMA = false;
128 
129  // Armv8.5-A Extensions
130  bool HasAlternativeNZCV = false;
131  bool HasFRInt3264 = false;
132  bool HasSpecRestrict = false;
133  bool HasSSBS = false;
134  bool HasSB = false;
135  bool HasPredRes = false;
136  bool HasCCDP = false;
137  bool HasBTI = false;
138  bool HasRandGen = false;
139  bool HasMTE = false;
140  bool HasTME = false;
141 
142  // Arm SVE2 extensions
143  bool HasSVE2AES = false;
144  bool HasSVE2SM4 = false;
145  bool HasSVE2SHA3 = false;
146  bool HasSVE2BitPerm = false;
147 
148  // Future architecture extensions.
149  bool HasETE = false;
150  bool HasTRBE = false;
151 
152  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
153  bool HasZeroCycleRegMove = false;
154 
155  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
156  bool HasZeroCycleZeroing = false;
157  bool HasZeroCycleZeroingGP = false;
158  bool HasZeroCycleZeroingFP = false;
160 
161  // StrictAlign - Disallow unaligned memory accesses.
162  bool StrictAlign = false;
163 
164  // NegativeImmediates - transform instructions with negative immediates
165  bool NegativeImmediates = true;
166 
167  // Enable 64-bit vectorization in SLP.
169 
170  bool UseAA = false;
172  bool BalanceFPOps = false;
173  bool CustomAsCheapAsMove = false;
174  bool ExynosAsCheapAsMove = false;
175  bool UsePostRAScheduler = false;
177  bool Paired128IsSlow = false;
178  bool STRQroIsSlow = false;
182  bool HasFuseAddress = false;
183  bool HasFuseAES = false;
185  bool HasFuseCCSelect = false;
186  bool HasFuseCryptoEOR = false;
187  bool HasFuseLiterals = false;
189  bool UseRSqrt = false;
190  bool Force32BitJumpTables = false;
191  bool UseEL1ForTP = false;
192  bool UseEL2ForTP = false;
193  bool UseEL3ForTP = false;
194  bool AllowTaggedGlobals = false;
195  uint8_t MaxInterleaveFactor = 2;
197  uint16_t CacheLineSize = 0;
198  uint16_t PrefetchDistance = 0;
199  uint16_t MinPrefetchStride = 1;
200  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
202  unsigned PrefLoopLogAlignment = 0;
203  unsigned MaxJumpTableSize = 0;
204  unsigned WideningBaseCost = 0;
205 
206  // ReserveXRegister[i] - X#i is not available as a general purpose register.
208 
209  // CustomCallUsedXRegister[i] - X#i call saved.
211 
212  bool IsLittle;
213 
214  /// TargetTriple - What processor and OS we're targeting.
216 
221 
222  /// GlobalISel related APIs.
223  std::unique_ptr<CallLowering> CallLoweringInfo;
224  std::unique_ptr<InstructionSelector> InstSelector;
225  std::unique_ptr<LegalizerInfo> Legalizer;
226  std::unique_ptr<RegisterBankInfo> RegBankInfo;
227 
228 private:
229  /// initializeSubtargetDependencies - Initializes using CPUString and the
230  /// passed in feature string so that we can use initializer lists for
231  /// subtarget initialization.
232  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
233  StringRef CPUString);
234 
235  /// Initialize properties based on the selected processor family.
236  void initializeProperties();
237 
238 public:
239  /// This constructor initializes the data members to match that
240  /// of the specified triple.
241  AArch64Subtarget(const Triple &TT, const std::string &CPU,
242  const std::string &FS, const TargetMachine &TM,
243  bool LittleEndian);
244 
246  return &TSInfo;
247  }
248  const AArch64FrameLowering *getFrameLowering() const override {
249  return &FrameLowering;
250  }
251  const AArch64TargetLowering *getTargetLowering() const override {
252  return &TLInfo;
253  }
254  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
255  const AArch64RegisterInfo *getRegisterInfo() const override {
256  return &getInstrInfo()->getRegisterInfo();
257  }
258  const CallLowering *getCallLowering() const override;
260  const LegalizerInfo *getLegalizerInfo() const override;
261  const RegisterBankInfo *getRegBankInfo() const override;
262  const Triple &getTargetTriple() const { return TargetTriple; }
263  bool enableMachineScheduler() const override { return true; }
264  bool enablePostRAScheduler() const override {
265  return UsePostRAScheduler;
266  }
267 
268  /// Returns ARM processor family.
269  /// Avoid this function! CPU specifics should be kept local to this class
270  /// and preferably modeled with SubtargetFeatures or properties in
271  /// initializeProperties().
273  return ARMProcFamily;
274  }
275 
276  bool hasV8_1aOps() const { return HasV8_1aOps; }
277  bool hasV8_2aOps() const { return HasV8_2aOps; }
278  bool hasV8_3aOps() const { return HasV8_3aOps; }
279  bool hasV8_4aOps() const { return HasV8_4aOps; }
280  bool hasV8_5aOps() const { return HasV8_5aOps; }
281 
282  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
283 
285 
287 
290  }
291 
292  bool requiresStrictAlign() const { return StrictAlign; }
293 
294  bool isXRaySupported() const override { return true; }
295 
296  unsigned getMinVectorRegisterBitWidth() const {
298  }
299 
300  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
301  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
302  bool isXRegCustomCalleeSaved(size_t i) const {
303  return CustomCallSavedXRegs[i];
304  }
305  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
306  bool hasFPARMv8() const { return HasFPARMv8; }
307  bool hasNEON() const { return HasNEON; }
308  bool hasCrypto() const { return HasCrypto; }
309  bool hasDotProd() const { return HasDotProd; }
310  bool hasCRC() const { return HasCRC; }
311  bool hasLSE() const { return HasLSE; }
312  bool hasRAS() const { return HasRAS; }
313  bool hasRDM() const { return HasRDM; }
314  bool hasSM4() const { return HasSM4; }
315  bool hasSHA3() const { return HasSHA3; }
316  bool hasSHA2() const { return HasSHA2; }
317  bool hasAES() const { return HasAES; }
318  bool balanceFPOps() const { return BalanceFPOps; }
321  }
325  bool isPaired128Slow() const { return Paired128IsSlow; }
326  bool isSTRQroSlow() const { return STRQroIsSlow; }
329  }
332  bool hasFuseAddress() const { return HasFuseAddress; }
333  bool hasFuseAES() const { return HasFuseAES; }
335  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
336  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
337  bool hasFuseLiterals() const { return HasFuseLiterals; }
338 
339  /// Return true if the CPU supports any kind of instruction fusion.
340  bool hasFusion() const {
344  }
345 
346  bool useEL1ForTP() const { return UseEL1ForTP; }
347  bool useEL2ForTP() const { return UseEL2ForTP; }
348  bool useEL3ForTP() const { return UseEL3ForTP; }
349 
350  bool useRSqrt() const { return UseRSqrt; }
352  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
355  }
356  unsigned getCacheLineSize() const { return CacheLineSize; }
357  unsigned getPrefetchDistance() const { return PrefetchDistance; }
358  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
359  unsigned getMaxPrefetchIterationsAhead() const {
361  }
362  unsigned getPrefFunctionLogAlignment() const {
364  }
365  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
366 
367  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
368 
369  unsigned getWideningBaseCost() const { return WideningBaseCost; }
370 
371  /// CPU has TBI (top byte of addresses is ignored during HW address
372  /// translation) and OS enables it.
373  bool supportsAddressTopByteIgnored() const;
374 
375  bool hasPerfMon() const { return HasPerfMon; }
376  bool hasFullFP16() const { return HasFullFP16; }
377  bool hasFP16FML() const { return HasFP16FML; }
378  bool hasSPE() const { return HasSPE; }
379  bool hasLSLFast() const { return HasLSLFast; }
380  bool hasSVE() const { return HasSVE; }
381  bool hasSVE2() const { return HasSVE2; }
382  bool hasRCPC() const { return HasRCPC; }
383  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
384  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
385  bool hasFRInt3264() const { return HasFRInt3264; }
386  bool hasSpecRestrict() const { return HasSpecRestrict; }
387  bool hasSSBS() const { return HasSSBS; }
388  bool hasSB() const { return HasSB; }
389  bool hasPredRes() const { return HasPredRes; }
390  bool hasCCDP() const { return HasCCDP; }
391  bool hasBTI() const { return HasBTI; }
392  bool hasRandGen() const { return HasRandGen; }
393  bool hasMTE() const { return HasMTE; }
394  bool hasTME() const { return HasTME; }
395  // Arm SVE2 extensions
396  bool hasSVE2AES() const { return HasSVE2AES; }
397  bool hasSVE2SM4() const { return HasSVE2SM4; }
398  bool hasSVE2SHA3() const { return HasSVE2SHA3; }
399  bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
400 
401  bool isLittleEndian() const { return IsLittle; }
402 
403  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
404  bool isTargetIOS() const { return TargetTriple.isiOS(); }
405  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
406  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
407  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
408  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
409 
410  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
411  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
412  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
413 
414  bool isTargetILP32() const { return TargetTriple.isArch32Bit(); }
415 
416  bool useAA() const override { return UseAA; }
417 
418  bool hasVH() const { return HasVH; }
419  bool hasPAN() const { return HasPAN; }
420  bool hasLOR() const { return HasLOR; }
421 
422  bool hasPsUAO() const { return HasPsUAO; }
423  bool hasPAN_RWV() const { return HasPAN_RWV; }
424  bool hasCCPP() const { return HasCCPP; }
425 
426  bool hasPA() const { return HasPA; }
427  bool hasJS() const { return HasJS; }
428  bool hasCCIDX() const { return HasCCIDX; }
429  bool hasComplxNum() const { return HasComplxNum; }
430 
431  bool hasNV() const { return HasNV; }
432  bool hasRASv8_4() const { return HasRASv8_4; }
433  bool hasMPAM() const { return HasMPAM; }
434  bool hasDIT() const { return HasDIT; }
435  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
436  bool hasAM() const { return HasAM; }
437  bool hasSEL2() const { return HasSEL2; }
438  bool hasTLB_RMI() const { return HasTLB_RMI; }
439  bool hasFMI() const { return HasFMI; }
440  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
441 
442  bool addrSinkUsingGEPs() const override {
443  // Keeping GEPs inbounds is important for exploiting AArch64
444  // addressing-modes in ILP32 mode.
445  return useAA() || isTargetILP32();
446  }
447 
448  bool useSmallAddressing() const {
449  switch (TLInfo.getTargetMachine().getCodeModel()) {
450  case CodeModel::Kernel:
451  // Kernel is currently allowed only for Fuchsia targets,
452  // where it is the same as Small for almost all purposes.
453  case CodeModel::Small:
454  return true;
455  default:
456  return false;
457  }
458  }
459 
460  /// ParseSubtargetFeatures - Parses features string setting specified
461  /// subtarget options. Definition of function is auto generated by tblgen.
463 
464  /// ClassifyGlobalReference - Find the target operand flags that describe
465  /// how a global value should be referenced for the current subtarget.
466  unsigned ClassifyGlobalReference(const GlobalValue *GV,
467  const TargetMachine &TM) const;
468 
469  unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
470  const TargetMachine &TM) const;
471 
473  unsigned NumRegionInstrs) const override;
474 
475  bool enableEarlyIfConversion() const override;
476 
477  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
478 
480  switch (CC) {
481  case CallingConv::C:
482  case CallingConv::Fast:
483  case CallingConv::Swift:
484  return isTargetWindows();
485  case CallingConv::Win64:
486  return true;
487  default:
488  return false;
489  }
490  }
491 
492  void mirFileLoaded(MachineFunction &MF) const override;
493 };
494 } // End llvm namespace
495 
496 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
bool hasAlternativeNZCV() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
bool isMisaligned128StoreSlow() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
bool predictableSelectIsExpensive() const
InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:505
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool hasFuseArithmeticLogic() const
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
bool force32BitJumpTables() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1296
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
unsigned getPrefFunctionLogAlignment() const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
const AArch64TargetLowering * getTargetLowering() const override
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
unsigned getPrefLoopLogAlignment() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
bool hasExynosCheapAsMoveHandling() const
bool addrSinkUsingGEPs() const override
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:180
bool useSmallAddressing() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:153
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
bool hasZeroCycleZeroingGP() const
unsigned getMaxPrefetchIterationsAhead() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AArch64TargetLowering TLInfo
unsigned getVectorInsertExtractBaseCost() const