LLVM  15.0.0git
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
85  };
86 
87 protected:
88  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
90 
91  // Enable 64-bit vectorization in SLP.
93 
94 // Bool members corresponding to the SubtargetFeatures defined in tablegen
95 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
96  bool ATTRIBUTE = DEFAULT;
97 #include "AArch64GenSubtargetInfo.inc"
98 
99  uint8_t MaxInterleaveFactor = 2;
104  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
106  unsigned PrefLoopLogAlignment = 0;
108  unsigned MaxJumpTableSize = 0;
109 
110  // ReserveXRegister[i] - X#i is not available as a general purpose register.
112 
113  // CustomCallUsedXRegister[i] - X#i call saved.
115 
116  bool IsLittle;
117 
120  unsigned VScaleForTuning = 2;
121 
122  /// TargetTriple - What processor and OS we're targeting.
124 
129 
130  /// GlobalISel related APIs.
131  std::unique_ptr<CallLowering> CallLoweringInfo;
132  std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
133  std::unique_ptr<InstructionSelector> InstSelector;
134  std::unique_ptr<LegalizerInfo> Legalizer;
135  std::unique_ptr<RegisterBankInfo> RegBankInfo;
136 
137 private:
138  /// initializeSubtargetDependencies - Initializes using CPUString and the
139  /// passed in feature string so that we can use initializer lists for
140  /// subtarget initialization.
141  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
142  StringRef CPUString,
143  StringRef TuneCPUString);
144 
145  /// Initialize properties based on the selected processor family.
146  void initializeProperties();
147 
148 public:
149  /// This constructor initializes the data members to match that
150  /// of the specified triple.
151  AArch64Subtarget(const Triple &TT, const std::string &CPU,
152  const std::string &TuneCPU, const std::string &FS,
153  const TargetMachine &TM, bool LittleEndian,
154  unsigned MinSVEVectorSizeInBitsOverride = 0,
155  unsigned MaxSVEVectorSizeInBitsOverride = 0);
156 
157 // Getters for SubtargetFeatures defined in tablegen
158 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
159  bool GETTER() const { return ATTRIBUTE; }
160 #include "AArch64GenSubtargetInfo.inc"
161 
163  return &TSInfo;
164  }
165  const AArch64FrameLowering *getFrameLowering() const override {
166  return &FrameLowering;
167  }
168  const AArch64TargetLowering *getTargetLowering() const override {
169  return &TLInfo;
170  }
171  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
172  const AArch64RegisterInfo *getRegisterInfo() const override {
173  return &getInstrInfo()->getRegisterInfo();
174  }
175  const CallLowering *getCallLowering() const override;
176  const InlineAsmLowering *getInlineAsmLowering() const override;
178  const LegalizerInfo *getLegalizerInfo() const override;
179  const RegisterBankInfo *getRegBankInfo() const override;
180  const Triple &getTargetTriple() const { return TargetTriple; }
181  bool enableMachineScheduler() const override { return true; }
182  bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
183 
184  /// Returns ARM processor family.
185  /// Avoid this function! CPU specifics should be kept local to this class
186  /// and preferably modeled with SubtargetFeatures or properties in
187  /// initializeProperties().
189  return ARMProcFamily;
190  }
191 
192  bool isXRaySupported() const override { return true; }
193 
194  unsigned getMinVectorRegisterBitWidth() const {
196  }
197 
198  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
199  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
200  bool isXRegCustomCalleeSaved(size_t i) const {
201  return CustomCallSavedXRegs[i];
202  }
203  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
204 
205  /// Return true if the CPU supports any kind of instruction fusion.
206  bool hasFusion() const {
207  return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
208  hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
209  hasFuseAdrpAdd() || hasFuseLiterals();
210  }
211 
212  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
213  unsigned getVectorInsertExtractBaseCost() const;
214  unsigned getCacheLineSize() const override { return CacheLineSize; }
215  unsigned getPrefetchDistance() const override { return PrefetchDistance; }
216  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
217  unsigned NumStridedMemAccesses,
218  unsigned NumPrefetches,
219  bool HasCall) const override {
220  return MinPrefetchStride;
221  }
222  unsigned getMaxPrefetchIterationsAhead() const override {
224  }
225  unsigned getPrefFunctionLogAlignment() const {
227  }
228  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
229 
230  unsigned getMaxBytesForLoopAlignment() const {
232  }
233 
234  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
235 
236  /// CPU has TBI (top byte of addresses is ignored during HW address
237  /// translation) and OS enables it.
238  bool supportsAddressTopByteIgnored() const;
239 
240  bool isLittleEndian() const { return IsLittle; }
241 
242  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
243  bool isTargetIOS() const { return TargetTriple.isiOS(); }
244  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
245  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
246  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
247  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
248 
249  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
250  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
251  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
252 
253  bool isTargetILP32() const {
254  return TargetTriple.isArch32Bit() ||
256  }
257 
258  bool useAA() const override;
259 
260  bool addrSinkUsingGEPs() const override {
261  // Keeping GEPs inbounds is important for exploiting AArch64
262  // addressing-modes in ILP32 mode.
263  return useAA() || isTargetILP32();
264  }
265 
266  bool useSmallAddressing() const {
267  switch (TLInfo.getTargetMachine().getCodeModel()) {
268  case CodeModel::Kernel:
269  // Kernel is currently allowed only for Fuchsia targets,
270  // where it is the same as Small for almost all purposes.
271  case CodeModel::Small:
272  return true;
273  default:
274  return false;
275  }
276  }
277 
278  /// ParseSubtargetFeatures - Parses features string setting specified
279  /// subtarget options. Definition of function is auto generated by tblgen.
281 
282  /// ClassifyGlobalReference - Find the target operand flags that describe
283  /// how a global value should be referenced for the current subtarget.
284  unsigned ClassifyGlobalReference(const GlobalValue *GV,
285  const TargetMachine &TM) const;
286 
287  unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
288  const TargetMachine &TM) const;
289 
291  unsigned NumRegionInstrs) const override;
292 
293  bool enableEarlyIfConversion() const override;
294 
295  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
296 
298  switch (CC) {
299  case CallingConv::C:
300  case CallingConv::Fast:
301  case CallingConv::Swift:
302  return isTargetWindows();
303  case CallingConv::Win64:
304  return true;
305  default:
306  return false;
307  }
308  }
309 
310  /// Return whether FrameLowering should always set the "extended frame
311  /// present" bit in FP, or set it based on a symbol in the runtime.
313  // Older OS versions (particularly system unwinders) are confused by the
314  // Swift extended frame, so when building code that might be run on them we
315  // must dynamically query the concurrency library to determine whether
316  // extended frames should be flagged as present.
317  const Triple &TT = getTargetTriple();
318 
319  unsigned Major = TT.getOSVersion().getMajor();
320  switch(TT.getOS()) {
321  default:
322  return false;
323  case Triple::IOS:
324  case Triple::TvOS:
325  return Major < 15;
326  case Triple::WatchOS:
327  return Major < 8;
328  case Triple::MacOSX:
329  case Triple::Darwin:
330  return Major < 12;
331  }
332  }
333 
334  void mirFileLoaded(MachineFunction &MF) const override;
335 
336  // Return the known range for the bit length of SVE data registers. A value
337  // of 0 means nothing is known about that particular limit beyong what's
338  // implied by the architecture.
339  unsigned getMaxSVEVectorSizeInBits() const {
340  assert(HasSVE && "Tried to get SVE vector length without SVE support!");
341  return MaxSVEVectorSizeInBits;
342  }
343 
344  unsigned getMinSVEVectorSizeInBits() const {
345  assert(HasSVE && "Tried to get SVE vector length without SVE support!");
346  return MinSVEVectorSizeInBits;
347  }
348 
350  // Prefer NEON unless larger SVE registers are available.
351  return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
352  }
353 
354  unsigned getVScaleForTuning() const { return VScaleForTuning; }
355 };
356 } // End llvm namespace
357 
358 #endif
i
i
Definition: README.txt:29
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:52
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:46
llvm::AArch64Subtarget::isTargetWindows
bool isTargetWindows() const
Definition: AArch64Subtarget.h:245
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
AArch64RegisterInfo.h
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:384
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AArch64Subtarget::getVectorInsertExtractBaseCost
unsigned getVectorInsertExtractBaseCost() const
Definition: AArch64Subtarget.cpp:59
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:89
llvm::AArch64Subtarget::swiftAsyncContextIsDynamicallySet
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: AArch64Subtarget.h:312
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:78
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:233
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:108
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:55
CallLowering.h
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::isTargetIOS
bool isTargetIOS() const
Definition: AArch64Subtarget.h:243
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:80
llvm::AArch64Subtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: AArch64Subtarget.h:249
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:83
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:661
llvm::AArch64Subtarget::CortexX1C
@ CortexX1C
Definition: AArch64Subtarget.h:67
llvm::AArch64Subtarget::getPrefFunctionLogAlignment
unsigned getPrefFunctionLogAlignment() const
Definition: AArch64Subtarget.h:225
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:61
llvm::Triple::Darwin
@ Darwin
Definition: Triple.h:186
llvm::AArch64Subtarget::getMinSVEVectorSizeInBits
unsigned getMinSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:344
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:135
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:57
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:131
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:74
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:260
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:60
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:99
RegisterBankInfo.h
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:133
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:242
llvm::AArch64Subtarget::isTargetELF
bool isTargetELF() const
Definition: AArch64Subtarget.h:250
llvm::Triple::IOS
@ IOS
Definition: Triple.h:190
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AArch64Subtarget::TLInfo
AArch64TargetLowering TLInfo
Definition: AArch64Subtarget.h:128
llvm::AArch64Subtarget::getInstrInfo
const AArch64InstrInfo * getInstrInfo() const override
Definition: AArch64Subtarget.h:171
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:103
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:100
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:619
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:50
llvm::AArch64Subtarget::isXRegCustomCalleeSaved
bool isXRegCustomCalleeSaved(size_t i) const
Definition: AArch64Subtarget.h:200
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:79
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:84
llvm::AArch64Subtarget::CortexX2
@ CortexX2
Definition: AArch64Subtarget.h:68
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:47
llvm::AArch64Subtarget::MaxBytesForLoopAlignment
unsigned MaxBytesForLoopAlignment
Definition: AArch64Subtarget.h:107
AArch64SelectionDAGInfo.h
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::AArch64Subtarget::getPrefetchDistance
unsigned getPrefetchDistance() const override
Definition: AArch64Subtarget.h:215
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:106
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:62
LegalizerInfo.h
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:73
llvm::Triple::WatchOS
@ WatchOS
Definition: Triple.h:212
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:168
llvm::AArch64Subtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
Definition: AArch64Subtarget.h:182
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:76
llvm::AArch64Subtarget::addrSinkUsingGEPs
bool addrSinkUsingGEPs() const override
Definition: AArch64Subtarget.h:260
llvm::AArch64FrameLowering
Definition: AArch64FrameLowering.h:23
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:398
llvm::AArch64Subtarget::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AArch64Subtarget.h:194
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:701
llvm::AArch64SelectionDAGInfo
Definition: AArch64SelectionDAGInfo.h:20
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:656
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:296
AArch64InstrInfo.h
llvm::AArch64Subtarget::MinSVEVectorSizeInBits
unsigned MinSVEVectorSizeInBits
Definition: AArch64Subtarget.h:118
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:300
InlineAsmLowering.h
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:37
llvm::Triple::TvOS
@ TvOS
Definition: Triple.h:211
llvm::AArch64Subtarget::isLittleEndian
bool isLittleEndian() const
Definition: AArch64Subtarget.h:240
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:508
llvm::AArch64Subtarget::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Definition: AArch64Subtarget.h:234
llvm::AArch64Subtarget::isTargetILP32
bool isTargetILP32() const
Definition: AArch64Subtarget.h:253
llvm::BitVector::count
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:155
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:101
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:380
llvm::AArch64Subtarget::Neoverse512TVB
@ Neoverse512TVB
Definition: AArch64Subtarget.h:75
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:402
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:669
AArch64GenSubtargetInfo
llvm::AArch64Subtarget::isXRaySupported
bool isXRaySupported() const override
Definition: AArch64Subtarget.h:192
llvm::AArch64Subtarget::VScaleForTuning
unsigned VScaleForTuning
Definition: AArch64Subtarget.h:120
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:63
llvm::BitVector
Definition: BitVector.h:75
llvm::AArch64Subtarget::getProcFamily
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
Definition: AArch64Subtarget.h:188
llvm::AArch64Subtarget::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: AArch64Subtarget.h:214
llvm::AArch64Subtarget::IsLittle
bool IsLittle
Definition: AArch64Subtarget.h:116
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:105
llvm::Triple::isOSFuchsia
bool isOSFuchsia() const
Definition: Triple.h:538
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:66
llvm::AArch64Subtarget::MaxSVEVectorSizeInBits
unsigned MaxSVEVectorSizeInBits
Definition: AArch64Subtarget.h:119
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:82
InstructionSelector.h
llvm::AArch64Subtarget::getSelectionDAGInfo
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: AArch64Subtarget.h:162
llvm::Triple::MacOSX
@ MacOSX
Definition: Triple.h:194
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:292
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:111
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:59
AArch64FrameLowering.h
llvm::AArch64Subtarget::useSVEForFixedLengthVectors
bool useSVEForFixedLengthVectors() const
Definition: AArch64Subtarget.h:349
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:163
llvm::AArch64Subtarget::Ampere1
@ Ampere1
Definition: AArch64Subtarget.h:43
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:266
llvm::Triple::isArch32Bit
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1448
llvm::AArch64Subtarget::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
Definition: AArch64Subtarget.h:216
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:49
llvm::AArch64Subtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: AArch64Subtarget.h:181
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:72
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::AArch64Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: AArch64Subtarget.h:244
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:92
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:297
llvm::AArch64Subtarget::TSInfo
AArch64SelectionDAGInfo TSInfo
Definition: AArch64Subtarget.h:127
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::AArch64Subtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: AArch64Subtarget.h:212
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: AArch64Subtarget.cpp:347
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:203
llvm::AArch64Subtarget::CortexA710
@ CortexA710
Definition: AArch64Subtarget.h:64
llvm::AArch64Subtarget::isXRegisterReserved
bool isXRegisterReserved(size_t i) const
Definition: AArch64Subtarget.h:198
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AArch64Subtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: AArch64Subtarget.h:134
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:180
llvm::AArch64Subtarget::getFrameLowering
const AArch64FrameLowering * getFrameLowering() const override
Definition: AArch64Subtarget.h:165
TargetSubtargetInfo.h
llvm::AArch64Subtarget::getVScaleForTuning
unsigned getVScaleForTuning() const
Definition: AArch64Subtarget.h:354
llvm::AArch64Subtarget::getMaxBytesForLoopAlignment
unsigned getMaxBytesForLoopAlignment() const
Definition: AArch64Subtarget.h:230
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:484
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:44
AArch64ISelLowering.h
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:81
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:51
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:571
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:53
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:172
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:47
llvm::AArch64Subtarget::getNumXRegisterReserved
unsigned getNumXRegisterReserved() const
Definition: AArch64Subtarget.h:199
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:169
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:308
llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits
unsigned getMaxSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:339
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:69
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:315
uint16_t
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:132
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:72
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:102
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:104
llvm::AArch64Subtarget::isTargetFuchsia
bool isTargetFuchsia() const
Definition: AArch64Subtarget.h:247
llvm::AArch64Subtarget::InstrInfo
AArch64InstrInfo InstrInfo
Definition: AArch64Subtarget.h:126
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:251
llvm::AArch64Subtarget::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const override
Definition: AArch64Subtarget.h:222
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:58
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:77
llvm::AArch64Subtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: AArch64Subtarget.h:228
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:123
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:362
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:304
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::CortexA510
@ CortexA510
Definition: AArch64Subtarget.h:54
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:65
llvm::AArch64Subtarget::CustomCallSavedXRegs
BitVector CustomCallSavedXRegs
Definition: AArch64Subtarget.h:114
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:179
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:480
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:412
llvm::CallLowering
Definition: CallLowering.h:44
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:70
llvm::AArch64Subtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: AArch64Subtarget.h:206
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:368
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:45
llvm::AArch64Subtarget::FrameLowering
AArch64FrameLowering FrameLowering
Definition: AArch64Subtarget.h:125
llvm::AArch64Subtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: AArch64Subtarget.h:246
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:48
llvm::AArch64Subtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: AArch64Subtarget.h:40
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:56