LLVM 19.0.0git
AArch64Subtarget.h
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1//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15
17#include "AArch64ISelLowering.h"
18#include "AArch64InstrInfo.h"
19#include "AArch64PointerAuth.h"
20#include "AArch64RegisterInfo.h"
28#include "llvm/IR/DataLayout.h"
29
30#define GET_SUBTARGETINFO_HEADER
31#include "AArch64GenSubtargetInfo.inc"
32
33namespace llvm {
34class GlobalValue;
35class StringRef;
36class Triple;
37
39public:
40 enum ARMProcFamilyEnum : uint8_t {
95 TSV110
96 };
97
98protected:
99 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
101
102 // Enable 64-bit vectorization in SLP.
104
105// Bool members corresponding to the SubtargetFeatures defined in tablegen
106#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
107 bool ATTRIBUTE = DEFAULT;
108#include "AArch64GenSubtargetInfo.inc"
109
115 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
120 unsigned MaxJumpTableSize = 0;
121
122 // ReserveXRegister[i] - X#i is not available as a general purpose register.
124
125 // ReserveXRegisterForRA[i] - X#i is not available for register allocator.
127
128 // CustomCallUsedXRegister[i] - X#i call saved.
130
132
137 unsigned VScaleForTuning = 2;
139
140 /// TargetTriple - What processor and OS we're targeting.
142
147
148 /// GlobalISel related APIs.
149 std::unique_ptr<CallLowering> CallLoweringInfo;
150 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
151 std::unique_ptr<InstructionSelector> InstSelector;
152 std::unique_ptr<LegalizerInfo> Legalizer;
153 std::unique_ptr<RegisterBankInfo> RegBankInfo;
154
155private:
156 /// initializeSubtargetDependencies - Initializes using CPUString and the
157 /// passed in feature string so that we can use initializer lists for
158 /// subtarget initialization.
159 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
160 StringRef CPUString,
161 StringRef TuneCPUString,
162 bool HasMinSize);
163
164 /// Initialize properties based on the selected processor family.
165 void initializeProperties(bool HasMinSize);
166
167public:
168 /// This constructor initializes the data members to match that
169 /// of the specified triple.
170 AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
171 StringRef FS, const TargetMachine &TM, bool LittleEndian,
172 unsigned MinSVEVectorSizeInBitsOverride = 0,
173 unsigned MaxSVEVectorSizeInBitsOverride = 0,
174 bool StreamingSVEMode = false,
175 bool StreamingCompatibleSVEMode = false,
176 bool HasMinSize = false);
177
178// Getters for SubtargetFeatures defined in tablegen
179#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
180 bool GETTER() const { return ATTRIBUTE; }
181#include "AArch64GenSubtargetInfo.inc"
182
184 return &TSInfo;
185 }
186 const AArch64FrameLowering *getFrameLowering() const override {
187 return &FrameLowering;
188 }
189 const AArch64TargetLowering *getTargetLowering() const override {
190 return &TLInfo;
191 }
192 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
193 const AArch64RegisterInfo *getRegisterInfo() const override {
194 return &getInstrInfo()->getRegisterInfo();
195 }
196 const CallLowering *getCallLowering() const override;
197 const InlineAsmLowering *getInlineAsmLowering() const override;
199 const LegalizerInfo *getLegalizerInfo() const override;
200 const RegisterBankInfo *getRegBankInfo() const override;
201 const Triple &getTargetTriple() const { return TargetTriple; }
202 bool enableMachineScheduler() const override { return true; }
203 bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
204
205 bool enableMachinePipeliner() const override;
206 bool useDFAforSMS() const override { return false; }
207
208 /// Returns ARM processor family.
209 /// Avoid this function! CPU specifics should be kept local to this class
210 /// and preferably modeled with SubtargetFeatures or properties in
211 /// initializeProperties().
213 return ARMProcFamily;
214 }
215
216 bool isXRaySupported() const override { return true; }
217
218 /// Returns true if the function has a streaming body.
219 bool isStreaming() const { return StreamingSVEMode; }
220
221 /// Returns true if the function has a streaming-compatible body.
222 bool isStreamingCompatible() const;
223
224 /// Returns true if the target has NEON and the function at runtime is known
225 /// to have NEON enabled (e.g. the function is known not to be in streaming-SVE
226 /// mode, which disables NEON instructions).
227 bool isNeonAvailable() const;
228
229 /// Returns true if the target has SVE and can use the full range of SVE
230 /// instructions, for example because it knows the function is known not to be
231 /// in streaming-SVE mode or when the target has FEAT_FA64 enabled.
232 bool isSVEAvailable() const;
233
235 // Don't assume any minimum vector size when PSTATE.SM may not be 0, because
236 // we don't yet support streaming-compatible codegen support that we trust
237 // is safe for functions that may be executed in streaming-SVE mode.
238 // By returning '0' here, we disable vectorization.
239 if (!isSVEAvailable() && !isNeonAvailable())
240 return 0;
242 }
243
244 bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
245 bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
246 unsigned getNumXRegisterReserved() const {
247 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
248 AllReservedX |= ReserveXRegister;
249 AllReservedX |= ReserveXRegisterForRA;
250 return AllReservedX.count();
251 }
252 bool isXRegCustomCalleeSaved(size_t i) const {
253 return CustomCallSavedXRegs[i];
254 }
256
257 /// Return true if the CPU supports any kind of instruction fusion.
258 bool hasFusion() const {
259 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
260 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
261 hasFuseAdrpAdd() || hasFuseLiterals();
262 }
263
264 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
265 unsigned getVectorInsertExtractBaseCost() const;
266 unsigned getCacheLineSize() const override { return CacheLineSize; }
267 unsigned getPrefetchDistance() const override { return PrefetchDistance; }
268 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
269 unsigned NumStridedMemAccesses,
270 unsigned NumPrefetches,
271 bool HasCall) const override {
272 return MinPrefetchStride;
273 }
274 unsigned getMaxPrefetchIterationsAhead() const override {
276 }
279 }
281
284 }
285
286 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
287 unsigned getMinimumJumpTableEntries() const {
289 }
290
291 /// CPU has TBI (top byte of addresses is ignored during HW address
292 /// translation) and OS enables it.
294
295 bool isLittleEndian() const { return IsLittle; }
296
297 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
298 bool isTargetIOS() const { return TargetTriple.isiOS(); }
299 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
300 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
301 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
302 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
304
305 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
306 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
308
309 bool isTargetILP32() const {
310 return TargetTriple.isArch32Bit() ||
312 }
313
314 bool useAA() const override;
315
316 bool addrSinkUsingGEPs() const override {
317 // Keeping GEPs inbounds is important for exploiting AArch64
318 // addressing-modes in ILP32 mode.
319 return useAA() || isTargetILP32();
320 }
321
322 bool useSmallAddressing() const {
325 // Kernel is currently allowed only for Fuchsia targets,
326 // where it is the same as Small for almost all purposes.
327 case CodeModel::Small:
328 return true;
329 default:
330 return false;
331 }
332 }
333
334 /// ParseSubtargetFeatures - Parses features string setting specified
335 /// subtarget options. Definition of function is auto generated by tblgen.
337
338 /// ClassifyGlobalReference - Find the target operand flags that describe
339 /// how a global value should be referenced for the current subtarget.
340 unsigned ClassifyGlobalReference(const GlobalValue *GV,
341 const TargetMachine &TM) const;
342
344 const TargetMachine &TM) const;
345
346 /// This function is design to compatible with the function def in other
347 /// targets and escape build error about the virtual function def in base
348 /// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
349 unsigned char
351 return 0;
352 }
353
355 unsigned NumRegionInstrs) const override;
356
357 bool enableEarlyIfConversion() const override;
358
359 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
360
362 switch (CC) {
363 case CallingConv::C:
367 return isTargetWindows();
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 /// Return whether FrameLowering should always set the "extended frame
376 /// present" bit in FP, or set it based on a symbol in the runtime.
378 // Older OS versions (particularly system unwinders) are confused by the
379 // Swift extended frame, so when building code that might be run on them we
380 // must dynamically query the concurrency library to determine whether
381 // extended frames should be flagged as present.
382 const Triple &TT = getTargetTriple();
383
384 unsigned Major = TT.getOSVersion().getMajor();
385 switch(TT.getOS()) {
386 default:
387 return false;
388 case Triple::IOS:
389 case Triple::TvOS:
390 return Major < 15;
391 case Triple::WatchOS:
392 return Major < 8;
393 case Triple::MacOSX:
394 case Triple::Darwin:
395 return Major < 12;
396 }
397 }
398
399 void mirFileLoaded(MachineFunction &MF) const override;
400
401 bool hasSVEorSME() const { return hasSVE() || hasSME(); }
402 bool hasSVE2orSME() const { return hasSVE2() || hasSME(); }
403
404 // Return the known range for the bit length of SVE data registers. A value
405 // of 0 means nothing is known about that particular limit beyong what's
406 // implied by the architecture.
407 unsigned getMaxSVEVectorSizeInBits() const {
409 "Tried to get SVE vector length without SVE support!");
411 }
412
413 unsigned getMinSVEVectorSizeInBits() const {
415 "Tried to get SVE vector length without SVE support!");
417 }
418
420 if (!isNeonAvailable())
421 return hasSVEorSME();
422
423 // Prefer NEON unless larger SVE registers are available.
424 return hasSVEorSME() && getMinSVEVectorSizeInBits() >= 256;
425 }
426
429 return false;
432 }
433
434 unsigned getVScaleForTuning() const { return VScaleForTuning; }
435
437 return DefaultSVETFOpts;
438 }
439
440 const char* getChkStkName() const {
441 if (isWindowsArm64EC())
442 return "#__chkstk_arm64ec";
443 return "__chkstk";
444 }
445
446 const char* getSecurityCheckCookieName() const {
447 if (isWindowsArm64EC())
448 return "#__security_check_cookie_arm64ec";
449 return "__security_check_cookie";
450 }
451
452 /// Choose a method of checking LR before performing a tail call.
454
456 return AddressCheckPSV.get();
457 }
458
459private:
460 /// Pseudo value representing memory load performed to check an address.
461 ///
462 /// This load operation is solely used for its side-effects: if the address
463 /// is not mapped (or not readable), it triggers CPU exception, otherwise
464 /// execution proceeds and the value is not used.
465 class AddressCheckPseudoSourceValue : public PseudoSourceValue {
466 public:
467 AddressCheckPseudoSourceValue(const TargetMachine &TM)
469
470 bool isConstant(const MachineFrameInfo *) const override { return false; }
471 bool isAliased(const MachineFrameInfo *) const override { return true; }
472 bool mayAlias(const MachineFrameInfo *) const override { return true; }
473 void printCustom(raw_ostream &OS) const override { OS << "AddressCheck"; }
474 };
475
476 std::unique_ptr<AddressCheckPseudoSourceValue> AddressCheckPSV;
477};
478} // End llvm namespace
479
480#endif
This file describes how to lower LLVM calls to machine code calls.
This file describes how to lower LLVM inline asm to machine code INLINEASM.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
const CallLowering * getCallLowering() const override
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
bool addrSinkUsingGEPs() const override
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned getMinimumJumpTableEntries() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSVEForFixedLengthVectors(EVT VT) const
const AArch64InstrInfo * getInstrInfo() const override
bool useSmallAddressing() const
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
AArch64SelectionDAGInfo TSInfo
const char * getSecurityCheckCookieName() const
unsigned getMaximumJumpTableSize() const
bool isStreamingCompatible() const
Returns true if the function has a streaming-compatible body.
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
AArch64FrameLowering FrameLowering
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getCacheLineSize() const override
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
Align getPrefLoopAlignment() const
Align getPrefFunctionAlignment() const
unsigned getMaxBytesForLoopAlignment() const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
unsigned getMaxInterleaveFactor() const
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override
This function is design to compatible with the function def in other targets and escape build error a...
const Triple & getTargetTriple() const
const PseudoSourceValue * getAddressCheckPSV() const
bool isCallingConvWin64(CallingConv::ID CC) const
const char * getChkStkName() const
bool isXRegCustomCalleeSaved(size_t i) const
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
TailFoldingOpts getSVETailFoldingDefaultOpts() const
bool useSVEForFixedLengthVectors() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getMinVectorRegisterBitWidth() const
bool isStreaming() const
Returns true if the function has a streaming body.
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const
Choose a method of checking LR before performing a tail call.
bool isSVEAvailable() const
Returns true if the target has SVE and can use the full range of SVE instructions,...
bool isXRegisterReserved(size_t i) const
unsigned getMaxPrefetchIterationsAhead() const override
bool useDFAforSMS() const override
const LegalizerInfo * getLegalizerInfo() const override
bool enableMachineScheduler() const override
bool enablePostRAScheduler() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
unsigned getMaxSVEVectorSizeInBits() const
unsigned getVScaleForTuning() const
unsigned getMinSVEVectorSizeInBits() const
AArch64InstrInfo InstrInfo
AArch64TargetLowering TLInfo
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
bool isXRaySupported() const override
bool hasCustomCallingConv() const
const AArch64FrameLowering * getFrameLowering() const override
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
unsigned getPrefetchDistance() const override
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:162
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:170
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
const TargetMachine & getTargetMachine() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:753
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:716
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:708
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:378
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:608
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:662
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:542
bool isWindowsArm64EC() const
Definition: Triple.h:624
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:515
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1542
bool isOSFuchsia() const
Definition: Triple.h:572
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:703
AuthCheckMethod
Variants of check performed on an authenticated pointer.
static constexpr unsigned SVEBitsPerBlock
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:159
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: ValueTypes.h:359
bool isFixedLengthVector() const
Definition: ValueTypes.h:170
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.