LLVM 19.0.0git
AArch64Subtarget.h
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1//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15
17#include "AArch64ISelLowering.h"
18#include "AArch64InstrInfo.h"
19#include "AArch64PointerAuth.h"
20#include "AArch64RegisterInfo.h"
28#include "llvm/IR/DataLayout.h"
29
30#define GET_SUBTARGETINFO_HEADER
31#include "AArch64GenSubtargetInfo.inc"
32
33namespace llvm {
34class GlobalValue;
35class StringRef;
36class Triple;
37
39public:
40 enum ARMProcFamilyEnum : uint8_t {
42#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
43#include "llvm/TargetParser/AArch64TargetParserDef.inc"
44#undef ARM_PROCESSOR_FAMILY
45 };
46
47protected:
48 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
50
51 // Enable 64-bit vectorization in SLP.
53
54// Bool members corresponding to the SubtargetFeatures defined in tablegen
55#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
56 bool ATTRIBUTE = DEFAULT;
57#include "AArch64GenSubtargetInfo.inc"
58
64 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
69 unsigned MaxJumpTableSize = 0;
70
71 // ReserveXRegister[i] - X#i is not available as a general purpose register.
73
74 // ReserveXRegisterForRA[i] - X#i is not available for register allocator.
76
77 // CustomCallUsedXRegister[i] - X#i call saved.
79
81
86 unsigned VScaleForTuning = 2;
88
89 /// TargetTriple - What processor and OS we're targeting.
91
96
97 /// GlobalISel related APIs.
98 std::unique_ptr<CallLowering> CallLoweringInfo;
99 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
100 std::unique_ptr<InstructionSelector> InstSelector;
101 std::unique_ptr<LegalizerInfo> Legalizer;
102 std::unique_ptr<RegisterBankInfo> RegBankInfo;
103
104private:
105 /// initializeSubtargetDependencies - Initializes using CPUString and the
106 /// passed in feature string so that we can use initializer lists for
107 /// subtarget initialization.
108 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
109 StringRef CPUString,
110 StringRef TuneCPUString,
111 bool HasMinSize);
112
113 /// Initialize properties based on the selected processor family.
114 void initializeProperties(bool HasMinSize);
115
116public:
117 /// This constructor initializes the data members to match that
118 /// of the specified triple.
119 AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
120 StringRef FS, const TargetMachine &TM, bool LittleEndian,
121 unsigned MinSVEVectorSizeInBitsOverride = 0,
122 unsigned MaxSVEVectorSizeInBitsOverride = 0,
123 bool IsStreaming = false, bool IsStreamingCompatible = false,
124 bool HasMinSize = false);
125
126// Getters for SubtargetFeatures defined in tablegen
127#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
128 bool GETTER() const { return ATTRIBUTE; }
129#include "AArch64GenSubtargetInfo.inc"
130
132 return &TSInfo;
133 }
134 const AArch64FrameLowering *getFrameLowering() const override {
135 return &FrameLowering;
136 }
137 const AArch64TargetLowering *getTargetLowering() const override {
138 return &TLInfo;
139 }
140 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
141 const AArch64RegisterInfo *getRegisterInfo() const override {
142 return &getInstrInfo()->getRegisterInfo();
143 }
144 const CallLowering *getCallLowering() const override;
145 const InlineAsmLowering *getInlineAsmLowering() const override;
147 const LegalizerInfo *getLegalizerInfo() const override;
148 const RegisterBankInfo *getRegBankInfo() const override;
149 const Triple &getTargetTriple() const { return TargetTriple; }
150 bool enableMachineScheduler() const override { return true; }
151 bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
152
153 bool enableMachinePipeliner() const override;
154 bool useDFAforSMS() const override { return false; }
155
156 /// Returns ARM processor family.
157 /// Avoid this function! CPU specifics should be kept local to this class
158 /// and preferably modeled with SubtargetFeatures or properties in
159 /// initializeProperties().
161 return ARMProcFamily;
162 }
163
164 bool isXRaySupported() const override { return true; }
165
166 /// Returns true if the function has a streaming body.
167 bool isStreaming() const { return IsStreaming; }
168
169 /// Returns true if the function has a streaming-compatible body.
171
172 /// Returns true if the target has NEON and the function at runtime is known
173 /// to have NEON enabled (e.g. the function is known not to be in streaming-SVE
174 /// mode, which disables NEON instructions).
175 bool isNeonAvailable() const {
176 return hasNEON() &&
177 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
178 }
179
180 /// Returns true if the target has SVE and can use the full range of SVE
181 /// instructions, for example because it knows the function is known not to be
182 /// in streaming-SVE mode or when the target has FEAT_FA64 enabled.
183 bool isSVEAvailable() const {
184 return hasSVE() &&
185 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
186 }
187
189 // Don't assume any minimum vector size when PSTATE.SM may not be 0, because
190 // we don't yet support streaming-compatible codegen support that we trust
191 // is safe for functions that may be executed in streaming-SVE mode.
192 // By returning '0' here, we disable vectorization.
193 if (!isSVEAvailable() && !isNeonAvailable())
194 return 0;
196 }
197
198 bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
199 bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
200 unsigned getNumXRegisterReserved() const {
201 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
202 AllReservedX |= ReserveXRegister;
203 AllReservedX |= ReserveXRegisterForRA;
204 return AllReservedX.count();
205 }
206 bool isXRegCustomCalleeSaved(size_t i) const {
207 return CustomCallSavedXRegs[i];
208 }
210
211 /// Return true if the CPU supports any kind of instruction fusion.
212 bool hasFusion() const {
213 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
214 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
215 hasFuseAdrpAdd() || hasFuseLiterals();
216 }
217
218 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
219 unsigned getVectorInsertExtractBaseCost() const;
220 unsigned getCacheLineSize() const override { return CacheLineSize; }
221 unsigned getPrefetchDistance() const override { return PrefetchDistance; }
222 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
223 unsigned NumStridedMemAccesses,
224 unsigned NumPrefetches,
225 bool HasCall) const override {
226 return MinPrefetchStride;
227 }
228 unsigned getMaxPrefetchIterationsAhead() const override {
230 }
233 }
235
238 }
239
240 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
241 unsigned getMinimumJumpTableEntries() const {
243 }
244
245 /// CPU has TBI (top byte of addresses is ignored during HW address
246 /// translation) and OS enables it.
248
249 bool isLittleEndian() const { return IsLittle; }
250
251 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
252 bool isTargetIOS() const { return TargetTriple.isiOS(); }
253 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
254 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
255 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
256 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
258
259 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
260 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
262
263 bool isTargetILP32() const {
264 return TargetTriple.isArch32Bit() ||
266 }
267
268 bool useAA() const override;
269
270 bool addrSinkUsingGEPs() const override {
271 // Keeping GEPs inbounds is important for exploiting AArch64
272 // addressing-modes in ILP32 mode.
273 return useAA() || isTargetILP32();
274 }
275
276 bool useSmallAddressing() const {
279 // Kernel is currently allowed only for Fuchsia targets,
280 // where it is the same as Small for almost all purposes.
281 case CodeModel::Small:
282 return true;
283 default:
284 return false;
285 }
286 }
287
288 /// ParseSubtargetFeatures - Parses features string setting specified
289 /// subtarget options. Definition of function is auto generated by tblgen.
291
292 /// ClassifyGlobalReference - Find the target operand flags that describe
293 /// how a global value should be referenced for the current subtarget.
294 unsigned ClassifyGlobalReference(const GlobalValue *GV,
295 const TargetMachine &TM) const;
296
298 const TargetMachine &TM) const;
299
300 /// This function is design to compatible with the function def in other
301 /// targets and escape build error about the virtual function def in base
302 /// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
303 unsigned char
305 return 0;
306 }
307
309 unsigned NumRegionInstrs) const override;
310 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
311 SDep &Dep,
312 const TargetSchedModel *SchedModel) const override;
313
314 bool enableEarlyIfConversion() const override;
315
316 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
317
319 switch (CC) {
320 case CallingConv::C:
324 return isTargetWindows();
326 return true;
327 default:
328 return false;
329 }
330 }
331
332 /// Return whether FrameLowering should always set the "extended frame
333 /// present" bit in FP, or set it based on a symbol in the runtime.
335 // Older OS versions (particularly system unwinders) are confused by the
336 // Swift extended frame, so when building code that might be run on them we
337 // must dynamically query the concurrency library to determine whether
338 // extended frames should be flagged as present.
339 const Triple &TT = getTargetTriple();
340
341 unsigned Major = TT.getOSVersion().getMajor();
342 switch(TT.getOS()) {
343 default:
344 return false;
345 case Triple::IOS:
346 case Triple::TvOS:
347 return Major < 15;
348 case Triple::WatchOS:
349 return Major < 8;
350 case Triple::MacOSX:
351 case Triple::Darwin:
352 return Major < 12;
353 }
354 }
355
356 void mirFileLoaded(MachineFunction &MF) const override;
357
358 bool hasSVEorSME() const { return hasSVE() || hasSME(); }
359 bool hasSVE2orSME() const { return hasSVE2() || hasSME(); }
360
361 // Return the known range for the bit length of SVE data registers. A value
362 // of 0 means nothing is known about that particular limit beyong what's
363 // implied by the architecture.
364 unsigned getMaxSVEVectorSizeInBits() const {
366 "Tried to get SVE vector length without SVE support!");
368 }
369
370 unsigned getMinSVEVectorSizeInBits() const {
372 "Tried to get SVE vector length without SVE support!");
374 }
375
377 if (!isNeonAvailable())
378 return hasSVEorSME();
379
380 // Prefer NEON unless larger SVE registers are available.
381 return hasSVEorSME() && getMinSVEVectorSizeInBits() >= 256;
382 }
383
386 return false;
389 }
390
391 unsigned getVScaleForTuning() const { return VScaleForTuning; }
392
394 return DefaultSVETFOpts;
395 }
396
397 const char* getChkStkName() const {
398 if (isWindowsArm64EC())
399 return "#__chkstk_arm64ec";
400 return "__chkstk";
401 }
402
403 const char* getSecurityCheckCookieName() const {
404 if (isWindowsArm64EC())
405 return "#__security_check_cookie_arm64ec";
406 return "__security_check_cookie";
407 }
408
409 /// Choose a method of checking LR before performing a tail call.
411
413 return AddressCheckPSV.get();
414 }
415
416private:
417 /// Pseudo value representing memory load performed to check an address.
418 ///
419 /// This load operation is solely used for its side-effects: if the address
420 /// is not mapped (or not readable), it triggers CPU exception, otherwise
421 /// execution proceeds and the value is not used.
422 class AddressCheckPseudoSourceValue : public PseudoSourceValue {
423 public:
424 AddressCheckPseudoSourceValue(const TargetMachine &TM)
426
427 bool isConstant(const MachineFrameInfo *) const override { return false; }
428 bool isAliased(const MachineFrameInfo *) const override { return true; }
429 bool mayAlias(const MachineFrameInfo *) const override { return true; }
430 void printCustom(raw_ostream &OS) const override { OS << "AddressCheck"; }
431 };
432
433 std::unique_ptr<AddressCheckPseudoSourceValue> AddressCheckPSV;
434};
435} // End llvm namespace
436
437#endif
This file describes how to lower LLVM calls to machine code calls.
This file describes how to lower LLVM inline asm to machine code INLINEASM.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
const CallLowering * getCallLowering() const override
const AArch64RegisterInfo * getRegisterInfo() const override
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
TailFoldingOpts DefaultSVETFOpts
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
bool addrSinkUsingGEPs() const override
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned getMinimumJumpTableEntries() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSVEForFixedLengthVectors(EVT VT) const
const AArch64InstrInfo * getInstrInfo() const override
bool useSmallAddressing() const
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
AArch64SelectionDAGInfo TSInfo
const char * getSecurityCheckCookieName() const
unsigned getMaximumJumpTableSize() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
AArch64FrameLowering FrameLowering
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getCacheLineSize() const override
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
Align getPrefLoopAlignment() const
Align getPrefFunctionAlignment() const
unsigned getMaxBytesForLoopAlignment() const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
unsigned getMaxInterleaveFactor() const
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override
This function is design to compatible with the function def in other targets and escape build error a...
const Triple & getTargetTriple() const
const PseudoSourceValue * getAddressCheckPSV() const
bool isStreamingCompatible() const
Returns true if the function has a streaming-compatible body.
bool isCallingConvWin64(CallingConv::ID CC) const
const char * getChkStkName() const
bool isXRegCustomCalleeSaved(size_t i) const
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
TailFoldingOpts getSVETailFoldingDefaultOpts() const
bool useSVEForFixedLengthVectors() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getMinVectorRegisterBitWidth() const
bool isStreaming() const
Returns true if the function has a streaming body.
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const
Choose a method of checking LR before performing a tail call.
bool isXRegisterReserved(size_t i) const
unsigned getMaxPrefetchIterationsAhead() const override
bool useDFAforSMS() const override
const LegalizerInfo * getLegalizerInfo() const override
bool enableMachineScheduler() const override
bool enablePostRAScheduler() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
unsigned getMaxSVEVectorSizeInBits() const
unsigned getVScaleForTuning() const
unsigned getMinSVEVectorSizeInBits() const
AArch64InstrInfo InstrInfo
AArch64TargetLowering TLInfo
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
bool isXRaySupported() const override
bool isSVEAvailable() const
Returns true if the target has SVE and can use the full range of SVE instructions,...
bool hasCustomCallingConv() const
const AArch64FrameLowering * getFrameLowering() const override
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
unsigned getPrefetchDistance() const override
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:162
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:170
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
Scheduling dependency.
Definition: ScheduleDAG.h:49
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
const TargetMachine & getTargetMachine() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
CodeModel::Model getCodeModel() const
Returns the code model.
Provide an instruction scheduling machine model to CodeGen passes.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:769
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:732
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:724
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:390
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:624
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:678
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:558
bool isWindowsArm64EC() const
Definition: Triple.h:640
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:531
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1665
bool isOSFuchsia() const
Definition: Triple.h:588
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
AuthCheckMethod
Variants of check performed on an authenticated pointer.
static constexpr unsigned SVEBitsPerBlock
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:159
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: ValueTypes.h:366
bool isFixedLengthVector() const
Definition: ValueTypes.h:177
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.