LLVM 20.0.0git
AArch64Subtarget.cpp
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1//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Subtarget.h"
14
15#include "AArch64.h"
16#include "AArch64InstrInfo.h"
17#include "AArch64PBQPRegAlloc.h"
26#include "llvm/IR/GlobalValue.h"
29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-subtarget"
33
34#define GET_SUBTARGETINFO_CTOR
35#define GET_SUBTARGETINFO_TARGET_DESC
36#include "AArch64GenSubtargetInfo.inc"
37
38static cl::opt<bool>
39EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
40 "converter pass"), cl::init(true), cl::Hidden);
41
42// If OS supports TBI, use this flag to enable it.
43static cl::opt<bool>
44UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
45 "an address is ignored"), cl::init(false), cl::Hidden);
46
48 "aarch64-macho-enable-nonlazybind",
49 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),
51
52static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
53 cl::desc("Enable the use of AA during codegen."));
54
56 "aarch64-insert-extract-base-cost",
57 cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
58
59// Reserve a list of X# registers, so they are unavailable for register
60// allocator, but can still be used as ABI requests, such as passing arguments
61// to function call.
63ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
64 "registers, so they can't be used by register allocator. "
65 "Should only be used for testing register allocator."),
67
69 AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",
71 cl::desc("Override the variant of check applied "
72 "to authenticated LR during tail call"),
74
76 "aarch64-min-jump-table-entries", cl::init(13), cl::Hidden,
77 cl::desc("Set minimum number of entries to use a jump table on AArch64"));
78
80 if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
83}
84
85AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
86 StringRef FS, StringRef CPUString, StringRef TuneCPUString,
87 bool HasMinSize) {
88 // Determine default and user-specified characteristics
89
90 if (CPUString.empty())
91 CPUString = "generic";
92
93 if (TuneCPUString.empty())
94 TuneCPUString = CPUString;
95
96 ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
97 initializeProperties(HasMinSize);
98
99 return *this;
100}
101
102void AArch64Subtarget::initializeProperties(bool HasMinSize) {
103 // Initialize CPU specific properties. We should add a tablegen feature for
104 // this in the future so we can specify it together with the subtarget
105 // features.
106 switch (ARMProcFamily) {
107 case Others:
108 break;
109 case Carmel:
110 CacheLineSize = 64;
111 break;
112 case CortexA35:
113 case CortexA53:
114 case CortexA55:
115 case CortexR82:
116 case CortexR82AE:
120 break;
121 case CortexA57:
126 break;
127 case CortexA65:
129 break;
130 case CortexA72:
131 case CortexA73:
132 case CortexA75:
136 break;
137 case CortexA76:
138 case CortexA77:
139 case CortexA78:
140 case CortexA78AE:
141 case CortexA78C:
142 case CortexX1:
146 break;
147 case CortexA510:
148 case CortexA520:
150 VScaleForTuning = 1;
153 break;
154 case CortexA710:
155 case CortexA715:
156 case CortexA720:
157 case CortexA725:
158 case CortexX2:
159 case CortexX3:
160 case CortexX4:
161 case CortexX925:
163 VScaleForTuning = 1;
166 break;
167 case A64FX:
168 CacheLineSize = 256;
172 PrefetchDistance = 128;
173 MinPrefetchStride = 1024;
175 VScaleForTuning = 4;
176 break;
177 case AppleA7:
178 case AppleA10:
179 case AppleA11:
180 case AppleA12:
181 case AppleA13:
182 case AppleA14:
183 case AppleA15:
184 case AppleA16:
185 case AppleA17:
186 case AppleM4:
187 CacheLineSize = 64;
188 PrefetchDistance = 280;
189 MinPrefetchStride = 2048;
191 switch (ARMProcFamily) {
192 case AppleA14:
193 case AppleA15:
194 case AppleA16:
195 case AppleA17:
196 case AppleM4:
198 break;
199 default:
200 break;
201 }
202 break;
203 case ExynosM3:
205 MaxJumpTableSize = 20;
208 break;
209 case Falkor:
211 // FIXME: remove this to enable 64-bit SLP if performance looks good.
213 CacheLineSize = 128;
214 PrefetchDistance = 820;
215 MinPrefetchStride = 2048;
217 break;
218 case Kryo:
221 CacheLineSize = 128;
222 PrefetchDistance = 740;
223 MinPrefetchStride = 1024;
225 // FIXME: remove this to enable 64-bit SLP if performance looks good.
227 break;
228 case NeoverseE1:
230 break;
231 case NeoverseN1:
235 break;
236 case NeoverseV2:
237 // Specialize cost for Neoverse-V2.
238 ScatterOverhead = 13;
240 case NeoverseN2:
241 case NeoverseN3:
242 case NeoverseV3:
246 VScaleForTuning = 1;
247 break;
248 case NeoverseV1:
252 VScaleForTuning = 2;
254 break;
255 case Neoverse512TVB:
257 VScaleForTuning = 1;
259 break;
260 case Saphira:
262 // FIXME: remove this to enable 64-bit SLP if performance looks good.
264 break;
265 case ThunderX2T99:
266 CacheLineSize = 64;
270 PrefetchDistance = 128;
271 MinPrefetchStride = 1024;
273 // FIXME: remove this to enable 64-bit SLP if performance looks good.
275 break;
276 case ThunderX:
277 case ThunderXT88:
278 case ThunderXT81:
279 case ThunderXT83:
280 CacheLineSize = 128;
283 // FIXME: remove this to enable 64-bit SLP if performance looks good.
285 break;
286 case TSV110:
287 CacheLineSize = 64;
290 break;
291 case ThunderX3T110:
292 CacheLineSize = 64;
296 PrefetchDistance = 128;
297 MinPrefetchStride = 1024;
299 // FIXME: remove this to enable 64-bit SLP if performance looks good.
301 break;
302 case Ampere1:
303 case Ampere1A:
304 case Ampere1B:
305 CacheLineSize = 64;
309 break;
310 case Oryon:
311 CacheLineSize = 64;
314 PrefetchDistance = 128;
315 MinPrefetchStride = 1024;
316 break;
317 }
318
319 if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)
321}
322
324 StringRef TuneCPU, StringRef FS,
325 const TargetMachine &TM, bool LittleEndian,
326 unsigned MinSVEVectorSizeInBitsOverride,
327 unsigned MaxSVEVectorSizeInBitsOverride,
328 bool IsStreaming, bool IsStreamingCompatible,
329 bool HasMinSize)
330 : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
331 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
332 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
333 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
334 IsLittle(LittleEndian), IsStreaming(IsStreaming),
335 IsStreamingCompatible(IsStreamingCompatible),
336 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
337 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
338 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),
339 TLInfo(TM, *this) {
342
345 Legalizer.reset(new AArch64LegalizerInfo(*this));
346
347 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
348
349 // FIXME: At this point, we can't rely on Subtarget having RBI.
350 // It's awkward to mix passing RBI and the Subtarget; should we pass
351 // TII/TRI as well?
353 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
354
355 RegBankInfo.reset(RBI);
356
357 auto TRI = getRegisterInfo();
358 StringSet<> ReservedRegNames;
359 ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end());
360 for (unsigned i = 0; i < 29; ++i) {
361 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
363 }
364 // X30 is named LR, so we can't use TRI->getName to check X30.
365 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))
367 // X29 is named FP, so we can't use TRI->getName to check X29.
368 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))
370
371 AddressCheckPSV.reset(new AddressCheckPseudoSourceValue(TM));
372}
373
375 return CallLoweringInfo.get();
376}
377
379 return InlineAsmLoweringInfo.get();
380}
381
383 return InstSelector.get();
384}
385
387 return Legalizer.get();
388}
389
391 return RegBankInfo.get();
392}
393
394/// Find the target operand flags that describe how a global value should be
395/// referenced for the current subtarget.
396unsigned
398 const TargetMachine &TM) const {
399 // MachO large model always goes via a GOT, simply to get a single 8-byte
400 // absolute relocation on all global addresses.
401 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
402 return AArch64II::MO_GOT;
403
404 // All globals dynamically protected by MTE must have their address tags
405 // synthesized. This is done by having the loader stash the tag in the GOT
406 // entry. Force all tagged globals (even ones with internal linkage) through
407 // the GOT.
408 if (GV->isTagged())
409 return AArch64II::MO_GOT;
410
411 if (!TM.shouldAssumeDSOLocal(GV)) {
412 if (GV->hasDLLImportStorageClass()) {
414 }
415 if (getTargetTriple().isOSWindows())
417 return AArch64II::MO_GOT;
418 }
419
420 // The small code model's direct accesses use ADRP, which cannot
421 // necessarily produce the value 0 (if the code is above 4GB).
422 // Same for the tiny code model, where we have a pc relative LDR.
423 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
425 return AArch64II::MO_GOT;
426
427 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
428 // that their nominal addresses are tagged and outside of the code model. In
429 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
430 // tag if necessary based on MO_TAGGED.
431 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
433
435}
436
438 const GlobalValue *GV, const TargetMachine &TM) const {
439 // MachO large model always goes via a GOT, because we don't have the
440 // relocations available to do anything else..
441 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
442 !GV->hasInternalLinkage())
443 return AArch64II::MO_GOT;
444
445 // NonLazyBind goes via GOT unless we know it's available locally.
446 auto *F = dyn_cast<Function>(GV);
447 if ((!isTargetMachO() || MachOUseNonLazyBind) && F &&
448 F->hasFnAttribute(Attribute::NonLazyBind) && !TM.shouldAssumeDSOLocal(GV))
449 return AArch64II::MO_GOT;
450
451 if (getTargetTriple().isOSWindows()) {
452 if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {
453 if (GV->hasDLLImportStorageClass()) {
454 // On Arm64EC, if we're calling a symbol from the import table
455 // directly, use MO_ARM64EC_CALLMANGLE.
458 }
459 if (GV->hasExternalLinkage()) {
460 // If we're calling a symbol directly, use the mangled form in the
461 // call instruction.
463 }
464 }
465
466 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
467 return ClassifyGlobalReference(GV, TM);
468 }
469
471}
472
474 unsigned NumRegionInstrs) const {
475 // LNT run (at least on Cyclone) showed reasonably significant gains for
476 // bi-directional scheduling. 253.perlbmk.
477 Policy.OnlyTopDown = false;
478 Policy.OnlyBottomUp = false;
479 // Enabling or Disabling the latency heuristic is a close call: It seems to
480 // help nearly no benchmark on out-of-order architectures, on the other hand
481 // it regresses register pressure on a few benchmarking.
482 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
483}
484
486 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep,
487 const TargetSchedModel *SchedModel) const {
488 if (!SchedModel || Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||
489 !Def->isInstr() || !Use->isInstr() ||
490 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&
491 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))
492 return;
493
494 // If the Def is a BUNDLE, find the last instruction in the bundle that defs
495 // the register.
496 const MachineInstr *DefMI = Def->getInstr();
497 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {
498 Register Reg = DefMI->getOperand(DefOpIdx).getReg();
499 for (const auto &Op : const_mi_bundle_ops(*DefMI)) {
500 if (Op.isReg() && Op.isDef() && Op.getReg() == Reg) {
501 DefMI = Op.getParent();
502 DefOpIdx = Op.getOperandNo();
503 }
504 }
505 }
506
507 // If the Use is a BUNDLE, find the first instruction that uses the Reg.
508 const MachineInstr *UseMI = Use->getInstr();
509 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) {
510 Register Reg = UseMI->getOperand(UseOpIdx).getReg();
511 for (const auto &Op : const_mi_bundle_ops(*UseMI)) {
512 if (Op.isReg() && Op.isUse() && Op.getReg() == Reg) {
513 UseMI = Op.getParent();
514 UseOpIdx = Op.getOperandNo();
515 break;
516 }
517 }
518 }
519
520 Dep.setLatency(
521 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx));
522}
523
526}
527
530 return false;
531
533 return true;
534 if (TargetTriple.isiOS()) {
536 }
537
538 return false;
539}
540
541std::unique_ptr<PBQPRAConstraint>
543 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
544}
545
547 // We usually compute max call frame size after ISel. Do the computation now
548 // if the .mir file didn't specify it. Note that this will probably give you
549 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
550 // instructions, specify explicitly if you need it to be correct.
551 MachineFrameInfo &MFI = MF.getFrameInfo();
554}
555
556bool AArch64Subtarget::useAA() const { return UseAA; }
557
558// If return address signing is enabled, tail calls are emitted as follows:
559//
560// ```
561// <authenticate LR>
562// <check LR>
563// TCRETURN ; the callee may sign and spill the LR in its prologue
564// ```
565//
566// LR may require explicit checking because if FEAT_FPAC is not implemented
567// and LR was tampered with, then `<authenticate LR>` will not generate an
568// exception on its own. Later, if the callee spills the signed LR value and
569// neither FEAT_PAuth2 nor FEAT_EPAC are implemented, the valid PAC replaces
570// the higher bits of LR thus hiding the authentication failure.
572 const MachineFunction &MF) const {
573 // TODO: Check subtarget for the scheme. Present variant is a default for
574 // pauthtest ABI.
575 if (MF.getFunction().hasFnAttribute("ptrauth-returns") &&
576 MF.getFunction().hasFnAttribute("ptrauth-auth-traps"))
578 if (AuthenticatedLRCheckMethod.getNumOccurrences())
580
581 // At now, use None by default because checks may introduce an unexpected
582 // performance regression or incompatibility with execute-only mappings.
584}
585
586std::optional<uint16_t>
588 const Function &ParentFn) const {
589 if (!ParentFn.hasFnAttribute("ptrauth-indirect-gotos"))
590 return std::nullopt;
591 // We currently have one simple mechanism for all targets.
592 // This isn't ABI, so we can always do better in the future.
594 (Twine(ParentFn.getName()) + " blockaddress").str());
595}
596
598 return getSchedModel().hasInstrSchedModel();
599}
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
This file declares the targeting of the Machinelegalizer class for AArch64.
#define AUTH_CHECK_METHOD_CL_VALUES_LR
This file declares the targeting of the RegisterBankInfo class for AArch64.
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
static cl::opt< bool > MachOUseNonLazyBind("aarch64-macho-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"), cl::Hidden)
static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))
static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:309
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This class provides the information for the target register banks.
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)
This constructor initializes the data members to match that of the specified triple.
const CallLowering * getCallLowering() const override
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSmallAddressing() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
std::optional< uint16_t > getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const
Compute the integer discriminator for a given BlockAddress constant, if blockaddress signing is enabl...
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
const Triple & getTargetTriple() const
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod(const MachineFunction &MF) const
Choose a method of checking LR before performing a tail call.
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
BitVector & set()
Definition: BitVector.h:351
This class represents an Operation in the Expression.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:743
bool hasExternalLinkage() const
Definition: GlobalValue.h:511
bool isTagged() const
Definition: GlobalValue.h:365
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:529
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:278
bool hasInternalLinkage() const
Definition: GlobalValue.h:526
Type * getValueType() const
Definition: GlobalValue.h:296
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void computeMaxCallFrameSize(MachineFunction &MF, std::vector< MachineBasicBlock::iterator > *FrameSDOps=nullptr)
Computes the maximum size of a callframe.
bool isMaxCallFrameSizeComputed() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:569
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:579
Register getReg() const
getReg - Returns the register number.
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Scheduling dependency.
Definition: ScheduleDAG.h:49
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:504
@ Data
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
unsigned getReg() const
Returns the register associated with this edge.
Definition: ScheduleDAG.h:218
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
Definition: StringMap.h:276
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:38
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
Provide an instruction scheduling machine model to CodeGen passes.
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:553
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:531
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
Definition: Triple.cpp:1409
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool isFunctionTy() const
True if this is an instance of FunctionType.
Definition: Type.h:242
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:29
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
AuthCheckMethod
Variants of check performed on an authenticated pointer.
@ HighBitsNoTBI
Check by comparing bits 62 and 61 of the authenticated address.
@ None
Do not check the value at all.
bool isX18ReservedByDefault(const Triple &TT)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:711
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
@ CommaSeparated
Definition: CommandLine.h:163
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, const AArch64Subtarget &, const AArch64RegisterBankInfo &)
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
uint16_t getPointerAuthStableSipHash(StringRef S)
Compute a stable non-zero 16-bit hash of the given string.
Definition: SipHash.cpp:168
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.