LLVM  16.0.0git
AArch64Subtarget.cpp
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1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
26 #include "llvm/IR/GlobalValue.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "aarch64-subtarget"
33 
34 #define GET_SUBTARGETINFO_CTOR
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #include "AArch64GenSubtargetInfo.inc"
37 
38 static cl::opt<bool>
39 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
40  "converter pass"), cl::init(true), cl::Hidden);
41 
42 // If OS supports TBI, use this flag to enable it.
43 static cl::opt<bool>
44 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
45  "an address is ignored"), cl::init(false), cl::Hidden);
46 
47 static cl::opt<bool>
48  UseNonLazyBind("aarch64-enable-nonlazybind",
49  cl::desc("Call nonlazybind functions via direct GOT load"),
50  cl::init(false), cl::Hidden);
51 
52 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
53  cl::desc("Enable the use of AA during codegen."));
54 
56  "aarch64-insert-extract-base-cost",
57  cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
58 
59 // Reserve a list of X# registers, so they are unavailable for register
60 // allocator, but can still be used as ABI requests, such as passing arguments
61 // to function call.
63 ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
64  "registers, so they can't be used by register allocator. "
65  "Should only be used for testing register allocator."),
67 
68 static cl::opt<bool>
69  ForceStreamingCompatibleSVE("force-streaming-compatible-sve",
70  cl::init(false), cl::Hidden);
71 
73  if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
76 }
77 
78 AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
79  StringRef FS, StringRef CPUString, StringRef TuneCPUString) {
80  // Determine default and user-specified characteristics
81 
82  if (CPUString.empty())
83  CPUString = "generic";
84 
85  if (TuneCPUString.empty())
86  TuneCPUString = CPUString;
87 
88  ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
89  initializeProperties();
90 
91  return *this;
92 }
93 
94 void AArch64Subtarget::initializeProperties() {
95  // Initialize CPU specific properties. We should add a tablegen feature for
96  // this in the future so we can specify it together with the subtarget
97  // features.
98  switch (ARMProcFamily) {
99  case Others:
100  break;
101  case Carmel:
102  CacheLineSize = 64;
103  break;
104  case CortexA35:
105  case CortexA53:
106  case CortexA55:
110  break;
111  case CortexA57:
116  break;
117  case CortexA65:
119  break;
120  case CortexA72:
121  case CortexA73:
122  case CortexA75:
126  break;
127  case CortexA76:
128  case CortexA77:
129  case CortexA78:
130  case CortexA78C:
131  case CortexR82:
132  case CortexX1:
133  case CortexX1C:
137  break;
138  case CortexA510:
140  VScaleForTuning = 1;
143  break;
144  case CortexA710:
145  case CortexA715:
146  case CortexX2:
147  case CortexX3:
149  VScaleForTuning = 1;
152  break;
153  case A64FX:
154  CacheLineSize = 256;
158  PrefetchDistance = 128;
159  MinPrefetchStride = 1024;
161  VScaleForTuning = 4;
162  break;
163  case AppleA7:
164  case AppleA10:
165  case AppleA11:
166  case AppleA12:
167  case AppleA13:
168  case AppleA14:
169  case AppleA15:
170  case AppleA16:
171  CacheLineSize = 64;
172  PrefetchDistance = 280;
173  MinPrefetchStride = 2048;
175  break;
176  case ExynosM3:
178  MaxJumpTableSize = 20;
181  break;
182  case Falkor:
184  // FIXME: remove this to enable 64-bit SLP if performance looks good.
186  CacheLineSize = 128;
187  PrefetchDistance = 820;
188  MinPrefetchStride = 2048;
190  break;
191  case Kryo:
194  CacheLineSize = 128;
195  PrefetchDistance = 740;
196  MinPrefetchStride = 1024;
198  // FIXME: remove this to enable 64-bit SLP if performance looks good.
200  break;
201  case NeoverseE1:
203  break;
204  case NeoverseN1:
208  break;
209  case NeoverseN2:
210  case NeoverseV2:
214  VScaleForTuning = 1;
215  break;
216  case NeoverseV1:
220  VScaleForTuning = 2;
221  break;
222  case Neoverse512TVB:
224  VScaleForTuning = 1;
226  break;
227  case Saphira:
229  // FIXME: remove this to enable 64-bit SLP if performance looks good.
231  break;
232  case ThunderX2T99:
233  CacheLineSize = 64;
237  PrefetchDistance = 128;
238  MinPrefetchStride = 1024;
240  // FIXME: remove this to enable 64-bit SLP if performance looks good.
242  break;
243  case ThunderX:
244  case ThunderXT88:
245  case ThunderXT81:
246  case ThunderXT83:
247  CacheLineSize = 128;
250  // FIXME: remove this to enable 64-bit SLP if performance looks good.
252  break;
253  case TSV110:
254  CacheLineSize = 64;
257  break;
258  case ThunderX3T110:
259  CacheLineSize = 64;
263  PrefetchDistance = 128;
264  MinPrefetchStride = 1024;
266  // FIXME: remove this to enable 64-bit SLP if performance looks good.
268  break;
269  case Ampere1:
270  CacheLineSize = 64;
274  break;
275  }
276 }
277 
278 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
279  const std::string &TuneCPU,
280  const std::string &FS,
281  const TargetMachine &TM, bool LittleEndian,
282  unsigned MinSVEVectorSizeInBitsOverride,
283  unsigned MaxSVEVectorSizeInBitsOverride,
284  bool StreamingSVEModeDisabled)
285  : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
286  ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
287  ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
288  CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
289  IsLittle(LittleEndian),
290  StreamingSVEModeDisabled(StreamingSVEModeDisabled),
291  MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
292  MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
293  InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
294  TLInfo(TM, *this) {
296  ReserveXRegister.set(18);
297 
300  Legalizer.reset(new AArch64LegalizerInfo(*this));
301 
302  auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
303 
304  // FIXME: At this point, we can't rely on Subtarget having RBI.
305  // It's awkward to mix passing RBI and the Subtarget; should we pass
306  // TII/TRI as well?
308  *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
309 
310  RegBankInfo.reset(RBI);
311 
312  auto TRI = getRegisterInfo();
313  StringSet<> ReservedRegNames;
314  ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end());
315  for (unsigned i = 0; i < 29; ++i) {
316  if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
318  }
319  // X30 is named LR, so we can't use TRI->getName to check X30.
320  if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))
322  // X29 is named FP, so we can't use TRI->getName to check X29.
323  if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))
325 }
326 
328  return CallLoweringInfo.get();
329 }
330 
332  return InlineAsmLoweringInfo.get();
333 }
334 
336  return InstSelector.get();
337 }
338 
340  return Legalizer.get();
341 }
342 
344  return RegBankInfo.get();
345 }
346 
347 /// Find the target operand flags that describe how a global value should be
348 /// referenced for the current subtarget.
349 unsigned
351  const TargetMachine &TM) const {
352  // MachO large model always goes via a GOT, simply to get a single 8-byte
353  // absolute relocation on all global addresses.
354  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
355  return AArch64II::MO_GOT;
356 
357  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
358  if (GV->hasDLLImportStorageClass()) {
359  if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy())
362  }
363  if (getTargetTriple().isOSWindows())
365  return AArch64II::MO_GOT;
366  }
367 
368  // The small code model's direct accesses use ADRP, which cannot
369  // necessarily produce the value 0 (if the code is above 4GB).
370  // Same for the tiny code model, where we have a pc relative LDR.
371  if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
373  return AArch64II::MO_GOT;
374 
375  // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
376  // that their nominal addresses are tagged and outside of the code model. In
377  // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
378  // tag if necessary based on MO_TAGGED.
379  if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
381 
382  return AArch64II::MO_NO_FLAG;
383 }
384 
386  const GlobalValue *GV, const TargetMachine &TM) const {
387  // MachO large model always goes via a GOT, because we don't have the
388  // relocations available to do anything else..
389  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
390  !GV->hasInternalLinkage())
391  return AArch64II::MO_GOT;
392 
393  // NonLazyBind goes via GOT unless we know it's available locally.
394  auto *F = dyn_cast<Function>(GV);
395  if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
396  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
397  return AArch64II::MO_GOT;
398 
399  if (getTargetTriple().isOSWindows()) {
400  if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy() &&
401  GV->hasDLLImportStorageClass()) {
402  // On Arm64EC, if we're calling a function directly, use MO_DLLIMPORT,
403  // not MO_DLLIMPORTAUX.
405  }
406 
407  // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
408  return ClassifyGlobalReference(GV, TM);
409  }
410 
411  return AArch64II::MO_NO_FLAG;
412 }
413 
415  unsigned NumRegionInstrs) const {
416  // LNT run (at least on Cyclone) showed reasonably significant gains for
417  // bi-directional scheduling. 253.perlbmk.
418  Policy.OnlyTopDown = false;
419  Policy.OnlyBottomUp = false;
420  // Enabling or Disabling the latency heuristic is a close call: It seems to
421  // help nearly no benchmark on out-of-order architectures, on the other hand
422  // it regresses register pressure on a few benchmarking.
423  Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
424 }
425 
427  return EnableEarlyIfConvert;
428 }
429 
432  return false;
433 
435  return true;
436  if (TargetTriple.isiOS()) {
437  return TargetTriple.getiOSVersion() >= VersionTuple(8);
438  }
439 
440  return false;
441 }
442 
443 std::unique_ptr<PBQPRAConstraint>
445  return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
446 }
447 
449  // We usually compute max call frame size after ISel. Do the computation now
450  // if the .mir file didn't specify it. Note that this will probably give you
451  // bogus values after PEI has eliminated the callframe setup/destroy pseudo
452  // instructions, specify explicitly if you need it to be correct.
453  MachineFrameInfo &MFI = MF.getFrameInfo();
454  if (!MFI.isMaxCallFrameSizeComputed())
455  MFI.computeMaxCallFrameSize(MF);
456 }
457 
458 bool AArch64Subtarget::useAA() const { return UseAA; }
459 
462  assert(hasSVEorSME() && "Expected SVE to be available");
463  return hasSVEorSME();
464  }
465  return false;
466 }
AArch64LegalizerInfo.h
i
i
Definition: README.txt:29
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:54
llvm::MachineSchedPolicy::OnlyBottomUp
bool OnlyBottomUp
Definition: MachineScheduler.h:191
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:46
llvm::MachineFrameInfo::isMaxCallFrameSizeComputed
bool isMaxCallFrameSizeComputed() const
Definition: MachineFrameInfo.h:661
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::AArch64RegisterBankInfo
This class provides the information for the target register banks.
Definition: AArch64RegisterBankInfo.h:104
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:430
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64Subtarget::getVectorInsertExtractBaseCost
unsigned getVectorInsertExtractBaseCost() const
Definition: AArch64Subtarget.cpp:72
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:94
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:83
AArch64.h
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:113
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:57
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:85
AArch64RegisterBankInfo.h
AArch64TargetParser.h
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:88
llvm::AArch64Subtarget::CortexX1C
@ CortexX1C
Definition: AArch64Subtarget.h:70
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:63
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:144
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:59
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:140
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:78
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:62
llvm::cl::CommaSeparated
@ CommaSeparated
Definition: CommandLine.h:166
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:104
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:142
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::Triple::isDriverKit
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:512
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEModeDisabled=true)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:278
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:108
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:105
llvm::AArch64Subtarget::ReserveXRegisterForRA
BitVector ReserveXRegisterForRA
Definition: AArch64Subtarget.h:119
llvm::X86AS::FS
@ FS
Definition: X86.h:200
InstructionSelect.h
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:52
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:84
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:89
llvm::AArch64Subtarget::CortexX2
@ CortexX2
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:47
llvm::StringSet::insert
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:34
llvm::AArch64Subtarget::MaxBytesForLoopAlignment
unsigned MaxBytesForLoopAlignment
Definition: AArch64Subtarget.h:112
TargetParser.h
llvm::AArch64Subtarget::AppleA15
@ AppleA15
Definition: AArch64Subtarget.h:50
llvm::AArch64Subtarget::isWindowsArm64EC
bool isWindowsArm64EC() const
Definition: AArch64Subtarget.h:267
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:111
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:64
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:77
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AArch64Subtarget::CortexA715
@ CortexA715
Definition: AArch64Subtarget.h:67
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:524
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:178
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:80
AArch64PBQPRegAlloc.h
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:444
ForceStreamingCompatibleSVE
static cl::opt< bool > ForceStreamingCompatibleSVE("force-streaming-compatible-sve", cl::init(false), cl::Hidden)
InstrInfo
return InstrInfo
Definition: RISCVInsertVSETVLI.cpp:668
GlobalValue.h
AArch64TargetMachine.h
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:331
AArch64InstrInfo.h
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:335
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::AArch64Subtarget::AppleA16
@ AppleA16
Definition: AArch64Subtarget.h:51
llvm::Legalizer
Definition: Legalizer.h:36
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:106
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:426
llvm::AArch64Subtarget::Neoverse512TVB
@ Neoverse512TVB
Definition: AArch64Subtarget.h:79
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:448
llvm::MachineSchedPolicy::DisableLatencyHeuristic
bool DisableLatencyHeuristic
Definition: MachineScheduler.h:195
AArch64GenSubtargetInfo
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:23
llvm::VersionTuple
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:31
llvm::AArch64Subtarget::VScaleForTuning
unsigned VScaleForTuning
Definition: AArch64Subtarget.h:129
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:65
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:521
UseNonLazyBind
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
llvm::AArch64II::MO_DLLIMPORTAUX
@ MO_DLLIMPORTAUX
MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub.
Definition: AArch64BaseInfo.h:809
llvm::Type::isFunctionTy
bool isFunctionTy() const
True if this is an instance of FunctionType.
Definition: Type.h:228
UseAddressTopByteIgnored
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
llvm::Triple::getiOSVersion
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
Definition: Triple.cpp:1265
llvm::AArch64::isX18ReservedByDefault
bool isX18ReservedByDefault(const Triple &TT)
Definition: AArch64TargetParser.cpp:138
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:110
AArch64AddressingModes.h
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:69
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:87
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::AArch64Subtarget::forceStreamingCompatibleSVE
bool forceStreamingCompatibleSVE() const
Definition: AArch64Subtarget.cpp:460
llvm::cl::opt< bool >
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:327
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
ReservedRegsForRA
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:116
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: AArch64BaseInfo.h:786
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:61
AArch64CallLowering.h
llvm::AArch64Subtarget::Ampere1
@ Ampere1
Definition: AArch64Subtarget.h:43
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:286
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition: AArch64BaseInfo.h:775
llvm::MachineFrameInfo::computeMaxCallFrameSize
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
Definition: MachineFrameInfo.cpp:187
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:49
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::AArch64Subtarget::hasSVEorSME
bool hasSVEorSME() const
Definition: AArch64Subtarget.h:364
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:727
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:76
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:97
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: AArch64Subtarget.cpp:385
llvm::StringSet
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
llvm::AArch64Subtarget::CortexA710
@ CortexA710
Definition: AArch64Subtarget.h:66
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:190
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:493
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:44
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:86
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:53
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:55
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:182
llvm::AArch64CallLowering
Definition: AArch64CallLowering.h:30
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:343
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:73
llvm::MachineSchedPolicy::OnlyTopDown
bool OnlyTopDown
Definition: MachineScheduler.h:190
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:350
llvm::AArch64Subtarget::NeoverseV2
@ NeoverseV2
Definition: AArch64Subtarget.h:81
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:141
llvm::AArch64LegalizerInfo
This class provides the information for the target register banks.
Definition: AArch64LegalizerInfo.h:27
MachineFrameInfo.h
llvm::AArch64Subtarget::CortexX3
@ CortexX3
Definition: AArch64Subtarget.h:72
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:75
llvm::StringMap< std::nullopt_t, MallocAllocator >::count
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
Definition: StringMap.h:245
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:107
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:109
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:271
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
MachineScheduler.h
AArch64Subtarget.h
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:60
UseAA
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:82
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:132
llvm::GlobalValue::hasDLLImportStorageClass
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:274
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:339
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1182
llvm::GlobalValue::getValueType
Type * getValueType() const
Definition: GlobalValue.h:292
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::CortexA510
@ CortexA510
Definition: AArch64Subtarget.h:56
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:68
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: AArch64BaseInfo.h:765
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:181
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:802
llvm::cl::desc
Definition: CommandLine.h:413
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64InstructionSelector
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
Definition: AArch64InstructionSelector.cpp:6956
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:458
llvm::CallLowering
Definition: CallLowering.h:44
EnableEarlyIfConvert
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:770
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:74
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:414
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:45
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:48
OverrideVectorInsertExtractBaseCost
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:58
llvm::cl::list
Definition: CommandLine.h:1648