LLVM  15.0.0git
AArch64Subtarget.cpp
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1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
26 #include "llvm/IR/GlobalValue.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "aarch64-subtarget"
33 
34 #define GET_SUBTARGETINFO_CTOR
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #include "AArch64GenSubtargetInfo.inc"
37 
38 static cl::opt<bool>
39 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
40  "converter pass"), cl::init(true), cl::Hidden);
41 
42 // If OS supports TBI, use this flag to enable it.
43 static cl::opt<bool>
44 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
45  "an address is ignored"), cl::init(false), cl::Hidden);
46 
47 static cl::opt<bool>
48  UseNonLazyBind("aarch64-enable-nonlazybind",
49  cl::desc("Call nonlazybind functions via direct GOT load"),
50  cl::init(false), cl::Hidden);
51 
52 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
53  cl::desc("Enable the use of AA during codegen."));
54 
56  "aarch64-insert-extract-base-cost",
57  cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
58 
60  if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
63 }
64 
65 AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
66  StringRef FS, StringRef CPUString, StringRef TuneCPUString) {
67  // Determine default and user-specified characteristics
68 
69  if (CPUString.empty())
70  CPUString = "generic";
71 
72  if (TuneCPUString.empty())
73  TuneCPUString = CPUString;
74 
75  ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
76  initializeProperties();
77 
78  return *this;
79 }
80 
81 void AArch64Subtarget::initializeProperties() {
82  // Initialize CPU specific properties. We should add a tablegen feature for
83  // this in the future so we can specify it together with the subtarget
84  // features.
85  switch (ARMProcFamily) {
86  case Others:
87  break;
88  case Carmel:
89  CacheLineSize = 64;
90  break;
91  case CortexA35:
92  case CortexA53:
93  case CortexA55:
97  break;
98  case CortexA57:
103  break;
104  case CortexA65:
106  break;
107  case CortexA72:
108  case CortexA73:
109  case CortexA75:
113  break;
114  case CortexA76:
115  case CortexA77:
116  case CortexA78:
117  case CortexA78C:
118  case CortexR82:
119  case CortexX1:
120  case CortexX1C:
124  break;
125  case CortexA510:
127  VScaleForTuning = 1;
130  break;
131  case CortexA710:
132  case CortexX2:
134  VScaleForTuning = 1;
137  break;
138  case A64FX:
139  CacheLineSize = 256;
143  PrefetchDistance = 128;
144  MinPrefetchStride = 1024;
146  VScaleForTuning = 4;
147  break;
148  case AppleA7:
149  case AppleA10:
150  case AppleA11:
151  case AppleA12:
152  case AppleA13:
153  case AppleA14:
154  CacheLineSize = 64;
155  PrefetchDistance = 280;
156  MinPrefetchStride = 2048;
158  break;
159  case ExynosM3:
161  MaxJumpTableSize = 20;
164  break;
165  case Falkor:
167  // FIXME: remove this to enable 64-bit SLP if performance looks good.
169  CacheLineSize = 128;
170  PrefetchDistance = 820;
171  MinPrefetchStride = 2048;
173  break;
174  case Kryo:
177  CacheLineSize = 128;
178  PrefetchDistance = 740;
179  MinPrefetchStride = 1024;
181  // FIXME: remove this to enable 64-bit SLP if performance looks good.
183  break;
184  case NeoverseE1:
186  break;
187  case NeoverseN1:
191  break;
192  case NeoverseN2:
196  VScaleForTuning = 1;
197  break;
198  case NeoverseV1:
202  VScaleForTuning = 2;
203  break;
204  case Neoverse512TVB:
206  VScaleForTuning = 1;
208  break;
209  case Saphira:
211  // FIXME: remove this to enable 64-bit SLP if performance looks good.
213  break;
214  case ThunderX2T99:
215  CacheLineSize = 64;
219  PrefetchDistance = 128;
220  MinPrefetchStride = 1024;
222  // FIXME: remove this to enable 64-bit SLP if performance looks good.
224  break;
225  case ThunderX:
226  case ThunderXT88:
227  case ThunderXT81:
228  case ThunderXT83:
229  CacheLineSize = 128;
232  // FIXME: remove this to enable 64-bit SLP if performance looks good.
234  break;
235  case TSV110:
236  CacheLineSize = 64;
239  break;
240  case ThunderX3T110:
241  CacheLineSize = 64;
245  PrefetchDistance = 128;
246  MinPrefetchStride = 1024;
248  // FIXME: remove this to enable 64-bit SLP if performance looks good.
250  break;
251  case Ampere1:
252  CacheLineSize = 64;
256  break;
257  }
258 }
259 
260 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
261  const std::string &TuneCPU,
262  const std::string &FS,
263  const TargetMachine &TM, bool LittleEndian,
264  unsigned MinSVEVectorSizeInBitsOverride,
265  unsigned MaxSVEVectorSizeInBitsOverride)
266  : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
267  ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
268  CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
269  IsLittle(LittleEndian),
270  MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
271  MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
272  InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
273  TLInfo(TM, *this) {
275  ReserveXRegister.set(18);
276 
279  Legalizer.reset(new AArch64LegalizerInfo(*this));
280 
281  auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
282 
283  // FIXME: At this point, we can't rely on Subtarget having RBI.
284  // It's awkward to mix passing RBI and the Subtarget; should we pass
285  // TII/TRI as well?
287  *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
288 
289  RegBankInfo.reset(RBI);
290 }
291 
293  return CallLoweringInfo.get();
294 }
295 
297  return InlineAsmLoweringInfo.get();
298 }
299 
301  return InstSelector.get();
302 }
303 
305  return Legalizer.get();
306 }
307 
309  return RegBankInfo.get();
310 }
311 
312 /// Find the target operand flags that describe how a global value should be
313 /// referenced for the current subtarget.
314 unsigned
316  const TargetMachine &TM) const {
317  // MachO large model always goes via a GOT, simply to get a single 8-byte
318  // absolute relocation on all global addresses.
319  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
320  return AArch64II::MO_GOT;
321 
322  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
323  if (GV->hasDLLImportStorageClass())
325  if (getTargetTriple().isOSWindows())
327  return AArch64II::MO_GOT;
328  }
329 
330  // The small code model's direct accesses use ADRP, which cannot
331  // necessarily produce the value 0 (if the code is above 4GB).
332  // Same for the tiny code model, where we have a pc relative LDR.
333  if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
335  return AArch64II::MO_GOT;
336 
337  // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
338  // that their nominal addresses are tagged and outside of the code model. In
339  // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
340  // tag if necessary based on MO_TAGGED.
341  if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
343 
344  return AArch64II::MO_NO_FLAG;
345 }
346 
348  const GlobalValue *GV, const TargetMachine &TM) const {
349  // MachO large model always goes via a GOT, because we don't have the
350  // relocations available to do anything else..
351  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
352  !GV->hasInternalLinkage())
353  return AArch64II::MO_GOT;
354 
355  // NonLazyBind goes via GOT unless we know it's available locally.
356  auto *F = dyn_cast<Function>(GV);
357  if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
358  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
359  return AArch64II::MO_GOT;
360 
361  // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
362  if (getTargetTriple().isOSWindows())
363  return ClassifyGlobalReference(GV, TM);
364 
365  return AArch64II::MO_NO_FLAG;
366 }
367 
369  unsigned NumRegionInstrs) const {
370  // LNT run (at least on Cyclone) showed reasonably significant gains for
371  // bi-directional scheduling. 253.perlbmk.
372  Policy.OnlyTopDown = false;
373  Policy.OnlyBottomUp = false;
374  // Enabling or Disabling the latency heuristic is a close call: It seems to
375  // help nearly no benchmark on out-of-order architectures, on the other hand
376  // it regresses register pressure on a few benchmarking.
377  Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
378 }
379 
381  return EnableEarlyIfConvert;
382 }
383 
386  return false;
387 
389  return true;
390  if (TargetTriple.isiOS()) {
391  return TargetTriple.getiOSVersion() >= VersionTuple(8);
392  }
393 
394  return false;
395 }
396 
397 std::unique_ptr<PBQPRAConstraint>
399  return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
400 }
401 
403  // We usually compute max call frame size after ISel. Do the computation now
404  // if the .mir file didn't specify it. Note that this will probably give you
405  // bogus values after PEI has eliminated the callframe setup/destroy pseudo
406  // instructions, specify explicitly if you need it to be correct.
407  MachineFrameInfo &MFI = MF.getFrameInfo();
408  if (!MFI.isMaxCallFrameSizeComputed())
409  MFI.computeMaxCallFrameSize(MF);
410 }
411 
412 bool AArch64Subtarget::useAA() const { return UseAA; }
AArch64LegalizerInfo.h
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:52
llvm::MachineSchedPolicy::OnlyBottomUp
bool OnlyBottomUp
Definition: MachineScheduler.h:189
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:46
llvm::MachineFrameInfo::isMaxCallFrameSizeComputed
bool isMaxCallFrameSizeComputed() const
Definition: MachineFrameInfo.h:653
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::AArch64RegisterBankInfo
This class provides the information for the target register banks.
Definition: AArch64RegisterBankInfo.h:104
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:384
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AArch64Subtarget::getVectorInsertExtractBaseCost
unsigned getVectorInsertExtractBaseCost() const
Definition: AArch64Subtarget.cpp:59
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:89
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:78
AArch64.h
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:108
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:55
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:80
AArch64RegisterBankInfo.h
AArch64TargetParser.h
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:83
llvm::AArch64Subtarget::CortexX1C
@ CortexX1C
Definition: AArch64Subtarget.h:67
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:61
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:135
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:57
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:131
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:74
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:260
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:60
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:99
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:133
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::Triple::isDriverKit
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:495
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:103
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:100
InstructionSelect.h
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:50
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:79
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:84
llvm::AArch64Subtarget::CortexX2
@ CortexX2
Definition: AArch64Subtarget.h:68
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:47
llvm::AArch64Subtarget::MaxBytesForLoopAlignment
unsigned MaxBytesForLoopAlignment
Definition: AArch64Subtarget.h:107
TargetParser.h
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:106
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:62
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:73
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:451
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:168
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:76
AArch64PBQPRegAlloc.h
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:398
GlobalValue.h
AArch64TargetMachine.h
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:296
AArch64InstrInfo.h
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:300
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::Legalizer
Definition: Legalizer.h:36
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:101
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:380
llvm::AArch64Subtarget::Neoverse512TVB
@ Neoverse512TVB
Definition: AArch64Subtarget.h:75
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:402
llvm::MachineSchedPolicy::DisableLatencyHeuristic
bool DisableLatencyHeuristic
Definition: MachineScheduler.h:193
AArch64GenSubtargetInfo
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:23
llvm::VersionTuple
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:31
llvm::AArch64Subtarget::VScaleForTuning
unsigned VScaleForTuning
Definition: AArch64Subtarget.h:120
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:63
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:448
UseNonLazyBind
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
UseAddressTopByteIgnored
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
llvm::Triple::getiOSVersion
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
Definition: Triple.cpp:1235
llvm::AArch64::isX18ReservedByDefault
bool isX18ReservedByDefault(const Triple &TT)
Definition: AArch64TargetParser.cpp:172
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:105
AArch64AddressingModes.h
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:66
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:82
llvm::cl::opt< bool >
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:292
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:111
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: AArch64BaseInfo.h:732
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:59
AArch64CallLowering.h
llvm::AArch64Subtarget::Ampere1
@ Ampere1
Definition: AArch64Subtarget.h:43
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:577
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:266
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition: AArch64BaseInfo.h:721
llvm::MachineFrameInfo::computeMaxCallFrameSize
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
Definition: MachineFrameInfo.cpp:187
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:49
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:673
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:72
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:92
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: AArch64Subtarget.cpp:347
llvm::AArch64Subtarget::CortexA710
@ CortexA710
Definition: AArch64Subtarget.h:64
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:180
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:476
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:44
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:81
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:51
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:53
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:172
llvm::AArch64CallLowering
Definition: AArch64CallLowering.h:30
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:308
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:69
llvm::MachineSchedPolicy::OnlyTopDown
bool OnlyTopDown
Definition: MachineScheduler.h:188
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:315
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:132
llvm::AArch64LegalizerInfo
This class provides the information for the target register banks.
Definition: AArch64LegalizerInfo.h:27
MachineFrameInfo.h
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:102
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:104
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:251
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
MachineScheduler.h
AArch64Subtarget.h
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:58
UseAA
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:77
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:123
llvm::GlobalValue::hasDLLImportStorageClass
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:258
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:304
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
llvm::GlobalValue::getValueType
Type * getValueType() const
Definition: GlobalValue.h:272
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::CortexA510
@ CortexA510
Definition: AArch64Subtarget.h:54
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:65
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: AArch64BaseInfo.h:711
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:179
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:748
llvm::cl::desc
Definition: CommandLine.h:405
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64InstructionSelector
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
Definition: AArch64InstructionSelector.cpp:6925
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:412
llvm::CallLowering
Definition: CallLowering.h:44
EnableEarlyIfConvert
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:716
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:70
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:368
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:45
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:48
OverrideVectorInsertExtractBaseCost
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:56