31#define DEBUG_TYPE "aarch64-subtarget"
33#define GET_SUBTARGETINFO_CTOR
34#define GET_SUBTARGETINFO_TARGET_DESC
35#include "AArch64GenSubtargetInfo.inc"
48 cl::desc(
"Call nonlazybind functions via direct GOT load"),
52 cl::desc(
"Enable the use of AA during codegen."));
55 "aarch64-insert-extract-base-cost",
63 "registers, so they can't be used by register allocator. "
64 "Should only be used for testing register allocator."),
68 "force-streaming-compatible-sve",
70 "Force the use of streaming-compatible SVE code for all functions"),
83 if (CPUString.
empty())
84 CPUString =
"generic";
86 if (TuneCPUString.
empty())
87 TuneCPUString = CPUString;
90 initializeProperties();
95void AArch64Subtarget::initializeProperties() {
293 unsigned MinSVEVectorSizeInBitsOverride,
294 unsigned MaxSVEVectorSizeInBitsOverride,
295 bool StreamingSVEMode,
296 bool StreamingCompatibleSVEMode)
298 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
299 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
300 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
301 IsLittle(LittleEndian),
302 StreamingSVEMode(StreamingSVEMode),
303 StreamingCompatibleSVEMode(StreamingCompatibleSVEMode),
304 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
305 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
306 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
328 for (
unsigned i = 0; i < 29; ++i) {
329 if (ReservedRegNames.
count(
TRI->getName(AArch64::X0 + i)))
333 if (ReservedRegNames.
count(
"X30") || ReservedRegNames.
count(
"LR"))
336 if (ReservedRegNames.
count(
"X29") || ReservedRegNames.
count(
"FP"))
377 if (!
TM.shouldAssumeDSOLocal(*GV->
getParent(), GV)) {
399 if (AllowTaggedGlobals && !isa<FunctionType>(GV->
getValueType()))
414 auto *
F = dyn_cast<Function>(GV);
435 unsigned NumRegionInstrs)
const {
463std::unique_ptr<PBQPRAConstraint>
465 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() :
nullptr;
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for AArch64.
This file declares the targeting of the RegisterBankInfo class for AArch64.
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
static cl::opt< bool > ForceStreamingCompatibleSVE("force-streaming-compatible-sve", cl::desc("Force the use of streaming-compatible SVE code for all functions"), cl::Hidden)
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This class provides the information for the target register banks.
This class provides the information for the target register banks.
BitVector ReserveXRegisterForRA
BitVector ReserveXRegister
const CallLowering * getCallLowering() const override
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
std::unique_ptr< InstructionSelector > InstSelector
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEMode=false, bool StreamingCompatibleSVEMode=false)
This constructor initializes the data members to match that of the specified triple.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSmallAddressing() const
bool isStreamingCompatible() const
Returns true if the function has a streaming-compatible body.
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned MaxPrefetchIterationsAhead
unsigned getVectorInsertExtractBaseCost() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
uint8_t VectorInsertExtractBaseCost
const AArch64TargetLowering * getTargetLowering() const override
bool isTargetMachO() const
uint16_t PrefetchDistance
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
bool StreamingCompatibleSVEMode
Align PrefFunctionAlignment
const Triple & getTargetTriple() const
unsigned MinVectorRegisterBitWidth
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
uint16_t MinPrefetchStride
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned MaxJumpTableSize
bool isWindowsArm64EC() const
bool isStreaming() const
Returns true if the function has a streaming body.
bool isSVEAvailable() const
Returns true if the target has SVE and can use the full range of SVE instructions,...
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
uint8_t MaxInterleaveFactor
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxBytesForLoopAlignment
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
bool hasExternalWeakLinkage() const
bool hasDLLImportStorageClass() const
Module * getParent()
Get the module that this global value is contained inside of...
bool hasInternalLinkage() const
Type * getValueType() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
bool isMaxCallFrameSizeComputed() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Holds all the information related to register banks.
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
StringSet - A wrapper for StringMap that provides set-like functionality.
std::pair< typename Base::iterator, bool > insert(StringRef key)
Primary interface to the complete machine description for the target machine.
Triple - Helper class for working with autoconf configuration names.
bool isDriverKit() const
Is this an Apple DriverKit triple.
bool isiOS() const
Is this an iOS triple.
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
bool isFunctionTy() const
True if this is an instance of FunctionType.
Represents a version number in the form major[.minor[.subminor[.build]]].
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_DLLIMPORTAUX
MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub.
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
bool isX18ReservedByDefault(const Triple &TT)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
bool DisableLatencyHeuristic