LLVM 20.0.0git
AArch64Subtarget.cpp
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1//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Subtarget.h"
14
15#include "AArch64.h"
16#include "AArch64InstrInfo.h"
17#include "AArch64PBQPRegAlloc.h"
26#include "llvm/IR/GlobalValue.h"
29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-subtarget"
33
34#define GET_SUBTARGETINFO_CTOR
35#define GET_SUBTARGETINFO_TARGET_DESC
36#include "AArch64GenSubtargetInfo.inc"
37
38static cl::opt<bool>
39EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
40 "converter pass"), cl::init(true), cl::Hidden);
41
42// If OS supports TBI, use this flag to enable it.
43static cl::opt<bool>
44UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
45 "an address is ignored"), cl::init(false), cl::Hidden);
46
48 "aarch64-macho-enable-nonlazybind",
49 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),
51
52static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
53 cl::desc("Enable the use of AA during codegen."));
54
56 "aarch64-insert-extract-base-cost",
57 cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
58
59// Reserve a list of X# registers, so they are unavailable for register
60// allocator, but can still be used as ABI requests, such as passing arguments
61// to function call.
63ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
64 "registers, so they can't be used by register allocator. "
65 "Should only be used for testing register allocator."),
67
69 AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",
71 cl::desc("Override the variant of check applied "
72 "to authenticated LR during tail call"),
74
76 "aarch64-min-jump-table-entries", cl::init(13), cl::Hidden,
77 cl::desc("Set minimum number of entries to use a jump table on AArch64"));
78
80 "aarch64-streaming-hazard-size",
81 cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."),
83
85 "aarch64-stack-hazard-size",
86 cl::desc("alias for -aarch64-streaming-hazard-size"),
88
89// Subreg liveness tracking is disabled by default for now until all issues
90// are ironed out. This option allows the feature to be used in tests.
91static cl::opt<bool>
92 EnableSubregLivenessTracking("aarch64-enable-subreg-liveness-tracking",
93 cl::init(false), cl::Hidden,
94 cl::desc("Enable subreg liveness tracking"));
95
96static cl::opt<bool>
97 UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden,
98 cl::desc("Prefer add+cnt over addvl/inc/dec"));
99
101 if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
104}
105
106AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
107 StringRef FS, StringRef CPUString, StringRef TuneCPUString,
108 bool HasMinSize) {
109 // Determine default and user-specified characteristics
110
111 if (CPUString.empty())
112 CPUString = "generic";
113
114 if (TuneCPUString.empty())
115 TuneCPUString = CPUString;
116
117 ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
118 initializeProperties(HasMinSize);
119
120 return *this;
121}
122
123void AArch64Subtarget::initializeProperties(bool HasMinSize) {
124 // Initialize CPU specific properties. We should add a tablegen feature for
125 // this in the future so we can specify it together with the subtarget
126 // features.
127 switch (ARMProcFamily) {
128 case Others:
129 break;
130 case Carmel:
131 CacheLineSize = 64;
132 break;
133 case CortexA35:
134 case CortexA53:
135 case CortexA55:
136 case CortexR82:
137 case CortexR82AE:
141 break;
142 case CortexA57:
147 break;
148 case CortexA65:
150 break;
151 case CortexA72:
152 case CortexA73:
153 case CortexA75:
157 break;
158 case CortexA76:
159 case CortexA77:
160 case CortexA78:
161 case CortexA78AE:
162 case CortexA78C:
163 case CortexX1:
167 break;
168 case CortexA510:
169 case CortexA520:
171 VScaleForTuning = 1;
174 break;
175 case CortexA710:
176 case CortexA715:
177 case CortexA720:
178 case CortexA725:
179 case CortexX2:
180 case CortexX3:
181 case CortexX4:
182 case CortexX925:
184 VScaleForTuning = 1;
187 break;
188 case A64FX:
189 CacheLineSize = 256;
193 PrefetchDistance = 128;
194 MinPrefetchStride = 1024;
196 VScaleForTuning = 4;
197 break;
198 case MONAKA:
199 VScaleForTuning = 2;
200 break;
201 case AppleA7:
202 case AppleA10:
203 case AppleA11:
204 case AppleA12:
205 case AppleA13:
206 case AppleA14:
207 case AppleA15:
208 case AppleA16:
209 case AppleA17:
210 case AppleM4:
211 CacheLineSize = 64;
212 PrefetchDistance = 280;
213 MinPrefetchStride = 2048;
215 switch (ARMProcFamily) {
216 case AppleA14:
217 case AppleA15:
218 case AppleA16:
219 case AppleA17:
220 case AppleM4:
222 break;
223 default:
224 break;
225 }
226 break;
227 case ExynosM3:
229 MaxJumpTableSize = 20;
232 break;
233 case Falkor:
235 // FIXME: remove this to enable 64-bit SLP if performance looks good.
237 CacheLineSize = 128;
238 PrefetchDistance = 820;
239 MinPrefetchStride = 2048;
241 break;
242 case Kryo:
245 CacheLineSize = 128;
246 PrefetchDistance = 740;
247 MinPrefetchStride = 1024;
249 // FIXME: remove this to enable 64-bit SLP if performance looks good.
251 break;
252 case NeoverseE1:
254 break;
255 case NeoverseN1:
259 break;
260 case NeoverseV2:
261 case NeoverseV3:
264 ScatterOverhead = 13;
266 case NeoverseN2:
267 case NeoverseN3:
271 VScaleForTuning = 1;
272 break;
273 case NeoverseV1:
277 VScaleForTuning = 2;
279 break;
280 case Neoverse512TVB:
282 VScaleForTuning = 1;
284 break;
285 case Saphira:
287 // FIXME: remove this to enable 64-bit SLP if performance looks good.
289 break;
290 case ThunderX2T99:
291 CacheLineSize = 64;
295 PrefetchDistance = 128;
296 MinPrefetchStride = 1024;
298 // FIXME: remove this to enable 64-bit SLP if performance looks good.
300 break;
301 case ThunderX:
302 case ThunderXT88:
303 case ThunderXT81:
304 case ThunderXT83:
305 CacheLineSize = 128;
308 // FIXME: remove this to enable 64-bit SLP if performance looks good.
310 break;
311 case TSV110:
312 CacheLineSize = 64;
315 break;
316 case ThunderX3T110:
317 CacheLineSize = 64;
321 PrefetchDistance = 128;
322 MinPrefetchStride = 1024;
324 // FIXME: remove this to enable 64-bit SLP if performance looks good.
326 break;
327 case Ampere1:
328 case Ampere1A:
329 case Ampere1B:
330 CacheLineSize = 64;
334 break;
335 case Oryon:
336 CacheLineSize = 64;
339 PrefetchDistance = 128;
340 MinPrefetchStride = 1024;
341 break;
342 }
343
344 if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)
346}
347
349 StringRef TuneCPU, StringRef FS,
350 const TargetMachine &TM, bool LittleEndian,
351 unsigned MinSVEVectorSizeInBitsOverride,
352 unsigned MaxSVEVectorSizeInBitsOverride,
353 bool IsStreaming, bool IsStreamingCompatible,
354 bool HasMinSize)
355 : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
356 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
357 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
358 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
359 IsLittle(LittleEndian), IsStreaming(IsStreaming),
360 IsStreamingCompatible(IsStreamingCompatible),
361 StreamingHazardSize(AArch64StreamingHazardSize),
362 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
363 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
364 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),
365 TLInfo(TM, *this) {
368
371 Legalizer.reset(new AArch64LegalizerInfo(*this));
372
373 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
374
375 // FIXME: At this point, we can't rely on Subtarget having RBI.
376 // It's awkward to mix passing RBI and the Subtarget; should we pass
377 // TII/TRI as well?
379 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
380
381 RegBankInfo.reset(RBI);
382
383 auto TRI = getRegisterInfo();
384 StringSet<> ReservedRegNames;
385 ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end());
386 for (unsigned i = 0; i < 29; ++i) {
387 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
389 }
390 // X30 is named LR, so we can't use TRI->getName to check X30.
391 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))
393 // X29 is named FP, so we can't use TRI->getName to check X29.
394 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))
396
398}
399
401 return CallLoweringInfo.get();
402}
403
405 return InlineAsmLoweringInfo.get();
406}
407
409 return InstSelector.get();
410}
411
413 return Legalizer.get();
414}
415
417 return RegBankInfo.get();
418}
419
420/// Find the target operand flags that describe how a global value should be
421/// referenced for the current subtarget.
422unsigned
424 const TargetMachine &TM) const {
425 // MachO large model always goes via a GOT, simply to get a single 8-byte
426 // absolute relocation on all global addresses.
427 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
428 return AArch64II::MO_GOT;
429
430 // All globals dynamically protected by MTE must have their address tags
431 // synthesized. This is done by having the loader stash the tag in the GOT
432 // entry. Force all tagged globals (even ones with internal linkage) through
433 // the GOT.
434 if (GV->isTagged())
435 return AArch64II::MO_GOT;
436
437 if (!TM.shouldAssumeDSOLocal(GV)) {
438 if (GV->hasDLLImportStorageClass()) {
440 }
441 if (getTargetTriple().isOSWindows())
443 return AArch64II::MO_GOT;
444 }
445
446 // The small code model's direct accesses use ADRP, which cannot
447 // necessarily produce the value 0 (if the code is above 4GB).
448 // Same for the tiny code model, where we have a pc relative LDR.
449 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
451 return AArch64II::MO_GOT;
452
453 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
454 // that their nominal addresses are tagged and outside of the code model. In
455 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
456 // tag if necessary based on MO_TAGGED.
457 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
459
461}
462
464 const GlobalValue *GV, const TargetMachine &TM) const {
465 // MachO large model always goes via a GOT, because we don't have the
466 // relocations available to do anything else..
467 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
468 !GV->hasInternalLinkage())
469 return AArch64II::MO_GOT;
470
471 // NonLazyBind goes via GOT unless we know it's available locally.
472 auto *F = dyn_cast<Function>(GV);
473 if ((!isTargetMachO() || MachOUseNonLazyBind) && F &&
474 F->hasFnAttribute(Attribute::NonLazyBind) && !TM.shouldAssumeDSOLocal(GV))
475 return AArch64II::MO_GOT;
476
477 if (getTargetTriple().isOSWindows()) {
478 if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {
479 if (GV->hasDLLImportStorageClass()) {
480 // On Arm64EC, if we're calling a symbol from the import table
481 // directly, use MO_ARM64EC_CALLMANGLE.
484 }
485 if (GV->hasExternalLinkage()) {
486 // If we're calling a symbol directly, use the mangled form in the
487 // call instruction.
489 }
490 }
491
492 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
493 return ClassifyGlobalReference(GV, TM);
494 }
495
497}
498
500 unsigned NumRegionInstrs) const {
501 // LNT run (at least on Cyclone) showed reasonably significant gains for
502 // bi-directional scheduling. 253.perlbmk.
503 Policy.OnlyTopDown = false;
504 Policy.OnlyBottomUp = false;
505 // Enabling or Disabling the latency heuristic is a close call: It seems to
506 // help nearly no benchmark on out-of-order architectures, on the other hand
507 // it regresses register pressure on a few benchmarking.
508 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
509}
510
512 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep,
513 const TargetSchedModel *SchedModel) const {
514 if (!SchedModel || Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||
515 !Def->isInstr() || !Use->isInstr() ||
516 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&
517 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))
518 return;
519
520 // If the Def is a BUNDLE, find the last instruction in the bundle that defs
521 // the register.
522 const MachineInstr *DefMI = Def->getInstr();
523 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {
524 Register Reg = DefMI->getOperand(DefOpIdx).getReg();
525 for (const auto &Op : const_mi_bundle_ops(*DefMI)) {
526 if (Op.isReg() && Op.isDef() && Op.getReg() == Reg) {
527 DefMI = Op.getParent();
528 DefOpIdx = Op.getOperandNo();
529 }
530 }
531 }
532
533 // If the Use is a BUNDLE, find the first instruction that uses the Reg.
534 const MachineInstr *UseMI = Use->getInstr();
535 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) {
536 Register Reg = UseMI->getOperand(UseOpIdx).getReg();
537 for (const auto &Op : const_mi_bundle_ops(*UseMI)) {
538 if (Op.isReg() && Op.isUse() && Op.getReg() == Reg) {
539 UseMI = Op.getParent();
540 UseOpIdx = Op.getOperandNo();
541 break;
542 }
543 }
544 }
545
546 Dep.setLatency(
547 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx));
548}
549
552}
553
556 return false;
557
559 return true;
560 if (TargetTriple.isiOS()) {
562 }
563
564 return false;
565}
566
567std::unique_ptr<PBQPRAConstraint>
569 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
570}
571
573 // We usually compute max call frame size after ISel. Do the computation now
574 // if the .mir file didn't specify it. Note that this will probably give you
575 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
576 // instructions, specify explicitly if you need it to be correct.
577 MachineFrameInfo &MFI = MF.getFrameInfo();
580}
581
582bool AArch64Subtarget::useAA() const { return UseAA; }
583
585 // If SVE2 or SME is present (we are not SVE-1 only) and UseScalarIncVL
586 // is not otherwise set, enable it by default.
587 if (UseScalarIncVL.getNumOccurrences())
588 return UseScalarIncVL;
589 return hasSVE2() || hasSME();
590}
591
592// If return address signing is enabled, tail calls are emitted as follows:
593//
594// ```
595// <authenticate LR>
596// <check LR>
597// TCRETURN ; the callee may sign and spill the LR in its prologue
598// ```
599//
600// LR may require explicit checking because if FEAT_FPAC is not implemented
601// and LR was tampered with, then `<authenticate LR>` will not generate an
602// exception on its own. Later, if the callee spills the signed LR value and
603// neither FEAT_PAuth2 nor FEAT_EPAC are implemented, the valid PAC replaces
604// the higher bits of LR thus hiding the authentication failure.
606 const MachineFunction &MF) const {
607 // TODO: Check subtarget for the scheme. Present variant is a default for
608 // pauthtest ABI.
609 if (MF.getFunction().hasFnAttribute("ptrauth-returns") &&
610 MF.getFunction().hasFnAttribute("ptrauth-auth-traps"))
612 if (AuthenticatedLRCheckMethod.getNumOccurrences())
614
615 // At now, use None by default because checks may introduce an unexpected
616 // performance regression or incompatibility with execute-only mappings.
618}
619
620std::optional<uint16_t>
622 const Function &ParentFn) const {
623 if (!ParentFn.hasFnAttribute("ptrauth-indirect-gotos"))
624 return std::nullopt;
625 // We currently have one simple mechanism for all targets.
626 // This isn't ABI, so we can always do better in the future.
628 (Twine(ParentFn.getName()) + " blockaddress").str());
629}
630
632 return getSchedModel().hasInstrSchedModel();
633}
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
This file declares the targeting of the Machinelegalizer class for AArch64.
#define AUTH_CHECK_METHOD_CL_VALUES_LR
This file declares the targeting of the RegisterBankInfo class for AArch64.
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
static cl::opt< bool > MachOUseNonLazyBind("aarch64-macho-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"), cl::Hidden)
static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))
static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))
static cl::opt< bool > EnableSubregLivenessTracking("aarch64-enable-subreg-liveness-tracking", cl::init(false), cl::Hidden, cl::desc("Enable subreg liveness tracking"))
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > AArch64StreamingHazardSize("aarch64-streaming-hazard-size", cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."), cl::init(0), cl::Hidden)
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::alias AArch64StreamingStackHazardSize("aarch64-stack-hazard-size", cl::desc("alias for -aarch64-streaming-hazard-size"), cl::aliasopt(AArch64StreamingHazardSize))
static cl::opt< bool > UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden, cl::desc("Prefer add+cnt over addvl/inc/dec"))
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:388
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
This class provides the information for the target register banks.
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)
This constructor initializes the data members to match that of the specified triple.
const CallLowering * getCallLowering() const override
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSmallAddressing() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
std::optional< uint16_t > getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const
Compute the integer discriminator for a given BlockAddress constant, if blockaddress signing is enabl...
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
const Triple & getTargetTriple() const
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useScalarIncVL() const
Returns true to use the addvl/inc/dec instructions, as opposed to separate add + cnt instructions.
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod(const MachineFunction &MF) const
Choose a method of checking LR before performing a tail call.
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
BitVector & set()
Definition: BitVector.h:351
This class represents an Operation in the Expression.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:731
bool hasExternalLinkage() const
Definition: GlobalValue.h:511
bool isTagged() const
Definition: GlobalValue.h:365
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:529
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:278
bool hasInternalLinkage() const
Definition: GlobalValue.h:526
Type * getValueType() const
Definition: GlobalValue.h:296
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void computeMaxCallFrameSize(MachineFunction &MF, std::vector< MachineBasicBlock::iterator > *FrameSDOps=nullptr)
Computes the maximum size of a callframe.
bool isMaxCallFrameSizeComputed() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:575
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:585
Register getReg() const
getReg - Returns the register number.
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Scheduling dependency.
Definition: ScheduleDAG.h:49
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:504
@ Data
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
unsigned getReg() const
Returns the register associated with this edge.
Definition: ScheduleDAG.h:218
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
Definition: StringMap.h:276
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:147
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:38
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
Provide an instruction scheduling machine model to CodeGen passes.
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:563
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:541
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
Definition: Triple.cpp:1439
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool isFunctionTy() const
True if this is an instance of FunctionType.
Definition: Type.h:255
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:29
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
AuthCheckMethod
Variants of check performed on an authenticated pointer.
@ HighBitsNoTBI
Check by comparing bits 62 and 61 of the authenticated address.
@ None
Do not check the value at all.
bool isX18ReservedByDefault(const Triple &TT)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:711
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
@ CommaSeparated
Definition: CommandLine.h:163
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, const AArch64Subtarget &, const AArch64RegisterBankInfo &)
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
uint16_t getPointerAuthStableSipHash(StringRef S)
Compute a stable non-zero 16-bit hash of the given string.
Definition: SipHash.cpp:168
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.