LLVM 20.0.0git
AArch64TargetParser.h
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1//===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise AArch64 hardware features
10// such as FPU/CPU/ARCH and extension names.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGETPARSER_AARCH64TARGETPARSER_H
15#define LLVM_TARGETPARSER_AARCH64TARGETPARSER_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/Bitset.h"
19#include "llvm/ADT/StringMap.h"
20#include "llvm/ADT/StringRef.h"
24#include <array>
25#include <set>
26#include <vector>
27
28namespace llvm {
29
30class Triple;
31
32namespace AArch64 {
33
34struct ArchInfo;
35struct CpuInfo;
36
38
39static_assert(FEAT_MAX < 62,
40 "Number of features in CPUFeatures are limited to 62 entries");
41
42// Each ArchExtKind correponds directly to a possible -target-feature.
43#define EMIT_ARCHEXTKIND_ENUM
44#include "llvm/TargetParser/AArch64TargetParserDef.inc"
45
47
48// Represents an extension that can be enabled with -march=<arch>+<extension>.
49// Typically these correspond to Arm Architecture extensions, unlike
50// SubtargetFeature which may represent either an actual extension or some
51// internal LLVM property.
53 StringRef UserVisibleName; // Human readable name used in -march, -cpu
54 // and target func attribute, e.g. "profile".
55 std::optional<StringRef> Alias; // An alias for this extension, if one exists.
56 ArchExtKind ID; // Corresponding to the ArchExtKind, this
57 // extensions representation in the bitfield.
58 StringRef ArchFeatureName; // The feature name defined by the
59 // Architecture, e.g. FEAT_AdvSIMD.
60 StringRef Description; // The textual description of the extension.
61 StringRef PosTargetFeature; // -target-feature/-mattr enable string,
62 // e.g. "+spe".
63 StringRef NegTargetFeature; // -target-feature/-mattr disable string,
64 // e.g. "-spe".
65};
66
67#define EMIT_EXTENSIONS
68#include "llvm/TargetParser/AArch64TargetParserDef.inc"
69
70struct FMVInfo {
71 StringRef Name; // The target_version/target_clones spelling.
72 CPUFeatures Bit; // Index of the bit in the FMV feature bitset.
73 StringRef Features; // List of SubtargetFeatures to enable.
74 unsigned Priority; // FMV priority.
76 unsigned Priority)
78
81 Features.split(Feats, ',', -1, false); // discard empty strings
82 return Feats;
83 }
84};
85
86const std::vector<FMVInfo> &getFMVInfo();
87
88// Represents a dependency between two architecture extensions. Later is the
89// feature which was added to the architecture after Earlier, and expands the
90// functionality provided by it. If Later is enabled, then Earlier will also be
91// enabled. If Earlier is disabled, then Later will also be disabled.
93 ArchExtKind Earlier;
94 ArchExtKind Later;
95};
96
97#define EMIT_EXTENSION_DEPENDENCIES
98#include "llvm/TargetParser/AArch64TargetParserDef.inc"
99
100enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' };
101
102// Information about a specific architecture, e.g. V8.1-A
103struct ArchInfo {
104 VersionTuple Version; // Architecture version, major + minor.
105 ArchProfile Profile; // Architecuture profile
106 StringRef Name; // Name as supplied to -march e.g. "armv8.1-a"
107 StringRef ArchFeature; // Name as supplied to -target-feature, e.g. "+v8a"
109 DefaultExts; // bitfield of default extensions ArchExtKind
110
111 bool operator==(const ArchInfo &Other) const {
112 return this->Name == Other.Name;
113 }
114 bool operator!=(const ArchInfo &Other) const {
115 return this->Name != Other.Name;
116 }
117
118 // Defines the following partial order, indicating when an architecture is
119 // a superset of another:
120 //
121 // v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a;
122 // v v v v v
123 // v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a;
124 //
125 // v8r has no relation to anything. This is used to determine which
126 // features to enable for a given architecture. See
127 // AArch64TargetInfo::setFeatureEnabled.
128 bool implies(const ArchInfo &Other) const {
129 if (this->Profile != Other.Profile)
130 return false; // ARMV8R
131 if (this->Version.getMajor() == Other.Version.getMajor()) {
132 return this->Version > Other.Version;
133 }
134 if (this->Version.getMajor() == 9 && Other.Version.getMajor() == 8) {
135 assert(this->Version.getMinor() && Other.Version.getMinor() &&
136 "AArch64::ArchInfo should have a minor version.");
137 return this->Version.getMinor().value_or(0) + 5 >=
138 Other.Version.getMinor().value_or(0);
139 }
140 return false;
141 }
142
143 // True if this architecture is a superset of Other (including being equal to
144 // it).
145 bool is_superset(const ArchInfo &Other) const {
146 return (*this == Other) || implies(Other);
147 }
148
149 // Return ArchFeature without the leading "+".
150 StringRef getSubArch() const { return ArchFeature.substr(1); }
151
152 // Search for ArchInfo by SubArch name
153 static std::optional<ArchInfo> findBySubArch(StringRef SubArch);
154};
155
156#define EMIT_ARCHITECTURES
157#include "llvm/TargetParser/AArch64TargetParserDef.inc"
158
159// Details of a specific CPU.
160struct CpuInfo {
161 StringRef Name; // Name, as written for -mcpu.
164 DefaultExtensions; // Default extensions for this CPU.
165
167 return DefaultExtensions;
168 }
169};
170
171#define EMIT_CPU_INFO
172#include "llvm/TargetParser/AArch64TargetParserDef.inc"
173
175 // Set of extensions which are currently enabled.
177 // Set of extensions which have been enabled or disabled at any point. Used
178 // to avoid cluttering the cc1 command-line with lots of unneeded features.
180 // Base architecture version, which we need to know because some feature
181 // dependencies change depending on this.
183
184 ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {}
185
186 // Enable the given architecture extension, and any other extensions it
187 // depends on. Does not change the base architecture, or follow dependencies
188 // between features which are only related by required arcitecture versions.
189 void enable(ArchExtKind E);
190
191 // Disable the given architecture extension, and any other extensions which
192 // depend on it. Does not change the base architecture, or follow
193 // dependencies between features which are only related by required
194 // arcitecture versions.
195 void disable(ArchExtKind E);
196
197 // Add default extensions for the given CPU. Records the base architecture,
198 // to later resolve dependencies which depend on it.
199 void addCPUDefaults(const CpuInfo &CPU);
200
201 // Add default extensions for the given architecture version. Records the
202 // base architecture, to later resolve dependencies which depend on it.
203 void addArchDefaults(const ArchInfo &Arch);
204
205 // Add or remove a feature based on a modifier string. The string must be of
206 // the form "<name>" to enable a feature or "no<name>" to disable it. This
207 // will also enable or disable any features as required by the dependencies
208 // between them.
209 bool parseModifier(StringRef Modifier, const bool AllowNoDashForm = false);
210
211 // Constructs a new ExtensionSet by toggling the corresponding bits for every
212 // feature in the \p Features list without expanding their dependencies. Used
213 // for reconstructing an ExtensionSet from the output of toLLVMFeatures().
214 // Features that are not recognized are pushed back to \p NonExtensions.
215 void reconstructFromParsedFeatures(const std::vector<std::string> &Features,
216 std::vector<std::string> &NonExtensions);
217
218 // Convert the set of enabled extension to an LLVM feature list, appending
219 // them to Features.
220 template <typename T> void toLLVMFeatureList(std::vector<T> &Features) const {
222 Features.emplace_back(T(BaseArch->ArchFeature));
223
224 for (const auto &E : Extensions) {
225 if (E.PosTargetFeature.empty() || !Touched.test(E.ID))
226 continue;
227 if (Enabled.test(E.ID))
228 Features.emplace_back(T(E.PosTargetFeature));
229 else
230 Features.emplace_back(T(E.NegTargetFeature));
231 }
232 }
233
234 void dump() const;
235};
236
237// Name alias.
238struct Alias {
241};
242
243#define EMIT_CPU_ALIAS
244#include "llvm/TargetParser/AArch64TargetParserDef.inc"
245
246const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID));
247
250 std::vector<StringRef> &Features);
251
254
255// Information by Name
257
258// Parser
259const ArchInfo *parseArch(StringRef Arch);
260
261// Return the extension which has the given -target-feature name.
262std::optional<ExtensionInfo> targetFeatureToExtension(StringRef TargetFeature);
263
264// Parse a name as defined by the Extension class in tablegen.
265std::optional<ExtensionInfo> parseArchExtension(StringRef Extension);
266
267// Parse a name as defined by the FMVInfo class in tablegen.
268std::optional<FMVInfo> parseFMVExtension(StringRef Extension);
269
270// Given the name of a CPU or alias, return the correponding CpuInfo.
271std::optional<CpuInfo> parseCpu(StringRef Name);
272// Used by target parser tests
274
275bool isX18ReservedByDefault(const Triple &TT);
276
277// For given feature names, return a bitmask corresponding to the entries of
278// AArch64::CPUFeatures. The values in CPUFeatures are not bitmasks
279// themselves, they are sequential (0, 1, 2, 3, ...).
281
283
284void printEnabledExtensions(const std::set<StringRef> &EnabledFeatureNames);
285
286} // namespace AArch64
287} // namespace llvm
288
289#endif
This file defines the StringMap class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::string Name
#define T
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< std::set< SPIRV::Extension::Extension >, false, SPIRVExtensionsParser > Extensions("spirv-ext", cl::desc("Specify list of enabled SPIR-V extensions"))
Defines the llvm::VersionTuple class, which represents a version in the form major[....
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
constexpr bool test(unsigned I) const
Definition: Bitset.h:77
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:587
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:685
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:556
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:29
unsigned getMajor() const
Retrieve the major version number.
Definition: VersionTuple.h:71
std::optional< unsigned > getMinor() const
Retrieve the minor version number, if provided.
Definition: VersionTuple.h:74
bool isX18ReservedByDefault(const Triple &TT)
StringRef getArchExtFeature(StringRef ArchExt)
std::optional< ExtensionInfo > parseArchExtension(StringRef Extension)
std::optional< CpuInfo > parseCpu(StringRef Name)
uint64_t getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
const ArchInfo * parseArch(StringRef Arch)
const ArchInfo * getArchForCpu(StringRef CPU)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
const ExtensionInfo & getExtensionByID(ArchExtKind(ExtID))
void printEnabledExtensions(const std::set< StringRef > &EnabledFeatureNames)
std::optional< FMVInfo > parseFMVExtension(StringRef Extension)
const std::vector< FMVInfo > & getFMVInfo()
std::optional< ExtensionInfo > targetFeatureToExtension(StringRef TargetFeature)
StringRef resolveCPUAlias(StringRef CPU)
bool getExtensionFeatures(const AArch64::ExtensionBitset &Extensions, std::vector< StringRef > &Features)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.
bool is_superset(const ArchInfo &Other) const
StringRef getSubArch() const
bool implies(const ArchInfo &Other) const
AArch64::ExtensionBitset DefaultExts
static std::optional< ArchInfo > findBySubArch(StringRef SubArch)
bool operator==(const ArchInfo &Other) const
bool operator!=(const ArchInfo &Other) const
AArch64::ExtensionBitset getImpliedExtensions() const
AArch64::ExtensionBitset DefaultExtensions
std::optional< StringRef > Alias
bool parseModifier(StringRef Modifier, const bool AllowNoDashForm=false)
void addCPUDefaults(const CpuInfo &CPU)
void toLLVMFeatureList(std::vector< T > &Features) const
void addArchDefaults(const ArchInfo &Arch)
void reconstructFromParsedFeatures(const std::vector< std::string > &Features, std::vector< std::string > &NonExtensions)
FMVInfo(StringRef Name, CPUFeatures Bit, StringRef Features, unsigned Priority)
SmallVector< StringRef, 8 > getImpliedFeatures()