LLVM 19.0.0git
InstructionSelector.h
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1//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the API for the instruction selector.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
14#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
15
17
18namespace llvm {
20public:
22
23 /// Select the (possibly generic) instruction \p I to only use target-specific
24 /// opcodes. It is OK to insert multiple instructions, but they cannot be
25 /// generic pre-isel instructions.
26 ///
27 /// \returns whether selection succeeded.
28 /// \pre I.getParent() && I.getParent()->getParent()
29 /// \post
30 /// if returns true:
31 /// for I in all mutated/inserted instructions:
32 /// !isPreISelGenericOpcode(I.getOpcode())
33 virtual bool select(MachineInstr &I) = 0;
34
36
38
39protected:
40 const TargetPassConfig *TPC = nullptr;
42};
43} // namespace llvm
44
45#endif
#define I(x, y, z)
Definition: MD5.cpp:58
#define T
Provides the logic to execute GlobalISel match tables, which are used by the instruction selector and...
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
const TargetPassConfig * TPC
MachineOptimizationRemarkEmitter * MORE
void setTargetPassConfig(const TargetPassConfig *T)
void setRemarkEmitter(MachineOptimizationRemarkEmitter *M)
Representation of each machine instruction.
Definition: MachineInstr.h:68
Target-Independent Code Generator Pass Configuration Options.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18