LLVM 19.0.0git
AArch64InstrInfo.h
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1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15
16#include "AArch64.h"
17#include "AArch64RegisterInfo.h"
20#include <optional>
21
22#define GET_INSTRINFO_HEADER
23#include "AArch64GenInstrInfo.inc"
24
25namespace llvm {
26
27class AArch64Subtarget;
28
33
34#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
35
37 const AArch64RegisterInfo RI;
38 const AArch64Subtarget &Subtarget;
39
40public:
41 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
42
43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44 /// such, whenever a client has an instance of instruction info, it should
45 /// always be able to get register info as well (through this method).
46 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
47
48 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
49
50 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
51
52 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
53 Register &DstReg, unsigned &SubIdx) const override;
54
55 bool
57 const MachineInstr &MIb) const override;
58
60 int &FrameIndex) const override;
62 int &FrameIndex) const override;
63
64 /// Does this instruction set its full destination register to zero?
65 static bool isGPRZero(const MachineInstr &MI);
66
67 /// Does this instruction rename a GPR without modifying bits?
68 static bool isGPRCopy(const MachineInstr &MI);
69
70 /// Does this instruction rename an FPR without modifying bits?
71 static bool isFPRCopy(const MachineInstr &MI);
72
73 /// Return true if pairing the given load or store is hinted to be
74 /// unprofitable.
75 static bool isLdStPairSuppressed(const MachineInstr &MI);
76
77 /// Return true if the given load or store is a strided memory access.
78 static bool isStridedAccess(const MachineInstr &MI);
79
80 /// Return true if it has an unscaled load/store offset.
81 static bool hasUnscaledLdStOffset(unsigned Opc);
83 return hasUnscaledLdStOffset(MI.getOpcode());
84 }
85
86 /// Returns the unscaled load/store for the scaled load/store opcode,
87 /// if there is a corresponding unscaled variant available.
88 static std::optional<unsigned> getUnscaledLdSt(unsigned Opc);
89
90 /// Scaling factor for (scaled or unscaled) load or store.
91 static int getMemScale(unsigned Opc);
92 static int getMemScale(const MachineInstr &MI) {
93 return getMemScale(MI.getOpcode());
94 }
95
96 /// Returns whether the instruction is a pre-indexed load.
97 static bool isPreLd(const MachineInstr &MI);
98
99 /// Returns whether the instruction is a pre-indexed store.
100 static bool isPreSt(const MachineInstr &MI);
101
102 /// Returns whether the instruction is a pre-indexed load/store.
103 static bool isPreLdSt(const MachineInstr &MI);
104
105 /// Returns whether the instruction is a paired load/store.
106 static bool isPairedLdSt(const MachineInstr &MI);
107
108 /// Returns the base register operator of a load/store.
109 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI);
110
111 /// Returns the immediate offset operator of a load/store.
112 static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI);
113
114 /// Returns whether the instruction is FP or NEON.
115 static bool isFpOrNEON(const MachineInstr &MI);
116
117 /// Returns whether the instruction is in H form (16 bit operands)
118 static bool isHForm(const MachineInstr &MI);
119
120 /// Returns whether the instruction is in Q form (128 bit operands)
121 static bool isQForm(const MachineInstr &MI);
122
123 /// Returns whether the instruction can be compatible with non-zero BTYPE.
124 static bool hasBTISemantics(const MachineInstr &MI);
125
126 /// Returns the index for the immediate for a given instruction.
127 static unsigned getLoadStoreImmIdx(unsigned Opc);
128
129 /// Return true if pairing the given load or store may be paired with another.
130 static bool isPairableLdStInst(const MachineInstr &MI);
131
132 /// Returns true if MI is one of the TCRETURN* instructions.
133 static bool isTailCallReturnInst(const MachineInstr &MI);
134
135 /// Return the opcode that set flags when possible. The caller is
136 /// responsible for ensuring the opc has a flag setting equivalent.
137 static unsigned convertToFlagSettingOpc(unsigned Opc);
138
139 /// Return true if this is a load/store that can be potentially paired/merged.
140 bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
141
142 /// Hint that pairing the given load or store is unprofitable.
143 static void suppressLdStPair(MachineInstr &MI);
144
145 std::optional<ExtAddrMode>
147 const TargetRegisterInfo *TRI) const override;
148
150 const MachineInstr &AddrI,
151 ExtAddrMode &AM) const override;
152
154 const ExtAddrMode &AM) const override;
155
158 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
159 const TargetRegisterInfo *TRI) const override;
160
161 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
162 /// This is true for some SVE instructions like ldr/str that have a
163 /// 'reg + imm' addressing mode where the immediate is an index to the
164 /// scalable vector located at 'reg + imm * vscale x #bytes'.
166 const MachineOperand *&BaseOp,
167 int64_t &Offset, bool &OffsetIsScalable,
168 TypeSize &Width,
169 const TargetRegisterInfo *TRI) const;
170
171 /// Return the immediate offset of the base register in a load/store \p LdSt.
173
174 /// Returns true if opcode \p Opc is a memory operation. If it is, set
175 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
176 ///
177 /// For unscaled instructions, \p Scale is set to 1.
178 static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width,
179 int64_t &MinOffset, int64_t &MaxOffset);
180
182 int64_t Offset1, bool OffsetIsScalable1,
184 int64_t Offset2, bool OffsetIsScalable2,
185 unsigned ClusterSize,
186 unsigned NumBytes) const override;
187
189 const DebugLoc &DL, MCRegister DestReg,
190 MCRegister SrcReg, bool KillSrc, unsigned Opcode,
191 llvm::ArrayRef<unsigned> Indices) const;
193 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
194 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
195 llvm::ArrayRef<unsigned> Indices) const;
197 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
198 bool KillSrc) const override;
199
202 bool isKill, int FrameIndex,
203 const TargetRegisterClass *RC,
204 const TargetRegisterInfo *TRI,
205 Register VReg) const override;
206
209 int FrameIndex, const TargetRegisterClass *RC,
210 const TargetRegisterInfo *TRI,
211 Register VReg) const override;
212
213 // This tells target independent code that it is okay to pass instructions
214 // with subreg operands to foldMemoryOperandImpl.
215 bool isSubregFoldable() const override { return true; }
216
221 MachineBasicBlock::iterator InsertPt, int FrameIndex,
222 LiveIntervals *LIS = nullptr,
223 VirtRegMap *VRM = nullptr) const override;
224
225 /// \returns true if a branch from an instruction with opcode \p BranchOpc
226 /// bytes is capable of jumping to a position \p BrOffset bytes away.
227 bool isBranchOffsetInRange(unsigned BranchOpc,
228 int64_t BrOffset) const override;
229
230 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
231
233 MachineBasicBlock &NewDestBB,
234 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
235 int64_t BrOffset, RegScavenger *RS) const override;
236
238 MachineBasicBlock *&FBB,
240 bool AllowModify = false) const override;
242 MachineBranchPredicate &MBP,
243 bool AllowModify) const override;
245 int *BytesRemoved = nullptr) const override;
248 const DebugLoc &DL,
249 int *BytesAdded = nullptr) const override;
250
251 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
252 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
253
254 bool
257 Register, Register, Register, int &, int &,
258 int &) const override;
260 const DebugLoc &DL, Register DstReg,
262 Register FalseReg) const override;
263
265 MachineBasicBlock::iterator MI) const override;
266
267 MCInst getNop() const override;
268
270 const MachineBasicBlock *MBB,
271 const MachineFunction &MF) const override;
272
273 /// analyzeCompare - For a comparison instruction, return the source registers
274 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
275 /// Return true if the comparison instruction can be analyzed.
276 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
277 Register &SrcReg2, int64_t &CmpMask,
278 int64_t &CmpValue) const override;
279 /// optimizeCompareInstr - Convert the instruction supplying the argument to
280 /// the comparison into one that sets the zero bit in the flags register.
281 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
282 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
283 const MachineRegisterInfo *MRI) const override;
284 bool optimizeCondBranch(MachineInstr &MI) const override;
285
286 /// Return true when a code sequence can improve throughput. It
287 /// should be called only for instructions in loops.
288 /// \param Pattern - combiner pattern
290 /// Return true when there is potentially a faster code sequence
291 /// for an instruction chain ending in ``Root``. All potential patterns are
292 /// listed in the ``Patterns`` array.
293 bool
296 bool DoRegPressureReduce) const override;
297 /// Return true when Inst is associative and commutative so that it can be
298 /// reassociated. If Invert is true, then the inverse of Inst operation must
299 /// be checked.
301 bool Invert) const override;
302 /// When getMachineCombinerPatterns() finds patterns, this function generates
303 /// the instructions that could replace the original code sequence
308 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
309 /// AArch64 supports MachineCombiner.
310 bool useMachineCombiner() const override;
311
312 bool expandPostRAPseudo(MachineInstr &MI) const override;
313
314 std::pair<unsigned, unsigned>
315 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
322
324 bool OutlineFromLinkOnceODRs) const override;
325 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
326 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
328 Function &F, std::vector<outliner::Candidate> &Candidates) const override;
330 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
332 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
333 getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override;
335 const outliner::OutlinedFunction &OF) const override;
339 outliner::Candidate &C) const override;
341
344 bool AllowSideEffects = true) const override;
345
346 /// Returns the vector element size (B, H, S or D) of an SVE opcode.
347 uint64_t getElementSizeForOpcode(unsigned Opc) const;
348 /// Returns true if the opcode is for an SVE instruction that sets the
349 /// condition codes as if it's results had been fed to a PTEST instruction
350 /// along with the same general predicate.
351 bool isPTestLikeOpcode(unsigned Opc) const;
352 /// Returns true if the opcode is for an SVE WHILE## instruction.
353 bool isWhileOpcode(unsigned Opc) const;
354 /// Returns true if the instruction has a shift by immediate that can be
355 /// executed in one cycle less.
356 static bool isFalkorShiftExtFast(const MachineInstr &MI);
357 /// Return true if the instructions is a SEH instruciton used for unwinding
358 /// on Windows.
359 static bool isSEHInstruction(const MachineInstr &MI);
360
361 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
362 Register Reg) const override;
363
364 bool isFunctionSafeToSplit(const MachineFunction &MF) const override;
365
366 bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const override;
367
368 std::optional<ParamLoadedValue>
369 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
370
371 unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
372
374 MachineRegisterInfo &MRI) const override;
375
377 int64_t &NumBytes,
378 int64_t &NumPredicateVectors,
379 int64_t &NumDataVectors);
381 int64_t &ByteSized,
382 int64_t &VGSized);
383
384 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
385
386 // Return true if address of the form BaseReg + Scale * ScaledReg + Offset can
387 // be used for a load/store of NumBytes. BaseReg is always present and
388 // implicit.
389 bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset,
390 unsigned Scale) const;
391
392 // Decrement the SP, issuing probes along the way. `TargetReg` is the new top
393 // of the stack. `FrameSetup` is passed as true, if the allocation is a part
394 // of constructing the activation frame of a function.
396 Register TargetReg,
397 bool FrameSetup) const;
398
399#define GET_INSTRINFO_HELPER_DECLS
400#include "AArch64GenInstrInfo.inc"
401
402protected:
403 /// If the specific machine instruction is an instruction that moves/copies
404 /// value from one register to another register return destination and source
405 /// registers as machine operands.
406 std::optional<DestSourcePair>
407 isCopyInstrImpl(const MachineInstr &MI) const override;
408 std::optional<DestSourcePair>
409 isCopyLikeInstrImpl(const MachineInstr &MI) const override;
410
411private:
412 unsigned getInstBundleLength(const MachineInstr &MI) const;
413
414 /// Sets the offsets on outlined instructions in \p MBB which use SP
415 /// so that they will be valid post-outlining.
416 ///
417 /// \param MBB A \p MachineBasicBlock in an outlined function.
418 void fixupPostOutline(MachineBasicBlock &MBB) const;
419
420 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
421 MachineBasicBlock *TBB,
422 ArrayRef<MachineOperand> Cond) const;
423 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
424 const MachineRegisterInfo &MRI) const;
425 bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
426 int CmpValue, const MachineRegisterInfo &MRI) const;
427
428 /// Returns an unused general-purpose register which can be used for
429 /// constructing an outlined call if one exists. Returns 0 otherwise.
430 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
431
432 /// Remove a ptest of a predicate-generating operation that already sets, or
433 /// can be made to set, the condition codes in an identical manner
434 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
435 unsigned PredReg,
436 const MachineRegisterInfo *MRI) const;
437};
438
439struct UsedNZCV {
440 bool N = false;
441 bool Z = false;
442 bool C = false;
443 bool V = false;
444
445 UsedNZCV() = default;
446
447 UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
448 this->N |= UsedFlags.N;
449 this->Z |= UsedFlags.Z;
450 this->C |= UsedFlags.C;
451 this->V |= UsedFlags.V;
452 return *this;
453 }
454};
455
456/// \returns Conditions flags used after \p CmpInstr in its MachineBB if NZCV
457/// flags are not alive in successors of the same \p CmpInstr and \p MI parent.
458/// \returns std::nullopt otherwise.
459///
460/// Collect instructions using that flags in \p CCUseInstrs if provided.
461std::optional<UsedNZCV>
462examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
463 const TargetRegisterInfo &TRI,
464 SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr);
465
466/// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
467/// which either reads or clobbers NZCV.
468bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
469 const MachineInstr &UseMI,
470 const TargetRegisterInfo *TRI);
471
472MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,
473 unsigned Reg, const StackOffset &Offset,
474 bool LastAdjustmentWasScalable = true);
475MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg,
476 const StackOffset &OffsetFromDefCFA);
477
478/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
479/// plus Offset. This is intended to be used from within the prolog/epilog
480/// insertion (PEI) pass, where a virtual scratch register may be allocated
481/// if necessary, to be replaced by the scavenger at the end of PEI.
482void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
483 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
484 StackOffset Offset, const TargetInstrInfo *TII,
486 bool SetNZCV = false, bool NeedsWinCFI = false,
487 bool *HasWinCFI = nullptr, bool EmitCFAOffset = false,
488 StackOffset InitialOffset = {},
489 unsigned FrameReg = AArch64::SP);
490
491/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
492/// FP. Return false if the offset could not be handled directly in MI, and
493/// return the left-over portion by reference.
494bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
495 unsigned FrameReg, StackOffset &Offset,
496 const AArch64InstrInfo *TII);
497
498/// Use to report the frame offset status in isAArch64FrameOffsetLegal.
500 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
501 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
502 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
504
505/// Check if the @p Offset is a valid frame offset for @p MI.
506/// The returned value reports the validity of the frame offset for @p MI.
507/// It uses the values defined by AArch64FrameOffsetStatus for that.
508/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
509/// use an offset.eq
510/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
511/// rewritten in @p MI.
512/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
513/// amount that is off the limit of the legal offset.
514/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
515/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
516/// If set, @p EmittableOffset contains the amount that can be set in @p MI
517/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
518/// is a legal offset.
519int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
520 bool *OutUseUnscaledOp = nullptr,
521 unsigned *OutUnscaledOp = nullptr,
522 int64_t *EmittableOffset = nullptr);
523
524static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
525
526static inline bool isCondBranchOpcode(int Opc) {
527 switch (Opc) {
528 case AArch64::Bcc:
529 case AArch64::CBZW:
530 case AArch64::CBZX:
531 case AArch64::CBNZW:
532 case AArch64::CBNZX:
533 case AArch64::TBZW:
534 case AArch64::TBZX:
535 case AArch64::TBNZW:
536 case AArch64::TBNZX:
537 return true;
538 default:
539 return false;
540 }
541}
542
543static inline bool isIndirectBranchOpcode(int Opc) {
544 switch (Opc) {
545 case AArch64::BR:
546 case AArch64::BRAA:
547 case AArch64::BRAB:
548 case AArch64::BRAAZ:
549 case AArch64::BRABZ:
550 return true;
551 }
552 return false;
553}
554
555static inline bool isPTrueOpcode(unsigned Opc) {
556 switch (Opc) {
557 case AArch64::PTRUE_B:
558 case AArch64::PTRUE_H:
559 case AArch64::PTRUE_S:
560 case AArch64::PTRUE_D:
561 return true;
562 default:
563 return false;
564 }
565}
566
567/// Return opcode to be used for indirect calls.
568unsigned getBLRCallOpcode(const MachineFunction &MF);
569
570/// Return XPAC opcode to be used for a ptrauth strip using the given key.
571static inline unsigned getXPACOpcodeForKey(AArch64PACKey::ID K) {
572 using namespace AArch64PACKey;
573 switch (K) {
574 case IA: case IB: return AArch64::XPACI;
575 case DA: case DB: return AArch64::XPACD;
576 }
577 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
578}
579
580/// Return AUT opcode to be used for a ptrauth auth using the given key, or its
581/// AUT*Z variant that doesn't take a discriminator operand, using zero instead.
582static inline unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
583 using namespace AArch64PACKey;
584 switch (K) {
585 case IA: return Zero ? AArch64::AUTIZA : AArch64::AUTIA;
586 case IB: return Zero ? AArch64::AUTIZB : AArch64::AUTIB;
587 case DA: return Zero ? AArch64::AUTDZA : AArch64::AUTDA;
588 case DB: return Zero ? AArch64::AUTDZB : AArch64::AUTDB;
589 }
590}
591
592/// Return PAC opcode to be used for a ptrauth sign using the given key, or its
593/// PAC*Z variant that doesn't take a discriminator operand, using zero instead.
594static inline unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
595 using namespace AArch64PACKey;
596 switch (K) {
597 case IA: return Zero ? AArch64::PACIZA : AArch64::PACIA;
598 case IB: return Zero ? AArch64::PACIZB : AArch64::PACIB;
599 case DA: return Zero ? AArch64::PACDZA : AArch64::PACDA;
600 case DB: return Zero ? AArch64::PACDZB : AArch64::PACDB;
601 }
602}
603
604// struct TSFlags {
605#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
606#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
607#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
608#define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
609#define TSFLAG_SME_MATRIX_TYPE(X) ((X) << 11) // 3-bits
610// }
611
612namespace AArch64 {
613
621};
622
635};
636
641};
642
643// NOTE: This is a bit field.
646
656};
657
658#undef TSFLAG_ELEMENT_SIZE_TYPE
659#undef TSFLAG_DESTRUCTIVE_INST_TYPE
660#undef TSFLAG_FALSE_LANE_TYPE
661#undef TSFLAG_INSTR_FLAGS
662#undef TSFLAG_SME_MATRIX_TYPE
663
667
669}
670
671} // end namespace llvm
672
673#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
#define TSFLAG_SME_MATRIX_TYPE(X)
#define TSFLAG_FALSE_LANE_TYPE(X)
#define TSFLAG_INSTR_FLAGS(X)
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isHForm(const MachineInstr &MI)
Returns whether the instruction is in H form (16 bit operands)
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool hasBTISemantics(const MachineInstr &MI)
Returns whether the instruction can be compatible with non-zero BTYPE.
static bool isQForm(const MachineInstr &MI)
Returns whether the instruction is in Q form (128 bit operands)
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
static bool isTailCallReturnInst(const MachineInstr &MI)
Returns true if MI is one of the TCRETURN* instructions.
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
static int getMemScale(const MachineInstr &MI)
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool isSubregFoldable() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
static unsigned convertToFlagSettingOpc(unsigned Opc)
Return the opcode that set flags when possible.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the immediate offset operator of a load/store.
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
static std::optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
static bool hasUnscaledLdStOffset(MachineInstr &MI)
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, TypeSize &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
static bool isFpOrNEON(const MachineInstr &MI)
Returns whether the instruction is FP or NEON.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
bool isFunctionSafeToSplit(const MachineFunction &MF) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
Return true when Inst is associative and commutative so that it can be reassociated.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock::iterator probedStackAlloc(MachineBasicBlock::iterator MBBI, Register TargetReg, bool FrameSetup) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset, unsigned Scale) const
std::optional< DestSourcePair > isCopyLikeInstrImpl(const MachineInstr &MI) const override
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MCInst getNop() const override
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getSVERevInstr(uint16_t Opcode)
int getSMEPseudoMap(uint16_t Opcode)
static const uint64_t InstrFlagIsWhile
static const uint64_t InstrFlagIsPTestLike
int getSVEPseudoMap(uint16_t Opcode)
int getSVENonRevInstr(uint16_t Opcode)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
static bool isCondBranchOpcode(int Opc)
MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)
static bool isPTrueOpcode(unsigned Opc)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
static bool isIndirectBranchOpcode(int Opc)
static unsigned getXPACOpcodeForKey(AArch64PACKey::ID K)
Return XPAC opcode to be used for a ptrauth strip using the given key.
MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA)
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
std::optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
static bool isUncondBranchOpcode(int Opc)
static unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return PAC opcode to be used for a ptrauth sign using the given key, or its PAC*Z variant that doesn'...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static const MachineMemOperand::Flags MOSuppressPair
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
static const MachineMemOperand::Flags MOStridedAccess
static unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return AUT opcode to be used for a ptrauth auth using the given key, or its AUT*Z variant that doesn'...
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
UsedNZCV & operator|=(const UsedNZCV &UsedFlags)
UsedNZCV()=default
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.