LLVM 19.0.0git
AArch64InstrInfo.h
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1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15
16#include "AArch64.h"
17#include "AArch64RegisterInfo.h"
20#include <optional>
21
22#define GET_INSTRINFO_HEADER
23#include "AArch64GenInstrInfo.inc"
24
25namespace llvm {
26
27class AArch64Subtarget;
28
33
34#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
35
36// AArch64 MachineCombiner patterns
38 // These are patterns used to reduce the length of dependence chain.
41
42 // These are multiply-add patterns matched by the AArch64 machine combiner.
55 // NEON integers vectors
68
81
90
99
100 // Floating Point
162
173
175};
177 const AArch64RegisterInfo RI;
178 const AArch64Subtarget &Subtarget;
179
180public:
181 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
182
183 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
184 /// such, whenever a client has an instance of instruction info, it should
185 /// always be able to get register info as well (through this method).
186 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
187
188 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
189
190 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
191
192 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
193 Register &DstReg, unsigned &SubIdx) const override;
194
195 bool
197 const MachineInstr &MIb) const override;
198
200 int &FrameIndex) const override;
202 int &FrameIndex) const override;
203
204 /// Does this instruction set its full destination register to zero?
205 static bool isGPRZero(const MachineInstr &MI);
206
207 /// Does this instruction rename a GPR without modifying bits?
208 static bool isGPRCopy(const MachineInstr &MI);
209
210 /// Does this instruction rename an FPR without modifying bits?
211 static bool isFPRCopy(const MachineInstr &MI);
212
213 /// Return true if pairing the given load or store is hinted to be
214 /// unprofitable.
215 static bool isLdStPairSuppressed(const MachineInstr &MI);
216
217 /// Return true if the given load or store is a strided memory access.
218 static bool isStridedAccess(const MachineInstr &MI);
219
220 /// Return true if it has an unscaled load/store offset.
221 static bool hasUnscaledLdStOffset(unsigned Opc);
223 return hasUnscaledLdStOffset(MI.getOpcode());
224 }
225
226 /// Returns the unscaled load/store for the scaled load/store opcode,
227 /// if there is a corresponding unscaled variant available.
228 static std::optional<unsigned> getUnscaledLdSt(unsigned Opc);
229
230 /// Scaling factor for (scaled or unscaled) load or store.
231 static int getMemScale(unsigned Opc);
232 static int getMemScale(const MachineInstr &MI) {
233 return getMemScale(MI.getOpcode());
234 }
235
236 /// Returns whether the instruction is a pre-indexed load.
237 static bool isPreLd(const MachineInstr &MI);
238
239 /// Returns whether the instruction is a pre-indexed store.
240 static bool isPreSt(const MachineInstr &MI);
241
242 /// Returns whether the instruction is a pre-indexed load/store.
243 static bool isPreLdSt(const MachineInstr &MI);
244
245 /// Returns whether the instruction is a paired load/store.
246 static bool isPairedLdSt(const MachineInstr &MI);
247
248 /// Returns the base register operator of a load/store.
249 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI);
250
251 /// Returns the immediate offset operator of a load/store.
252 static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI);
253
254 /// Returns whether the physical register is FP or NEON.
255 static bool isFpOrNEON(Register Reg);
256
257 /// Returns whether the instruction is FP or NEON.
258 static bool isFpOrNEON(const MachineInstr &MI);
259
260 /// Returns whether the instruction is in H form (16 bit operands)
261 static bool isHForm(const MachineInstr &MI);
262
263 /// Returns whether the instruction is in Q form (128 bit operands)
264 static bool isQForm(const MachineInstr &MI);
265
266 /// Returns whether the instruction can be compatible with non-zero BTYPE.
267 static bool hasBTISemantics(const MachineInstr &MI);
268
269 /// Returns the index for the immediate for a given instruction.
270 static unsigned getLoadStoreImmIdx(unsigned Opc);
271
272 /// Return true if pairing the given load or store may be paired with another.
273 static bool isPairableLdStInst(const MachineInstr &MI);
274
275 /// Returns true if MI is one of the TCRETURN* instructions.
276 static bool isTailCallReturnInst(const MachineInstr &MI);
277
278 /// Return the opcode that set flags when possible. The caller is
279 /// responsible for ensuring the opc has a flag setting equivalent.
280 static unsigned convertToFlagSettingOpc(unsigned Opc);
281
282 /// Return true if this is a load/store that can be potentially paired/merged.
283 bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
284
285 /// Hint that pairing the given load or store is unprofitable.
286 static void suppressLdStPair(MachineInstr &MI);
287
288 std::optional<ExtAddrMode>
290 const TargetRegisterInfo *TRI) const override;
291
293 const MachineInstr &AddrI,
294 ExtAddrMode &AM) const override;
295
297 const ExtAddrMode &AM) const override;
298
301 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
302 const TargetRegisterInfo *TRI) const override;
303
304 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
305 /// This is true for some SVE instructions like ldr/str that have a
306 /// 'reg + imm' addressing mode where the immediate is an index to the
307 /// scalable vector located at 'reg + imm * vscale x #bytes'.
309 const MachineOperand *&BaseOp,
310 int64_t &Offset, bool &OffsetIsScalable,
311 TypeSize &Width,
312 const TargetRegisterInfo *TRI) const;
313
314 /// Return the immediate offset of the base register in a load/store \p LdSt.
316
317 /// Returns true if opcode \p Opc is a memory operation. If it is, set
318 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
319 ///
320 /// For unscaled instructions, \p Scale is set to 1.
321 static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width,
322 int64_t &MinOffset, int64_t &MaxOffset);
323
325 int64_t Offset1, bool OffsetIsScalable1,
327 int64_t Offset2, bool OffsetIsScalable2,
328 unsigned ClusterSize,
329 unsigned NumBytes) const override;
330
332 const DebugLoc &DL, MCRegister DestReg,
333 MCRegister SrcReg, bool KillSrc, unsigned Opcode,
334 llvm::ArrayRef<unsigned> Indices) const;
336 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
337 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
338 llvm::ArrayRef<unsigned> Indices) const;
340 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
341 bool KillSrc) const override;
342
345 bool isKill, int FrameIndex,
346 const TargetRegisterClass *RC,
347 const TargetRegisterInfo *TRI,
348 Register VReg) const override;
349
352 int FrameIndex, const TargetRegisterClass *RC,
353 const TargetRegisterInfo *TRI,
354 Register VReg) const override;
355
356 // This tells target independent code that it is okay to pass instructions
357 // with subreg operands to foldMemoryOperandImpl.
358 bool isSubregFoldable() const override { return true; }
359
364 MachineBasicBlock::iterator InsertPt, int FrameIndex,
365 LiveIntervals *LIS = nullptr,
366 VirtRegMap *VRM = nullptr) const override;
367
368 /// \returns true if a branch from an instruction with opcode \p BranchOpc
369 /// bytes is capable of jumping to a position \p BrOffset bytes away.
370 bool isBranchOffsetInRange(unsigned BranchOpc,
371 int64_t BrOffset) const override;
372
373 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
374
376 MachineBasicBlock &NewDestBB,
377 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
378 int64_t BrOffset, RegScavenger *RS) const override;
379
381 MachineBasicBlock *&FBB,
383 bool AllowModify = false) const override;
385 MachineBranchPredicate &MBP,
386 bool AllowModify) const override;
388 int *BytesRemoved = nullptr) const override;
391 const DebugLoc &DL,
392 int *BytesAdded = nullptr) const override;
393
394 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
395 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
396
397 bool
400 Register, Register, Register, int &, int &,
401 int &) const override;
403 const DebugLoc &DL, Register DstReg,
405 Register FalseReg) const override;
406
408 MachineBasicBlock::iterator MI) const override;
409
410 MCInst getNop() const override;
411
413 const MachineBasicBlock *MBB,
414 const MachineFunction &MF) const override;
415
416 /// analyzeCompare - For a comparison instruction, return the source registers
417 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
418 /// Return true if the comparison instruction can be analyzed.
419 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
420 Register &SrcReg2, int64_t &CmpMask,
421 int64_t &CmpValue) const override;
422 /// optimizeCompareInstr - Convert the instruction supplying the argument to
423 /// the comparison into one that sets the zero bit in the flags register.
424 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
425 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
426 const MachineRegisterInfo *MRI) const override;
427 bool optimizeCondBranch(MachineInstr &MI) const override;
428
429 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
430 /// Return true when a code sequence can improve throughput. It
431 /// should be called only for instructions in loops.
432 /// \param Pattern - combiner pattern
433 bool isThroughputPattern(unsigned Pattern) const override;
434 /// Return true when there is potentially a faster code sequence
435 /// for an instruction chain ending in ``Root``. All potential patterns are
436 /// listed in the ``Patterns`` array.
439 bool DoRegPressureReduce) const override;
440 /// Return true when Inst is associative and commutative so that it can be
441 /// reassociated. If Invert is true, then the inverse of Inst operation must
442 /// be checked.
444 bool Invert) const override;
445 /// When getMachineCombinerPatterns() finds patterns, this function generates
446 /// the instructions that could replace the original code sequence
448 MachineInstr &Root, unsigned Pattern,
451 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
452 /// AArch64 supports MachineCombiner.
453 bool useMachineCombiner() const override;
454
455 bool expandPostRAPseudo(MachineInstr &MI) const override;
456
457 std::pair<unsigned, unsigned>
458 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
465
467 bool OutlineFromLinkOnceODRs) const override;
468 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
469 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
471 Function &F, std::vector<outliner::Candidate> &Candidates) const override;
473 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
475 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
476 getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override;
478 const outliner::OutlinedFunction &OF) const override;
482 outliner::Candidate &C) const override;
484
487 bool AllowSideEffects = true) const override;
488
489 /// Returns the vector element size (B, H, S or D) of an SVE opcode.
490 uint64_t getElementSizeForOpcode(unsigned Opc) const;
491 /// Returns true if the opcode is for an SVE instruction that sets the
492 /// condition codes as if it's results had been fed to a PTEST instruction
493 /// along with the same general predicate.
494 bool isPTestLikeOpcode(unsigned Opc) const;
495 /// Returns true if the opcode is for an SVE WHILE## instruction.
496 bool isWhileOpcode(unsigned Opc) const;
497 /// Returns true if the instruction has a shift by immediate that can be
498 /// executed in one cycle less.
499 static bool isFalkorShiftExtFast(const MachineInstr &MI);
500 /// Return true if the instructions is a SEH instruciton used for unwinding
501 /// on Windows.
502 static bool isSEHInstruction(const MachineInstr &MI);
503
504 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
505 Register Reg) const override;
506
507 bool isFunctionSafeToSplit(const MachineFunction &MF) const override;
508
509 bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const override;
510
511 std::optional<ParamLoadedValue>
512 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
513
514 unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
515
517 MachineRegisterInfo &MRI) const override;
518
520 int64_t &NumBytes,
521 int64_t &NumPredicateVectors,
522 int64_t &NumDataVectors);
524 int64_t &ByteSized,
525 int64_t &VGSized);
526
527 // Return true if address of the form BaseReg + Scale * ScaledReg + Offset can
528 // be used for a load/store of NumBytes. BaseReg is always present and
529 // implicit.
530 bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset,
531 unsigned Scale) const;
532
533 // Decrement the SP, issuing probes along the way. `TargetReg` is the new top
534 // of the stack. `FrameSetup` is passed as true, if the allocation is a part
535 // of constructing the activation frame of a function.
537 Register TargetReg,
538 bool FrameSetup) const;
539
540#define GET_INSTRINFO_HELPER_DECLS
541#include "AArch64GenInstrInfo.inc"
542
543protected:
544 /// If the specific machine instruction is an instruction that moves/copies
545 /// value from one register to another register return destination and source
546 /// registers as machine operands.
547 std::optional<DestSourcePair>
548 isCopyInstrImpl(const MachineInstr &MI) const override;
549 std::optional<DestSourcePair>
550 isCopyLikeInstrImpl(const MachineInstr &MI) const override;
551
552private:
553 unsigned getInstBundleLength(const MachineInstr &MI) const;
554
555 /// Sets the offsets on outlined instructions in \p MBB which use SP
556 /// so that they will be valid post-outlining.
557 ///
558 /// \param MBB A \p MachineBasicBlock in an outlined function.
559 void fixupPostOutline(MachineBasicBlock &MBB) const;
560
561 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
562 MachineBasicBlock *TBB,
563 ArrayRef<MachineOperand> Cond) const;
564 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
565 const MachineRegisterInfo &MRI) const;
566 bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
567 int CmpValue, const MachineRegisterInfo &MRI) const;
568
569 /// Returns an unused general-purpose register which can be used for
570 /// constructing an outlined call if one exists. Returns 0 otherwise.
571 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
572
573 /// Remove a ptest of a predicate-generating operation that already sets, or
574 /// can be made to set, the condition codes in an identical manner
575 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
576 unsigned PredReg,
577 const MachineRegisterInfo *MRI) const;
578 std::optional<unsigned>
579 canRemovePTestInstr(MachineInstr *PTest, MachineInstr *Mask,
580 MachineInstr *Pred, const MachineRegisterInfo *MRI) const;
581};
582
583struct UsedNZCV {
584 bool N = false;
585 bool Z = false;
586 bool C = false;
587 bool V = false;
588
589 UsedNZCV() = default;
590
591 UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
592 this->N |= UsedFlags.N;
593 this->Z |= UsedFlags.Z;
594 this->C |= UsedFlags.C;
595 this->V |= UsedFlags.V;
596 return *this;
597 }
598};
599
600/// \returns Conditions flags used after \p CmpInstr in its MachineBB if NZCV
601/// flags are not alive in successors of the same \p CmpInstr and \p MI parent.
602/// \returns std::nullopt otherwise.
603///
604/// Collect instructions using that flags in \p CCUseInstrs if provided.
605std::optional<UsedNZCV>
606examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
607 const TargetRegisterInfo &TRI,
608 SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr);
609
610/// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
611/// which either reads or clobbers NZCV.
612bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
613 const MachineInstr &UseMI,
614 const TargetRegisterInfo *TRI);
615
616MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,
617 unsigned Reg, const StackOffset &Offset,
618 bool LastAdjustmentWasScalable = true);
619MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg,
620 const StackOffset &OffsetFromDefCFA);
621
622/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
623/// plus Offset. This is intended to be used from within the prolog/epilog
624/// insertion (PEI) pass, where a virtual scratch register may be allocated
625/// if necessary, to be replaced by the scavenger at the end of PEI.
626void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
627 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
628 StackOffset Offset, const TargetInstrInfo *TII,
630 bool SetNZCV = false, bool NeedsWinCFI = false,
631 bool *HasWinCFI = nullptr, bool EmitCFAOffset = false,
632 StackOffset InitialOffset = {},
633 unsigned FrameReg = AArch64::SP);
634
635/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
636/// FP. Return false if the offset could not be handled directly in MI, and
637/// return the left-over portion by reference.
638bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
639 unsigned FrameReg, StackOffset &Offset,
640 const AArch64InstrInfo *TII);
641
642/// Use to report the frame offset status in isAArch64FrameOffsetLegal.
644 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
645 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
646 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
648
649/// Check if the @p Offset is a valid frame offset for @p MI.
650/// The returned value reports the validity of the frame offset for @p MI.
651/// It uses the values defined by AArch64FrameOffsetStatus for that.
652/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
653/// use an offset.eq
654/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
655/// rewritten in @p MI.
656/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
657/// amount that is off the limit of the legal offset.
658/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
659/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
660/// If set, @p EmittableOffset contains the amount that can be set in @p MI
661/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
662/// is a legal offset.
663int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
664 bool *OutUseUnscaledOp = nullptr,
665 unsigned *OutUnscaledOp = nullptr,
666 int64_t *EmittableOffset = nullptr);
667
668static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
669
670static inline bool isCondBranchOpcode(int Opc) {
671 switch (Opc) {
672 case AArch64::Bcc:
673 case AArch64::CBZW:
674 case AArch64::CBZX:
675 case AArch64::CBNZW:
676 case AArch64::CBNZX:
677 case AArch64::TBZW:
678 case AArch64::TBZX:
679 case AArch64::TBNZW:
680 case AArch64::TBNZX:
681 return true;
682 default:
683 return false;
684 }
685}
686
687static inline bool isIndirectBranchOpcode(int Opc) {
688 switch (Opc) {
689 case AArch64::BR:
690 case AArch64::BRAA:
691 case AArch64::BRAB:
692 case AArch64::BRAAZ:
693 case AArch64::BRABZ:
694 return true;
695 }
696 return false;
697}
698
699static inline bool isPTrueOpcode(unsigned Opc) {
700 switch (Opc) {
701 case AArch64::PTRUE_B:
702 case AArch64::PTRUE_H:
703 case AArch64::PTRUE_S:
704 case AArch64::PTRUE_D:
705 return true;
706 default:
707 return false;
708 }
709}
710
711/// Return opcode to be used for indirect calls.
712unsigned getBLRCallOpcode(const MachineFunction &MF);
713
714/// Return XPAC opcode to be used for a ptrauth strip using the given key.
715static inline unsigned getXPACOpcodeForKey(AArch64PACKey::ID K) {
716 using namespace AArch64PACKey;
717 switch (K) {
718 case IA: case IB: return AArch64::XPACI;
719 case DA: case DB: return AArch64::XPACD;
720 }
721 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
722}
723
724/// Return AUT opcode to be used for a ptrauth auth using the given key, or its
725/// AUT*Z variant that doesn't take a discriminator operand, using zero instead.
726static inline unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
727 using namespace AArch64PACKey;
728 switch (K) {
729 case IA: return Zero ? AArch64::AUTIZA : AArch64::AUTIA;
730 case IB: return Zero ? AArch64::AUTIZB : AArch64::AUTIB;
731 case DA: return Zero ? AArch64::AUTDZA : AArch64::AUTDA;
732 case DB: return Zero ? AArch64::AUTDZB : AArch64::AUTDB;
733 }
734 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
735}
736
737/// Return PAC opcode to be used for a ptrauth sign using the given key, or its
738/// PAC*Z variant that doesn't take a discriminator operand, using zero instead.
739static inline unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
740 using namespace AArch64PACKey;
741 switch (K) {
742 case IA: return Zero ? AArch64::PACIZA : AArch64::PACIA;
743 case IB: return Zero ? AArch64::PACIZB : AArch64::PACIB;
744 case DA: return Zero ? AArch64::PACDZA : AArch64::PACDA;
745 case DB: return Zero ? AArch64::PACDZB : AArch64::PACDB;
746 }
747 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
748}
749
750// struct TSFlags {
751#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
752#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
753#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
754#define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
755#define TSFLAG_SME_MATRIX_TYPE(X) ((X) << 11) // 3-bits
756// }
757
758namespace AArch64 {
759
767};
768
781};
782
787};
788
789// NOTE: This is a bit field.
792
802};
803
804#undef TSFLAG_ELEMENT_SIZE_TYPE
805#undef TSFLAG_DESTRUCTIVE_INST_TYPE
806#undef TSFLAG_FALSE_LANE_TYPE
807#undef TSFLAG_INSTR_FLAGS
808#undef TSFLAG_SME_MATRIX_TYPE
809
813
815}
816
817} // end namespace llvm
818
819#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
#define TSFLAG_SME_MATRIX_TYPE(X)
#define TSFLAG_FALSE_LANE_TYPE(X)
#define TSFLAG_INSTR_FLAGS(X)
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isHForm(const MachineInstr &MI)
Returns whether the instruction is in H form (16 bit operands)
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool hasBTISemantics(const MachineInstr &MI)
Returns whether the instruction can be compatible with non-zero BTYPE.
static bool isQForm(const MachineInstr &MI)
Returns whether the instruction is in Q form (128 bit operands)
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
static bool isTailCallReturnInst(const MachineInstr &MI)
Returns true if MI is one of the TCRETURN* instructions.
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
static int getMemScale(const MachineInstr &MI)
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool isSubregFoldable() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
static unsigned convertToFlagSettingOpc(unsigned Opc)
Return the opcode that set flags when possible.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the immediate offset operator of a load/store.
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
static std::optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
static bool hasUnscaledLdStOffset(MachineInstr &MI)
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, TypeSize &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isThroughputPattern(unsigned Pattern) const override
Return true when a code sequence can improve throughput.
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
bool isFunctionSafeToSplit(const MachineFunction &MF) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
Return true when Inst is associative and commutative so that it can be reassociated.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock::iterator probedStackAlloc(MachineBasicBlock::iterator MBBI, Register TargetReg, bool FrameSetup) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
CombinerObjective getCombinerObjective(unsigned Pattern) const override
static bool isFpOrNEON(Register Reg)
Returns whether the physical register is FP or NEON.
bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset, unsigned Scale) const
std::optional< DestSourcePair > isCopyLikeInstrImpl(const MachineInstr &MI) const override
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MCInst getNop() const override
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getSVERevInstr(uint16_t Opcode)
int getSMEPseudoMap(uint16_t Opcode)
static const uint64_t InstrFlagIsWhile
static const uint64_t InstrFlagIsPTestLike
int getSVEPseudoMap(uint16_t Opcode)
int getSVENonRevInstr(uint16_t Opcode)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
static bool isCondBranchOpcode(int Opc)
MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)
static bool isPTrueOpcode(unsigned Opc)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
static bool isIndirectBranchOpcode(int Opc)
static unsigned getXPACOpcodeForKey(AArch64PACKey::ID K)
Return XPAC opcode to be used for a ptrauth strip using the given key.
MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA)
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
AArch64MachineCombinerPattern
@ MULSUBv8i16_OP2
@ FMULv4i16_indexed_OP1
@ FMLSv1i32_indexed_OP2
@ MULSUBv2i32_indexed_OP1
@ MULADDXI_OP1
@ FMLAv2i32_indexed_OP2
@ MULADDv4i16_indexed_OP2
@ FMLAv1i64_indexed_OP1
@ MULSUBv16i8_OP1
@ FMLAv8i16_indexed_OP2
@ FMULv2i32_indexed_OP1
@ MULSUBv8i16_indexed_OP2
@ FMLAv1i64_indexed_OP2
@ MULSUBv4i16_indexed_OP2
@ FMLAv1i32_indexed_OP1
@ FMLAv2i64_indexed_OP2
@ FMLSv8i16_indexed_OP1
@ MULSUBv2i32_OP1
@ FMULv4i16_indexed_OP2
@ MULSUBv4i32_indexed_OP2
@ FMULv2i64_indexed_OP2
@ MULSUBXI_OP1
@ FMLAv4i32_indexed_OP1
@ MULADDWI_OP1
@ MULADDv4i16_OP2
@ FMULv8i16_indexed_OP2
@ MULSUBv4i16_OP1
@ MULADDv4i32_OP2
@ MULADDv8i8_OP1
@ MULADDv2i32_OP2
@ MULADDv16i8_OP2
@ MULADDv8i8_OP2
@ FMLSv4i16_indexed_OP1
@ MULADDv16i8_OP1
@ FMLAv2i64_indexed_OP1
@ FMLAv1i32_indexed_OP2
@ FMLSv2i64_indexed_OP2
@ MULADDv2i32_OP1
@ MULADDv4i32_OP1
@ MULADDv2i32_indexed_OP1
@ MULSUBv16i8_OP2
@ MULADDv4i32_indexed_OP1
@ MULADDv2i32_indexed_OP2
@ FMLAv4i16_indexed_OP2
@ MULSUBv8i16_OP1
@ FMULv2i32_indexed_OP2
@ FMLSv2i32_indexed_OP2
@ FMLSv4i32_indexed_OP1
@ FMULv2i64_indexed_OP1
@ MULSUBv4i16_OP2
@ FMLSv4i16_indexed_OP2
@ FMLAv2i32_indexed_OP1
@ FMLSv2i32_indexed_OP1
@ FMLAv8i16_indexed_OP1
@ MULSUBv4i16_indexed_OP1
@ FMLSv4i32_indexed_OP2
@ MULADDv4i32_indexed_OP2
@ MULSUBv4i32_OP2
@ MULSUBv8i16_indexed_OP1
@ MULADDv8i16_OP2
@ MULSUBv2i32_indexed_OP2
@ FMULv4i32_indexed_OP2
@ FMLSv2i64_indexed_OP1
@ MULADDv4i16_OP1
@ FMLAv4i32_indexed_OP2
@ MULADDv8i16_indexed_OP1
@ FMULv4i32_indexed_OP1
@ FMLAv4i16_indexed_OP1
@ FMULv8i16_indexed_OP1
@ MULSUBv8i8_OP1
@ MULADDv8i16_OP1
@ MULSUBv4i32_indexed_OP1
@ MULSUBv4i32_OP1
@ FMLSv8i16_indexed_OP2
@ MULADDv8i16_indexed_OP2
@ MULSUBWI_OP1
@ MULSUBv2i32_OP2
@ FMLSv1i64_indexed_OP2
@ MULADDv4i16_indexed_OP1
@ MULSUBv8i8_OP2
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
CombinerObjective
The combiner's goal may differ based on which pattern it is attempting to optimize.
std::optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
static bool isUncondBranchOpcode(int Opc)
static unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return PAC opcode to be used for a ptrauth sign using the given key, or its PAC*Z variant that doesn'...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static const MachineMemOperand::Flags MOSuppressPair
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
static const MachineMemOperand::Flags MOStridedAccess
static unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return AUT opcode to be used for a ptrauth auth using the given key, or its AUT*Z variant that doesn'...
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
UsedNZCV & operator|=(const UsedNZCV &UsedFlags)
UsedNZCV()=default
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.