LLVM 17.0.0git
AArch64InstrInfo.h
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1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15
16#include "AArch64.h"
17#include "AArch64RegisterInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "AArch64GenInstrInfo.inc"
23
24namespace llvm {
25
26class AArch64Subtarget;
27
32
33#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
34
36 const AArch64RegisterInfo RI;
37 const AArch64Subtarget &Subtarget;
38
39public:
40 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
41
42 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
43 /// such, whenever a client has an instance of instruction info, it should
44 /// always be able to get register info as well (through this method).
45 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
46
47 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
48
49 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
50
51 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
52 Register &DstReg, unsigned &SubIdx) const override;
53
54 bool
56 const MachineInstr &MIb) const override;
57
58 unsigned isLoadFromStackSlot(const MachineInstr &MI,
59 int &FrameIndex) const override;
60 unsigned isStoreToStackSlot(const MachineInstr &MI,
61 int &FrameIndex) const override;
62
63 /// Does this instruction set its full destination register to zero?
64 static bool isGPRZero(const MachineInstr &MI);
65
66 /// Does this instruction rename a GPR without modifying bits?
67 static bool isGPRCopy(const MachineInstr &MI);
68
69 /// Does this instruction rename an FPR without modifying bits?
70 static bool isFPRCopy(const MachineInstr &MI);
71
72 /// Return true if pairing the given load or store is hinted to be
73 /// unprofitable.
74 static bool isLdStPairSuppressed(const MachineInstr &MI);
75
76 /// Return true if the given load or store is a strided memory access.
77 static bool isStridedAccess(const MachineInstr &MI);
78
79 /// Return true if it has an unscaled load/store offset.
80 static bool hasUnscaledLdStOffset(unsigned Opc);
82 return hasUnscaledLdStOffset(MI.getOpcode());
83 }
84
85 /// Returns the unscaled load/store for the scaled load/store opcode,
86 /// if there is a corresponding unscaled variant available.
87 static std::optional<unsigned> getUnscaledLdSt(unsigned Opc);
88
89 /// Scaling factor for (scaled or unscaled) load or store.
90 static int getMemScale(unsigned Opc);
91 static int getMemScale(const MachineInstr &MI) {
92 return getMemScale(MI.getOpcode());
93 }
94
95 /// Returns whether the instruction is a pre-indexed load.
96 static bool isPreLd(const MachineInstr &MI);
97
98 /// Returns whether the instruction is a pre-indexed store.
99 static bool isPreSt(const MachineInstr &MI);
100
101 /// Returns whether the instruction is a pre-indexed load/store.
102 static bool isPreLdSt(const MachineInstr &MI);
103
104 /// Returns whether the instruction is a paired load/store.
105 static bool isPairedLdSt(const MachineInstr &MI);
106
107 /// Returns the base register operator of a load/store.
108 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI);
109
110 /// Returns the the immediate offset operator of a load/store.
111 static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI);
112
113 /// Returns whether the instruction is FP or NEON.
114 static bool isFpOrNEON(const MachineInstr &MI);
115
116 /// Returns whether the instruction is in Q form (128 bit operands)
117 static bool isQForm(const MachineInstr &MI);
118
119 /// Returns the index for the immediate for a given instruction.
120 static unsigned getLoadStoreImmIdx(unsigned Opc);
121
122 /// Return true if pairing the given load or store may be paired with another.
123 static bool isPairableLdStInst(const MachineInstr &MI);
124
125 /// Return the opcode that set flags when possible. The caller is
126 /// responsible for ensuring the opc has a flag setting equivalent.
127 static unsigned convertToFlagSettingOpc(unsigned Opc);
128
129 /// Return true if this is a load/store that can be potentially paired/merged.
130 bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
131
132 /// Hint that pairing the given load or store is unprofitable.
133 static void suppressLdStPair(MachineInstr &MI);
134
135 std::optional<ExtAddrMode>
137 const TargetRegisterInfo *TRI) const override;
138
141 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
142 const TargetRegisterInfo *TRI) const override;
143
144 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
145 /// This is true for some SVE instructions like ldr/str that have a
146 /// 'reg + imm' addressing mode where the immediate is an index to the
147 /// scalable vector located at 'reg + imm * vscale x #bytes'.
149 const MachineOperand *&BaseOp,
150 int64_t &Offset, bool &OffsetIsScalable,
151 unsigned &Width,
152 const TargetRegisterInfo *TRI) const;
153
154 /// Return the immediate offset of the base register in a load/store \p LdSt.
156
157 /// Returns true if opcode \p Opc is a memory operation. If it is, set
158 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
159 ///
160 /// For unscaled instructions, \p Scale is set to 1.
161 static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
162 int64_t &MinOffset, int64_t &MaxOffset);
163
166 unsigned NumLoads, unsigned NumBytes) const override;
167
169 const DebugLoc &DL, MCRegister DestReg,
170 MCRegister SrcReg, bool KillSrc, unsigned Opcode,
171 llvm::ArrayRef<unsigned> Indices) const;
173 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
174 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
175 llvm::ArrayRef<unsigned> Indices) const;
177 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
178 bool KillSrc) const override;
179
182 bool isKill, int FrameIndex,
183 const TargetRegisterClass *RC,
184 const TargetRegisterInfo *TRI,
185 Register VReg) const override;
186
189 int FrameIndex, const TargetRegisterClass *RC,
190 const TargetRegisterInfo *TRI,
191 Register VReg) const override;
192
193 // This tells target independent code that it is okay to pass instructions
194 // with subreg operands to foldMemoryOperandImpl.
195 bool isSubregFoldable() const override { return true; }
196
201 MachineBasicBlock::iterator InsertPt, int FrameIndex,
202 LiveIntervals *LIS = nullptr,
203 VirtRegMap *VRM = nullptr) const override;
204
205 /// \returns true if a branch from an instruction with opcode \p BranchOpc
206 /// bytes is capable of jumping to a position \p BrOffset bytes away.
207 bool isBranchOffsetInRange(unsigned BranchOpc,
208 int64_t BrOffset) const override;
209
210 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
211
213 MachineBasicBlock *&FBB,
215 bool AllowModify = false) const override;
217 MachineBranchPredicate &MBP,
218 bool AllowModify) const override;
220 int *BytesRemoved = nullptr) const override;
223 const DebugLoc &DL,
224 int *BytesAdded = nullptr) const override;
225 bool
228 Register, Register, Register, int &, int &,
229 int &) const override;
231 const DebugLoc &DL, Register DstReg,
233 Register FalseReg) const override;
234 MCInst getNop() const override;
235
237 const MachineBasicBlock *MBB,
238 const MachineFunction &MF) const override;
239
240 /// analyzeCompare - For a comparison instruction, return the source registers
241 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
242 /// Return true if the comparison instruction can be analyzed.
243 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
244 Register &SrcReg2, int64_t &CmpMask,
245 int64_t &CmpValue) const override;
246 /// optimizeCompareInstr - Convert the instruction supplying the argument to
247 /// the comparison into one that sets the zero bit in the flags register.
248 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
249 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
250 const MachineRegisterInfo *MRI) const override;
251 bool optimizeCondBranch(MachineInstr &MI) const override;
252
253 /// Return true when a code sequence can improve throughput. It
254 /// should be called only for instructions in loops.
255 /// \param Pattern - combiner pattern
257 /// Return true when there is potentially a faster code sequence
258 /// for an instruction chain ending in ``Root``. All potential patterns are
259 /// listed in the ``Patterns`` array.
260 bool
263 bool DoRegPressureReduce) const override;
264 /// Return true when Inst is associative and commutative so that it can be
265 /// reassociated. If Invert is true, then the inverse of Inst operation must
266 /// be checked.
268 bool Invert) const override;
269 /// When getMachineCombinerPatterns() finds patterns, this function generates
270 /// the instructions that could replace the original code sequence
275 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
276 /// AArch64 supports MachineCombiner.
277 bool useMachineCombiner() const override;
278
279 bool expandPostRAPseudo(MachineInstr &MI) const override;
280
281 std::pair<unsigned, unsigned>
282 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
289
291 bool OutlineFromLinkOnceODRs) const override;
293 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
295 unsigned Flags) const override;
297 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
298 getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override;
300 const outliner::OutlinedFunction &OF) const override;
304 outliner::Candidate &C) const override;
306 /// Returns the vector element size (B, H, S or D) of an SVE opcode.
307 uint64_t getElementSizeForOpcode(unsigned Opc) const;
308 /// Returns true if the opcode is for an SVE instruction that sets the
309 /// condition codes as if it's results had been fed to a PTEST instruction
310 /// along with the same general predicate.
311 bool isPTestLikeOpcode(unsigned Opc) const;
312 /// Returns true if the opcode is for an SVE WHILE## instruction.
313 bool isWhileOpcode(unsigned Opc) const;
314 /// Returns true if the instruction has a shift by immediate that can be
315 /// executed in one cycle less.
316 static bool isFalkorShiftExtFast(const MachineInstr &MI);
317 /// Return true if the instructions is a SEH instruciton used for unwinding
318 /// on Windows.
319 static bool isSEHInstruction(const MachineInstr &MI);
320
321 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
322 Register Reg) const override;
323
324 std::optional<ParamLoadedValue>
325 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
326
327 unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
328
330 MachineRegisterInfo &MRI) const override;
331
333 int64_t &NumBytes,
334 int64_t &NumPredicateVectors,
335 int64_t &NumDataVectors);
337 int64_t &ByteSized,
338 int64_t &VGSized);
339#define GET_INSTRINFO_HELPER_DECLS
340#include "AArch64GenInstrInfo.inc"
341
342protected:
343 /// If the specific machine instruction is an instruction that moves/copies
344 /// value from one register to another register return destination and source
345 /// registers as machine operands.
346 std::optional<DestSourcePair>
347 isCopyInstrImpl(const MachineInstr &MI) const override;
348
349private:
350 unsigned getInstBundleLength(const MachineInstr &MI) const;
351
352 /// Sets the offsets on outlined instructions in \p MBB which use SP
353 /// so that they will be valid post-outlining.
354 ///
355 /// \param MBB A \p MachineBasicBlock in an outlined function.
356 void fixupPostOutline(MachineBasicBlock &MBB) const;
357
358 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
359 MachineBasicBlock *TBB,
360 ArrayRef<MachineOperand> Cond) const;
361 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
362 const MachineRegisterInfo &MRI) const;
363 bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
364 int CmpValue, const MachineRegisterInfo &MRI) const;
365
366 /// Returns an unused general-purpose register which can be used for
367 /// constructing an outlined call if one exists. Returns 0 otherwise.
368 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
369
370 /// Remove a ptest of a predicate-generating operation that already sets, or
371 /// can be made to set, the condition codes in an identical manner
372 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
373 unsigned PredReg,
374 const MachineRegisterInfo *MRI) const;
375};
376
377struct UsedNZCV {
378 bool N = false;
379 bool Z = false;
380 bool C = false;
381 bool V = false;
382
383 UsedNZCV() = default;
384
385 UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
386 this->N |= UsedFlags.N;
387 this->Z |= UsedFlags.Z;
388 this->C |= UsedFlags.C;
389 this->V |= UsedFlags.V;
390 return *this;
391 }
392};
393
394/// \returns Conditions flags used after \p CmpInstr in its MachineBB if NZCV
395/// flags are not alive in successors of the same \p CmpInstr and \p MI parent.
396/// \returns std::nullopt otherwise.
397///
398/// Collect instructions using that flags in \p CCUseInstrs if provided.
399std::optional<UsedNZCV>
400examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
401 const TargetRegisterInfo &TRI,
402 SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr);
403
404/// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
405/// which either reads or clobbers NZCV.
406bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
407 const MachineInstr &UseMI,
408 const TargetRegisterInfo *TRI);
409
410MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,
411 unsigned Reg, const StackOffset &Offset,
412 bool LastAdjustmentWasScalable = true);
413MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg,
414 const StackOffset &OffsetFromDefCFA);
415
416/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
417/// plus Offset. This is intended to be used from within the prolog/epilog
418/// insertion (PEI) pass, where a virtual scratch register may be allocated
419/// if necessary, to be replaced by the scavenger at the end of PEI.
420void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
421 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
422 StackOffset Offset, const TargetInstrInfo *TII,
424 bool SetNZCV = false, bool NeedsWinCFI = false,
425 bool *HasWinCFI = nullptr, bool EmitCFAOffset = false,
426 StackOffset InitialOffset = {},
427 unsigned FrameReg = AArch64::SP);
428
429/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
430/// FP. Return false if the offset could not be handled directly in MI, and
431/// return the left-over portion by reference.
432bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
433 unsigned FrameReg, StackOffset &Offset,
434 const AArch64InstrInfo *TII);
435
436/// Use to report the frame offset status in isAArch64FrameOffsetLegal.
438 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
439 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
440 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
442
443/// Check if the @p Offset is a valid frame offset for @p MI.
444/// The returned value reports the validity of the frame offset for @p MI.
445/// It uses the values defined by AArch64FrameOffsetStatus for that.
446/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
447/// use an offset.eq
448/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
449/// rewritten in @p MI.
450/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
451/// amount that is off the limit of the legal offset.
452/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
453/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
454/// If set, @p EmittableOffset contains the amount that can be set in @p MI
455/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
456/// is a legal offset.
457int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
458 bool *OutUseUnscaledOp = nullptr,
459 unsigned *OutUnscaledOp = nullptr,
460 int64_t *EmittableOffset = nullptr);
461
462static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
463
464static inline bool isCondBranchOpcode(int Opc) {
465 switch (Opc) {
466 case AArch64::Bcc:
467 case AArch64::CBZW:
468 case AArch64::CBZX:
469 case AArch64::CBNZW:
470 case AArch64::CBNZX:
471 case AArch64::TBZW:
472 case AArch64::TBZX:
473 case AArch64::TBNZW:
474 case AArch64::TBNZX:
475 return true;
476 default:
477 return false;
478 }
479}
480
481static inline bool isIndirectBranchOpcode(int Opc) {
482 switch (Opc) {
483 case AArch64::BR:
484 case AArch64::BRAA:
485 case AArch64::BRAB:
486 case AArch64::BRAAZ:
487 case AArch64::BRABZ:
488 return true;
489 }
490 return false;
491}
492
493static inline bool isPTrueOpcode(unsigned Opc) {
494 switch (Opc) {
495 case AArch64::PTRUE_B:
496 case AArch64::PTRUE_H:
497 case AArch64::PTRUE_S:
498 case AArch64::PTRUE_D:
499 return true;
500 default:
501 return false;
502 }
503}
504
505/// Return opcode to be used for indirect calls.
506unsigned getBLRCallOpcode(const MachineFunction &MF);
507
508/// Return XPAC opcode to be used for a ptrauth strip using the given key.
509static inline unsigned getXPACOpcodeForKey(AArch64PACKey::ID K) {
510 using namespace AArch64PACKey;
511 switch (K) {
512 case IA: case IB: return AArch64::XPACI;
513 case DA: case DB: return AArch64::XPACD;
514 }
515 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
516}
517
518/// Return AUT opcode to be used for a ptrauth auth using the given key, or its
519/// AUT*Z variant that doesn't take a discriminator operand, using zero instead.
520static inline unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
521 using namespace AArch64PACKey;
522 switch (K) {
523 case IA: return Zero ? AArch64::AUTIZA : AArch64::AUTIA;
524 case IB: return Zero ? AArch64::AUTIZB : AArch64::AUTIB;
525 case DA: return Zero ? AArch64::AUTDZA : AArch64::AUTDA;
526 case DB: return Zero ? AArch64::AUTDZB : AArch64::AUTDB;
527 }
528}
529
530/// Return PAC opcode to be used for a ptrauth sign using the given key, or its
531/// PAC*Z variant that doesn't take a discriminator operand, using zero instead.
532static inline unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
533 using namespace AArch64PACKey;
534 switch (K) {
535 case IA: return Zero ? AArch64::PACIZA : AArch64::PACIA;
536 case IB: return Zero ? AArch64::PACIZB : AArch64::PACIB;
537 case DA: return Zero ? AArch64::PACDZA : AArch64::PACDA;
538 case DB: return Zero ? AArch64::PACDZB : AArch64::PACDB;
539 }
540}
541
542// struct TSFlags {
543#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
544#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
545#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
546#define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
547#define TSFLAG_SME_MATRIX_TYPE(X) ((X) << 11) // 3-bits
548// }
549
550namespace AArch64 {
551
559};
560
573};
574
579};
580
581// NOTE: This is a bit field.
584
594};
595
596#undef TSFLAG_ELEMENT_SIZE_TYPE
597#undef TSFLAG_DESTRUCTIVE_INST_TYPE
598#undef TSFLAG_FALSE_LANE_TYPE
599#undef TSFLAG_INSTR_FLAGS
600#undef TSFLAG_SME_MATRIX_TYPE
601
605
607}
608
609} // end namespace llvm
610
611#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
#define TSFLAG_SME_MATRIX_TYPE(X)
#define TSFLAG_FALSE_LANE_TYPE(X)
#define TSFLAG_INSTR_FLAGS(X)
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallVector< MachineOperand, 4 > Cond
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isQForm(const MachineInstr &MI)
Returns whether the instruction is in Q form (128 bit operands)
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
static int getMemScale(const MachineInstr &MI)
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool isSubregFoldable() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
static unsigned convertToFlagSettingOpc(unsigned Opc)
Return the opcode that set flags when possible.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the the immediate offset operator of a load/store.
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
static std::optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
static bool hasUnscaledLdStOffset(MachineInstr &MI)
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
static bool isFpOrNEON(const MachineInstr &MI)
Returns whether the instruction is FP or NEON.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
Return true when Inst is associative and commutative so that it can be reassociated.
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
bool isAsCheapAsAMove(const MachineInstr &MI) const override
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MCInst getNop() const override
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getSVERevInstr(uint16_t Opcode)
int getSMEPseudoMap(uint16_t Opcode)
static const uint64_t InstrFlagIsWhile
static const uint64_t InstrFlagIsPTestLike
int getSVEPseudoMap(uint16_t Opcode)
int getSVENonRevInstr(uint16_t Opcode)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
static bool isCondBranchOpcode(int Opc)
MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)
static bool isPTrueOpcode(unsigned Opc)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
static bool isIndirectBranchOpcode(int Opc)
static unsigned getXPACOpcodeForKey(AArch64PACKey::ID K)
Return XPAC opcode to be used for a ptrauth strip using the given key.
MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA)
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
std::optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)
static bool isUncondBranchOpcode(int Opc)
static unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return PAC opcode to be used for a ptrauth sign using the given key, or its PAC*Z variant that doesn'...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static const MachineMemOperand::Flags MOSuppressPair
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
static const MachineMemOperand::Flags MOStridedAccess
static unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return AUT opcode to be used for a ptrauth auth using the given key, or its AUT*Z variant that doesn'...
UsedNZCV & operator|=(const UsedNZCV &UsedFlags)
UsedNZCV()=default
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.