LLVM  15.0.0git
AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "llvm/ADT/Optional.h"
21 #include "llvm/Support/TypeSize.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "AArch64GenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AArch64Subtarget;
29 
34 
35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
36 
37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
38  const AArch64RegisterInfo RI;
39  const AArch64Subtarget &Subtarget;
40 
41 public:
42  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 
44  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
45  /// such, whenever a client has an instance of instruction info, it should
46  /// always be able to get register info as well (through this method).
47  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
52 
53  bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
54  Register &DstReg, unsigned &SubIdx) const override;
55 
56  bool
58  const MachineInstr &MIb) const override;
59 
60  unsigned isLoadFromStackSlot(const MachineInstr &MI,
61  int &FrameIndex) const override;
62  unsigned isStoreToStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64 
65  /// Does this instruction set its full destination register to zero?
66  static bool isGPRZero(const MachineInstr &MI);
67 
68  /// Does this instruction rename a GPR without modifying bits?
69  static bool isGPRCopy(const MachineInstr &MI);
70 
71  /// Does this instruction rename an FPR without modifying bits?
72  static bool isFPRCopy(const MachineInstr &MI);
73 
74  /// Return true if pairing the given load or store is hinted to be
75  /// unprofitable.
76  static bool isLdStPairSuppressed(const MachineInstr &MI);
77 
78  /// Return true if the given load or store is a strided memory access.
79  static bool isStridedAccess(const MachineInstr &MI);
80 
81  /// Return true if it has an unscaled load/store offset.
82  static bool hasUnscaledLdStOffset(unsigned Opc);
84  return hasUnscaledLdStOffset(MI.getOpcode());
85  }
86 
87  /// Returns the unscaled load/store for the scaled load/store opcode,
88  /// if there is a corresponding unscaled variant available.
89  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
90 
91  /// Scaling factor for (scaled or unscaled) load or store.
92  static int getMemScale(unsigned Opc);
93  static int getMemScale(const MachineInstr &MI) {
94  return getMemScale(MI.getOpcode());
95  }
96 
97  /// Returns whether the instruction is a pre-indexed load.
98  static bool isPreLd(const MachineInstr &MI);
99 
100  /// Returns whether the instruction is a pre-indexed store.
101  static bool isPreSt(const MachineInstr &MI);
102 
103  /// Returns whether the instruction is a pre-indexed load/store.
104  static bool isPreLdSt(const MachineInstr &MI);
105 
106  /// Returns whether the instruction is a paired load/store.
107  static bool isPairedLdSt(const MachineInstr &MI);
108 
109  /// Returns the base register operator of a load/store.
110  static const MachineOperand &getLdStBaseOp(const MachineInstr &MI);
111 
112  /// Returns the the immediate offset operator of a load/store.
113  static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI);
114 
115  /// Returns whether the instruction is FP or NEON.
116  static bool isFpOrNEON(const MachineInstr &MI);
117 
118  /// Returns whether the instruction is in Q form (128 bit operands)
119  static bool isQForm(const MachineInstr &MI);
120 
121  /// Returns the index for the immediate for a given instruction.
122  static unsigned getLoadStoreImmIdx(unsigned Opc);
123 
124  /// Return true if pairing the given load or store may be paired with another.
125  static bool isPairableLdStInst(const MachineInstr &MI);
126 
127  /// Return the opcode that set flags when possible. The caller is
128  /// responsible for ensuring the opc has a flag setting equivalent.
129  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
130 
131  /// Return true if this is a load/store that can be potentially paired/merged.
132  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
133 
134  /// Hint that pairing the given load or store is unprofitable.
135  static void suppressLdStPair(MachineInstr &MI);
136 
139  const TargetRegisterInfo *TRI) const override;
140 
143  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
144  const TargetRegisterInfo *TRI) const override;
145 
146  /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
147  /// This is true for some SVE instructions like ldr/str that have a
148  /// 'reg + imm' addressing mode where the immediate is an index to the
149  /// scalable vector located at 'reg + imm * vscale x #bytes'.
151  const MachineOperand *&BaseOp,
152  int64_t &Offset, bool &OffsetIsScalable,
153  unsigned &Width,
154  const TargetRegisterInfo *TRI) const;
155 
156  /// Return the immediate offset of the base register in a load/store \p LdSt.
158 
159  /// Returns true if opcode \p Opc is a memory operation. If it is, set
160  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
161  ///
162  /// For unscaled instructions, \p Scale is set to 1.
163  static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
164  int64_t &MinOffset, int64_t &MaxOffset);
165 
168  unsigned NumLoads, unsigned NumBytes) const override;
169 
171  const DebugLoc &DL, MCRegister DestReg,
172  MCRegister SrcReg, bool KillSrc, unsigned Opcode,
173  llvm::ArrayRef<unsigned> Indices) const;
175  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
176  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
177  llvm::ArrayRef<unsigned> Indices) const;
179  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
180  bool KillSrc) const override;
181 
184  bool isKill, int FrameIndex,
185  const TargetRegisterClass *RC,
186  const TargetRegisterInfo *TRI) const override;
187 
190  int FrameIndex, const TargetRegisterClass *RC,
191  const TargetRegisterInfo *TRI) const override;
192 
193  // This tells target independent code that it is okay to pass instructions
194  // with subreg operands to foldMemoryOperandImpl.
195  bool isSubregFoldable() const override { return true; }
196 
198  MachineInstr *
200  ArrayRef<unsigned> Ops,
202  LiveIntervals *LIS = nullptr,
203  VirtRegMap *VRM = nullptr) const override;
204 
205  /// \returns true if a branch from an instruction with opcode \p BranchOpc
206  /// bytes is capable of jumping to a position \p BrOffset bytes away.
207  bool isBranchOffsetInRange(unsigned BranchOpc,
208  int64_t BrOffset) const override;
209 
210  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
211 
213  MachineBasicBlock *&FBB,
215  bool AllowModify = false) const override;
217  MachineBranchPredicate &MBP,
218  bool AllowModify) const override;
220  int *BytesRemoved = nullptr) const override;
223  const DebugLoc &DL,
224  int *BytesAdded = nullptr) const override;
225  bool
228  Register, Register, Register, int &, int &,
229  int &) const override;
231  const DebugLoc &DL, Register DstReg,
233  Register FalseReg) const override;
234  MCInst getNop() const override;
235 
237  const MachineBasicBlock *MBB,
238  const MachineFunction &MF) const override;
239 
240  /// analyzeCompare - For a comparison instruction, return the source registers
241  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
242  /// Return true if the comparison instruction can be analyzed.
243  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
244  Register &SrcReg2, int64_t &CmpMask,
245  int64_t &CmpValue) const override;
246  /// optimizeCompareInstr - Convert the instruction supplying the argument to
247  /// the comparison into one that sets the zero bit in the flags register.
248  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
249  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
250  const MachineRegisterInfo *MRI) const override;
251  bool optimizeCondBranch(MachineInstr &MI) const override;
252 
253  /// Return true when a code sequence can improve throughput. It
254  /// should be called only for instructions in loops.
255  /// \param Pattern - combiner pattern
257  /// Return true when there is potentially a faster code sequence
258  /// for an instruction chain ending in ``Root``. All potential patterns are
259  /// listed in the ``Patterns`` array.
260  bool
263  bool DoRegPressureReduce) const override;
264  /// Return true when Inst is associative and commutative so that it can be
265  /// reassociated.
266  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
267  /// When getMachineCombinerPatterns() finds patterns, this function generates
268  /// the instructions that could replace the original code sequence
273  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
274  /// AArch64 supports MachineCombiner.
275  bool useMachineCombiner() const override;
276 
277  bool expandPostRAPseudo(MachineInstr &MI) const override;
278 
279  std::pair<unsigned, unsigned>
280  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
287 
289  bool OutlineFromLinkOnceODRs) const override;
291  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
293  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
295  unsigned &Flags) const override;
297  const outliner::OutlinedFunction &OF) const override;
301  outliner::Candidate &C) const override;
302  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
303  /// Returns the vector element size (B, H, S or D) of an SVE opcode.
304  uint64_t getElementSizeForOpcode(unsigned Opc) const;
305  /// Returns true if the opcode is for an SVE instruction that sets the
306  /// condition codes as if it's results had been fed to a PTEST instruction
307  /// along with the same general predicate.
308  bool isPTestLikeOpcode(unsigned Opc) const;
309  /// Returns true if the opcode is for an SVE WHILE## instruction.
310  bool isWhileOpcode(unsigned Opc) const;
311  /// Returns true if the instruction has a shift by immediate that can be
312  /// executed in one cycle less.
313  static bool isFalkorShiftExtFast(const MachineInstr &MI);
314  /// Return true if the instructions is a SEH instruciton used for unwinding
315  /// on Windows.
316  static bool isSEHInstruction(const MachineInstr &MI);
317 
319  Register Reg) const override;
320 
322  Register Reg) const override;
323 
324  unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
325 
327  MachineRegisterInfo &MRI) const override;
328 
329  static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset,
330  int64_t &NumBytes,
331  int64_t &NumPredicateVectors,
332  int64_t &NumDataVectors);
333  static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset,
334  int64_t &ByteSized,
335  int64_t &VGSized);
336 #define GET_INSTRINFO_HELPER_DECLS
337 #include "AArch64GenInstrInfo.inc"
338 
339 protected:
340  /// If the specific machine instruction is an instruction that moves/copies
341  /// value from one register to another register return destination and source
342  /// registers as machine operands.
343  Optional<DestSourcePair>
344  isCopyInstrImpl(const MachineInstr &MI) const override;
345 
346 private:
347  unsigned getInstBundleLength(const MachineInstr &MI) const;
348 
349  /// Sets the offsets on outlined instructions in \p MBB which use SP
350  /// so that they will be valid post-outlining.
351  ///
352  /// \param MBB A \p MachineBasicBlock in an outlined function.
353  void fixupPostOutline(MachineBasicBlock &MBB) const;
354 
355  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
356  MachineBasicBlock *TBB,
357  ArrayRef<MachineOperand> Cond) const;
358  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
359  const MachineRegisterInfo &MRI) const;
360  bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
361  int CmpValue, const MachineRegisterInfo &MRI) const;
362 
363  /// Returns an unused general-purpose register which can be used for
364  /// constructing an outlined call if one exists. Returns 0 otherwise.
365  Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
366 
367  /// Remove a ptest of a predicate-generating operation that already sets, or
368  /// can be made to set, the condition codes in an identical manner
369  bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
370  unsigned PredReg,
371  const MachineRegisterInfo *MRI) const;
372 };
373 
374 struct UsedNZCV {
375  bool N = false;
376  bool Z = false;
377  bool C = false;
378  bool V = false;
379 
380  UsedNZCV() = default;
381 
382  UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
383  this->N |= UsedFlags.N;
384  this->Z |= UsedFlags.Z;
385  this->C |= UsedFlags.C;
386  this->V |= UsedFlags.V;
387  return *this;
388  }
389 };
390 
391 /// \returns Conditions flags used after \p CmpInstr in its MachineBB if NZCV
392 /// flags are not alive in successors of the same \p CmpInstr and \p MI parent.
393 /// \returns None otherwise.
394 ///
395 /// Collect instructions using that flags in \p CCUseInstrs if provided.
396 Optional<UsedNZCV>
397 examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
398  const TargetRegisterInfo &TRI,
399  SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr);
400 
401 /// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
402 /// which either reads or clobbers NZCV.
403 bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
404  const MachineInstr &UseMI,
405  const TargetRegisterInfo *TRI);
406 
407 MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,
408  unsigned Reg, const StackOffset &Offset,
409  bool LastAdjustmentWasScalable = true);
410 MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg,
411  const StackOffset &OffsetFromDefCFA);
412 
413 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
414 /// plus Offset. This is intended to be used from within the prolog/epilog
415 /// insertion (PEI) pass, where a virtual scratch register may be allocated
416 /// if necessary, to be replaced by the scavenger at the end of PEI.
417 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
418  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
419  StackOffset Offset, const TargetInstrInfo *TII,
421  bool SetNZCV = false, bool NeedsWinCFI = false,
422  bool *HasWinCFI = nullptr, bool EmitCFAOffset = false,
423  StackOffset InitialOffset = {},
424  unsigned FrameReg = AArch64::SP);
425 
426 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
427 /// FP. Return false if the offset could not be handled directly in MI, and
428 /// return the left-over portion by reference.
429 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
430  unsigned FrameReg, StackOffset &Offset,
431  const AArch64InstrInfo *TII);
432 
433 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
435  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
436  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
437  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
438 };
439 
440 /// Check if the @p Offset is a valid frame offset for @p MI.
441 /// The returned value reports the validity of the frame offset for @p MI.
442 /// It uses the values defined by AArch64FrameOffsetStatus for that.
443 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
444 /// use an offset.eq
445 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
446 /// rewritten in @p MI.
447 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
448 /// amount that is off the limit of the legal offset.
449 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
450 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
451 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
452 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
453 /// is a legal offset.
454 int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
455  bool *OutUseUnscaledOp = nullptr,
456  unsigned *OutUnscaledOp = nullptr,
457  int64_t *EmittableOffset = nullptr);
458 
459 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
460 
461 static inline bool isCondBranchOpcode(int Opc) {
462  switch (Opc) {
463  case AArch64::Bcc:
464  case AArch64::CBZW:
465  case AArch64::CBZX:
466  case AArch64::CBNZW:
467  case AArch64::CBNZX:
468  case AArch64::TBZW:
469  case AArch64::TBZX:
470  case AArch64::TBNZW:
471  case AArch64::TBNZX:
472  return true;
473  default:
474  return false;
475  }
476 }
477 
478 static inline bool isIndirectBranchOpcode(int Opc) {
479  switch (Opc) {
480  case AArch64::BR:
481  case AArch64::BRAA:
482  case AArch64::BRAB:
483  case AArch64::BRAAZ:
484  case AArch64::BRABZ:
485  return true;
486  }
487  return false;
488 }
489 
490 static inline bool isPTrueOpcode(unsigned Opc) {
491  switch (Opc) {
492  case AArch64::PTRUE_B:
493  case AArch64::PTRUE_H:
494  case AArch64::PTRUE_S:
495  case AArch64::PTRUE_D:
496  return true;
497  default:
498  return false;
499  }
500 }
501 
502 /// Return opcode to be used for indirect calls.
503 unsigned getBLRCallOpcode(const MachineFunction &MF);
504 
505 // struct TSFlags {
506 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
507 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
508 #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
509 #define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
510 // }
511 
512 namespace AArch64 {
513 
521 };
522 
535 };
536 
541 };
542 
543 // NOTE: This is a bit field.
546 
547 #undef TSFLAG_ELEMENT_SIZE_TYPE
548 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
549 #undef TSFLAG_FALSE_LANE_TYPE
550 #undef TSFLAG_INSTR_FLAGS
551 
552 int getSVEPseudoMap(uint16_t Opcode);
553 int getSVERevInstr(uint16_t Opcode);
554 int getSVENonRevInstr(uint16_t Opcode);
555 }
556 
557 } // end namespace llvm
558 
559 #endif
llvm::AArch64InstrInfo::getTailDuplicateSize
unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override
Definition: AArch64InstrInfo.cpp:8140
llvm::AArch64::DestructiveInstType
DestructiveInstType
Definition: AArch64InstrInfo.h:523
llvm::AArch64InstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:8080
llvm::AArch64::ElementSizeNone
@ ElementSizeNone
Definition: AArch64InstrInfo.h:516
AArch64RegisterInfo.h
llvm::AArch64InstrInfo::suppressLdStPair
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Definition: AArch64InstrInfo.cpp:2133
llvm::AArch64InstrInfo::isThroughputPattern
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
Definition: AArch64InstrInfo.cpp:5259
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
AArch64.h
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::AArch64InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: AArch64InstrInfo.cpp:3437
Optional.h
TSFLAG_DESTRUCTIVE_INST_TYPE
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
Definition: AArch64InstrInfo.h:507
llvm::AArch64InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:1835
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::AArch64InstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: AArch64InstrInfo.cpp:78
llvm::AArch64::FalseLanesZero
@ FalseLanesZero
Definition: AArch64InstrInfo.h:539
llvm::AArch64InstrInfo::getAddrModeFromMemoryOp
Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2560
llvm::AArch64::ElementSizeS
@ ElementSizeS
Definition: AArch64InstrInfo.h:519
llvm::AArch64FrameOffsetCanUpdate
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
Definition: AArch64InstrInfo.h:437
llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Definition: AArch64InstrInfo.cpp:2578
TypeSize.h
llvm::AArch64::InstrFlagIsPTestLike
static const uint64_t InstrFlagIsPTestLike
Definition: AArch64InstrInfo.h:545
llvm::UsedNZCV::V
bool V
Definition: AArch64InstrInfo.h:378
llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2544
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:8144
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::examineCFlagsUse
Optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)
Definition: AArch64InstrInfo.cpp:1614
llvm::AArch64InstrInfo::isPreLdSt
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
Definition: AArch64InstrInfo.cpp:3151
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(const MachineInstr &MI)
Definition: AArch64InstrInfo.h:93
llvm::AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6807
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
llvm::AArch64InstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
Definition: AArch64InstrInfo.cpp:7904
llvm::AArch64InstrInfo::getElementSizeForOpcode
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
Definition: AArch64InstrInfo.cpp:8127
TargetInstrInfo.h
llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: AArch64InstrInfo.cpp:1043
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:461
llvm::rewriteAArch64FrameIndex
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: AArch64InstrInfo.cpp:4694
llvm::UsedNZCV::operator|=
UsedNZCV & operator|=(const UsedNZCV &UsedFlags)
Definition: AArch64InstrInfo.h:382
llvm::AArch64InstrInfo::isFpOrNEON
static bool isFpOrNEON(const MachineInstr &MI)
Returns whether the instruction is FP or NEON.
Definition: AArch64InstrInfo.cpp:3212
llvm::AArch64::ElementSizeB
@ ElementSizeB
Definition: AArch64InstrInfo.h:517
llvm::AArch64::DestructiveTernaryCommWithRev
@ DestructiveTernaryCommWithRev
Definition: AArch64InstrInfo.h:533
llvm::Optional< unsigned >
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:459
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::AArch64InstrInfo::copyGPRRegTuple
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:3412
llvm::UsedNZCV
Definition: AArch64InstrInfo.h:374
llvm::AArch64::DestructiveOther
@ DestructiveOther
Definition: AArch64InstrInfo.h:526
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AArch64InstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: AArch64InstrInfo.cpp:7766
llvm::AArch64FrameOffsetCannotUpdate
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
Definition: AArch64InstrInfo.h:435
llvm::AArch64InstrInfo::isPairableLdStInst
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
Definition: AArch64InstrInfo.cpp:2343
llvm::AArch64::getSVERevInstr
int getSVERevInstr(uint16_t Opcode)
AArch64GenInstrInfo
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::AArch64InstrInfo::getLoadStoreImmIdx
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
Definition: AArch64InstrInfo.cpp:2211
llvm::AArch64::FalseLaneType
FalseLaneType
Definition: AArch64InstrInfo.h:537
llvm::AArch64InstrInfo::isWhileOpcode
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
Definition: AArch64InstrInfo.cpp:8135
llvm::MOStridedAccess
static const MachineMemOperand::Flags MOStridedAccess
Definition: AArch64InstrInfo.h:32
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:37
llvm::AArch64InstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:1081
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AArch64InstrInfo::isGPRZero
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
Definition: AArch64InstrInfo.cpp:2005
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AArch64::InstrFlagIsWhile
static const uint64_t InstrFlagIsWhile
Definition: AArch64InstrInfo.h:544
llvm::AArch64InstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:7980
llvm::AArch64InstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: AArch64InstrInfo.cpp:5414
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::AArch64InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: AArch64InstrInfo.cpp:493
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::AArch64InstrInfo::isStridedAccess
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
Definition: AArch64InstrInfo.cpp:2140
llvm::AArch64::DestructiveUnaryPassthru
@ DestructiveUnaryPassthru
Definition: AArch64InstrInfo.h:534
MachineCombinerPattern.h
llvm::AArch64InstrInfo::copyPhysRegTuple
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:3385
llvm::AArch64InstrInfo::isFPRCopy
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
Definition: AArch64InstrInfo.cpp:2059
llvm::AArch64InstrInfo::useMachineCombiner
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
Definition: AArch64InstrInfo.cpp:4734
llvm::createDefCFA
MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)
Definition: AArch64InstrInfo.cpp:4183
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AArch64InstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:211
llvm::AArch64::ElementSizeType
ElementSizeType
Definition: AArch64InstrInfo.h:514
llvm::AArch64InstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: AArch64InstrInfo.cpp:1023
llvm::AArch64FrameOffsetIsLegal
@ AArch64FrameOffsetIsLegal
Offset is legal.
Definition: AArch64InstrInfo.h:436
llvm::AArch64::NotDestructive
@ NotDestructive
Definition: AArch64InstrInfo.h:525
llvm::isAArch64FrameOffsetLegal
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
Definition: AArch64InstrInfo.cpp:4593
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:478
x2
gcc mainline compiles it x2(%rip)
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::AArch64InstrInfo::isPreLd
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
Definition: AArch64InstrInfo.cpp:3125
llvm::MOSuppressPair
static const MachineMemOperand::Flags MOSuppressPair
Definition: AArch64InstrInfo.h:30
TSFLAG_INSTR_FLAGS
#define TSFLAG_INSTR_FLAGS(X)
Definition: AArch64InstrInfo.h:509
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::UsedNZCV::C
bool C
Definition: AArch64InstrInfo.h:377
llvm::DenseMap< unsigned, unsigned >
llvm::AArch64InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: AArch64InstrInfo.cpp:441
TSFLAG_ELEMENT_SIZE_TYPE
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
Definition: AArch64InstrInfo.h:506
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AArch64InstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: AArch64InstrInfo.cpp:7513
llvm::AArch64InstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: AArch64InstrInfo.cpp:7414
llvm::AArch64InstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: AArch64InstrInfo.cpp:5730
llvm::UsedNZCV::N
bool N
Definition: AArch64InstrInfo.h:375
llvm::AArch64InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:2078
llvm::AArch64InstrInfo::getNop
MCInst getNop() const override
Definition: AArch64InstrInfo.cpp:4729
llvm::AArch64InstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: AArch64InstrInfo.cpp:7444
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::isNZCVTouchedInInstructionRange
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
Definition: AArch64InstrInfo.cpp:4065
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::AArch64InstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: AArch64InstrInfo.cpp:6984
llvm::AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6819
llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
Definition: AArch64InstrInfo.cpp:2627
llvm::AArch64InstrInfo::AArch64InstrInfo
AArch64InstrInfo(const AArch64Subtarget &STI)
Definition: AArch64InstrInfo.cpp:71
llvm::emitFrameOffset
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
Definition: AArch64InstrInfo.cpp:4360
llvm::AArch64InstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:8005
llvm::AArch64InstrInfo::getUnscaledLdSt
static Optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
Definition: AArch64InstrInfo.cpp:2181
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AArch64InstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
Definition: AArch64InstrInfo.cpp:3298
llvm::AArch64InstrInfo::isGPRCopy
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
Definition: AArch64InstrInfo.cpp:2029
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::AArch64InstrInfo::isPTestLikeOpcode
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
Definition: AArch64InstrInfo.cpp:8131
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::AArch64::FalseLanesMask
@ FalseLanesMask
Definition: AArch64InstrInfo.h:538
llvm::AArch64InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
Definition: AArch64InstrInfo.cpp:7986
llvm::AArch64InstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: AArch64InstrInfo.cpp:6801
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64InstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: AArch64InstrInfo.cpp:601
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3936
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6835
llvm::AArch64::DestructiveUnary
@ DestructiveUnary
Definition: AArch64InstrInfo.h:527
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::AArch64InstrInfo::decomposeStackOffsetForFrameOffsets
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
Definition: AArch64InstrInfo.cpp:4095
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64::ElementSizeD
@ ElementSizeD
Definition: AArch64InstrInfo.h:520
llvm::AArch64InstrInfo::hasUnscaledLdStOffset
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
Definition: AArch64InstrInfo.cpp:2146
llvm::AArch64InstrInfo::getLdStBaseOp
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
Definition: AArch64InstrInfo.cpp:3175
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:47
llvm::AArch64InstrInfo::isPairedLdSt
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
Definition: AArch64InstrInfo.cpp:3155
llvm::AArch64::DestructiveBinaryShImmUnpred
@ DestructiveBinaryShImmUnpred
Definition: AArch64InstrInfo.h:529
uint16_t
llvm::AArch64InstrInfo::convertToFlagSettingOpc
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Definition: AArch64InstrInfo.cpp:2385
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:982
llvm::AArch64InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3782
llvm::AArch64::ElementSizeMask
@ ElementSizeMask
Definition: AArch64InstrInfo.h:515
llvm::TypeSize
Definition: TypeSize.h:435
llvm::AArch64InstrInfo::getMemOpInfo
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
Definition: AArch64InstrInfo.cpp:2634
llvm::AArch64::DestructiveInstTypeMask
@ DestructiveInstTypeMask
Definition: AArch64InstrInfo.h:524
llvm::AArch64InstrInfo::isLdStPairSuppressed
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
Definition: AArch64InstrInfo.cpp:2126
llvm::AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
Definition: AArch64InstrInfo.cpp:4076
llvm::AArch64InstrInfo::analyzeBranchPredicate
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
Definition: AArch64InstrInfo.cpp:350
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::AArch64InstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: AArch64InstrInfo.cpp:650
llvm::AArch64InstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
Definition: AArch64InstrInfo.cpp:1422
llvm::AArch64InstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: AArch64InstrInfo.cpp:202
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::AArch64::DestructiveBinaryComm
@ DestructiveBinaryComm
Definition: AArch64InstrInfo.h:531
TSFLAG_FALSE_LANE_TYPE
#define TSFLAG_FALSE_LANE_TYPE(X)
Definition: AArch64InstrInfo.h:508
llvm::AArch64FrameOffsetStatus
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
Definition: AArch64InstrInfo.h:434
llvm::AArch64::DestructiveBinary
@ DestructiveBinary
Definition: AArch64InstrInfo.h:530
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1222
llvm::AArch64InstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: AArch64InstrInfo.cpp:4412
llvm::AArch64InstrInfo::isQForm
static bool isQForm(const MachineInstr &MI)
Returns whether the instruction is in Q form (128 bit operands)
Definition: AArch64InstrInfo.cpp:3198
llvm::UsedNZCV::Z
bool Z
Definition: AArch64InstrInfo.h:376
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::AArch64::getSVEPseudoMap
int getSVEPseudoMap(uint16_t Opcode)
llvm::AArch64InstrInfo::isExtendLikelyToBeFolded
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
Definition: AArch64InstrInfo.cpp:8107
llvm::AArch64InstrInfo::getLdStOffsetOp
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the the immediate offset operator of a load/store.
Definition: AArch64InstrInfo.cpp:3183
llvm::AArch64InstrInfo::hasUnscaledLdStOffset
static bool hasUnscaledLdStOffset(MachineInstr &MI)
Definition: AArch64InstrInfo.h:83
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::AArch64InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: AArch64InstrInfo.cpp:400
llvm::AArch64::DestructiveBinaryImm
@ DestructiveBinaryImm
Definition: AArch64InstrInfo.h:528
llvm::AArch64::DestructiveBinaryCommWithRev
@ DestructiveBinaryCommWithRev
Definition: AArch64InstrInfo.h:532
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
Definition: AArch64InstrInfo.cpp:3053
llvm::AArch64InstrInfo::optimizeCondBranch
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
Definition: AArch64InstrInfo.cpp:6663
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AArch64InstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
Definition: AArch64InstrInfo.cpp:1107
llvm::AArch64InstrInfo::isFalkorShiftExtFast
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition: AArch64InstrInfo.cpp:875
llvm::isPTrueOpcode
static bool isPTrueOpcode(unsigned Opc)
Definition: AArch64InstrInfo.h:490
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64InstrInfo::isCandidateToMergeOrPair
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
Definition: AArch64InstrInfo.cpp:2475
llvm::createCFAOffset
MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA)
Definition: AArch64InstrInfo.cpp:4197
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64::FalseLanesUndef
@ FalseLanesUndef
Definition: AArch64InstrInfo.h:540
llvm::AArch64::getSVENonRevInstr
int getSVENonRevInstr(uint16_t Opcode)
llvm::AArch64InstrInfo::isPreSt
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
Definition: AArch64InstrInfo.cpp:3138
llvm::AArch64InstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
Definition: AArch64InstrInfo.cpp:4894
llvm::AArch64InstrInfo::isSubregFoldable
bool isSubregFoldable() const override
Definition: AArch64InstrInfo.h:195
llvm::AArch64InstrInfo::isAsCheapAsAMove
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:796
llvm::AArch64InstrInfo::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
Definition: AArch64InstrInfo.cpp:997
llvm::AArch64InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:2101
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::UsedNZCV::UsedNZCV
UsedNZCV()=default
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::AArch64InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: AArch64InstrInfo.cpp:232
llvm::AArch64::ElementSizeH
@ ElementSizeH
Definition: AArch64InstrInfo.h:518