LLVM 20.0.0git
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#include "Target/AArch64/AArch64InstrInfo.h"
Static Public Member Functions | |
static bool | isGPRZero (const MachineInstr &MI) |
Does this instruction set its full destination register to zero? | |
static bool | isGPRCopy (const MachineInstr &MI) |
Does this instruction rename a GPR without modifying bits? | |
static bool | isFPRCopy (const MachineInstr &MI) |
Does this instruction rename an FPR without modifying bits? | |
static bool | isLdStPairSuppressed (const MachineInstr &MI) |
Return true if pairing the given load or store is hinted to be unprofitable. | |
static bool | isStridedAccess (const MachineInstr &MI) |
Return true if the given load or store is a strided memory access. | |
static bool | hasUnscaledLdStOffset (unsigned Opc) |
Return true if it has an unscaled load/store offset. | |
static bool | hasUnscaledLdStOffset (MachineInstr &MI) |
static std::optional< unsigned > | getUnscaledLdSt (unsigned Opc) |
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscaled variant available. | |
static int | getMemScale (unsigned Opc) |
Scaling factor for (scaled or unscaled) load or store. | |
static int | getMemScale (const MachineInstr &MI) |
static bool | isPreLd (const MachineInstr &MI) |
Returns whether the instruction is a pre-indexed load. | |
static bool | isPreSt (const MachineInstr &MI) |
Returns whether the instruction is a pre-indexed store. | |
static bool | isPreLdSt (const MachineInstr &MI) |
Returns whether the instruction is a pre-indexed load/store. | |
static bool | isPairedLdSt (const MachineInstr &MI) |
Returns whether the instruction is a paired load/store. | |
static const MachineOperand & | getLdStBaseOp (const MachineInstr &MI) |
Returns the base register operator of a load/store. | |
static const MachineOperand & | getLdStOffsetOp (const MachineInstr &MI) |
Returns the immediate offset operator of a load/store. | |
static bool | isFpOrNEON (Register Reg) |
Returns whether the physical register is FP or NEON. | |
static bool | isFpOrNEON (const MachineInstr &MI) |
Returns whether the instruction is FP or NEON. | |
static bool | isHForm (const MachineInstr &MI) |
Returns whether the instruction is in H form (16 bit operands) | |
static bool | isQForm (const MachineInstr &MI) |
Returns whether the instruction is in Q form (128 bit operands) | |
static bool | hasBTISemantics (const MachineInstr &MI) |
Returns whether the instruction can be compatible with non-zero BTYPE. | |
static unsigned | getLoadStoreImmIdx (unsigned Opc) |
Returns the index for the immediate for a given instruction. | |
static bool | isPairableLdStInst (const MachineInstr &MI) |
Return true if pairing the given load or store may be paired with another. | |
static bool | isTailCallReturnInst (const MachineInstr &MI) |
Returns true if MI is one of the TCRETURN* instructions. | |
static unsigned | convertToFlagSettingOpc (unsigned Opc) |
Return the opcode that set flags when possible. | |
static void | suppressLdStPair (MachineInstr &MI) |
Hint that pairing the given load or store is unprofitable. | |
static bool | getMemOpInfo (unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset) |
Returns true if opcode Opc is a memory operation. | |
static bool | isFalkorShiftExtFast (const MachineInstr &MI) |
Returns true if the instruction has a shift by immediate that can be executed in one cycle less. | |
static bool | isSEHInstruction (const MachineInstr &MI) |
Return true if the instructions is a SEH instruciton used for unwinding on Windows. | |
static void | decomposeStackOffsetForFrameOffsets (const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors) |
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset. | |
static void | decomposeStackOffsetForDwarfOffsets (const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized) |
Protected Member Functions | |
std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
std::optional< DestSourcePair > | isCopyLikeInstrImpl (const MachineInstr &MI) const override |
Definition at line 176 of file AArch64InstrInfo.h.
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Definition at line 82 of file AArch64InstrInfo.cpp.
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Definition at line 333 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), Cond, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), getBranchDestBlock(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::isUncondBranchOpcode(), MBB, parseCondBranch(), and TBB.
Referenced by analyzeLoopForPipelining().
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Definition at line 449 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), and MBB.
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1174 of file AArch64InstrInfo.cpp.
References assert(), llvm::AArch64_AM::decodeLogicalImmediate(), and MI.
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Definition at line 10156 of file AArch64InstrInfo.cpp.
References analyzeBranch(), assert(), Cond, llvm::MachineBasicBlock::getFirstTerminator(), getIndVarInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), isDefinedOutside(), isWhileOpcode(), MI, llvm::reverse(), reverseBranchCondition(), TBB, and TRI.
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Definition at line 1101 of file AArch64InstrInfo.cpp.
References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::MachineInstr::mayLoadOrStore(), and TRI.
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Definition at line 9485 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineBasicBlock::getParent(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MBB, and TRI.
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Definition at line 9275 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::any_of(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MCCFIInstruction::cfiDefCfaOffset(), llvm::MCCFIInstruction::createOffset(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::MachineInstr::FrameSetup, llvm::get(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::instr_end(), llvm::MachineBasicBlock::instrs(), llvm::MachineBasicBlock::isLiveIn(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, MRI, llvm::AArch64FunctionInfo::needsDwarfUnwindInfo(), llvm::MachineInstrBuilder::setMIFlags(), llvm::AArch64FunctionInfo::setOutliningStyle(), llvm::AArch64FunctionInfo::shouldSignReturnAddress(), and signOutlinedFunction().
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Definition at line 2737 of file AArch64InstrInfo.cpp.
References llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Basic, DefMI, llvm::ExtAddrMode::Displacement, llvm::ExtAddrMode::Form, llvm::AArch64_AM::getArithExtendType(), llvm::AArch64_AM::getArithShiftValue(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getRegInfo(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::Function::hasOptSize(), isLegalAddressingMode(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::AArch64_AM::LSL, MRI, llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, llvm::ExtAddrMode::SExtScaledReg, llvm::AArch64_AM::SXTW, llvm::AArch64_AM::UXTW, and llvm::ExtAddrMode::ZExtScaledReg.
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Definition at line 702 of file AArch64InstrInfo.cpp.
References canFoldIntoCSel(), Cond, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MBB, and MRI.
Return the opcode that set flags when possible.
The caller is responsible for ensuring the opc has a flag setting equivalent.
Definition at line 2537 of file AArch64InstrInfo.cpp.
References llvm_unreachable.
void AArch64InstrInfo::copyGPRRegTuple | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | I, | ||
DebugLoc | DL, | ||
unsigned | DestReg, | ||
unsigned | SrcReg, | ||
bool | KillSrc, | ||
unsigned | Opcode, | ||
unsigned | ZeroReg, | ||
llvm::ArrayRef< unsigned > | Indices | ||
) | const |
Definition at line 4640 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, MBB, llvm::ArrayRef< T >::size(), SubReg, and TRI.
Referenced by copyPhysReg().
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Definition at line 4665 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyGPRRegTuple(), copyPhysRegTuple(), llvm::RegState::Define, DL, llvm::errs(), llvm::get(), llvm::getKillRegState(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), I, llvm::RegState::Implicit, llvm::AArch64Subtarget::isNeonAvailable(), llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm_unreachable, llvm::AArch64_AM::LSL, MBB, TRI, and llvm::RegState::Undef.
void AArch64InstrInfo::copyPhysRegTuple | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | I, | ||
const DebugLoc & | DL, | ||
MCRegister | DestReg, | ||
MCRegister | SrcReg, | ||
bool | KillSrc, | ||
unsigned | Opcode, | ||
llvm::ArrayRef< unsigned > | Indices | ||
) | const |
Definition at line 4613 of file AArch64InstrInfo.cpp.
References AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, DL, End, forwardCopyWillClobberTuple(), llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, MBB, llvm::ArrayRef< T >::size(), SubReg, and TRI.
Referenced by copyPhysReg().
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Definition at line 8316 of file AArch64InstrInfo.cpp.
References llvm::AArch64II::MO_FRAGMENT.
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Definition at line 5378 of file AArch64InstrInfo.cpp.
References assert(), and llvm::Offset.
Referenced by llvm::createCFAOffset(), and createDefCFAExpression().
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Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset.
For non-scalable offsets this is simply its byte size.
Definition at line 5397 of file AArch64InstrInfo.cpp.
References assert(), and llvm::Offset.
Referenced by llvm::emitFrameOffset().
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Definition at line 9663 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::CreateImm(), llvm::TargetInstrInfo::describeLoadedValue(), describeORRLoadedValue(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MI, and TRI.
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Definition at line 3413 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Basic, llvm::BuildMI(), llvm::RegState::Define, llvm::ExtAddrMode::Displacement, DL, llvm::ExtAddrMode::Form, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm_unreachable, llvm::MachineInstr::mayLoad(), MBB, llvm::MachineInstr::memoperands(), MRI, offsetExtendOpcode(), regOffsetOpcode(), llvm::ExtAddrMode::Scale, scaledOffsetOpcode(), llvm::ExtAddrMode::ScaledReg, llvm::MachineInstrBuilder::setMemRefs(), llvm::MachineInstrBuilder::setMIFlags(), llvm::ExtAddrMode::SExtScaledReg, unscaledOffsetOpcode(), and llvm::ExtAddrMode::ZExtScaledReg.
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Definition at line 1967 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::AArch64SysReg::SysReg::Encoding, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::FrameDestroy, llvm::get(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::GlobalValue::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isTargetILP32(), llvm::RegState::Kill, llvm::CodeModel::Large, llvm::AArch64SysReg::lookupSysRegByName(), MBB, MBBI, MI, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::Offset, llvm::RegState::Renamable, llvm::report_fatal_error(), TII, llvm::CodeModel::Tiny, TM, and TRI.
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Target-dependent implementation for foldMemoryOperand.
Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Definition at line 1350 of file TargetInstrInfo.h.
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Definition at line 5725 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::Register::isVirtual(), llvm::Register::isVirtualRegister(), loadRegFromStackSlot(), MBB, MI, MRI, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setSubReg(), llvm::ArrayRef< T >::size(), storeRegToStackSlot(), and TRI.
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Target-dependent implementation for foldMemoryOperand.
Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Definition at line 1363 of file TargetInstrInfo.h.
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When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.
Definition at line 7198 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::AArch64_IMM::expandMOVImm(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f16_OP1, llvm::FMLAv4f16_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i16_indexed_OP1, llvm::FMLAv4i16_indexed_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLAv8f16_OP1, llvm::FMLAv8f16_OP2, llvm::FMLAv8i16_indexed_OP1, llvm::FMLAv8i16_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP1, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP1, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP1, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP1, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f16_OP1, llvm::FMLSv4f16_OP2, llvm::FMLSv4f32_OP1, llvm::FMLSv4f32_OP2, llvm::FMLSv4i16_indexed_OP1, llvm::FMLSv4i16_indexed_OP2, llvm::FMLSv4i32_indexed_OP1, llvm::FMLSv4i32_indexed_OP2, llvm::FMLSv8f16_OP1, llvm::FMLSv8f16_OP2, llvm::FMLSv8i16_indexed_OP1, llvm::FMLSv8i16_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDH_OP1, llvm::FMULADDH_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBH_OP1, llvm::FMULSUBH_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FMULv2i32_indexed_OP1, llvm::FMULv2i32_indexed_OP2, llvm::FMULv2i64_indexed_OP1, llvm::FMULv2i64_indexed_OP2, llvm::FMULv4i16_indexed_OP1, llvm::FMULv4i16_indexed_OP2, llvm::FMULv4i32_indexed_OP1, llvm::FMULv4i32_indexed_OP2, llvm::FMULv8i16_indexed_OP1, llvm::FMULv8i16_indexed_OP2, llvm::FNMADD, llvm::FNMULSUBD_OP1, llvm::FNMULSUBH_OP1, llvm::FNMULSUBS_OP1, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFNegatedMAD(), genFusedMultiply(), genFusedMultiplyAcc(), genFusedMultiplyAccNeg(), genFusedMultiplyIdx(), genFusedMultiplyIdxNeg(), genIndexedMultiply(), genMaddR(), genSubAdd2SubSub(), llvm::MachineInstr::getFlags(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), Insn, llvm::MachineOperand::isImm(), MBB, llvm::MachineInstr::mergeFlagsWith(), MI, MRI, llvm::MULADDv16i8_OP1, llvm::MULADDv16i8_OP2, llvm::MULADDv2i32_indexed_OP1, llvm::MULADDv2i32_indexed_OP2, llvm::MULADDv2i32_OP1, llvm::MULADDv2i32_OP2, llvm::MULADDv4i16_indexed_OP1, llvm::MULADDv4i16_indexed_OP2, llvm::MULADDv4i16_OP1, llvm::MULADDv4i16_OP2, llvm::MULADDv4i32_indexed_OP1, llvm::MULADDv4i32_indexed_OP2, llvm::MULADDv4i32_OP1, llvm::MULADDv4i32_OP2, llvm::MULADDv8i16_indexed_OP1, llvm::MULADDv8i16_indexed_OP2, llvm::MULADDv8i16_OP1, llvm::MULADDv8i16_OP2, llvm::MULADDv8i8_OP1, llvm::MULADDv8i8_OP2, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBv16i8_OP1, llvm::MULSUBv16i8_OP2, llvm::MULSUBv2i32_indexed_OP1, llvm::MULSUBv2i32_indexed_OP2, llvm::MULSUBv2i32_OP1, llvm::MULSUBv2i32_OP2, llvm::MULSUBv4i16_indexed_OP1, llvm::MULSUBv4i16_indexed_OP2, llvm::MULSUBv4i16_OP1, llvm::MULSUBv4i16_OP2, llvm::MULSUBv4i32_indexed_OP1, llvm::MULSUBv4i32_indexed_OP2, llvm::MULSUBv4i32_OP1, llvm::MULSUBv4i32_OP2, llvm::MULSUBv8i16_indexed_OP1, llvm::MULSUBv8i16_indexed_OP2, llvm::MULSUBv8i16_OP1, llvm::MULSUBv8i16_OP2, llvm::MULSUBv8i8_OP1, llvm::MULSUBv8i8_OP2, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SignExtend64(), llvm::SUBADD_OP1, llvm::SUBADD_OP2, and TII.
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Definition at line 2719 of file AArch64InstrInfo.cpp.
References llvm::sampleprof::Base, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Displacement, llvm::Offset, llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, and TRI.
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Definition at line 240 of file AArch64InstrInfo.cpp.
References llvm_unreachable, and MI.
Referenced by analyzeBranch().
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Definition at line 6817 of file AArch64InstrInfo.cpp.
References llvm::TargetInstrInfo::getCombinerObjective(), llvm::MustReduceDepth, llvm::SUBADD_OP1, and llvm::SUBADD_OP2.
Returns the vector element size (B, H, S or D) of an SVE opcode.
Definition at line 9710 of file AArch64InstrInfo.cpp.
References llvm::AArch64::ElementSizeMask, and llvm::get().
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GetInstSize - Return the number of bytes of code the specified instruction may be.
This returns the maximum number of bytes.
Definition at line 89 of file AArch64InstrInfo.cpp.
References assert(), F, llvm::MachineFunction::getFunction(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::StatepointOpers::getNumPatchBytes(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), MBB, and MI.
Referenced by getOutliningCandidateInfo().
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Returns the base register operator of a load/store.
Definition at line 4326 of file AArch64InstrInfo.cpp.
References assert(), Idx, isPairedLdSt(), isPreLdSt(), and MI.
Referenced by mayOverlapWrite().
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Returns the immediate offset operator of a load/store.
Definition at line 4335 of file AArch64InstrInfo.cpp.
References assert(), Idx, isPairedLdSt(), isPreLdSt(), and MI.
Referenced by isLdOffsetInRangeOfSt(), isMergeableLdStUpdate(), mayOverlapWrite(), and needReorderStoreMI().
Returns the index for the immediate for a given instruction.
Definition at line 2344 of file AArch64InstrInfo.cpp.
Referenced by llvm::isAArch64FrameOffsetLegal().
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Return true when there is potentially a faster code sequence for an instruction chain ending in Root
.
Return true when there is potentially a faster code sequence for an instruction chain ending in Root
.
All potential patterns are listed in the Patterns
array.
All potential patterns are listed in the Pattern
vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
Definition at line 6832 of file AArch64InstrInfo.cpp.
References getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), getMaddPatterns(), and getMiscPatterns().
MachineOperand & AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand | ( | MachineInstr & | LdSt | ) | const |
Return the immediate offset of the base register in a load/store LdSt
.
Definition at line 3762 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and llvm::MachineInstr::mayLoadOrStore().
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Definition at line 2699 of file AArch64InstrInfo.cpp.
References getMemOperandWithOffsetWidth(), llvm::MachineInstr::mayLoadOrStore(), llvm::Offset, llvm::LocationSize::precise(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
bool AArch64InstrInfo::getMemOperandWithOffsetWidth | ( | const MachineInstr & | MI, |
const MachineOperand *& | BaseOp, | ||
int64_t & | Offset, | ||
bool & | OffsetIsScalable, | ||
TypeSize & | Width, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
If OffsetIsScalable
is set to 'true', the offset is scaled by vscale
.
This is true for some SVE instructions like ldr/str that have a 'reg + imm' addressing mode where the immediate is an index to the scalable vector located at 'reg + imm * vscale x #bytes'.
Definition at line 3713 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getMemOpInfo(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isPostIndexLdStOpcode(), llvm::MachineOperand::isReg(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::MachineInstr::mayLoadOrStore(), and llvm::Offset.
Referenced by areMemAccessesTriviallyDisjoint(), and getMemOperandsWithOffsetWidth().
|
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Returns true if opcode Opc
is a memory operation.
If it is, set Scale
, Width
, MinOffset
, and MaxOffset
accordingly.
For unscaled instructions, Scale
is set to 1. All values are in bytes. MinOffset/MaxOffset are the un-scaled limits of the immediate in the instruction, the actual offset limit is [MinOffset*Scale, MaxOffset*Scale].
Definition at line 3769 of file AArch64InstrInfo.cpp.
References llvm::TypeSize::getFixed(), and llvm::TypeSize::getScalable().
Referenced by emitLoad(), emitStore(), getMemOperandWithOffsetWidth(), and llvm::isAArch64FrameOffsetLegal().
|
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Definition at line 232 of file AArch64InstrInfo.h.
References getMemScale(), and MI.
|
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Scaling factor for (scaled or unscaled) load or store.
Definition at line 4202 of file AArch64InstrInfo.cpp.
References llvm_unreachable.
Referenced by getMemScale(), getPrePostIndexedMemOpInfo(), mayOverlapWrite(), scaleOffset(), and shouldClusterFI().
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Definition at line 6025 of file AArch64InstrInfo.cpp.
References llvm::MCInstBuilder::addImm().
|
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Definition at line 8971 of file AArch64InstrInfo.cpp.
References llvm::LiveRegUnits::addLiveOuts(), assert(), llvm::LiveRegUnits::available(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineBasicBlock::instr_rbegin(), llvm::MachineBasicBlock::instr_rend(), llvm::make_range(), MBB, MI, llvm::LiveRegUnits::stepBackward(), and llvm::MachineRegisterInfo::tracksLiveness().
|
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Definition at line 8502 of file AArch64InstrInfo.cpp.
References getInstSizeInBytes(), and MI.
|
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Definition at line 9084 of file AArch64InstrInfo.cpp.
References assert(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::getLOHRelated(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::MachineFrameInfo::getStackSize(), hasBTISemantics(), llvm::outliner::Illegal, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::outliner::Legal, llvm::outliner::LegalTerminator, MBB, and MI.
|
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 186 of file AArch64InstrInfo.h.
Referenced by analyzeLoopForPipelining(), areMemAccessesTriviallyDisjoint(), copyGPRRegTuple(), copyPhysReg(), copyPhysRegTuple(), getOutlinableRanges(), getOutliningTypeImpl(), llvm::AArch64Subtarget::getRegisterInfo(), isCandidateToMergeOrPair(), loadRegFromStackSlot(), optimizeCondBranch(), and storeRegToStackSlot().
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Definition at line 8334 of file AArch64InstrInfo.cpp.
|
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Definition at line 8322 of file AArch64InstrInfo.cpp.
|
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Definition at line 8352 of file AArch64InstrInfo.cpp.
References llvm::MOStridedAccess, and llvm::MOSuppressPair.
|
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Definition at line 9723 of file AArch64InstrInfo.cpp.
References llvm::Aggressive.
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscaled variant available.
Definition at line 2314 of file AArch64InstrInfo.cpp.
Referenced by llvm::isAArch64FrameOffsetLegal().
|
static |
Returns whether the instruction can be compatible with non-zero BTYPE.
Definition at line 4379 of file AArch64InstrInfo.cpp.
References MI.
Referenced by getOutliningTypeImpl(), and isSchedulingBoundary().
|
inlinestatic |
Definition at line 222 of file AArch64InstrInfo.h.
References hasUnscaledLdStOffset(), and MI.
Return true if it has an unscaled load/store offset.
Definition at line 2278 of file AArch64InstrInfo.cpp.
Referenced by hasUnscaledLdStOffset(), mayOverlapWrite(), and shouldClusterMemOps().
|
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Definition at line 592 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), MBB, and TBB.
|
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Definition at line 260 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MBBSectionID::ColdSectionID, llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::RegScavenger::FindUnusedReg(), llvm::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineBasicBlock::getSectionID(), llvm::AArch64FunctionInfo::hasRedZone(), llvm::RegScavenger::isRegUsed(), MBB, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::MachineBasicBlock::pred_size(), llvm::report_fatal_error(), and llvm::RegScavenger::setRegUsed().
|
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Definition at line 6019 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), MBB, and MI.
|
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Definition at line 9404 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::CallingConv::C, llvm::RegState::Define, llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::isLiveIn(), MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, and MBB.
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Definition at line 751 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), canFoldIntoCSel(), CC, Cond, DL, llvm::AArch64_AM::encodeLogicalImmediate(), llvm::AArch64CC::EQ, llvm::get(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), I, llvm_unreachable, MBB, MRI, and llvm::AArch64CC::NE.
|
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Definition at line 9540 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, and llvm::Offset.
|
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Definition at line 903 of file AArch64InstrInfo.cpp.
References isCheapImmediate(), and MI.
|
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Return true when Inst is associative and commutative so that it can be reassociated.
If Invert is true, then the inverse of Inst operation must be checked.
Definition at line 6190 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
|
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BranchOpc
bytes is capable of jumping to a position BrOffset
bytes away. Definition at line 231 of file AArch64InstrInfo.cpp.
References assert(), getBranchDisplacementBits(), and llvm::isIntN().
bool AArch64InstrInfo::isCandidateToMergeOrPair | ( | const MachineInstr & | MI | ) | const |
Return true if this is a load/store that can be potentially paired/merged.
Definition at line 2629 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, getRegisterInfo(), isLdStPairSuppressed(), isPreLdSt(), MI, TRI, and llvm::MCAsmInfo::usesWindowsCFI().
Referenced by shouldClusterMemOps().
|
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Definition at line 1081 of file AArch64InstrInfo.cpp.
References MI.
|
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If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 9506 of file AArch64InstrInfo.cpp.
References MI.
|
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Definition at line 9531 of file AArch64InstrInfo.cpp.
References MI.
|
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Definition at line 9690 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and MRI.
|
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Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition at line 930 of file AArch64InstrInfo.cpp.
References llvm::AArch64_AM::ASR, llvm::AArch64_AM::getArithExtendType(), llvm::AArch64_AM::getArithShiftValue(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::AArch64_AM::LSL, MI, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::AArch64_AM::UXTX.
|
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Returns whether the instruction is FP or NEON.
Definition at line 4416 of file AArch64InstrInfo.cpp.
References llvm::any_of(), getRegClass(), isFpOrNEON(), and MI.
Returns whether the physical register is FP or NEON.
Definition at line 4405 of file AArch64InstrInfo.cpp.
References assert().
Referenced by llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), computeCalleeSaveRegisterPairs(), isFpOrNEON(), and llvm::AArch64FrameLowering::orderFrameObjects().
|
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Does this instruction rename an FPR without modifying bits?
Definition at line 2191 of file AArch64InstrInfo.cpp.
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Definition at line 8933 of file AArch64InstrInfo.cpp.
References F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), llvm::AArch64FunctionInfo::hasRedZone(), llvm::AArch64FunctionInfo::hasStreamingModeChanges(), and llvm::MCAsmInfo::usesWindowsCFI().
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Definition at line 9613 of file AArch64InstrInfo.cpp.
References llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::hasRedZone(), and llvm::TargetInstrInfo::isFunctionSafeToSplit().
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static |
Does this instruction rename a GPR without modifying bits?
Definition at line 2161 of file AArch64InstrInfo.cpp.
References assert(), contains(), and MI.
|
static |
Does this instruction set its full destination register to zero?
Definition at line 2137 of file AArch64InstrInfo.cpp.
|
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Returns whether the instruction is in H form (16 bit operands)
Definition at line 4351 of file AArch64InstrInfo.cpp.
References llvm::any_of(), contains(), getRegClass(), and MI.
|
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Return true if pairing the given load or store is hinted to be unprofitable.
Check all MachineMemOperands for a hint to suppress pairing.
Definition at line 2258 of file AArch64InstrInfo.cpp.
References llvm::any_of(), and MI.
Referenced by isCandidateToMergeOrPair().
bool AArch64InstrInfo::isLegalAddressingMode | ( | unsigned | NumBytes, |
int64_t | Offset, | ||
unsigned | Scale | ||
) | const |
Definition at line 9727 of file AArch64InstrInfo.cpp.
References llvm::Log2_64(), and llvm::Offset.
Referenced by canFoldIntoAddrMode(), and llvm::AArch64TargetLowering::isLegalAddressingMode().
|
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Definition at line 2210 of file AArch64InstrInfo.cpp.
References MI.
|
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Definition at line 9624 of file AArch64InstrInfo.cpp.
References llvm::any_of(), llvm::MachineFunction::getJumpTableInfo(), llvm::MachineJumpTableInfo::getJumpTables(), llvm::MachineBasicBlock::getParent(), llvm::is_contained(), llvm::MachineBasicBlock::isInlineAsmBrIndirectTarget(), MBB, and MI.
|
static |
Return true if pairing the given load or store may be paired with another.
Definition at line 2476 of file AArch64InstrInfo.cpp.
References MI.
Referenced by shouldClusterMemOps().
|
static |
Returns whether the instruction is a paired load/store.
Definition at line 4306 of file AArch64InstrInfo.cpp.
References MI.
Referenced by getLdStBaseOp(), getLdStOffsetOp(), getLdStRegOp(), getPrePostIndexedMemOpInfo(), and mayOverlapWrite().
|
static |
Returns whether the instruction is a pre-indexed load.
Definition at line 4275 of file AArch64InstrInfo.cpp.
References MI.
Referenced by isPreLdSt().
|
static |
Returns whether the instruction is a pre-indexed load/store.
Definition at line 4302 of file AArch64InstrInfo.cpp.
References isPreLd(), isPreSt(), and MI.
Referenced by areCandidatesToMergeOrPair(), getLdStBaseOp(), getLdStOffsetOp(), getLdStRegOp(), and isCandidateToMergeOrPair().
|
static |
Returns whether the instruction is a pre-indexed store.
Definition at line 4289 of file AArch64InstrInfo.cpp.
References MI.
Referenced by isPreLdSt().
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results had been fed to a PTEST instruction along with the same general predicate.
Definition at line 9714 of file AArch64InstrInfo.cpp.
References llvm::get(), and llvm::AArch64::InstrFlagIsPTestLike.
|
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Returns whether the instruction is in Q form (128 bit operands)
Definition at line 4365 of file AArch64InstrInfo.cpp.
References llvm::any_of(), contains(), getRegClass(), and MI.
|
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Definition at line 1140 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::end(), hasBTISemantics(), llvm::TargetInstrInfo::isSchedulingBoundary(), isSEHInstruction(), MBB, and MI.
|
static |
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
Definition at line 1052 of file AArch64InstrInfo.cpp.
References MI.
Referenced by convertCalleeSaveRestoreToSPPrePostIncDec(), llvm::AArch64FrameLowering::emitEpilogue(), fixupCalleeSaveRestoreStackOffset(), and isSchedulingBoundary().
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Definition at line 2234 of file AArch64InstrInfo.cpp.
References MI.
|
static |
Return true if the given load or store is a strided memory access.
Check all MachineMemOperands for a hint that the load/store is strided.
Definition at line 2272 of file AArch64InstrInfo.cpp.
References llvm::any_of(), and MI.
|
inlineoverride |
Definition at line 361 of file AArch64InstrInfo.h.
|
static |
Returns true if MI is one of the TCRETURN* instructions.
Definition at line 2519 of file AArch64InstrInfo.cpp.
Referenced by getArgumentStackToRestore().
Return true when a code sequence can improve throughput.
It should be called only for instructions in loops.
Pattern | - combiner pattern |
Definition at line 6667 of file AArch64InstrInfo.cpp.
References llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f16_OP1, llvm::FMLAv4f16_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i16_indexed_OP1, llvm::FMLAv4i16_indexed_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLAv8f16_OP1, llvm::FMLAv8f16_OP2, llvm::FMLAv8i16_indexed_OP1, llvm::FMLAv8i16_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f16_OP1, llvm::FMLSv4f16_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i16_indexed_OP1, llvm::FMLSv4i16_indexed_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMLSv8f16_OP1, llvm::FMLSv8f16_OP2, llvm::FMLSv8i16_indexed_OP1, llvm::FMLSv8i16_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDH_OP1, llvm::FMULADDH_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBH_OP1, llvm::FMULSUBH_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FMULv2i32_indexed_OP1, llvm::FMULv2i32_indexed_OP2, llvm::FMULv2i64_indexed_OP1, llvm::FMULv2i64_indexed_OP2, llvm::FMULv4i16_indexed_OP1, llvm::FMULv4i16_indexed_OP2, llvm::FMULv4i32_indexed_OP1, llvm::FMULv4i32_indexed_OP2, llvm::FMULv8i16_indexed_OP1, llvm::FMULv8i16_indexed_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBH_OP1, llvm::FNMULSUBS_OP1, llvm::MULADDv16i8_OP1, llvm::MULADDv16i8_OP2, llvm::MULADDv2i32_indexed_OP1, llvm::MULADDv2i32_indexed_OP2, llvm::MULADDv2i32_OP1, llvm::MULADDv2i32_OP2, llvm::MULADDv4i16_indexed_OP1, llvm::MULADDv4i16_indexed_OP2, llvm::MULADDv4i16_OP1, llvm::MULADDv4i16_OP2, llvm::MULADDv4i32_indexed_OP1, llvm::MULADDv4i32_indexed_OP2, llvm::MULADDv4i32_OP1, llvm::MULADDv4i32_OP2, llvm::MULADDv8i16_indexed_OP1, llvm::MULADDv8i16_indexed_OP2, llvm::MULADDv8i16_OP1, llvm::MULADDv8i16_OP2, llvm::MULADDv8i8_OP1, llvm::MULADDv8i8_OP2, llvm::MULSUBv16i8_OP1, llvm::MULSUBv16i8_OP2, llvm::MULSUBv2i32_indexed_OP1, llvm::MULSUBv2i32_indexed_OP2, llvm::MULSUBv2i32_OP1, llvm::MULSUBv2i32_OP2, llvm::MULSUBv4i16_indexed_OP1, llvm::MULSUBv4i16_indexed_OP2, llvm::MULSUBv4i16_OP1, llvm::MULSUBv4i16_OP2, llvm::MULSUBv4i32_indexed_OP1, llvm::MULSUBv4i32_indexed_OP2, llvm::MULSUBv4i32_OP1, llvm::MULSUBv4i32_OP2, llvm::MULSUBv8i16_indexed_OP1, llvm::MULSUBv8i16_indexed_OP2, llvm::MULSUBv8i16_OP1, llvm::MULSUBv8i16_OP2, llvm::MULSUBv8i8_OP1, and llvm::MULSUBv8i8_OP2.
Returns true if the opcode is for an SVE WHILE## instruction.
Definition at line 9718 of file AArch64InstrInfo.cpp.
References llvm::get(), and llvm::AArch64::InstrFlagIsWhile.
Referenced by analyzeLoopForPipelining().
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Definition at line 5214 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetStackID::Default, llvm::get(), llvm::getDefRegState(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm::Register::isValid(), llvm::Register::isVirtual(), loadRegPairFromStackSlot(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::MCRegister::NoRegister, llvm::Offset, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), and TRI.
Referenced by foldMemoryOperandImpl().
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Definition at line 8912 of file AArch64InstrInfo.cpp.
References F.
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optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.
Try to optimize a compare instruction.
A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.
The following steps are tried in order:
Definition at line 1535 of file AArch64InstrInfo.cpp.
References assert(), convertToNonFlagSettingOpc(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::get(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), MRI, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::succeeded(), and UpdateOperandRegClass().
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Replace csincr-branch sequence by simple conditional branch.
Examples:
Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.
Examples:
to
MI | Conditional Branch |
Definition at line 8177 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), CC, llvm::AArch64_AM::decodeLogicalImmediate(), DefMI, DL, llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::get(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::Register::isVirtual(), llvm_unreachable, llvm::Log2_64(), MBB, MI, MRI, llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setSubReg(), and TBB.
MachineBasicBlock::iterator AArch64InstrInfo::probedStackAlloc | ( | MachineBasicBlock::iterator | MBBI, |
Register | TargetReg, | ||
bool | FrameSetup | ||
) | const |
Definition at line 9759 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::RegState::Define, DL, llvm::emitFrameOffset(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineInstr::FrameSetup, llvm::fullyRecomputeLiveIns(), llvm::AArch64_AM::getArithExtendImm(), llvm::MachineBasicBlock::getBasicBlock(), llvm::StackOffset::getFixed(), llvm::MachineFunction::getInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::AArch64_AM::getShifterImm(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::AArch64CC::LE, llvm::AArch64_AM::LSL, MBB, MBBI, llvm::MachineInstr::NoFlags, llvm::MachineRegisterInfo::reservedRegsFrozen(), llvm::MachineInstrBuilder::setMIFlags(), llvm::MachineBasicBlock::splice(), TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::AArch64_AM::UXTX.
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Definition at line 540 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and MBB.
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Definition at line 499 of file AArch64InstrInfo.cpp.
References CC, Cond, llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.
Referenced by analyzeLoopForPipelining().
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override |
Detect opportunities for ldp/stp formation.
Only called for LdSt for which getMemOperandWithOffset returns true.
Definition at line 4525 of file AArch64InstrInfo.cpp.
References assert(), canPairLdStOpc(), llvm::ArrayRef< T >::front(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), hasUnscaledLdStOffset(), isCandidateToMergeOrPair(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isIdenticalTo(), isPairableLdStInst(), llvm::MachineOperand::isReg(), scaleOffset(), shouldClusterFI(), and llvm::ArrayRef< T >::size().
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Definition at line 9480 of file AArch64InstrInfo.cpp.
References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().
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Definition at line 5042 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetStackID::Default, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm::MCRegister::isValid(), llvm::Register::isVirtual(), MBB, MBBI, MI, llvm::MachineMemOperand::MOStore, llvm::MCRegister::NoRegister, llvm::Offset, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), storeRegPairToStackSlot(), and TRI.
Referenced by foldMemoryOperandImpl().
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Hint that pairing the given load or store is unprofitable.
Set a flag on the first MachineMemOperand to suppress pairing.
Definition at line 2265 of file AArch64InstrInfo.cpp.
References MI, and llvm::MOSuppressPair.
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AArch64 supports MachineCombiner.
Definition at line 6030 of file AArch64InstrInfo.cpp.