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AArch64ISelLowering.h
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1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AArch64 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16
17#include "AArch64.h"
23#include "llvm/IR/CallingConv.h"
24#include "llvm/IR/Instruction.h"
25
26namespace llvm {
27
28namespace AArch64ISD {
29
30// For predicated nodes where the result is a vector, the operation is
31// controlled by a governing predicate and the inactive lanes are explicitly
32// defined with a value, please stick the following naming convention:
33//
34// _MERGE_OP<n> The result value is a vector with inactive lanes equal
35// to source operand OP<n>.
36//
37// _MERGE_ZERO The result value is a vector with inactive lanes
38// actively zeroed.
39//
40// _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
41// to the last source operand which only purpose is being
42// a passthru value.
43//
44// For other cases where no explicit action is needed to set the inactive lanes,
45// or when the result is not a vector and it is needed or helpful to
46// distinguish a node from similar unpredicated nodes, use:
47//
48// _PRED
49//
50enum NodeType : unsigned {
52 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
53 CALL, // Function call.
54
55 // Pseudo for a OBJC call that gets emitted together with a special `mov
56 // x29, x29` marker instruction.
58
59 CALL_BTI, // Function call followed by a BTI instruction.
60
61 // Essentially like a normal COPY that works on GPRs, but cannot be
62 // rematerialised by passes like the simple register coalescer. It's
63 // required for SME when lowering calls because we cannot allow frame
64 // index calculations using addvl to slip in between the smstart/smstop
65 // and the bl instruction. The scalable vector length may change across
66 // the smstart/smstop boundary.
71
72 // Produces the full sequence of instructions for getting the thread pointer
73 // offset of a variable into X0, using the TLSDesc model.
75 ADRP, // Page address of a TargetGlobalAddress operand.
76 ADR, // ADR
77 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
78 LOADgot, // Load from automatically generated descriptor (e.g. Global
79 // Offset Table, TLS record).
80 RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand.
81 BRCOND, // Conditional branch instruction; "b.cond".
83 CSINV, // Conditional select invert.
84 CSNEG, // Conditional select negate.
85 CSINC, // Conditional select increment.
86
87 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
88 // ELF.
91 SBC, // adc, sbc instructions
92
93 // Predicated instructions where inactive lanes produce undefined results.
121
122 // Unpredicated vector instructions
124
126
127 // Predicated instructions with the result of inactive lanes provided by the
128 // last operand.
150
152
153 // Arithmetic instructions which write flags.
159
160 // Conditional compares. Operands: left,right,falsecc,cc,flags
164
165 // Floating point comparison
167
168 // Scalar extract
170
171 // Scalar-to-vector duplication
178
179 // Vector immedate moves
187
188 // Vector immediate ops
191
192 // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
193 // element must be identical.
195
196 // Vector shuffles
208
209 // Vector shift by scalar
213
214 // Vector shift by scalar (again)
220
221 // Vector shift by constant and insert
224
225 // Vector comparisons
234
235 // Vector zero comparisons
246
247 // Vector across-lanes addition
248 // Only the lower result lane is defined.
251
252 // Add Pairwise of two vectors
254 // Add Long Pairwise
257
258 // udot/sdot instructions
261
262 // Vector across-lanes min/max
263 // Only the lower result lane is defined.
268
278
279 // Vector bitwise insertion
281
282 // Compare-and-branch
287
288 // Tail calls
290
291 // Custom prefetch handling
293
294 // {s|u}int to FP within a FP register.
297
298 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
299 /// world w.r.t vectors; which causes additional REV instructions to be
300 /// generated to compensate for the byte-swapping. But sometimes we do
301 /// need to re-interpret the data in SIMD vector registers in big-endian
302 /// mode without emitting such REV instructions.
304
305 MRS, // MRS, also sets the flags via a glue.
306
309
311
312 // Reciprocal estimates and steps.
317
322
328
329 // Floating-point reductions.
336
341
350
351 // Cast between vectors of the same element type but differ in length.
353
354 // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
357
366
367 // Structured loads.
371
372 // Unsigned gather loads.
380
381 // Signed gather loads
389
390 // Unsigned gather loads.
398
399 // Signed gather loads.
407
408 // Non-temporal gather loads
412
413 // Contiguous masked store.
415
416 // Scatter store
424
425 // Non-temporal scatter store
428
429 // SME
432
433 // Asserts that a function argument (i32) is zero-extended to i8 by
434 // the caller
436
437 // 128-bit system register accesses
438 // lo64, hi64, chain = MRRS(chain, sysregname)
440 // chain = MSRR(chain, sysregname, lo64, hi64)
442
443 // Strict (exception-raising) floating point comparison
446
447 // NEON Load/Store with post-increment base updates
471
476
483
484 // Memory Operations
489};
490
491} // end namespace AArch64ISD
492
493namespace AArch64 {
494/// Possible values of current rounding mode, which is specified in bits
495/// 23:22 of FPCR.
497 RN = 0, // Round to Nearest
498 RP = 1, // Round towards Plus infinity
499 RM = 2, // Round towards Minus infinity
500 RZ = 3, // Round towards Zero
501 rmMask = 3 // Bit mask selecting rounding mode
503
504// Bit position of rounding mode bits in FPCR.
505const unsigned RoundingBitsPos = 22;
506
507// Registers used to pass function arguments.
510
511} // namespace AArch64
512
513class AArch64Subtarget;
514
516public:
517 explicit AArch64TargetLowering(const TargetMachine &TM,
518 const AArch64Subtarget &STI);
519
520 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
521 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
523 SDValue N1) const override;
524
525 /// Selects the correct CCAssignFn for a given CallingConvention value.
526 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
527
528 /// Selects the correct CCAssignFn for a given CallingConvention value.
530
531 /// Determine which of the bits specified in Mask are known to be either zero
532 /// or one and return them in the KnownZero/KnownOne bitsets.
533 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
534 const APInt &DemandedElts,
535 const SelectionDAG &DAG,
536 unsigned Depth = 0) const override;
537
539 const APInt &DemandedElts,
540 const SelectionDAG &DAG,
541 unsigned Depth) const override;
542
543 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
544 // Returning i64 unconditionally here (i.e. even for ILP32) means that the
545 // *DAG* representation of pointers will always be 64-bits. They will be
546 // truncated and extended when transferred to memory, but the 64-bit DAG
547 // allows us to use AArch64's addressing modes much more easily.
548 return MVT::getIntegerVT(64);
549 }
550
552 const APInt &DemandedElts,
553 TargetLoweringOpt &TLO) const override;
554
555 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
556
557 /// Returns true if the target allows unaligned memory accesses of the
558 /// specified type.
560 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
562 unsigned *Fast = nullptr) const override;
563 /// LLT variant.
564 bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
565 Align Alignment,
567 unsigned *Fast = nullptr) const override;
568
569 /// Provide custom lowering hooks for some operations.
570 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
571
572 const char *getTargetNodeName(unsigned Opcode) const override;
573
574 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
575
576 /// This method returns a target specific FastISel object, or null if the
577 /// target does not support "fast" ISel.
579 const TargetLibraryInfo *libInfo) const override;
580
581 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
582
583 bool isFPImmLegal(const APFloat &Imm, EVT VT,
584 bool ForCodeSize) const override;
585
586 /// Return true if the given shuffle mask can be codegen'd directly, or if it
587 /// should be stack expanded.
588 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
589
590 /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
591 /// shuffle mask can be codegen'd directly.
592 bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
593
594 /// Return the ISD::SETCC ValueType.
596 EVT VT) const override;
597
599
601 MachineBasicBlock *BB) const;
602
604 MachineBasicBlock *BB) const;
605
606 MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
608 MachineBasicBlock *BB) const;
610 MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
612 bool HasTile) const;
614
617 MachineBasicBlock *MBB) const override;
618
619 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
620 MachineFunction &MF,
621 unsigned Intrinsic) const override;
622
624 EVT NewVT) const override;
625
626 bool shouldRemoveRedundantExtend(SDValue Op) const override;
627
628 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
629 bool isTruncateFree(EVT VT1, EVT VT2) const override;
630
631 bool isProfitableToHoist(Instruction *I) const override;
632
633 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
634 bool isZExtFree(EVT VT1, EVT VT2) const override;
635 bool isZExtFree(SDValue Val, EVT VT2) const override;
636
638 SmallVectorImpl<Use *> &Ops) const override;
639
641 Loop *L) const override;
642
643 bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
644
645 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
646
649 ArrayRef<unsigned> Indices,
650 unsigned Factor) const override;
652 unsigned Factor) const override;
653
654 bool isLegalAddImmediate(int64_t) const override;
655 bool isLegalICmpImmediate(int64_t) const override;
656
658 SDValue ConstNode) const override;
659
660 bool shouldConsiderGEPOffsetSplit() const override;
661
662 EVT getOptimalMemOpType(const MemOp &Op,
663 const AttributeList &FuncAttributes) const override;
664
665 LLT getOptimalMemOpLLT(const MemOp &Op,
666 const AttributeList &FuncAttributes) const override;
667
668 /// Return true if the addressing mode represented by AM is legal for this
669 /// target, for a load/store of the specified type.
670 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
671 unsigned AS,
672 Instruction *I = nullptr) const override;
673
674 /// Return true if an FMA operation is faster than a pair of fmul and fadd
675 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
676 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
678 EVT VT) const override;
679 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
680
682 CodeGenOpt::Level OptLevel) const override;
683
684 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
686
687 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
689 CombineLevel Level) const override;
690
691 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
692 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
693
694 /// Return true if it is profitable to fold a pair of shifts into a mask.
696 CombineLevel Level) const override;
697
698 /// Returns true if it is beneficial to convert a load of a constant
699 /// to just the constant itself.
701 Type *Ty) const override;
702
703 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
704 /// with this index.
705 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
706 unsigned Index) const override;
707
708 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
709 bool MathUsed) const override {
710 // Using overflow ops for overflow checks only should beneficial on
711 // AArch64.
712 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
713 }
714
715 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
716 AtomicOrdering Ord) const override;
718 AtomicOrdering Ord) const override;
719
720 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
721
722 bool isOpSuitableForLDPSTP(const Instruction *I) const;
723 bool isOpSuitableForLSE128(const Instruction *I) const;
724 bool isOpSuitableForRCPC3(const Instruction *I) const;
725 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
726 bool
728
730 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
732 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
734 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
735
738
739 bool useLoadStackGuardNode() const override;
741 getPreferredVectorAction(MVT VT) const override;
742
743 /// If the target has a standard location for the stack protector cookie,
744 /// returns the address of that location. Otherwise, returns nullptr.
745 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
746
747 void insertSSPDeclarations(Module &M) const override;
748 Value *getSDagStackGuard(const Module &M) const override;
749 Function *getSSPStackGuardCheck(const Module &M) const override;
750
751 /// If the target has a standard location for the unsafe stack pointer,
752 /// returns the address of that location. Otherwise, returns nullptr.
753 Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
754
755 /// If a physical register, this returns the register that receives the
756 /// exception address on entry to an EH pad.
758 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
759 // FIXME: This is a guess. Has this been defined yet?
760 return AArch64::X0;
761 }
762
763 /// If a physical register, this returns the register that receives the
764 /// exception typeid on entry to a landing pad.
766 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
767 // FIXME: This is a guess. Has this been defined yet?
768 return AArch64::X1;
769 }
770
771 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
772
773 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
774 const MachineFunction &MF) const override {
775 // Do not merge to float value size (128 bytes) if no implicit
776 // float attribute is set.
777
778 bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
779
780 if (NoFloat)
781 return (MemVT.getSizeInBits() <= 64);
782 return true;
783 }
784
785 bool isCheapToSpeculateCttz(Type *) const override {
786 return true;
787 }
788
789 bool isCheapToSpeculateCtlz(Type *) const override {
790 return true;
791 }
792
793 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
794
795 bool hasAndNotCompare(SDValue V) const override {
796 // We can use bics for any scalar.
797 return V.getValueType().isScalarInteger();
798 }
799
800 bool hasAndNot(SDValue Y) const override {
801 EVT VT = Y.getValueType();
802
803 if (!VT.isVector())
804 return hasAndNotCompare(Y);
805
806 TypeSize TS = VT.getSizeInBits();
807 // TODO: We should be able to use bic/bif too for SVE.
808 return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
809 }
810
813 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
814 SelectionDAG &DAG) const override;
815
818 unsigned ExpansionFactor) const override;
819
821 unsigned KeptBits) const override {
822 // For vectors, we don't have a preference..
823 if (XVT.isVector())
824 return false;
825
826 auto VTIsOk = [](EVT VT) -> bool {
827 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
828 VT == MVT::i64;
829 };
830
831 // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
832 // XVT will be larger than KeptBitsVT.
833 MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
834 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
835 }
836
837 bool preferIncOfAddToSubOfNot(EVT VT) const override;
838
839 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
840
841 bool isComplexDeinterleavingSupported() const override;
843 ComplexDeinterleavingOperation Operation, Type *Ty) const override;
844
847 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
848 Value *Accumulator = nullptr) const override;
849
850 bool supportSplitCSR(MachineFunction *MF) const override {
852 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
853 }
854 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
856 MachineBasicBlock *Entry,
857 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
858
859 bool supportSwiftError() const override {
860 return true;
861 }
862
863 bool supportKCFIBundles() const override { return true; }
864
867 const TargetInstrInfo *TII) const override;
868
869 /// Enable aggressive FMA fusion on targets that want it.
870 bool enableAggressiveFMAFusion(EVT VT) const override;
871
872 /// Returns the size of the platform's va_list object.
873 unsigned getVaListSizeInBits(const DataLayout &DL) const override;
874
875 /// Returns true if \p VecTy is a legal interleaved access type. This
876 /// function checks the vector element type and the overall width of the
877 /// vector.
879 bool &UseScalable) const;
880
881 /// Returns the number of interleaved accesses that will be generated when
882 /// lowering accesses of the given type.
883 unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
884 bool UseScalable) const;
885
887 const Instruction &I) const override;
888
890 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
891 const DataLayout &DL) const override;
892
893 /// Used for exception handling on Win64.
894 bool needsFixedCatchObjects() const override;
895
896 bool fallBackToDAGISel(const Instruction &Inst) const override;
897
898 /// SVE code generation for fixed length vectors does not custom lower
899 /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
900 /// merge. However, merging them creates a BUILD_VECTOR that is just as
901 /// illegal as the original, thus leading to an infinite legalisation loop.
902 /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
903 /// vector types this override can be removed.
904 bool mergeStoresAfterLegalization(EVT VT) const override;
905
906 // If the platform/function should have a redzone, return the size in bytes.
907 unsigned getRedZoneSize(const Function &F) const {
908 if (F.hasFnAttribute(Attribute::NoRedZone))
909 return 0;
910 return 128;
911 }
912
913 bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
915
917 bool AllowUnknown = false) const override;
918
919 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
920
921 /// If a change in streaming mode is required on entry to/return from a
922 /// function call it emits and returns the corresponding SMSTART or SMSTOP node.
923 /// \p Entry tells whether this is before/after the Call, which is necessary
924 /// because PSTATE.SM is only queried once.
926 SDValue Chain, SDValue InGlue,
927 SDValue PStateSM, bool Entry) const;
928
929 bool isVScaleKnownToBeAPowerOfTwo() const override { return true; }
930
931 // Normally SVE is only used for byte size vectors that do not fit within a
932 // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
933 // used for 64bit and 128bit vectors as well.
934 bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
935
936private:
937 /// Keep a pointer to the AArch64Subtarget around so that we can
938 /// make the right decision when generating code for different targets.
939 const AArch64Subtarget *Subtarget;
940
941 bool isExtFreeImpl(const Instruction *Ext) const override;
942
943 void addTypeForNEON(MVT VT);
944 void addTypeForFixedLengthSVE(MVT VT, bool StreamingSVE);
945 void addDRTypeForNEON(MVT VT);
946 void addQRTypeForNEON(MVT VT);
947
948 unsigned allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL,
949 SelectionDAG &DAG) const;
950
951 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
952 bool isVarArg,
954 const SDLoc &DL, SelectionDAG &DAG,
955 SmallVectorImpl<SDValue> &InVals) const override;
956
957 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
958 SmallVectorImpl<SDValue> &InVals) const override;
959
960 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
961 CallingConv::ID CallConv, bool isVarArg,
962 const SmallVectorImpl<CCValAssign> &RVLocs,
963 const SDLoc &DL, SelectionDAG &DAG,
964 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
965 SDValue ThisVal) const;
966
967 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
968 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
969 SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
970 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
971
972 SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
973 SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
974
975 SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
976
977 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
978 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
979 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
980
981 bool
982 isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
983
984 /// Finds the incoming stack arguments which overlap the given fixed stack
985 /// object and incorporates their load into the current chain. This prevents
986 /// an upcoming store from clobbering the stack argument before it's used.
987 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
988 MachineFrameInfo &MFI, int ClobberedFI) const;
989
990 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
991
992 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
993 SDValue &Chain) const;
994
995 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
996 bool isVarArg,
998 LLVMContext &Context) const override;
999
1000 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1002 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
1003 SelectionDAG &DAG) const override;
1004
1005 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1006 unsigned Flag) const;
1007 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
1008 unsigned Flag) const;
1009 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
1010 unsigned Flag) const;
1011 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1012 unsigned Flag) const;
1013 template <class NodeTy>
1014 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1015 template <class NodeTy>
1016 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1017 template <class NodeTy>
1018 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1019 template <class NodeTy>
1020 SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1021 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1023 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1024 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1026 SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
1027 const SDLoc &DL, SelectionDAG &DAG) const;
1028 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
1029 SelectionDAG &DAG) const;
1030 SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1031 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1032 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1033 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
1034 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1035 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1036 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
1037 SDValue TVal, SDValue FVal, const SDLoc &dl,
1038 SelectionDAG &DAG) const;
1039 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1040 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
1041 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1042 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1043 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
1044 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
1045 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
1046 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1047 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1048 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1049 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1050 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
1051 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1052 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1053 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1054 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1055 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1056 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1057 SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
1058 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1059 SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1060 SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
1061 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
1062 unsigned NewOp) const;
1063 SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
1064 SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
1065 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1066 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1067 SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1068 SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1069 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1070 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1071 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
1072 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
1073 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
1074 SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const;
1075 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
1076 SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
1077 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
1078 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
1079 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1080 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1081 SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1082 SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1083 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1084 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1085 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1086 SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1087 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
1088 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1089 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
1090 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
1091 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1092 SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
1093 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1094 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
1095 SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
1096 SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
1097 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1098 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
1099 SDValue &Size,
1100 SelectionDAG &DAG) const;
1101 SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const;
1102
1103 SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
1104 SelectionDAG &DAG) const;
1105 SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
1106 SelectionDAG &DAG) const;
1107 SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1108 SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1109 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1110 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1111 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
1112 SelectionDAG &DAG) const;
1113 SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
1114 SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
1115 SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
1116 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1117 SelectionDAG &DAG) const;
1118 SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
1119 SelectionDAG &DAG) const;
1120 SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
1121 SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
1122 SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
1123 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
1124 SelectionDAG &DAG) const;
1125 SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
1126 SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
1127 SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
1128 SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
1129 SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
1130 SelectionDAG &DAG) const;
1131
1132 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1133 SmallVectorImpl<SDNode *> &Created) const override;
1134 SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1135 SmallVectorImpl<SDNode *> &Created) const override;
1136 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1137 int &ExtraSteps, bool &UseOneConst,
1138 bool Reciprocal) const override;
1139 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1140 int &ExtraSteps) const override;
1141 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1142 const DenormalMode &Mode) const override;
1143 SDValue getSqrtResultForDenormInput(SDValue Operand,
1144 SelectionDAG &DAG) const override;
1145 unsigned combineRepeatedFPDivisors() const override;
1146
1147 ConstraintType getConstraintType(StringRef Constraint) const override;
1148 Register getRegisterByName(const char* RegName, LLT VT,
1149 const MachineFunction &MF) const override;
1150
1151 /// Examine constraint string and operand type and determine a weight value.
1152 /// The operand object must already have been set up with the operand type.
1154 getSingleConstraintMatchWeight(AsmOperandInfo &info,
1155 const char *constraint) const override;
1156
1157 std::pair<unsigned, const TargetRegisterClass *>
1158 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1159 StringRef Constraint, MVT VT) const override;
1160
1161 const char *LowerXConstraint(EVT ConstraintVT) const override;
1162
1163 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1164 std::vector<SDValue> &Ops,
1165 SelectionDAG &DAG) const override;
1166
1167 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1168 if (ConstraintCode == "Q")
1170 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1171 // followed by llvm_unreachable so we'll leave them unimplemented in
1172 // the backend for now.
1173 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1174 }
1175
1176 /// Handle Lowering flag assembly outputs.
1177 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
1178 const SDLoc &DL,
1179 const AsmOperandInfo &Constraint,
1180 SelectionDAG &DAG) const override;
1181
1182 bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1183 bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
1184 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1185 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1186 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1187 bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1188 SDValue &Offset, SelectionDAG &DAG) const;
1189 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1191 SelectionDAG &DAG) const override;
1192 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1193 SDValue &Offset, ISD::MemIndexedMode &AM,
1194 SelectionDAG &DAG) const override;
1195
1196 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1197 SelectionDAG &DAG) const override;
1198 void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1199 SelectionDAG &DAG) const;
1200 void ReplaceExtractSubVectorResults(SDNode *N,
1201 SmallVectorImpl<SDValue> &Results,
1202 SelectionDAG &DAG) const;
1203
1204 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1205
1206 void finalizeLowering(MachineFunction &MF) const override;
1207
1208 bool shouldLocalize(const MachineInstr &MI,
1209 const TargetTransformInfo *TTI) const override;
1210
1211 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
1212 const APInt &OriginalDemandedBits,
1213 const APInt &OriginalDemandedElts,
1214 KnownBits &Known,
1215 TargetLoweringOpt &TLO,
1216 unsigned Depth) const override;
1217
1218 bool isTargetCanonicalConstantNode(SDValue Op) const override;
1219
1220 // With the exception of data-predicate transitions, no instructions are
1221 // required to cast between legal scalable vector types. However:
1222 // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1223 // is not universally useable.
1224 // 2. Most unpacked integer types are not legal and thus integer extends
1225 // cannot be used to convert between unpacked and packed types.
1226 // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1227 // to transition between unpacked and packed types of the same element type,
1228 // with BITCAST used otherwise.
1229 // This function does not handle predicate bitcasts.
1230 SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1231
1232 // Returns the runtime value for PSTATE.SM. When the function is streaming-
1233 // compatible, this generates a call to __arm_sme_state.
1234 SDValue getPStateSM(SelectionDAG &DAG, SDValue Chain, SMEAttrs Attrs,
1235 SDLoc DL, EVT VT) const;
1236
1237 bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
1238 LLT Ty2) const override;
1239
1240 bool preferScalarizeSplat(SDNode *N) const override;
1241};
1242
1243namespace AArch64 {
1244FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1245 const TargetLibraryInfo *libInfo);
1246} // end namespace AArch64
1247
1248} // end namespace llvm
1249
1250#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const char LLVMTargetMachineRef TM
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
@ Flags
Definition: TextStubV5.cpp:93
Value * RHS
Value * LHS
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, SDValue PStateSM, bool Entry) const
If a change in streaming mode is required on entry to/return from a function call it emits and return...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L) const override
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOpt::Level OptLevel) const override
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveRedundantExtend(SDValue Op) const override
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
MachineBasicBlock * EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB, bool HasTile) const
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
bool isOpSuitableForLSE128(const Instruction *I) const
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
bool fallBackToDAGISel(const Instruction &Inst) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
bool isOpSuitableForRCPC3(const Instruction *I) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
unsigned getRedZoneSize(const Function &F) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isOpSuitableForLDPSTP(const Instruction *I) const
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool shouldConsiderGEPOffsetSplit() const override
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override
Similar to isShuffleMaskLegal.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
ArrayRef< MCPhysReg > getRoundingControlRegisters() const override
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:237
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:644
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:47
Machine Value Type.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:400
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:182
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:166
@ NVCAST
Natural vector cast.
const ArrayRef< MCPhysReg > getFPRArgRegs()
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
const ArrayRef< MCPhysReg > getGPRArgRegs()
const unsigned RoundingBitsPos
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1324
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1336
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1396
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1330
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1447
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1427
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
AddressSpace
Definition: NVPTXBaseInfo.h:21
AtomicOrdering
Atomic ordering for LLVM's memory model.
TargetTransformInfo TTI
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
@ Enable
Enable colors.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Represent subnormal handling kind for floating point instruction inputs and outputs.
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160