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AArch64ISelLowering.h
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1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AArch64 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16
17#include "AArch64.h"
23#include "llvm/IR/CallingConv.h"
24#include "llvm/IR/Instruction.h"
25
26namespace llvm {
27
28namespace AArch64ISD {
29
30// For predicated nodes where the result is a vector, the operation is
31// controlled by a governing predicate and the inactive lanes are explicitly
32// defined with a value, please stick the following naming convention:
33//
34// _MERGE_OP<n> The result value is a vector with inactive lanes equal
35// to source operand OP<n>.
36//
37// _MERGE_ZERO The result value is a vector with inactive lanes
38// actively zeroed.
39//
40// _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
41// to the last source operand which only purpose is being
42// a passthru value.
43//
44// For other cases where no explicit action is needed to set the inactive lanes,
45// or when the result is not a vector and it is needed or helpful to
46// distinguish a node from similar unpredicated nodes, use:
47//
48// _PRED
49//
50enum NodeType : unsigned {
52 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
53 CALL, // Function call.
54
55 // Pseudo for a OBJC call that gets emitted together with a special `mov
56 // x29, x29` marker instruction.
58
59 CALL_BTI, // Function call followed by a BTI instruction.
60
61 // Function call, authenticating the callee value first:
62 // AUTH_CALL chain, callee, auth key #, int disc, addr disc, operands.
64 // AUTH_TC_RETURN chain, callee, fpdiff, auth key #, int disc, addr disc,
65 // operands.
67
68 // Authenticated variant of CALL_RVMARKER.
70
72
75
81
82 // A call with the callee in x16, i.e. "blr x16".
84
85 // Produces the full sequence of instructions for getting the thread pointer
86 // offset of a variable into X0, using the TLSDesc model.
88 ADRP, // Page address of a TargetGlobalAddress operand.
89 ADR, // ADR
90 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
91 LOADgot, // Load from automatically generated descriptor (e.g. Global
92 // Offset Table, TLS record).
93 RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand.
94 BRCOND, // Conditional branch instruction; "b.cond".
96 CSINV, // Conditional select invert.
97 CSNEG, // Conditional select negate.
98 CSINC, // Conditional select increment.
99
100 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
101 // ELF.
104 SBC, // adc, sbc instructions
105
106 // To avoid stack clash, allocation is performed by block and each block is
107 // probed.
109
110 // Predicated instructions where inactive lanes produce undefined results.
138
139 // Unpredicated vector instructions
141
143
144 // Predicated instructions with the result of inactive lanes provided by the
145 // last operand.
167
169
170 // Arithmetic instructions which write flags.
176
177 // Conditional compares. Operands: left,right,falsecc,cc,flags
181
182 // Floating point comparison
184
185 // Scalar-to-vector duplication
192
193 // Vector immedate moves
201
202 // Vector immediate ops
205
206 // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
207 // element must be identical.
209
210 // Vector shuffles
222
223 // Vector shift by scalar
227
228 // Vector shift by scalar (again)
235
236 // Vector narrowing shift by immediate (bottom)
238
239 // Vector shift by constant and insert
242
243 // Vector comparisons
252
253 // Vector zero comparisons
264
265 // Round wide FP to narrow FP with inexact results to odd.
267
268 // Vector across-lanes addition
269 // Only the lower result lane is defined.
272
273 // Unsigned sum Long across Vector
276
277 // Add Pairwise of two vectors
279 // Add Long Pairwise
282
283 // udot/sdot instructions
286
287 // Vector across-lanes min/max
288 // Only the lower result lane is defined.
293
303
304 // Compare-and-branch
309
310 // Tail calls
312
313 // Custom prefetch handling
315
316 // {s|u}int to FP within a FP register.
319
320 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
321 /// world w.r.t vectors; which causes additional REV instructions to be
322 /// generated to compensate for the byte-swapping. But sometimes we do
323 /// need to re-interpret the data in SIMD vector registers in big-endian
324 /// mode without emitting such REV instructions.
326
327 MRS, // MRS, also sets the flags via a glue.
328
331
333
334 // Reciprocal estimates and steps.
339
344
350
351 // Floating-point reductions.
358
363
365
374
375 // Cast between vectors of the same element type but differ in length.
377
378 // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
381
390
391 // Structured loads.
395
396 // Unsigned gather loads.
406
407 // Signed gather loads
415
416 // Unsigned gather loads.
424
425 // Signed gather loads.
433
434 // Non-temporal gather loads
438
439 // Contiguous masked store.
441
442 // Scatter store
452
453 // Non-temporal scatter store
456
457 // SME
462
463 // Asserts that a function argument (i32) is zero-extended to i8 by
464 // the caller
466
467 // 128-bit system register accesses
468 // lo64, hi64, chain = MRRS(chain, sysregname)
470 // chain = MSRR(chain, sysregname, lo64, hi64)
472
473 // Strict (exception-raising) floating point comparison
476
477 // SME ZA loads and stores
480
481 // NEON Load/Store with post-increment base updates
505
510
517
518 // Memory Operations
523};
524
525} // end namespace AArch64ISD
526
527namespace AArch64 {
528/// Possible values of current rounding mode, which is specified in bits
529/// 23:22 of FPCR.
531 RN = 0, // Round to Nearest
532 RP = 1, // Round towards Plus infinity
533 RM = 2, // Round towards Minus infinity
534 RZ = 3, // Round towards Zero
535 rmMask = 3 // Bit mask selecting rounding mode
537
538// Bit position of rounding mode bits in FPCR.
539const unsigned RoundingBitsPos = 22;
540
541// Reserved bits should be preserved when modifying FPCR.
542const uint64_t ReservedFPControlBits = 0xfffffffff80040f8;
543
544// Registers used to pass function arguments.
547
548/// Maximum allowed number of unprobed bytes above SP at an ABI
549/// boundary.
550const unsigned StackProbeMaxUnprobedStack = 1024;
551
552/// Maximum number of iterations to unroll for a constant size probing loop.
553const unsigned StackProbeMaxLoopUnroll = 4;
554
555} // namespace AArch64
556
557class AArch64Subtarget;
558
560public:
561 explicit AArch64TargetLowering(const TargetMachine &TM,
562 const AArch64Subtarget &STI);
563
564 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
565 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
567 SDValue N1) const override;
568
569 /// Selects the correct CCAssignFn for a given CallingConvention value.
570 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
571
572 /// Selects the correct CCAssignFn for a given CallingConvention value.
574
575 /// Determine which of the bits specified in Mask are known to be either zero
576 /// or one and return them in the KnownZero/KnownOne bitsets.
578 const APInt &DemandedElts,
579 const SelectionDAG &DAG,
580 unsigned Depth = 0) const override;
581
583 const APInt &DemandedElts,
584 const SelectionDAG &DAG,
585 unsigned Depth) const override;
586
587 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
588 // Returning i64 unconditionally here (i.e. even for ILP32) means that the
589 // *DAG* representation of pointers will always be 64-bits. They will be
590 // truncated and extended when transferred to memory, but the 64-bit DAG
591 // allows us to use AArch64's addressing modes much more easily.
592 return MVT::getIntegerVT(64);
593 }
594
596 const APInt &DemandedElts,
597 TargetLoweringOpt &TLO) const override;
598
599 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
600
601 /// Returns true if the target allows unaligned memory accesses of the
602 /// specified type.
604 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
606 unsigned *Fast = nullptr) const override;
607 /// LLT variant.
608 bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
609 Align Alignment,
611 unsigned *Fast = nullptr) const override;
612
613 /// Provide custom lowering hooks for some operations.
614 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
615
616 const char *getTargetNodeName(unsigned Opcode) const override;
617
618 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
619
620 /// This method returns a target specific FastISel object, or null if the
621 /// target does not support "fast" ISel.
623 const TargetLibraryInfo *libInfo) const override;
624
625 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
626
627 bool isFPImmLegal(const APFloat &Imm, EVT VT,
628 bool ForCodeSize) const override;
629
630 /// Return true if the given shuffle mask can be codegen'd directly, or if it
631 /// should be stack expanded.
632 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
633
634 /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
635 /// shuffle mask can be codegen'd directly.
636 bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
637
638 /// Return the ISD::SETCC ValueType.
640 EVT VT) const override;
641
643
645 MachineBasicBlock *BB) const;
646
648 MachineBasicBlock *BB) const;
649
651 MachineBasicBlock *MBB) const;
652
653 MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
655 MachineBasicBlock *BB) const;
657 MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
658 MachineInstr &MI, MachineBasicBlock *BB) const;
660 unsigned Opcode, bool Op0IsDef) const;
663 MachineBasicBlock *BB) const;
665 MachineBasicBlock *BB) const;
666
669 MachineBasicBlock *MBB) const override;
670
671 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
672 MachineFunction &MF,
673 unsigned Intrinsic) const override;
674
676 EVT NewVT) const override;
677
678 bool shouldRemoveRedundantExtend(SDValue Op) const override;
679
680 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
681 bool isTruncateFree(EVT VT1, EVT VT2) const override;
682
683 bool isProfitableToHoist(Instruction *I) const override;
684
685 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
686 bool isZExtFree(EVT VT1, EVT VT2) const override;
687 bool isZExtFree(SDValue Val, EVT VT2) const override;
688
690 SmallVectorImpl<Use *> &Ops) const override;
691
693 Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override;
694
695 bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
696
697 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
698
701 ArrayRef<unsigned> Indices,
702 unsigned Factor) const override;
704 unsigned Factor) const override;
705
707 IntrinsicInst *DI, LoadInst *LI,
708 SmallVectorImpl<Instruction *> &DeadInsts) const override;
709
712 SmallVectorImpl<Instruction *> &DeadInsts) const override;
713
714 bool isLegalAddImmediate(int64_t) const override;
715 bool isLegalAddScalableImmediate(int64_t) const override;
716 bool isLegalICmpImmediate(int64_t) const override;
717
719 SDValue ConstNode) const override;
720
721 bool shouldConsiderGEPOffsetSplit() const override;
722
724 const AttributeList &FuncAttributes) const override;
725
727 const AttributeList &FuncAttributes) const override;
728
729 /// Return true if the addressing mode represented by AM is legal for this
730 /// target, for a load/store of the specified type.
731 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
732 unsigned AS,
733 Instruction *I = nullptr) const override;
734
735 int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset,
736 int64_t MaxOffset) const override;
737
738 /// Return true if an FMA operation is faster than a pair of fmul and fadd
739 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
740 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
742 EVT VT) const override;
743 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
744
746 CodeGenOptLevel OptLevel) const override;
747
748 /// Return true if the target has native support for
749 /// the specified value type and it is 'desirable' to use the type for the
750 /// given node type.
751 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
752
753 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
755
756 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
758 CombineLevel Level) const override;
759
760 bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override {
761 return false;
762 }
763
764 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
765 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
766
767 /// Return true if it is profitable to fold a pair of shifts into a mask.
769 CombineLevel Level) const override;
770
771 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
772 EVT VT) const override;
773
774 /// Returns true if it is beneficial to convert a load of a constant
775 /// to just the constant itself.
777 Type *Ty) const override;
778
779 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
780 /// with this index.
781 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
782 unsigned Index) const override;
783
784 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
785 bool MathUsed) const override {
786 // Using overflow ops for overflow checks only should beneficial on
787 // AArch64.
788 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
789 }
790
791 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
792 AtomicOrdering Ord) const override;
794 AtomicOrdering Ord) const override;
795
796 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
797
798 bool isOpSuitableForLDPSTP(const Instruction *I) const;
799 bool isOpSuitableForLSE128(const Instruction *I) const;
800 bool isOpSuitableForRCPC3(const Instruction *I) const;
801 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
802 bool
804
806 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
808 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
810 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
811
814
815 bool useLoadStackGuardNode() const override;
817 getPreferredVectorAction(MVT VT) const override;
818
819 /// If the target has a standard location for the stack protector cookie,
820 /// returns the address of that location. Otherwise, returns nullptr.
821 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
822
823 void insertSSPDeclarations(Module &M) const override;
824 Value *getSDagStackGuard(const Module &M) const override;
825 Function *getSSPStackGuardCheck(const Module &M) const override;
826
827 /// If the target has a standard location for the unsafe stack pointer,
828 /// returns the address of that location. Otherwise, returns nullptr.
829 Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
830
831 /// If a physical register, this returns the register that receives the
832 /// exception address on entry to an EH pad.
834 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
835 // FIXME: This is a guess. Has this been defined yet?
836 return AArch64::X0;
837 }
838
839 /// If a physical register, this returns the register that receives the
840 /// exception typeid on entry to a landing pad.
842 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
843 // FIXME: This is a guess. Has this been defined yet?
844 return AArch64::X1;
845 }
846
847 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
848
849 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
850 const MachineFunction &MF) const override {
851 // Do not merge to float value size (128 bytes) if no implicit
852 // float attribute is set.
853
854 bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
855
856 if (NoFloat)
857 return (MemVT.getSizeInBits() <= 64);
858 return true;
859 }
860
861 bool isCheapToSpeculateCttz(Type *) const override {
862 return true;
863 }
864
865 bool isCheapToSpeculateCtlz(Type *) const override {
866 return true;
867 }
868
869 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
870
871 bool hasAndNotCompare(SDValue V) const override {
872 // We can use bics for any scalar.
873 return V.getValueType().isScalarInteger();
874 }
875
876 bool hasAndNot(SDValue Y) const override {
877 EVT VT = Y.getValueType();
878
879 if (!VT.isVector())
880 return hasAndNotCompare(Y);
881
882 TypeSize TS = VT.getSizeInBits();
883 // TODO: We should be able to use bic/bif too for SVE.
884 return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
885 }
886
889 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
890 SelectionDAG &DAG) const override;
891
894 unsigned ExpansionFactor) const override;
895
897 unsigned KeptBits) const override {
898 // For vectors, we don't have a preference..
899 if (XVT.isVector())
900 return false;
901
902 auto VTIsOk = [](EVT VT) -> bool {
903 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
904 VT == MVT::i64;
905 };
906
907 // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
908 // XVT will be larger than KeptBitsVT.
909 MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
910 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
911 }
912
913 bool preferIncOfAddToSubOfNot(EVT VT) const override;
914
915 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
916
917 bool shouldExpandCmpUsingSelects() const override { return true; }
918
919 bool isComplexDeinterleavingSupported() const override;
921 ComplexDeinterleavingOperation Operation, Type *Ty) const override;
922
925 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
926 Value *Accumulator = nullptr) const override;
927
928 bool supportSplitCSR(MachineFunction *MF) const override {
930 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
931 }
932 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
934 MachineBasicBlock *Entry,
935 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
936
937 bool supportSwiftError() const override {
938 return true;
939 }
940
941 bool supportPtrAuthBundles() const override { return true; }
942
943 bool supportKCFIBundles() const override { return true; }
944
947 const TargetInstrInfo *TII) const override;
948
949 /// Enable aggressive FMA fusion on targets that want it.
950 bool enableAggressiveFMAFusion(EVT VT) const override;
951
952 /// Returns the size of the platform's va_list object.
953 unsigned getVaListSizeInBits(const DataLayout &DL) const override;
954
955 /// Returns true if \p VecTy is a legal interleaved access type. This
956 /// function checks the vector element type and the overall width of the
957 /// vector.
959 bool &UseScalable) const;
960
961 /// Returns the number of interleaved accesses that will be generated when
962 /// lowering accesses of the given type.
963 unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
964 bool UseScalable) const;
965
967 const Instruction &I) const override;
968
970 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
971 const DataLayout &DL) const override;
972
973 /// Used for exception handling on Win64.
974 bool needsFixedCatchObjects() const override;
975
976 bool fallBackToDAGISel(const Instruction &Inst) const override;
977
978 /// SVE code generation for fixed length vectors does not custom lower
979 /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
980 /// merge. However, merging them creates a BUILD_VECTOR that is just as
981 /// illegal as the original, thus leading to an infinite legalisation loop.
982 /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
983 /// vector types this override can be removed.
984 bool mergeStoresAfterLegalization(EVT VT) const override;
985
986 // If the platform/function should have a redzone, return the size in bytes.
987 unsigned getRedZoneSize(const Function &F) const {
988 if (F.hasFnAttribute(Attribute::NoRedZone))
989 return 0;
990 return 128;
991 }
992
993 bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
995
997 bool AllowUnknown = false) const override;
998
999 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
1000
1001 bool shouldExpandCttzElements(EVT VT) const override;
1002
1003 /// If a change in streaming mode is required on entry to/return from a
1004 /// function call it emits and returns the corresponding SMSTART or SMSTOP
1005 /// node. \p Condition should be one of the enum values from
1006 /// AArch64SME::ToggleCondition.
1008 SDValue Chain, SDValue InGlue, unsigned Condition,
1009 SDValue PStateSM = SDValue()) const;
1010
1011 bool isVScaleKnownToBeAPowerOfTwo() const override { return true; }
1012
1013 // Normally SVE is only used for byte size vectors that do not fit within a
1014 // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
1015 // used for 64bit and 128bit vectors as well.
1016 bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
1017
1018 // Follow NEON ABI rules even when using SVE for fixed length vectors.
1020 EVT VT) const override;
1023 EVT VT) const override;
1026 EVT &IntermediateVT,
1027 unsigned &NumIntermediates,
1028 MVT &RegisterVT) const override;
1029
1030 /// True if stack clash protection is enabled for this functions.
1031 bool hasInlineStackProbe(const MachineFunction &MF) const override;
1032
1033#ifndef NDEBUG
1034 void verifyTargetSDNode(const SDNode *N) const override;
1035#endif
1036
1037private:
1038 /// Keep a pointer to the AArch64Subtarget around so that we can
1039 /// make the right decision when generating code for different targets.
1040 const AArch64Subtarget *Subtarget;
1041
1042 llvm::BumpPtrAllocator BumpAlloc;
1043 llvm::StringSaver Saver{BumpAlloc};
1044
1045 bool isExtFreeImpl(const Instruction *Ext) const override;
1046
1047 void addTypeForNEON(MVT VT);
1048 void addTypeForFixedLengthSVE(MVT VT);
1049 void addDRType(MVT VT);
1050 void addQRType(MVT VT);
1051
1052 bool shouldExpandBuildVectorWithShuffles(EVT, unsigned) const override;
1053
1054 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
1055 bool isVarArg,
1056 const SmallVectorImpl<ISD::InputArg> &Ins,
1057 const SDLoc &DL, SelectionDAG &DAG,
1058 SmallVectorImpl<SDValue> &InVals) const override;
1059
1060 void AdjustInstrPostInstrSelection(MachineInstr &MI,
1061 SDNode *Node) const override;
1062
1063 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
1064 SmallVectorImpl<SDValue> &InVals) const override;
1065
1066 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
1067 CallingConv::ID CallConv, bool isVarArg,
1068 const SmallVectorImpl<CCValAssign> &RVLocs,
1069 const SDLoc &DL, SelectionDAG &DAG,
1070 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1071 SDValue ThisVal, bool RequiresSMChange) const;
1072
1073 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1074 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1075 SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
1076 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1077
1078 SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
1079 SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
1080
1081 SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
1082
1083 SDValue LowerVECTOR_COMPRESS(SDValue Op, SelectionDAG &DAG) const;
1084
1085 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1086 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1087 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1088
1089 bool
1090 isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
1091
1092 /// Finds the incoming stack arguments which overlap the given fixed stack
1093 /// object and incorporates their load into the current chain. This prevents
1094 /// an upcoming store from clobbering the stack argument before it's used.
1095 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
1096 MachineFrameInfo &MFI, int ClobberedFI) const;
1097
1098 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
1099
1100 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
1101 SDValue &Chain) const;
1102
1103 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1104 bool isVarArg,
1105 const SmallVectorImpl<ISD::OutputArg> &Outs,
1106 LLVMContext &Context) const override;
1107
1108 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1109 const SmallVectorImpl<ISD::OutputArg> &Outs,
1110 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
1111 SelectionDAG &DAG) const override;
1112
1113 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1114 unsigned Flag) const;
1115 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
1116 unsigned Flag) const;
1117 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
1118 unsigned Flag) const;
1119 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1120 unsigned Flag) const;
1121 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
1122 unsigned Flag) const;
1123 template <class NodeTy>
1124 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1125 template <class NodeTy>
1126 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1127 template <class NodeTy>
1128 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1129 template <class NodeTy>
1130 SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1131 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1132 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1133 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1134 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1135 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1136 SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
1137 const SDLoc &DL, SelectionDAG &DAG) const;
1138 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
1139 SelectionDAG &DAG) const;
1140 SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1141 SDValue LowerPtrAuthGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1142 SDValue LowerPtrAuthGlobalAddressStatically(SDValue TGA, SDLoc DL, EVT VT,
1144 SDValue Discriminator,
1145 SDValue AddrDiscriminator,
1146 SelectionDAG &DAG) const;
1147 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1148 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1149 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
1150 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1151 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1152 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
1153 SDValue TVal, SDValue FVal, const SDLoc &dl,
1154 SelectionDAG &DAG) const;
1155 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1156 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1157 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1158 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
1159 SDValue LowerBRIND(SDValue Op, SelectionDAG &DAG) const;
1160 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1161 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1162 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
1163 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
1164 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
1165 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1166 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1167 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1168 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1169 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
1170 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1171 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1172 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1173 SDValue LowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
1174 SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
1175 SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
1176 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1177 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1178 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1179 SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
1180 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1181 SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1182 SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
1183 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
1184 unsigned NewOp) const;
1185 SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
1186 SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
1187 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1188 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1189 SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1190 SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1191 SDValue LowerVECTOR_HISTOGRAM(SDValue Op, SelectionDAG &DAG) const;
1192 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1193 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1194 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
1195 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
1196 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
1197 SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const;
1198 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
1199 SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
1200 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
1201 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
1202 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1203 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1204 SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1205 SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1206 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1207 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1208 SDValue LowerVectorXRINT(SDValue Op, SelectionDAG &DAG) const;
1209 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1210 SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1211 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
1212 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1213 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
1214 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
1215 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1216 SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
1217 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1218 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
1219 SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
1220 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1221 SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1222 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1223
1224 SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const;
1225
1226 SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
1227 SelectionDAG &DAG) const;
1228 SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
1229 SelectionDAG &DAG) const;
1230 SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1231 SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1232 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1233 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1234 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
1235 SelectionDAG &DAG) const;
1236 SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
1237 SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
1238 SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
1239 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1240 SelectionDAG &DAG) const;
1241 SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
1242 SelectionDAG &DAG) const;
1243 SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
1244 SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
1245 SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
1246 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
1247 SelectionDAG &DAG) const;
1248 SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
1249 SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
1250 SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
1251 SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
1252 SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
1253 SelectionDAG &DAG) const;
1254
1255 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1256 SmallVectorImpl<SDNode *> &Created) const override;
1257 SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1258 SmallVectorImpl<SDNode *> &Created) const override;
1259 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1260 int &ExtraSteps, bool &UseOneConst,
1261 bool Reciprocal) const override;
1262 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1263 int &ExtraSteps) const override;
1264 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1265 const DenormalMode &Mode) const override;
1266 SDValue getSqrtResultForDenormInput(SDValue Operand,
1267 SelectionDAG &DAG) const override;
1268 unsigned combineRepeatedFPDivisors() const override;
1269
1270 ConstraintType getConstraintType(StringRef Constraint) const override;
1271 Register getRegisterByName(const char* RegName, LLT VT,
1272 const MachineFunction &MF) const override;
1273
1274 /// Examine constraint string and operand type and determine a weight value.
1275 /// The operand object must already have been set up with the operand type.
1277 getSingleConstraintMatchWeight(AsmOperandInfo &info,
1278 const char *constraint) const override;
1279
1280 std::pair<unsigned, const TargetRegisterClass *>
1281 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1282 StringRef Constraint, MVT VT) const override;
1283
1284 const char *LowerXConstraint(EVT ConstraintVT) const override;
1285
1286 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
1287 std::vector<SDValue> &Ops,
1288 SelectionDAG &DAG) const override;
1289
1291 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1292 if (ConstraintCode == "Q")
1294 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1295 // followed by llvm_unreachable so we'll leave them unimplemented in
1296 // the backend for now.
1297 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1298 }
1299
1300 /// Handle Lowering flag assembly outputs.
1301 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
1302 const SDLoc &DL,
1303 const AsmOperandInfo &Constraint,
1304 SelectionDAG &DAG) const override;
1305
1306 bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1307 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
1308 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1309 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1310 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1311 bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1312 SDValue &Offset, SelectionDAG &DAG) const;
1313 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1315 SelectionDAG &DAG) const override;
1316 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1317 SDValue &Offset, ISD::MemIndexedMode &AM,
1318 SelectionDAG &DAG) const override;
1319 bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
1320 bool IsPre, MachineRegisterInfo &MRI) const override;
1321
1322 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1323 SelectionDAG &DAG) const override;
1324 void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1325 SelectionDAG &DAG) const;
1326 void ReplaceExtractSubVectorResults(SDNode *N,
1327 SmallVectorImpl<SDValue> &Results,
1328 SelectionDAG &DAG) const;
1329
1330 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1331
1332 void finalizeLowering(MachineFunction &MF) const override;
1333
1334 bool shouldLocalize(const MachineInstr &MI,
1335 const TargetTransformInfo *TTI) const override;
1336
1337 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
1338 const APInt &OriginalDemandedBits,
1339 const APInt &OriginalDemandedElts,
1340 KnownBits &Known,
1341 TargetLoweringOpt &TLO,
1342 unsigned Depth) const override;
1343
1344 bool isTargetCanonicalConstantNode(SDValue Op) const override;
1345
1346 // With the exception of data-predicate transitions, no instructions are
1347 // required to cast between legal scalable vector types. However:
1348 // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1349 // is not universally useable.
1350 // 2. Most unpacked integer types are not legal and thus integer extends
1351 // cannot be used to convert between unpacked and packed types.
1352 // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1353 // to transition between unpacked and packed types of the same element type,
1354 // with BITCAST used otherwise.
1355 // This function does not handle predicate bitcasts.
1356 SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1357
1358 // Returns the runtime value for PSTATE.SM by generating a call to
1359 // __arm_sme_state.
1360 SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1361 EVT VT) const;
1362
1363 bool preferScalarizeSplat(SDNode *N) const override;
1364
1365 unsigned getMinimumJumpTableEntries() const override;
1366
1367 bool softPromoteHalfType() const override { return true; }
1368};
1369
1370namespace AArch64 {
1371FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1372 const TargetLibraryInfo *libInfo);
1373} // end namespace AArch64
1374
1375} // end namespace llvm
1376
1377#endif
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Addr
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool shouldExpandCmpUsingSelects() const override
Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean ...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) const override
Lower an interleave intrinsic to a target specific store intrinsic.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
MachineBasicBlock * EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const override
Return the prefered common base offset.
bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
bool shouldExpandCttzElements(EVT VT) const override
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) const override
Lower a deinterleave intrinsic to a target specific load intrinsic.
MachineBasicBlock * EmitInitTPIDR2Object(MachineInstr &MI, MachineBasicBlock *BB) const
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveRedundantExtend(SDValue Op) const override
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
bool supportPtrAuthBundles() const override
Return true if the target supports ptrauth operand bundles.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool hasInlineStackProbe(const MachineFunction &MF) const override
True if stack clash protection is enabled for this functions.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
bool isOpSuitableForLSE128(const Instruction *I) const
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
bool fallBackToDAGISel(const Instruction &Inst) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
bool isLegalAddScalableImmediate(int64_t) const override
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
bool isOpSuitableForRCPC3(const Instruction *I) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
unsigned getRedZoneSize(const Function &F) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
MachineBasicBlock * EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) const
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
void verifyTargetSDNode(const SDNode *N) const override
Check the given SDNode. Aborts if it is invalid.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override
GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x),...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
MachineBasicBlock * EmitAllocateZABuffer(MachineInstr &MI, MachineBasicBlock *BB) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const override
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isOpSuitableForLDPSTP(const Instruction *I) const
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool shouldConsiderGEPOffsetSplit() const override
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override
Similar to isShuffleMaskLegal.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
ArrayRef< MCPhysReg > getRoundingControlRegisters() const override
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MachineBasicBlock * EmitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, SDValue PStateSM=SDValue()) const
If a change in streaming mode is required on entry to/return from a function call it emits and return...
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Class for arbitrary precision integers.
Definition: APInt.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:495
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:696
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:42
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:281
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:743
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:91
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:174
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:39
Machine Value Type.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:226
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
An instruction for storing to memory.
Definition: Instructions.h:290
Saves strings in the provided stable storage and returns a StringRef with a stable character pointer.
Definition: StringSaver.h:21
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:202
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
@ NVCAST
Natural vector cast.
ArrayRef< MCPhysReg > getFPRArgRegs()
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
const unsigned StackProbeMaxLoopUnroll
Maximum number of iterations to unroll for a constant size probing loop.
const unsigned StackProbeMaxUnprobedStack
Maximum allowed number of unprobed bytes above SP at an ABI boundary.
const unsigned RoundingBitsPos
const uint64_t ReservedFPControlBits
ArrayRef< MCPhysReg > getGPRArgRegs()
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1480
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1492
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1552
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1486
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1603
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1583
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
AddressSpace
Definition: NVPTXBaseInfo.h:21
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
AtomicOrdering
Atomic ordering for LLVM's memory model.
TargetTransformInfo TTI
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
DWARFExpression::Operation Op
@ Enable
Enable colors.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:35
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:359
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:168