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AArch64ISelLowering.h
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1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AArch64 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16
21#include "llvm/IR/CallingConv.h"
22#include "llvm/IR/Instruction.h"
23
24namespace llvm {
25
26namespace AArch64ISD {
27
28// For predicated nodes where the result is a vector, the operation is
29// controlled by a governing predicate and the inactive lanes are explicitly
30// defined with a value, please stick the following naming convention:
31//
32// _MERGE_OP<n> The result value is a vector with inactive lanes equal
33// to source operand OP<n>.
34//
35// _MERGE_ZERO The result value is a vector with inactive lanes
36// actively zeroed.
37//
38// _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
39// to the last source operand which only purpose is being
40// a passthru value.
41//
42// For other cases where no explicit action is needed to set the inactive lanes,
43// or when the result is not a vector and it is needed or helpful to
44// distinguish a node from similar unpredicated nodes, use:
45//
46// _PRED
47//
48enum NodeType : unsigned {
50 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
51 CALL, // Function call.
52
53 // Pseudo for a OBJC call that gets emitted together with a special `mov
54 // x29, x29` marker instruction.
56
57 CALL_BTI, // Function call followed by a BTI instruction.
58
59 // Function call, authenticating the callee value first:
60 // AUTH_CALL chain, callee, auth key #, int disc, addr disc, operands.
62 // AUTH_TC_RETURN chain, callee, fpdiff, auth key #, int disc, addr disc,
63 // operands.
65
66 // Authenticated variant of CALL_RVMARKER.
68
70
73
79
80 // A call with the callee in x16, i.e. "blr x16".
82
83 // Produces the full sequence of instructions for getting the thread pointer
84 // offset of a variable into X0, using the TLSDesc model.
87 ADRP, // Page address of a TargetGlobalAddress operand.
88 ADR, // ADR
89 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
90 LOADgot, // Load from automatically generated descriptor (e.g. Global
91 // Offset Table, TLS record).
92 RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand.
93 BRCOND, // Conditional branch instruction; "b.cond".
95 CSINV, // Conditional select invert.
96 CSNEG, // Conditional select negate.
97 CSINC, // Conditional select increment.
98
99 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
100 // ELF.
103 SBC, // adc, sbc instructions
104
105 // To avoid stack clash, allocation is performed by block and each block is
106 // probed.
108
109 // Predicated instructions where inactive lanes produce undefined results.
137
138 // Unpredicated vector instructions
140
142
143 // Predicated instructions with the result of inactive lanes provided by the
144 // last operand.
167
169
170 // Arithmetic instructions which write flags.
176
177 // Conditional compares. Operands: left,right,falsecc,cc,flags
181
182 // Floating point comparison
184
185 // Scalar-to-vector duplication
192
193 // Vector immedate moves
201
202 // Vector immediate ops
205
206 // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
207 // element must be identical.
209
210 // Vector shuffles
222
223 // Vector shift by scalar
227
228 // Vector shift by scalar (again)
235
236 // Vector narrowing shift by immediate (bottom)
238
239 // Vector shift by constant and insert
242
243 // Vector comparisons
252
253 // Vector zero comparisons
264
265 // Round wide FP to narrow FP with inexact results to odd.
267
268 // Vector across-lanes addition
269 // Only the lower result lane is defined.
272
273 // Unsigned sum Long across Vector
276
277 // Wide adds
282
283 // Add Pairwise of two vectors
285 // Add Long Pairwise
288
289 // udot/sdot/usdot instructions
293
294 // Vector across-lanes min/max
295 // Only the lower result lane is defined.
300
310
311 // Compare-and-branch
316
317 // Tail calls
319
320 // Custom prefetch handling
322
323 // {s|u}int to FP within a FP register.
326
327 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
328 /// world w.r.t vectors; which causes additional REV instructions to be
329 /// generated to compensate for the byte-swapping. But sometimes we do
330 /// need to re-interpret the data in SIMD vector registers in big-endian
331 /// mode without emitting such REV instructions.
333
334 MRS, // MRS, also sets the flags via a glue.
335
338
340
341 // Reciprocal estimates and steps.
346
351
357
358 // Floating-point reductions.
365
370
372
381
382 // Cast between vectors of the same element type but differ in length.
384
385 // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
388
397
398 // Structured loads.
402
403 // Unsigned gather loads.
413
414 // Signed gather loads
422
423 // Unsigned gather loads.
431
432 // Signed gather loads.
440
441 // Non-temporal gather loads
445
446 // Contiguous masked store.
448
449 // Scatter store
459
460 // Non-temporal scatter store
463
464 // SME
469
470 // Needed for __arm_agnostic("sme_za_state")
473
474 // Asserts that a function argument (i32) is zero-extended to i8 by
475 // the caller
477
478 // 128-bit system register accesses
479 // lo64, hi64, chain = MRRS(chain, sysregname)
481 // chain = MSRR(chain, sysregname, lo64, hi64)
483
484 // Strict (exception-raising) floating point comparison
489
490 // NEON Load/Store with post-increment base updates
515
520
528
529 // SME ZA loads and stores
532};
533
534} // end namespace AArch64ISD
535
536namespace AArch64 {
537/// Possible values of current rounding mode, which is specified in bits
538/// 23:22 of FPCR.
540 RN = 0, // Round to Nearest
541 RP = 1, // Round towards Plus infinity
542 RM = 2, // Round towards Minus infinity
543 RZ = 3, // Round towards Zero
544 rmMask = 3 // Bit mask selecting rounding mode
546
547// Bit position of rounding mode bits in FPCR.
548const unsigned RoundingBitsPos = 22;
549
550// Reserved bits should be preserved when modifying FPCR.
551const uint64_t ReservedFPControlBits = 0xfffffffff80040f8;
552
553// Registers used to pass function arguments.
556
557/// Maximum allowed number of unprobed bytes above SP at an ABI
558/// boundary.
559const unsigned StackProbeMaxUnprobedStack = 1024;
560
561/// Maximum number of iterations to unroll for a constant size probing loop.
562const unsigned StackProbeMaxLoopUnroll = 4;
563
564} // namespace AArch64
565
566class AArch64Subtarget;
567
569public:
570 explicit AArch64TargetLowering(const TargetMachine &TM,
571 const AArch64Subtarget &STI);
572
573 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
574 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
576 SDValue N1) const override;
577
578 /// Selects the correct CCAssignFn for a given CallingConvention value.
579 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
580
581 /// Selects the correct CCAssignFn for a given CallingConvention value.
583
584 /// Determine which of the bits specified in Mask are known to be either zero
585 /// or one and return them in the KnownZero/KnownOne bitsets.
587 const APInt &DemandedElts,
588 const SelectionDAG &DAG,
589 unsigned Depth = 0) const override;
590
592 const APInt &DemandedElts,
593 const SelectionDAG &DAG,
594 unsigned Depth) const override;
595
596 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
597 // Returning i64 unconditionally here (i.e. even for ILP32) means that the
598 // *DAG* representation of pointers will always be 64-bits. They will be
599 // truncated and extended when transferred to memory, but the 64-bit DAG
600 // allows us to use AArch64's addressing modes much more easily.
601 return MVT::getIntegerVT(64);
602 }
603
605 const APInt &DemandedElts,
606 TargetLoweringOpt &TLO) const override;
607
608 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
609
610 /// Returns true if the target allows unaligned memory accesses of the
611 /// specified type.
613 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
615 unsigned *Fast = nullptr) const override;
616 /// LLT variant.
617 bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
618 Align Alignment,
620 unsigned *Fast = nullptr) const override;
621
622 /// Provide custom lowering hooks for some operations.
623 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
624
625 const char *getTargetNodeName(unsigned Opcode) const override;
626
627 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
628
629 /// This method returns a target specific FastISel object, or null if the
630 /// target does not support "fast" ISel.
632 const TargetLibraryInfo *libInfo) const override;
633
634 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
635
636 bool isFPImmLegal(const APFloat &Imm, EVT VT,
637 bool ForCodeSize) const override;
638
639 /// Return true if the given shuffle mask can be codegen'd directly, or if it
640 /// should be stack expanded.
641 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
642
643 /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
644 /// shuffle mask can be codegen'd directly.
645 bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
646
647 /// Return the ISD::SETCC ValueType.
649 EVT VT) const override;
650
652
654 MachineBasicBlock *BB) const;
655
657 MachineBasicBlock *BB) const;
658
660 MachineBasicBlock *MBB) const;
661
662 MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
664 MachineBasicBlock *BB) const;
666 MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
667 MachineInstr &MI, MachineBasicBlock *BB) const;
669 unsigned Opcode, bool Op0IsDef) const;
672 MachineBasicBlock *BB) const;
674 MachineBasicBlock *BB) const;
676 MachineBasicBlock *BB) const;
678 MachineBasicBlock *BB) const;
679
682 MachineBasicBlock *MBB) const override;
683
684 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
685 MachineFunction &MF,
686 unsigned Intrinsic) const override;
687
689 EVT NewVT) const override;
690
691 bool shouldRemoveRedundantExtend(SDValue Op) const override;
692
693 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
694 bool isTruncateFree(EVT VT1, EVT VT2) const override;
695
696 bool isProfitableToHoist(Instruction *I) const override;
697
698 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
699 bool isZExtFree(EVT VT1, EVT VT2) const override;
700 bool isZExtFree(SDValue Val, EVT VT2) const override;
701
703 Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override;
704
705 bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
706
707 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
708
711 ArrayRef<unsigned> Indices,
712 unsigned Factor) const override;
714 unsigned Factor) const override;
715
717 LoadInst *LI, ArrayRef<Value *> DeinterleaveValues) const override;
718
720 StoreInst *SI, ArrayRef<Value *> InterleaveValues) const override;
721
722 bool isLegalAddImmediate(int64_t) const override;
723 bool isLegalAddScalableImmediate(int64_t) const override;
724 bool isLegalICmpImmediate(int64_t) const override;
725
727 SDValue ConstNode) const override;
728
729 bool shouldConsiderGEPOffsetSplit() const override;
730
732 const AttributeList &FuncAttributes) const override;
733
735 const AttributeList &FuncAttributes) const override;
736
737 /// Return true if the addressing mode represented by AM is legal for this
738 /// target, for a load/store of the specified type.
739 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
740 unsigned AS,
741 Instruction *I = nullptr) const override;
742
743 int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset,
744 int64_t MaxOffset) const override;
745
746 /// Return true if an FMA operation is faster than a pair of fmul and fadd
747 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
748 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
750 EVT VT) const override;
751 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
752
754 CodeGenOptLevel OptLevel) const override;
755
756 /// Return true if the target has native support for
757 /// the specified value type and it is 'desirable' to use the type for the
758 /// given node type.
759 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
760
761 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
763
764 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
766 CombineLevel Level) const override;
767
768 bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override {
769 return false;
770 }
771
772 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
773 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
774
775 /// Return true if it is profitable to fold a pair of shifts into a mask.
777 CombineLevel Level) const override;
778
779 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
780 EVT VT) const override;
781
782 /// Returns true if it is beneficial to convert a load of a constant
783 /// to just the constant itself.
785 Type *Ty) const override;
786
787 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
788 /// with this index.
789 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
790 unsigned Index) const override;
791
792 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
793 bool MathUsed) const override {
794 // Using overflow ops for overflow checks only should beneficial on
795 // AArch64.
796 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
797 }
798
799 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
800 AtomicOrdering Ord) const override;
802 AtomicOrdering Ord) const override;
803
804 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
805
806 bool isOpSuitableForLDPSTP(const Instruction *I) const;
807 bool isOpSuitableForLSE128(const Instruction *I) const;
808 bool isOpSuitableForRCPC3(const Instruction *I) const;
809 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
810 bool
812
814 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
816 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
818 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
819
822
823 bool useLoadStackGuardNode(const Module &M) const override;
825 getPreferredVectorAction(MVT VT) const override;
826
827 /// If the target has a standard location for the stack protector cookie,
828 /// returns the address of that location. Otherwise, returns nullptr.
829 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
830
831 void insertSSPDeclarations(Module &M) const override;
832 Value *getSDagStackGuard(const Module &M) const override;
833 Function *getSSPStackGuardCheck(const Module &M) const override;
834
835 /// If the target has a standard location for the unsafe stack pointer,
836 /// returns the address of that location. Otherwise, returns nullptr.
837 Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
838
839 /// If a physical register, this returns the register that receives the
840 /// exception address on entry to an EH pad.
842 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
843
844 /// If a physical register, this returns the register that receives the
845 /// exception typeid on entry to a landing pad.
847 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
848
849 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
850
851 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
852 const MachineFunction &MF) const override;
853
854 bool isCheapToSpeculateCttz(Type *) const override {
855 return true;
856 }
857
858 bool isCheapToSpeculateCtlz(Type *) const override {
859 return true;
860 }
861
862 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
863
864 bool hasAndNotCompare(SDValue V) const override {
865 // We can use bics for any scalar.
866 return V.getValueType().isScalarInteger();
867 }
868
869 bool hasAndNot(SDValue Y) const override {
870 EVT VT = Y.getValueType();
871
872 if (!VT.isVector())
873 return hasAndNotCompare(Y);
874
875 TypeSize TS = VT.getSizeInBits();
876 // TODO: We should be able to use bic/bif too for SVE.
877 return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
878 }
879
882 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
883 SelectionDAG &DAG) const override;
884
887 unsigned ExpansionFactor) const override;
888
890 unsigned KeptBits) const override {
891 // For vectors, we don't have a preference..
892 if (XVT.isVector())
893 return false;
894
895 auto VTIsOk = [](EVT VT) -> bool {
896 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
897 VT == MVT::i64;
898 };
899
900 // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
901 // XVT will be larger than KeptBitsVT.
902 MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
903 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
904 }
905
906 bool preferIncOfAddToSubOfNot(EVT VT) const override;
907
908 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
909
910 bool shouldExpandCmpUsingSelects(EVT VT) const override;
911
912 bool isComplexDeinterleavingSupported() const override;
914 ComplexDeinterleavingOperation Operation, Type *Ty) const override;
915
918 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
919 Value *Accumulator = nullptr) const override;
920
921 bool supportSplitCSR(MachineFunction *MF) const override {
923 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
924 }
925 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
927 MachineBasicBlock *Entry,
928 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
929
930 bool supportSwiftError() const override {
931 return true;
932 }
933
934 bool supportPtrAuthBundles() const override { return true; }
935
936 bool supportKCFIBundles() const override { return true; }
937
940 const TargetInstrInfo *TII) const override;
941
942 /// Enable aggressive FMA fusion on targets that want it.
943 bool enableAggressiveFMAFusion(EVT VT) const override;
944
945 /// Returns the size of the platform's va_list object.
946 unsigned getVaListSizeInBits(const DataLayout &DL) const override;
947
948 /// Returns true if \p VecTy is a legal interleaved access type. This
949 /// function checks the vector element type and the overall width of the
950 /// vector.
952 bool &UseScalable) const;
953
954 /// Returns the number of interleaved accesses that will be generated when
955 /// lowering accesses of the given type.
956 unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
957 bool UseScalable) const;
958
960 const Instruction &I) const override;
961
963 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
964 const DataLayout &DL) const override;
965
966 /// Used for exception handling on Win64.
967 bool needsFixedCatchObjects() const override;
968
969 bool fallBackToDAGISel(const Instruction &Inst) const override;
970
971 /// SVE code generation for fixed length vectors does not custom lower
972 /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
973 /// merge. However, merging them creates a BUILD_VECTOR that is just as
974 /// illegal as the original, thus leading to an infinite legalisation loop.
975 /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
976 /// vector types this override can be removed.
977 bool mergeStoresAfterLegalization(EVT VT) const override;
978
979 // If the platform/function should have a redzone, return the size in bytes.
980 unsigned getRedZoneSize(const Function &F) const {
981 if (F.hasFnAttribute(Attribute::NoRedZone))
982 return 0;
983 return 128;
984 }
985
986 bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
988
990 bool AllowUnknown = false) const override;
991
992 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
993
994 bool
996
997 bool shouldExpandCttzElements(EVT VT) const override;
998
999 bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const override;
1000
1001 /// If a change in streaming mode is required on entry to/return from a
1002 /// function call it emits and returns the corresponding SMSTART or SMSTOP
1003 /// node. \p Condition should be one of the enum values from
1004 /// AArch64SME::ToggleCondition.
1006 SDValue Chain, SDValue InGlue, unsigned Condition,
1007 SDValue PStateSM = SDValue()) const;
1008
1009 bool isVScaleKnownToBeAPowerOfTwo() const override { return true; }
1010
1011 // Normally SVE is only used for byte size vectors that do not fit within a
1012 // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
1013 // used for 64bit and 128bit vectors as well.
1014 bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
1015
1016 // Follow NEON ABI rules even when using SVE for fixed length vectors.
1018 EVT VT) const override;
1021 EVT VT) const override;
1024 EVT &IntermediateVT,
1025 unsigned &NumIntermediates,
1026 MVT &RegisterVT) const override;
1027
1028 /// True if stack clash protection is enabled for this functions.
1029 bool hasInlineStackProbe(const MachineFunction &MF) const override;
1030
1031#ifndef NDEBUG
1032 void verifyTargetSDNode(const SDNode *N) const override;
1033#endif
1034
1035private:
1036 /// Keep a pointer to the AArch64Subtarget around so that we can
1037 /// make the right decision when generating code for different targets.
1038 const AArch64Subtarget *Subtarget;
1039
1040 llvm::BumpPtrAllocator BumpAlloc;
1041 llvm::StringSaver Saver{BumpAlloc};
1042
1043 bool isExtFreeImpl(const Instruction *Ext) const override;
1044
1045 void addTypeForNEON(MVT VT);
1046 void addTypeForFixedLengthSVE(MVT VT);
1047 void addDRType(MVT VT);
1048 void addQRType(MVT VT);
1049
1050 bool shouldExpandBuildVectorWithShuffles(EVT, unsigned) const override;
1051
1052 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
1053 bool isVarArg,
1054 const SmallVectorImpl<ISD::InputArg> &Ins,
1055 const SDLoc &DL, SelectionDAG &DAG,
1056 SmallVectorImpl<SDValue> &InVals) const override;
1057
1058 void AdjustInstrPostInstrSelection(MachineInstr &MI,
1059 SDNode *Node) const override;
1060
1061 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
1062 SmallVectorImpl<SDValue> &InVals) const override;
1063
1064 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
1065 CallingConv::ID CallConv, bool isVarArg,
1066 const SmallVectorImpl<CCValAssign> &RVLocs,
1067 const SDLoc &DL, SelectionDAG &DAG,
1068 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1069 SDValue ThisVal, bool RequiresSMChange) const;
1070
1071 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1072 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1073 SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
1074 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1075
1076 SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
1077 SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
1078
1079 SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
1080
1081 SDValue LowerVECTOR_COMPRESS(SDValue Op, SelectionDAG &DAG) const;
1082
1083 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1084 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1085 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1086
1087 bool
1088 isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
1089
1090 /// Finds the incoming stack arguments which overlap the given fixed stack
1091 /// object and incorporates their load into the current chain. This prevents
1092 /// an upcoming store from clobbering the stack argument before it's used.
1093 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
1094 MachineFrameInfo &MFI, int ClobberedFI) const;
1095
1096 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
1097
1098 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
1099 SDValue &Chain) const;
1100
1101 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1102 bool isVarArg,
1103 const SmallVectorImpl<ISD::OutputArg> &Outs,
1104 LLVMContext &Context, const Type *RetTy) const override;
1105
1106 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1107 const SmallVectorImpl<ISD::OutputArg> &Outs,
1108 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
1109 SelectionDAG &DAG) const override;
1110
1111 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1112 unsigned Flag) const;
1113 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
1114 unsigned Flag) const;
1115 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
1116 unsigned Flag) const;
1117 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1118 unsigned Flag) const;
1119 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
1120 unsigned Flag) const;
1121 template <class NodeTy>
1122 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1123 template <class NodeTy>
1124 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1125 template <class NodeTy>
1126 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1127 template <class NodeTy>
1128 SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1129 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1130 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1131 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1132 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1133 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1134 SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
1135 const SDLoc &DL, SelectionDAG &DAG) const;
1136 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
1137 SelectionDAG &DAG) const;
1138 SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1139 SDValue LowerPtrAuthGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1140 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1141 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1142 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
1143 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1144 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1145 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
1146 SDValue TVal, SDValue FVal, const SDLoc &dl,
1147 SelectionDAG &DAG) const;
1148 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1149 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1150 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1151 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
1152 SDValue LowerBRIND(SDValue Op, SelectionDAG &DAG) const;
1153 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1154 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1155 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
1156 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
1157 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
1158 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1159 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1160 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1161 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1162 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
1163 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1164 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1165 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1166 SDValue LowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
1167 SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
1168 SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
1169 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1170 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1171 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1172 SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
1173 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1174 SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1175 SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
1176 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
1177 unsigned NewOp) const;
1178 SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
1179 SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
1180 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1181 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1182 SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1183 SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1184 SDValue LowerVECTOR_HISTOGRAM(SDValue Op, SelectionDAG &DAG) const;
1185 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1186 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1187 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
1188 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
1189 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
1190 SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const;
1191 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
1192 SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
1193 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
1194 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
1195 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1196 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1197 SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1198 SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1199 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1200 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1201 SDValue LowerVectorXRINT(SDValue Op, SelectionDAG &DAG) const;
1202 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1203 SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1204 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
1205 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1206 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
1207 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
1208 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1209 SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
1210 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1211 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
1212 SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
1213 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1214 SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1215 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1216
1217 SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const;
1218
1219 SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
1220 SelectionDAG &DAG) const;
1221 SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
1222 SelectionDAG &DAG) const;
1223 SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1224 SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1225 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1226 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1227 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
1228 SelectionDAG &DAG) const;
1229 SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
1230 SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
1231 SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
1232 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1233 SelectionDAG &DAG) const;
1234 SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
1235 SelectionDAG &DAG) const;
1236 SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
1237 SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
1238 SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
1239 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
1240 SelectionDAG &DAG) const;
1241 SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
1242 SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
1243 SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
1244 SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
1245 SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
1246 SelectionDAG &DAG) const;
1247 SDValue LowerFixedLengthBuildVectorToSVE(SDValue Op, SelectionDAG &DAG) const;
1248
1249 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1250 SmallVectorImpl<SDNode *> &Created) const override;
1251 SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1252 SmallVectorImpl<SDNode *> &Created) const override;
1253 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1254 int &ExtraSteps, bool &UseOneConst,
1255 bool Reciprocal) const override;
1256 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1257 int &ExtraSteps) const override;
1258 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1259 const DenormalMode &Mode) const override;
1260 SDValue getSqrtResultForDenormInput(SDValue Operand,
1261 SelectionDAG &DAG) const override;
1262 unsigned combineRepeatedFPDivisors() const override;
1263
1264 ConstraintType getConstraintType(StringRef Constraint) const override;
1265 Register getRegisterByName(const char* RegName, LLT VT,
1266 const MachineFunction &MF) const override;
1267
1268 /// Examine constraint string and operand type and determine a weight value.
1269 /// The operand object must already have been set up with the operand type.
1271 getSingleConstraintMatchWeight(AsmOperandInfo &info,
1272 const char *constraint) const override;
1273
1274 std::pair<unsigned, const TargetRegisterClass *>
1275 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1276 StringRef Constraint, MVT VT) const override;
1277
1278 const char *LowerXConstraint(EVT ConstraintVT) const override;
1279
1280 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
1281 std::vector<SDValue> &Ops,
1282 SelectionDAG &DAG) const override;
1283
1285 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1286 if (ConstraintCode == "Q")
1288 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1289 // followed by llvm_unreachable so we'll leave them unimplemented in
1290 // the backend for now.
1291 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1292 }
1293
1294 /// Handle Lowering flag assembly outputs.
1295 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
1296 const SDLoc &DL,
1297 const AsmOperandInfo &Constraint,
1298 SelectionDAG &DAG) const override;
1299
1300 bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1301 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
1302 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1303 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1304 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1305 bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1306 SDValue &Offset, SelectionDAG &DAG) const;
1307 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1309 SelectionDAG &DAG) const override;
1310 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1311 SDValue &Offset, ISD::MemIndexedMode &AM,
1312 SelectionDAG &DAG) const override;
1313 bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
1314 bool IsPre, MachineRegisterInfo &MRI) const override;
1315
1316 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1317 SelectionDAG &DAG) const override;
1318 void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1319 SelectionDAG &DAG) const;
1320 void ReplaceExtractSubVectorResults(SDNode *N,
1321 SmallVectorImpl<SDValue> &Results,
1322 SelectionDAG &DAG) const;
1323
1324 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1325
1326 void finalizeLowering(MachineFunction &MF) const override;
1327
1328 bool shouldLocalize(const MachineInstr &MI,
1329 const TargetTransformInfo *TTI) const override;
1330
1331 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
1332 const APInt &OriginalDemandedBits,
1333 const APInt &OriginalDemandedElts,
1334 KnownBits &Known,
1335 TargetLoweringOpt &TLO,
1336 unsigned Depth) const override;
1337
1338 bool isTargetCanonicalConstantNode(SDValue Op) const override;
1339
1340 // With the exception of data-predicate transitions, no instructions are
1341 // required to cast between legal scalable vector types. However:
1342 // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1343 // is not universally useable.
1344 // 2. Most unpacked integer types are not legal and thus integer extends
1345 // cannot be used to convert between unpacked and packed types.
1346 // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1347 // to transition between unpacked and packed types of the same element type,
1348 // with BITCAST used otherwise.
1349 // This function does not handle predicate bitcasts.
1350 SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1351
1352 // Returns the runtime value for PSTATE.SM by generating a call to
1353 // __arm_sme_state.
1354 SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1355 EVT VT) const;
1356
1357 bool preferScalarizeSplat(SDNode *N) const override;
1358
1359 unsigned getMinimumJumpTableEntries() const override;
1360
1361 bool softPromoteHalfType() const override { return true; }
1362
1363 bool shouldScalarizeBinop(SDValue VecOp) const override {
1364 return VecOp.getOpcode() == ISD::SETCC;
1365 }
1366};
1367
1368namespace AArch64 {
1369FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1370 const TargetLibraryInfo *libInfo);
1371} // end namespace AArch64
1372
1373} // end namespace llvm
1374
1375#endif
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
return RetTy
uint64_t Addr
uint32_t Index
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) const override
Return true if the @llvm.experimental.vector.partial.reduce.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
MachineBasicBlock * EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const override
Return the prefered common base offset.
bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
bool shouldExpandCttzElements(EVT VT) const override
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
MachineBasicBlock * EmitInitTPIDR2Object(MachineInstr &MI, MachineBasicBlock *BB) const
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
bool shouldExpandCmpUsingSelects(EVT VT) const override
Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean ...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveRedundantExtend(SDValue Op) const override
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
bool supportPtrAuthBundles() const override
Return true if the target supports ptrauth operand bundles.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool hasInlineStackProbe(const MachineFunction &MF) const override
True if stack clash protection is enabled for this functions.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
bool isOpSuitableForLSE128(const Instruction *I) const
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool fallBackToDAGISel(const Instruction &Inst) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
bool isLegalAddScalableImmediate(int64_t) const override
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
bool isOpSuitableForRCPC3(const Instruction *I) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
unsigned getRedZoneSize(const Function &F) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
MachineBasicBlock * EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) const
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const override
Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ ...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
void verifyTargetSDNode(const SDNode *N) const override
Check the given SDNode. Aborts if it is invalid.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override
GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x),...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
MachineBasicBlock * EmitAllocateSMESaveBuffer(MachineInstr &MI, MachineBasicBlock *BB) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
MachineBasicBlock * EmitAllocateZABuffer(MachineInstr &MI, MachineBasicBlock *BB) const
bool lowerInterleaveIntrinsicToStore(StoreInst *SI, ArrayRef< Value * > InterleaveValues) const override
Lower an interleave intrinsic to a target specific store intrinsic.
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool lowerDeinterleaveIntrinsicToLoad(LoadInst *LI, ArrayRef< Value * > DeinterleaveValues) const override
Lower a deinterleave intrinsic to a target specific load intrinsic.
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const override
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isOpSuitableForLDPSTP(const Instruction *I) const
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
MachineBasicBlock * EmitGetSMESaveSize(MachineInstr &MI, MachineBasicBlock *BB) const
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool shouldConsiderGEPOffsetSplit() const override
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override
Similar to isShuffleMaskLegal.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool useLoadStackGuardNode(const Module &M) const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
ArrayRef< MCPhysReg > getRoundingControlRegisters() const override
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MachineBasicBlock * EmitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, SDValue PStateSM=SDValue()) const
If a change in streaming mode is required on entry to/return from a function call it emits and return...
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Class for arbitrary precision integers.
Definition: APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:501
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:704
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:42
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:277
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:731
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:113
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:176
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:39
Machine Value Type.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:71
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:228
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
An instruction for storing to memory.
Definition: Instructions.h:292
Saves strings in the provided stable storage and returns a StringRef with a stable character pointer.
Definition: StringSaver.h:21
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:427
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:202
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
@ NVCAST
Natural vector cast.
ArrayRef< MCPhysReg > getFPRArgRegs()
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
const unsigned StackProbeMaxLoopUnroll
Maximum number of iterations to unroll for a constant size probing loop.
const unsigned StackProbeMaxUnprobedStack
Maximum allowed number of unprobed bytes above SP at an ABI boundary.
const unsigned RoundingBitsPos
const uint64_t ReservedFPControlBits
ArrayRef< MCPhysReg > getGPRArgRegs()
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:780
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1494
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1559
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1610
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1590
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
AtomicOrdering
Atomic ordering for LLVM's memory model.
TargetTransformInfo TTI
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
DWARFExpression::Operation Op
@ Enable
Enable colors.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:35
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:368
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:168