14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
578 const APInt &DemandedElts,
580 unsigned Depth = 0)
const override;
583 const APInt &DemandedElts,
585 unsigned Depth)
const override;
596 const APInt &DemandedElts,
597 TargetLoweringOpt &TLO)
const override;
606 unsigned *
Fast =
nullptr)
const override;
611 unsigned *
Fast =
nullptr)
const override;
628 bool ForCodeSize)
const override;
640 EVT VT)
const override;
660 unsigned Opcode,
bool Op0IsDef)
const;
673 unsigned Intrinsic)
const override;
676 EVT NewVT)
const override;
702 unsigned Factor)
const override;
704 unsigned Factor)
const override;
717 SDValue ConstNode)
const override;
734 int64_t MaxOffset)
const override;
740 EVT VT)
const override;
765 EVT VT)
const override;
770 Type *Ty)
const override;
775 unsigned Index)
const override;
778 bool MathUsed)
const override {
866 return V.getValueType().isScalarInteger();
870 EVT VT =
Y.getValueType();
882 unsigned OldShiftOpcode,
unsigned NewShiftOpcode,
887 unsigned ExpansionFactor)
const override;
890 unsigned KeptBits)
const override {
895 auto VTIsOk = [](
EVT VT) ->
bool {
896 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
903 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
952 bool &UseScalable)
const;
957 bool UseScalable)
const;
981 if (
F.hasFnAttribute(Attribute::NoRedZone))
990 bool AllowUnknown =
false)
const override;
1013 EVT VT)
const override;
1016 EVT VT)
const override;
1019 EVT &IntermediateVT,
1020 unsigned &NumIntermediates,
1021 MVT &RegisterVT)
const override;
1038 bool isExtFreeImpl(
const Instruction *Ext)
const override;
1040 void addTypeForNEON(MVT VT);
1041 void addTypeForFixedLengthSVE(MVT VT);
1042 void addDRType(MVT VT);
1043 void addQRType(MVT VT);
1045 bool shouldExpandBuildVectorWithShuffles(EVT,
unsigned)
const override;
1049 const SmallVectorImpl<ISD::InputArg> &Ins,
1050 const SDLoc &
DL, SelectionDAG &DAG,
1051 SmallVectorImpl<SDValue> &InVals)
const override;
1053 void AdjustInstrPostInstrSelection(MachineInstr &
MI,
1054 SDNode *
Node)
const override;
1056 SDValue LowerCall(CallLoweringInfo & ,
1057 SmallVectorImpl<SDValue> &InVals)
const override;
1059 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
1061 const SmallVectorImpl<CCValAssign> &RVLocs,
1062 const SDLoc &
DL, SelectionDAG &DAG,
1063 SmallVectorImpl<SDValue> &InVals,
bool isThisReturn,
1064 SDValue ThisVal,
bool RequiresSMChange)
const;
1066 SDValue LowerLOAD(SDValue
Op, SelectionDAG &DAG)
const;
1067 SDValue LowerSTORE(SDValue
Op, SelectionDAG &DAG)
const;
1068 SDValue LowerStore128(SDValue
Op, SelectionDAG &DAG)
const;
1069 SDValue LowerABS(SDValue
Op, SelectionDAG &DAG)
const;
1071 SDValue LowerMGATHER(SDValue
Op, SelectionDAG &DAG)
const;
1072 SDValue LowerMSCATTER(SDValue
Op, SelectionDAG &DAG)
const;
1074 SDValue LowerMLOAD(SDValue
Op, SelectionDAG &DAG)
const;
1076 SDValue LowerINTRINSIC_W_CHAIN(SDValue
Op, SelectionDAG &DAG)
const;
1077 SDValue LowerINTRINSIC_WO_CHAIN(SDValue
Op, SelectionDAG &DAG)
const;
1078 SDValue LowerINTRINSIC_VOID(SDValue
Op, SelectionDAG &DAG)
const;
1081 isEligibleForTailCallOptimization(
const CallLoweringInfo &CLI)
const;
1086 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
1087 MachineFrameInfo &MFI,
int ClobberedFI)
const;
1089 bool DoesCalleeRestoreStack(
CallingConv::ID CallCC,
bool TailCallOpt)
const;
1091 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
const SDLoc &
DL,
1092 SDValue &Chain)
const;
1096 const SmallVectorImpl<ISD::OutputArg> &Outs,
1097 LLVMContext &Context)
const override;
1099 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1100 const SmallVectorImpl<ISD::OutputArg> &Outs,
1101 const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &
DL,
1102 SelectionDAG &DAG)
const override;
1104 SDValue getTargetNode(GlobalAddressSDNode *
N, EVT Ty, SelectionDAG &DAG,
1105 unsigned Flag)
const;
1106 SDValue getTargetNode(JumpTableSDNode *
N, EVT Ty, SelectionDAG &DAG,
1107 unsigned Flag)
const;
1108 SDValue getTargetNode(ConstantPoolSDNode *
N, EVT Ty, SelectionDAG &DAG,
1109 unsigned Flag)
const;
1110 SDValue getTargetNode(BlockAddressSDNode *
N, EVT Ty, SelectionDAG &DAG,
1111 unsigned Flag)
const;
1112 SDValue getTargetNode(ExternalSymbolSDNode *
N, EVT Ty, SelectionDAG &DAG,
1113 unsigned Flag)
const;
1114 template <
class NodeTy>
1115 SDValue getGOT(NodeTy *
N, SelectionDAG &DAG,
unsigned Flags = 0)
const;
1116 template <
class NodeTy>
1117 SDValue getAddrLarge(NodeTy *
N, SelectionDAG &DAG,
unsigned Flags = 0)
const;
1118 template <
class NodeTy>
1119 SDValue getAddr(NodeTy *
N, SelectionDAG &DAG,
unsigned Flags = 0)
const;
1120 template <
class NodeTy>
1121 SDValue getAddrTiny(NodeTy *
N, SelectionDAG &DAG,
unsigned Flags = 0)
const;
1122 SDValue LowerADDROFRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1123 SDValue LowerGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
1124 SDValue LowerGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1125 SDValue LowerDarwinGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1126 SDValue LowerELFGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1127 SDValue LowerELFTLSLocalExec(
const GlobalValue *GV, SDValue ThreadBase,
1128 const SDLoc &
DL, SelectionDAG &DAG)
const;
1129 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr,
const SDLoc &
DL,
1130 SelectionDAG &DAG)
const;
1131 SDValue LowerWindowsGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1132 SDValue LowerPtrAuthGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
1133 SDValue LowerPtrAuthGlobalAddressStatically(SDValue TGA, SDLoc
DL, EVT VT,
1135 SDValue Discriminator,
1136 SDValue AddrDiscriminator,
1137 SelectionDAG &DAG)
const;
1138 SDValue LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const;
1139 SDValue LowerSETCCCARRY(SDValue
Op, SelectionDAG &DAG)
const;
1140 SDValue LowerBR_CC(SDValue
Op, SelectionDAG &DAG)
const;
1141 SDValue LowerSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1142 SDValue LowerSELECT_CC(SDValue
Op, SelectionDAG &DAG)
const;
1144 SDValue TVal, SDValue FVal,
const SDLoc &dl,
1145 SelectionDAG &DAG)
const;
1146 SDValue LowerINIT_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1147 SDValue LowerADJUST_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1148 SDValue LowerJumpTable(SDValue
Op, SelectionDAG &DAG)
const;
1149 SDValue LowerBR_JT(SDValue
Op, SelectionDAG &DAG)
const;
1150 SDValue LowerBRIND(SDValue
Op, SelectionDAG &DAG)
const;
1151 SDValue LowerConstantPool(SDValue
Op, SelectionDAG &DAG)
const;
1152 SDValue LowerBlockAddress(SDValue
Op, SelectionDAG &DAG)
const;
1153 SDValue LowerAAPCS_VASTART(SDValue
Op, SelectionDAG &DAG)
const;
1154 SDValue LowerDarwin_VASTART(SDValue
Op, SelectionDAG &DAG)
const;
1155 SDValue LowerWin64_VASTART(SDValue
Op, SelectionDAG &DAG)
const;
1156 SDValue LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const;
1157 SDValue LowerVACOPY(SDValue
Op, SelectionDAG &DAG)
const;
1158 SDValue LowerVAARG(SDValue
Op, SelectionDAG &DAG)
const;
1159 SDValue LowerFRAMEADDR(SDValue
Op, SelectionDAG &DAG)
const;
1160 SDValue LowerSPONENTRY(SDValue
Op, SelectionDAG &DAG)
const;
1161 SDValue LowerRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1162 SDValue LowerGET_ROUNDING(SDValue
Op, SelectionDAG &DAG)
const;
1163 SDValue LowerSET_ROUNDING(SDValue
Op, SelectionDAG &DAG)
const;
1164 SDValue LowerGET_FPMODE(SDValue
Op, SelectionDAG &DAG)
const;
1165 SDValue LowerSET_FPMODE(SDValue
Op, SelectionDAG &DAG)
const;
1166 SDValue LowerRESET_FPMODE(SDValue
Op, SelectionDAG &DAG)
const;
1167 SDValue LowerINSERT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1168 SDValue LowerEXTRACT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1169 SDValue LowerBUILD_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1170 SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue
Op, SelectionDAG &DAG)
const;
1171 SDValue LowerVECTOR_SHUFFLE(SDValue
Op, SelectionDAG &DAG)
const;
1172 SDValue LowerSPLAT_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1173 SDValue LowerDUPQLane(SDValue
Op, SelectionDAG &DAG)
const;
1174 SDValue LowerToPredicatedOp(SDValue
Op, SelectionDAG &DAG,
1175 unsigned NewOp)
const;
1176 SDValue LowerToScalableOp(SDValue
Op, SelectionDAG &DAG)
const;
1177 SDValue LowerVECTOR_SPLICE(SDValue
Op, SelectionDAG &DAG)
const;
1178 SDValue LowerEXTRACT_SUBVECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1179 SDValue LowerINSERT_SUBVECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1180 SDValue LowerVECTOR_DEINTERLEAVE(SDValue
Op, SelectionDAG &DAG)
const;
1181 SDValue LowerVECTOR_INTERLEAVE(SDValue
Op, SelectionDAG &DAG)
const;
1182 SDValue LowerVECTOR_HISTOGRAM(SDValue
Op, SelectionDAG &DAG)
const;
1183 SDValue LowerDIV(SDValue
Op, SelectionDAG &DAG)
const;
1184 SDValue LowerMUL(SDValue
Op, SelectionDAG &DAG)
const;
1185 SDValue LowerVectorSRA_SRL_SHL(SDValue
Op, SelectionDAG &DAG)
const;
1186 SDValue LowerShiftParts(SDValue
Op, SelectionDAG &DAG)
const;
1187 SDValue LowerVSETCC(SDValue
Op, SelectionDAG &DAG)
const;
1188 SDValue LowerCTPOP_PARITY(SDValue
Op, SelectionDAG &DAG)
const;
1189 SDValue LowerCTTZ(SDValue
Op, SelectionDAG &DAG)
const;
1190 SDValue LowerBitreverse(SDValue
Op, SelectionDAG &DAG)
const;
1191 SDValue LowerMinMax(SDValue
Op, SelectionDAG &DAG)
const;
1192 SDValue LowerFCOPYSIGN(SDValue
Op, SelectionDAG &DAG)
const;
1193 SDValue LowerFP_EXTEND(SDValue
Op, SelectionDAG &DAG)
const;
1194 SDValue LowerFP_ROUND(SDValue
Op, SelectionDAG &DAG)
const;
1195 SDValue LowerVectorFP_TO_INT(SDValue
Op, SelectionDAG &DAG)
const;
1196 SDValue LowerVectorFP_TO_INT_SAT(SDValue
Op, SelectionDAG &DAG)
const;
1197 SDValue LowerFP_TO_INT(SDValue
Op, SelectionDAG &DAG)
const;
1198 SDValue LowerFP_TO_INT_SAT(SDValue
Op, SelectionDAG &DAG)
const;
1199 SDValue LowerVectorXRINT(SDValue
Op, SelectionDAG &DAG)
const;
1200 SDValue LowerINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1201 SDValue LowerVectorINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1202 SDValue LowerVectorOR(SDValue
Op, SelectionDAG &DAG)
const;
1203 SDValue LowerXOR(SDValue
Op, SelectionDAG &DAG)
const;
1204 SDValue LowerCONCAT_VECTORS(SDValue
Op, SelectionDAG &DAG)
const;
1205 SDValue LowerFSINCOS(SDValue
Op, SelectionDAG &DAG)
const;
1206 SDValue LowerBITCAST(SDValue
Op, SelectionDAG &DAG)
const;
1207 SDValue LowerVSCALE(SDValue
Op, SelectionDAG &DAG)
const;
1208 SDValue LowerTRUNCATE(SDValue
Op, SelectionDAG &DAG)
const;
1209 SDValue LowerVECREDUCE(SDValue
Op, SelectionDAG &DAG)
const;
1210 SDValue LowerATOMIC_LOAD_AND(SDValue
Op, SelectionDAG &DAG)
const;
1211 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1212 SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1213 SDValue LowerDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1215 SDValue LowerAVG(SDValue
Op, SelectionDAG &DAG,
unsigned NewOp)
const;
1217 SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue
Op,
1218 SelectionDAG &DAG)
const;
1219 SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue
Op,
1220 SelectionDAG &DAG)
const;
1221 SDValue LowerFixedLengthVectorLoadToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1222 SDValue LowerFixedLengthVectorMLoadToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1223 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG)
const;
1224 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG)
const;
1225 SDValue LowerReductionToSVE(
unsigned Opcode, SDValue ScalarOp,
1226 SelectionDAG &DAG)
const;
1227 SDValue LowerFixedLengthVectorSelectToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1228 SDValue LowerFixedLengthVectorSetccToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1229 SDValue LowerFixedLengthVectorStoreToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1230 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue
Op,
1231 SelectionDAG &DAG)
const;
1232 SDValue LowerFixedLengthVectorTruncateToSVE(SDValue
Op,
1233 SelectionDAG &DAG)
const;
1234 SDValue LowerFixedLengthExtractVectorElt(SDValue
Op, SelectionDAG &DAG)
const;
1235 SDValue LowerFixedLengthInsertVectorElt(SDValue
Op, SelectionDAG &DAG)
const;
1236 SDValue LowerFixedLengthBitcastToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1237 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue
Op,
1238 SelectionDAG &DAG)
const;
1239 SDValue LowerFixedLengthFPExtendToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1240 SDValue LowerFixedLengthFPRoundToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1241 SDValue LowerFixedLengthIntToFPToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1242 SDValue LowerFixedLengthFPToIntToSVE(SDValue
Op, SelectionDAG &DAG)
const;
1243 SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue
Op,
1244 SelectionDAG &DAG)
const;
1246 SDValue BuildSDIVPow2(SDNode *
N,
const APInt &Divisor, SelectionDAG &DAG,
1247 SmallVectorImpl<SDNode *> &Created)
const override;
1248 SDValue BuildSREMPow2(SDNode *
N,
const APInt &Divisor, SelectionDAG &DAG,
1249 SmallVectorImpl<SDNode *> &Created)
const override;
1250 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
1251 int &ExtraSteps,
bool &UseOneConst,
1252 bool Reciprocal)
const override;
1253 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
1254 int &ExtraSteps)
const override;
1255 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1256 const DenormalMode &
Mode)
const override;
1257 SDValue getSqrtResultForDenormInput(SDValue Operand,
1258 SelectionDAG &DAG)
const override;
1259 unsigned combineRepeatedFPDivisors()
const override;
1261 ConstraintType getConstraintType(StringRef Constraint)
const override;
1262 Register getRegisterByName(
const char*
RegName, LLT VT,
1263 const MachineFunction &MF)
const override;
1268 getSingleConstraintMatchWeight(AsmOperandInfo &
info,
1269 const char *constraint)
const override;
1271 std::pair<unsigned, const TargetRegisterClass *>
1272 getRegForInlineAsmConstraint(
const TargetRegisterInfo *
TRI,
1273 StringRef Constraint, MVT VT)
const override;
1275 const char *LowerXConstraint(EVT ConstraintVT)
const override;
1277 void LowerAsmOperandForConstraint(SDValue
Op, StringRef Constraint,
1278 std::vector<SDValue> &Ops,
1279 SelectionDAG &DAG)
const override;
1282 getInlineAsmMemConstraint(StringRef ConstraintCode)
const override {
1283 if (ConstraintCode ==
"Q")
1292 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
1294 const AsmOperandInfo &Constraint,
1295 SelectionDAG &DAG)
const override;
1297 bool shouldExtendGSIndex(EVT VT, EVT &EltTy)
const override;
1298 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT)
const override;
1299 bool isVectorLoadExtDesirable(SDValue ExtVal)
const override;
1300 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
1301 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
1302 bool getIndexedAddressParts(SDNode *
N, SDNode *
Op, SDValue &
Base,
1303 SDValue &
Offset, SelectionDAG &DAG)
const;
1304 bool getPreIndexedAddressParts(SDNode *
N, SDValue &
Base, SDValue &
Offset,
1306 SelectionDAG &DAG)
const override;
1307 bool getPostIndexedAddressParts(SDNode *
N, SDNode *
Op, SDValue &
Base,
1309 SelectionDAG &DAG)
const override;
1310 bool isIndexingLegal(MachineInstr &
MI, Register
Base, Register
Offset,
1311 bool IsPre, MachineRegisterInfo &
MRI)
const override;
1313 void ReplaceNodeResults(SDNode *
N, SmallVectorImpl<SDValue> &
Results,
1314 SelectionDAG &DAG)
const override;
1315 void ReplaceBITCASTResults(SDNode *
N, SmallVectorImpl<SDValue> &
Results,
1316 SelectionDAG &DAG)
const;
1317 void ReplaceExtractSubVectorResults(SDNode *
N,
1318 SmallVectorImpl<SDValue> &
Results,
1319 SelectionDAG &DAG)
const;
1321 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT)
const override;
1323 void finalizeLowering(MachineFunction &MF)
const override;
1325 bool shouldLocalize(
const MachineInstr &
MI,
1326 const TargetTransformInfo *
TTI)
const override;
1328 bool SimplifyDemandedBitsForTargetNode(SDValue
Op,
1329 const APInt &OriginalDemandedBits,
1330 const APInt &OriginalDemandedElts,
1332 TargetLoweringOpt &TLO,
1333 unsigned Depth)
const override;
1335 bool isTargetCanonicalConstantNode(SDValue
Op)
const override;
1347 SDValue getSVESafeBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG)
const;
1351 SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc
DL,
1354 bool preferScalarizeSplat(SDNode *
N)
const override;
1356 unsigned getMinimumJumpTableEntries()
const override;
1358 bool softPromoteHalfType()
const override {
return true; }
1363 const TargetLibraryInfo *libInfo);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const char LLVMTargetMachineRef TM
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool shouldExpandCmpUsingSelects() const override
Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean ...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
EVT getPromotedVTForPredicate(EVT VT) const
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
MachineBasicBlock * EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const override
Return the prefered common base offset.
bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
bool shouldExpandCttzElements(EVT VT) const override
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
MachineBasicBlock * EmitInitTPIDR2Object(MachineInstr &MI, MachineBasicBlock *BB) const
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveRedundantExtend(SDValue Op) const override
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
bool supportPtrAuthBundles() const override
Return true if the target supports ptrauth operand bundles.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool hasInlineStackProbe(const MachineFunction &MF) const override
True if stack clash protection is enabled for this functions.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
bool isOpSuitableForLSE128(const Instruction *I) const
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
bool fallBackToDAGISel(const Instruction &Inst) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
bool isLegalAddScalableImmediate(int64_t) const override
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
bool isOpSuitableForRCPC3(const Instruction *I) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
unsigned getRedZoneSize(const Function &F) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
MachineBasicBlock * EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) const
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
void verifyTargetSDNode(const SDNode *N) const override
Check the given SDNode. Aborts if it is invalid.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override
GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x),...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
MachineBasicBlock * EmitAllocateZABuffer(MachineInstr &MI, MachineBasicBlock *BB) const
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI) const override
Lower a deinterleave intrinsic to a target specific load intrinsic.
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const override
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isOpSuitableForLDPSTP(const Instruction *I) const
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool shouldConsiderGEPOffsetSplit() const override
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override
Similar to isShuffleMaskLegal.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
ArrayRef< MCPhysReg > getRoundingControlRegisters() const override
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI) const override
Lower an interleave intrinsic to a target specific store intrinsic.
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MachineBasicBlock * EmitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, SDValue PStateSM=SDValue()) const
If a change in streaming mode is required on entry to/return from a function call it emits and return...
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
An instruction that atomically checks whether a specified value is in a memory location,...
an instruction that atomically reads a memory location, combines it with another value,...
Allocate memory in an ever growing pool, as if by bump-pointer.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Common base class shared among various IRBuilders.
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
Represents a single loop in the control flow graph.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
An instruction for storing to memory.
Saves strings in the provided stable storage and returns a StringRef with a stable character pointer.
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
Base class of all SIMD vector types.
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
@ GLDFF1S_SXTW_MERGE_ZERO
@ GLDFF1_SCALED_MERGE_ZERO
@ GLD1_SXTW_SCALED_MERGE_ZERO
@ FP_EXTEND_MERGE_PASSTHRU
@ FP_ROUND_MERGE_PASSTHRU
@ GLDFF1_SXTW_SCALED_MERGE_ZERO
@ UINT_TO_FP_MERGE_PASSTHRU
@ FROUNDEVEN_MERGE_PASSTHRU
@ GLD1S_UXTW_SCALED_MERGE_ZERO
@ GLDNT1_INDEX_MERGE_ZERO
@ GLDFF1_UXTW_SCALED_MERGE_ZERO
@ FNEARBYINT_MERGE_PASSTHRU
@ GLDFF1S_SCALED_MERGE_ZERO
@ GLDFF1S_UXTW_SCALED_MERGE_ZERO
@ ZERO_EXTEND_INREG_MERGE_PASSTHRU
@ NVCAST
Natural vector cast.
@ BITREVERSE_MERGE_PASSTHRU
@ GLDFF1S_UXTW_MERGE_ZERO
@ SIGN_EXTEND_INREG_MERGE_PASSTHRU
@ GLDFF1S_SXTW_SCALED_MERGE_ZERO
@ GLD1S_SCALED_MERGE_ZERO
@ SINT_TO_FP_MERGE_PASSTHRU
@ GLD1_UXTW_SCALED_MERGE_ZERO
@ GLD1S_SXTW_SCALED_MERGE_ZERO
ArrayRef< MCPhysReg > getFPRArgRegs()
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
const unsigned StackProbeMaxLoopUnroll
Maximum number of iterations to unroll for a constant size probing loop.
const unsigned StackProbeMaxUnprobedStack
Maximum allowed number of unprobed bytes above SP at an ABI boundary.
const unsigned RoundingBitsPos
const uint64_t ReservedFPControlBits
ArrayRef< MCPhysReg > getGPRArgRegs()
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ CXX_FAST_TLS
Used for access functions.
@ Fast
Attempts to make calls as fast as possible (e.g.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
This is an optimization pass for GlobalISel generic memory operations.
ComplexDeinterleavingOperation
CodeGenOptLevel
Code generation optimization level.
AtomicOrdering
Atomic ordering for LLVM's memory model.
ComplexDeinterleavingRotation
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
DWARFExpression::Operation Op
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isVector() const
Return true if this is a vector value type.