33#include "llvm/IR/IntrinsicsXCore.h"
42#define DEBUG_TYPE "xcore-lower"
194 switch (
Op.getOpcode())
209 case ISD::SUB:
return ExpandADDSUB(
Op.getNode(), DAG);
217 return LowerATOMIC_FENCE(
Op, DAG);
228 switch (
N->getOpcode()) {
233 Results.push_back(ExpandADDSUB(
N, DAG));
251 const auto *GVar = dyn_cast<GlobalVariable>(GV);
268 unsigned ObjSize =
DL.getTypeAllocSize(ObjType);
281 int64_t FoldedOffset = std::max(
Offset & ~3, (int64_t)0);
283 GA = getGlobalAddressWrapper(GA, GV, DAG);
285 if (
Offset != FoldedOffset) {
307 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
319 EVT PtrVT =
Op.getValueType();
321 if (
CP->isMachineConstantPoolEntry()) {
323 CP->getAlign(),
CP->getOffset());
343 unsigned JTI = JT->getIndex();
348 unsigned NumEntries = MJTI->
getJumpTables()[JTI].MBBs.size();
349 if (NumEntries <= 32) {
352 assert((NumEntries >> 31) == 0);
359SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset(
363 if ((
Offset & 0x3) == 0) {
368 int32_t LowOffset = HighOffset - 4;
371 dyn_cast<GlobalAddressSDNode>(
Base.getNode())) {
407 "Unexpected extension type");
408 assert(
LD->getMemoryVT() == MVT::i32 &&
"Unexpected load EVT");
411 LD->getMemoryVT(), *
LD->getMemOperand()))
418 if (!
LD->isVolatile()) {
424 Offset = cast<ConstantSDNode>(
BasePtr->getOperand(1))->getSExtValue();
425 return lowerLoadWordFromAlignedBasePlusOffset(
DL, Chain, NewBasePtr,
432 return lowerLoadWordFromAlignedBasePlusOffset(
DL, Chain, NewBasePtr,
437 if (
LD->getAlign() ==
Align(2)) {
439 LD->getPointerInfo(), MVT::i16,
Align(2),
440 LD->getMemOperand()->getFlags());
445 LD->getPointerInfo().getWithOffset(2), MVT::i16,
446 Align(2),
LD->getMemOperand()->getFlags());
463 Args.push_back(Entry);
466 CLI.setDebugLoc(
DL).setChain(Chain).setLibCallee(
472 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
473 SDValue Ops[] = { CallResult.first, CallResult.second };
480 assert(!
ST->isTruncatingStore() &&
"Unexpected store type");
481 assert(
ST->getMemoryVT() == MVT::i32 &&
"Unexpected store EVT");
484 ST->getMemoryVT(), *
ST->getMemOperand()))
492 if (
ST->getAlign() ==
Align(2)) {
498 MVT::i16,
Align(2),
ST->getMemOperand()->getFlags());
502 Chain, dl,
High, HighAddr,
ST->getPointerInfo().getWithOffset(2),
503 MVT::i16,
Align(2),
ST->getMemOperand()->getFlags());
514 Args.push_back(Entry);
517 Args.push_back(Entry);
520 CLI.setDebugLoc(dl).setChain(Chain).setCallee(
526 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
527 return CallResult.second;
534 "Unexpected operand to lower!");
540 DAG.
getVTList(MVT::i32, MVT::i32), Zero, Zero,
551 "Unexpected operand to lower!");
557 DAG.
getVTList(MVT::i32, MVT::i32), LHS, RHS,
571 SDValue &Addend1,
bool requireIntermediatesHaveOneUse)
588 if (requireIntermediatesHaveOneUse && !AddOp.
hasOneUse())
592 if (requireIntermediatesHaveOneUse && !OtherOp.
hasOneUse())
628 if (
N->getOperand(0).getOpcode() ==
ISD::MUL) {
629 Mul =
N->getOperand(0);
631 }
else if (
N->getOperand(1).getOpcode() ==
ISD::MUL) {
632 Mul =
N->getOperand(1);
638 SDValue LL, RL, AddendL, AddendH;
654 DAG.
getVTList(MVT::i32, MVT::i32), AddendH,
659 if (LHSSB > 32 && RHSSB > 32) {
662 DAG.
getVTList(MVT::i32, MVT::i32), AddendH,
673 DAG.
getVTList(MVT::i32, MVT::i32), AddendH,
686 assert(
N->getValueType(0) == MVT::i64 &&
688 "Unknown operand to lower!");
691 if (
SDValue Result = TryExpandADDWithMul(
N, DAG))
731 EVT VT =
Node->getValueType(0);
735 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
770 if (
Op.getConstantOperandVal(0) > 0)
776 RegInfo->getFrameRegister(MF), MVT::i32);
786 if (
Op.getConstantOperandVal(0) > 0)
822 RegInfo->getFrameRegister(MF), MVT::i32);
830 unsigned StackReg = XCore::R2;
831 unsigned HandlerReg = XCore::R3;
848 return Op.getOperand(0);
858 const Value *TrmpAddr = cast<SrcValueSDNode>(
Op.getOperand(4))->getValue();
908 unsigned IntNo =
Op.getConstantOperandVal(0);
910 case Intrinsic::xcore_crc8:
911 EVT VT =
Op.getValueType();
914 Op.getOperand(1),
Op.getOperand(2) ,
Op.getOperand(3));
932#include "XCoreGenCallingConv.inc"
963 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
964 Outs, OutVals, Ins, dl, DAG, InVals);
976 for (
unsigned i = 0, e = RVLocs.
size(); i != e; ++i) {
994 for (
unsigned i = 0, e = ResultMemLocs.
size(); i != e; ++i) {
995 int offset = ResultMemLocs[i].first;
996 unsigned index = ResultMemLocs[i].second;
1000 InVals[index] =
load;
1006 if (!MemOpChains.
empty())
1016SDValue XCoreTargetLowering::LowerCCCCallTo(
1030 CCInfo.AllocateStack(4,
Align(4));
1032 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1038 RetCCInfo.AllocateStack(CCInfo.getStackSize(),
Align(4));
1039 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1042 unsigned NumBytes = RetCCInfo.getStackSize();
1050 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1087 if (!MemOpChains.
empty())
1095 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1096 Chain = DAG.
getCopyToReg(Chain, dl, RegsToPass[i].first,
1097 RegsToPass[i].second, InGlue);
1120 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
1122 RegsToPass[i].second.getValueType()));
1148SDValue XCoreTargetLowering::LowerFormalArguments(
1158 return LowerCCCArguments(Chain, CallConv, isVarArg,
1159 Ins, dl, DAG, InVals);
1167SDValue XCoreTargetLowering::LowerCCCArguments(
1181 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1185 unsigned LRSaveSize = StackSlotSize;
1202 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1214 errs() <<
"LowerFormalArguments Unhandled argument type: "
1220 Register VReg =
RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1230 if (ObjSize > StackSlotSize) {
1231 errs() <<
"LowerFormalArguments Unhandled argument type: "
1245 const ArgDataPair ADP = { ArgIn,
Ins[i].Flags };
1253 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1256 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
1257 if (FirstVAReg < std::size(ArgRegs)) {
1261 for (
int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1264 if (i == (
int)FirstVAReg) {
1267 offset -= StackSlotSize;
1270 Register VReg =
RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1271 RegInfo.addLiveIn(ArgRegs[i], VReg);
1287 if (!CFRegNode.
empty())
1294 for (
const ArgDataPair &ArgDI : ArgData) {
1295 if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) {
1296 unsigned Size = ArgDI.Flags.getByValSize();
1298 std::max(
Align(StackSlotSize), ArgDI.Flags.getNonZeroByValAlign());
1313 if (!MemOps.
empty()) {
1325bool XCoreTargetLowering::
1331 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1332 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1334 if (CCInfo.getStackSize() != 0 && isVarArg)
1362 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1368 RetOps.push_back(DAG.
getConstant(0, dl, MVT::i32));
1372 for (
unsigned i = 0, e = RVLocs.
size(); i != e; ++i) {
1384 int FI = MFI.CreateFixedObject(ObjSize,
Offset,
false);
1390 Chain, dl, OutVals[i], FIN,
1396 if (!MemOpChains.
empty())
1400 for (
unsigned i = 0, e = RVLocs.
size(); i != e; ++i) {
1417 RetOps.push_back(Glue);
1431 assert((
MI.getOpcode() == XCore::SELECT_CC) &&
1432 "Unexpected instr type to insert");
1451 F->insert(It, copy0MBB);
1452 F->insert(It, sinkMBB);
1485 MI.eraseFromParent();
1494 DAGCombinerInfo &DCI)
const {
1497 switch (
N->getOpcode()) {
1500 switch (
N->getConstantOperandVal(1)) {
1501 case Intrinsic::xcore_outt:
1502 case Intrinsic::xcore_outct:
1503 case Intrinsic::xcore_chkct: {
1511 !DCI.isBeforeLegalizeOps());
1515 DCI.CommitTargetLoweringOpt(TLO);
1519 case Intrinsic::xcore_setpt: {
1527 !DCI.isBeforeLegalizeOps());
1531 DCI.CommitTargetLoweringOpt(TLO);
1560 if (N1C && N1C->
isZero() &&
N->hasNUsesOfValue(0, 1)) {
1564 if ((Known.
Zero & Mask) == Mask) {
1586 if ((Known.
Zero & Mask) == Mask) {
1597 if (N1C && N1C->
isZero() &&
N->hasNUsesOfValue(0, 1)) {
1601 if ((Known.
Zero & Mask) == Mask) {
1620 if ((N0C && !N1C) ||
1626 if (N1C && N1C->
isZero()) {
1628 if (
N->hasNUsesOfValue(0, 0)) {
1647 SDValue Mul0, Mul1, Addend0, Addend1;
1648 if (
N->getValueType(0) == MVT::i32 &&
1651 DAG.
getVTList(MVT::i32, MVT::i32), Mul0,
1652 Mul1, Addend0, Addend1);
1661 if (
N->getValueType(0) == MVT::i64 &&
1676 DAG.
getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1677 Addend0L, Addend1L);
1686 if (!DCI.isBeforeLegalize() ||
1689 *
ST->getMemOperand()) ||
1690 ST->isVolatile() ||
ST->isIndexed()) {
1695 unsigned StoreBits =
ST->getMemoryVT().getStoreSizeInBits();
1696 assert((StoreBits % 8) == 0 &&
1697 "Store size in bits must be a multiple of 8");
1698 Align Alignment =
ST->getAlign();
1700 if (
LoadSDNode *LD = dyn_cast<LoadSDNode>(
ST->getValue())) {
1701 if (
LD->hasNUsesOfValue(1, 0) &&
ST->getMemoryVT() ==
LD->getMemoryVT() &&
1702 LD->getAlign() == Alignment &&
1703 !
LD->isVolatile() && !
LD->isIndexed() &&
1706 return DAG.
getMemmove(Chain, dl,
ST->getBasePtr(),
LD->getBasePtr(),
1708 Alignment,
false, isTail,
1709 ST->getPointerInfo(),
LD->getPointerInfo());
1718void XCoreTargetLowering::computeKnownBitsForTargetNode(
const SDValue Op,
1720 const APInt &DemandedElts,
1722 unsigned Depth)
const {
1724 switch (
Op.getOpcode()) {
1728 if (
Op.getResNo() == 1) {
1736 unsigned IntNo =
Op.getConstantOperandVal(1);
1738 case Intrinsic::xcore_getts:
1743 case Intrinsic::xcore_int:
1744 case Intrinsic::xcore_inct:
1749 case Intrinsic::xcore_testct:
1754 case Intrinsic::xcore_testwct:
1771 return (val >= 0 && val <= 11);
1776 return (val%2 == 0 &&
isImmUs(val/2));
1781 return (val%4 == 0 &&
isImmUs(val/4));
1793 unsigned Size =
DL.getTypeAllocSize(Ty);
1802 if (AM.
Scale == 0) {
1810 if (AM.
Scale == 0) {
1817 if (AM.
Scale == 0) {
1829std::pair<unsigned, const TargetRegisterClass *>
1833 if (Constraint.
size() == 1) {
1834 switch (Constraint[0]) {
1837 return std::make_pair(0U, &XCore::GRRegsRegClass);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMDGPU Mark last scratch load
Function Alias Analysis Results
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
static bool isImmUs(int64_t val)
static bool isImmUs4(int64_t val)
static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL)
static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
static bool isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, SDValue &Addend1, bool requireIntermediatesHaveOneUse)
isADDADDMUL - Return whether Op is in a form that is equivalent to add(add(mul(x,y),...
static bool isImmUs2(int64_t val)
Class for arbitrary precision integers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
LLVM Basic Block Representation.
The address of a basic block.
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
static Constant * getGetElementPtr(Type *Ty, Constant *C, ArrayRef< Constant * > IdxList, bool InBounds=false, std::optional< unsigned > InRangeIndex=std::nullopt, Type *OnlyIfReducedTy=nullptr)
Getelementptr form.
uint64_t getZExtValue() const
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
int64_t getOffset() const
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
StringRef getSection() const
Module * getParent()
Get the module that this global value is contained inside of...
Type * getValueType() const
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
@ EK_Inline
EK_Inline - Jump table entries are emitted inline at their point of use.
const std::vector< MachineJumpTableEntry > & getJumpTables() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
const TargetLowering & getTargetLoweringInfo() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
constexpr size_t size() const
size - Get the string size.
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
@ ZeroOrOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const
Check to see if the specified operand of the specified instruction is a constant integer.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Op.
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
Primary interface to the complete machine description for the target machine.
CodeModel::Model getCodeModel() const
Returns the code model.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
@ VoidTyID
type with no size
static Type * getVoidTy(LLVMContext &C)
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
static IntegerType * getInt8Ty(LLVMContext &C)
bool isFunctionTy() const
True if this is an instance of FunctionType.
static IntegerType * getInt32Ty(LLVMContext &C)
TypeID getTypeID() const
Return the type id for the type.
LLVM Value Representation.
Align getPointerAlignment(const DataLayout &DL) const
Returns an alignment of the pointer value.
static int stackSlotSize()
Stack slot size (4 bytes)
XCoreFunctionInfo - This class is derived from MachineFunction private XCore target-specific informat...
void setVarArgsFrameIndex(int off)
void setReturnStackOffset(unsigned value)
int getVarArgsFrameIndex() const
int createLRSpillSlot(MachineFunction &MF)
unsigned getReturnStackOffset() const
const TargetRegisterInfo * getRegisterInfo() const override
const XCoreInstrInfo * getInstrInfo() const override
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
XCoreTargetLowering(const TargetMachine &TM, const XCoreSubtarget &Subtarget)
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const unsigned CodeModelLargeSize
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Mul
Product of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
constexpr unsigned BitWidth
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isInteger() const
Return true if this is an integer or a vector integer type.
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
unsigned getBitWidth() const
Get the bit width of this value.
void resetAll()
Resets the known state of all bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...