AArch64ISelLowering.cpp File Reference

#include "AArch64ISelLowering.h"
#include "AArch64CallingConvention.h"
#include "AArch64ExpandImm.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64RegisterInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ObjCARCUtil.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GetElementPtrTypeIterator.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsAArch64.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/InstructionCost.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <bitset>
#include <cassert>
#include <cctype>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <optional>
#include <tuple>
#include <utility>
#include <vector>
#include "AArch64GenAsmMatcher.inc"

Go to the source code of this file.

Classes
struct	GenericSetCCInfo
	Helper structure to keep track of ISD::SET_CC operands. More...
struct	AArch64SetCCInfo
	Helper structure to keep track of a SET_CC lowered into AArch64 code. More...
union	SetCCInfo
	Helper structure to keep track of SetCC information. More...
struct	SetCCInfoAndKind
	Helper structure to be able to read SetCC information. More...

Macros
#define	DEBUG_TYPE   "aarch64-lower"
#define	LCALLNAMES(A, B, N)
#define	LCALLNAME4(A, B)
#define	LCALLNAME5(A, B)
#define	MAKE_CASE(V)
#define	GET_REGISTER_MATCHER

Enumerations
enum	PredicateConstraint { Uph , Upl , Upa , Invalid }

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
	STATISTIC (NumShiftInserts, "Number of vector shift inserts")
	STATISTIC (NumOptimizedImms, "Number of times immediates were optimized")
static EVT	getPackedSVEVectorVT (EVT VT)
static EVT	getPackedSVEVectorVT (ElementCount EC)
static EVT	getPromotedVTForPredicate (EVT VT)
static bool	isPackedVectorType (EVT VT, SelectionDAG &DAG)
	Returns true if VT's elements occupy the lowest bit positions of its associated register class without any intervening space.
static bool	isMergePassthruOpcode (unsigned Opc)
static bool	isZeroingInactiveLanes (SDValue Op)
static bool	isIntImmediate (const SDNode *N, uint64_t &Imm)
static bool	isOpcWithIntImmediate (const SDNode *N, unsigned Opc, uint64_t &Imm)
static bool	optimizeLogicalImm (SDValue Op, unsigned Size, uint64_t Imm, const APInt &Demanded, TargetLowering::TargetLoweringOpt &TLO, unsigned NewOpc)
static EVT	getContainerForFixedLengthVector (SelectionDAG &DAG, EVT VT)
static SDValue	convertToScalableVector (SelectionDAG &DAG, EVT VT, SDValue V)
static SDValue	convertFromScalableVector (SelectionDAG &DAG, EVT VT, SDValue V)
static SDValue	convertFixedMaskToScalableVector (SDValue Mask, SelectionDAG &DAG)
static SDValue	getPredicateForScalableVector (SelectionDAG &DAG, SDLoc &DL, EVT VT)
static bool	isZerosVector (const SDNode *N)
	isZerosVector - Check whether SDNode N is a zero-filled vector.
static AArch64CC::CondCode	changeIntCCToAArch64CC (ISD::CondCode CC)
	changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC
static void	changeFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
	changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
static void	changeFPCCToANDAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
	Convert a DAG fp condition code to an AArch64 CC.
static void	changeVectorFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)
	changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions.
static bool	isLegalArithImmed (uint64_t C)
static bool	isCMN (SDValue Op, ISD::CondCode CC)
static SDValue	emitStrictFPComparison (SDValue LHS, SDValue RHS, const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, bool IsSignaling)
static SDValue	emitComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
static unsigned	getCmpOperandFoldingProfit (SDValue Op)
	Returns how profitable it is to fold a comparison's operand's shift and/or extension operations.
static SDValue	getAArch64Cmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl)
static std::pair< SDValue, SDValue >	getAArch64XALUOOp (AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG)
static SDValue	valueToCarryFlag (SDValue Value, SelectionDAG &DAG, bool Invert)
static SDValue	carryFlagToValue (SDValue Glue, EVT VT, SelectionDAG &DAG, bool Invert)
static SDValue	overflowFlagToValue (SDValue Glue, EVT VT, SelectionDAG &DAG)
static SDValue	lowerADDSUBO_CARRY (SDValue Op, SelectionDAG &DAG, unsigned Opcode, bool IsSigned)
static SDValue	LowerXALUO (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerPREFETCH (SDValue Op, SelectionDAG &DAG)
static MVT	getSVEContainerType (EVT ContentTy)
static EVT	getExtensionTo64Bits (const EVT &OrigVT)
static SDValue	addRequiredExtensionForVectorMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
static std::optional< uint64_t >	getConstantLaneNumOfExtractHalfOperand (SDValue &Op)
static bool	isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
static SDValue	skipExtensionForVectorMULL (SDNode *N, SelectionDAG &DAG)
static bool	isSignExtended (SDNode *N, SelectionDAG &DAG)
static bool	isZeroExtended (SDNode *N, SelectionDAG &DAG)
static bool	isAddSubSExt (SDNode *N, SelectionDAG &DAG)
static bool	isAddSubZExt (SDNode *N, SelectionDAG &DAG)
static unsigned	selectUmullSmull (SDNode *&N0, SDNode *&N1, SelectionDAG &DAG, SDLoc DL, bool &IsMLA)
static SDValue	getPTrue (SelectionDAG &DAG, SDLoc DL, EVT VT, int Pattern)
static SDValue	optimizeWhile (SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsLess, bool IsEqual)
static SDValue	getSVEPredicateBitCast (EVT VT, SDValue Op, SelectionDAG &DAG)
unsigned	getGatherVecOpcode (bool IsScaled, bool IsSigned, bool NeedsExtend)
unsigned	getSignExtendedGatherOpcode (unsigned Opcode)
static SDValue	LowerTruncateVectorStore (SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG)
static SDValue	LowerBRCOND (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFunnelShift (SDValue Op, SelectionDAG &DAG)
static unsigned	getIntrinsicID (const SDNode *N)
static bool	canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls)
	Return true if the calling convention is one that we can guarantee TCO for.
static bool	mayTailCallThisCC (CallingConv::ID CC)
	Return true if we might ever do TCO for calls with this calling convention.
static void	analyzeCallOperands (const AArch64TargetLowering &TLI, const AArch64Subtarget *Subtarget, const TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo)
static bool	checkZExtBool (SDValue Arg, const SelectionDAG &DAG)
std::pair< SDValue, uint64_t >	lookThroughSignExtension (SDValue Val)
static bool	isOrXorChain (SDValue N, unsigned &Num, SmallVector< std::pair< SDValue, SDValue >, 16 > &WorkList)
static SDValue	performOrXorChainCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	getEstimate (const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps)
static PredicateConstraint	parsePredicateConstraint (StringRef Constraint)
static const TargetRegisterClass *	getPredicateRegisterClass (PredicateConstraint Constraint, EVT VT)
static AArch64CC::CondCode	parseConstraintCode (llvm::StringRef Constraint)
static SDValue	getSETCC (AArch64CC::CondCode CC, SDValue NZCV, const SDLoc &DL, SelectionDAG &DAG)
	Helper function to create 'CSET', which is equivalent to 'CSINC <Wd>, WZR, WZR, invert(<cond>)'.
static SDValue	WidenVector (SDValue V64Reg, SelectionDAG &DAG)
	WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class.
static unsigned	getExtFactor (SDValue &V)
	getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.
SDValue	ReconstructShuffleWithRuntimeMask (SDValue Op, SelectionDAG &DAG)
static bool	isSingletonEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
static SDValue	ReconstructTruncateFromBuildVector (SDValue V, SelectionDAG &DAG)
static bool	isWideDUPMask (ArrayRef< int > M, EVT VT, unsigned BlockSize, unsigned &DupLaneOp)
	Check if a vector shuffle corresponds to a DUP instructions with a larger element width than the vector lane type.
static bool	isEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm)
static bool	isREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize)
	isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.
static bool	isZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isINSMask (ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly)
static bool	isConcatMask (ArrayRef< int > Mask, EVT VT, bool SplitLHS)
static SDValue	tryFormConcatFromShuffle (SDValue Op, SelectionDAG &DAG)
static SDValue	GeneratePerfectShuffle (unsigned ID, SDValue V1, SDValue V2, unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
static SDValue	GenerateTBL (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static unsigned	getDUPLANEOp (EVT EltType)
static SDValue	constructDup (SDValue V, int Lane, SDLoc dl, EVT VT, unsigned Opcode, SelectionDAG &DAG)
static bool	isWideTypeMask (ArrayRef< int > M, EVT VT, SmallVectorImpl< int > &NewMask)
static SDValue	tryWidenMaskForShuffle (SDValue Op, SelectionDAG &DAG)
static SDValue	tryToConvertShuffleOfTbl2ToTbl4 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static bool	resolveBuildVector (BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits)
static SDValue	tryAdvSIMDModImm64 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
static SDValue	tryAdvSIMDModImm32 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr)
static SDValue	tryAdvSIMDModImm16 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr)
static SDValue	tryAdvSIMDModImm321s (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
static SDValue	tryAdvSIMDModImm8 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
static SDValue	tryAdvSIMDModImmFP (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
static bool	isAllConstantBuildVector (const SDValue &PotentialBVec, uint64_t &ConstVal)
static SDValue	tryLowerToSLI (SDNode *N, SelectionDAG &DAG)
static SDValue	NormalizeBuildVector (SDValue Op, SelectionDAG &DAG)
static SDValue	ConstantBuildVector (SDValue Op, SelectionDAG &DAG)
static bool	isPow2Splat (SDValue Op, uint64_t &SplatVal, bool &Negated)
static bool	getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
	getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
static bool	isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
	isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
static bool	isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt)
	isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
static SDValue	EmitVectorComparison (SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	getReductionSDNode (unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG)
static SDValue	getVectorBitwiseReduce (unsigned Opcode, SDValue Vec, EVT VT, SDLoc DL, SelectionDAG &DAG)
template<unsigned NumVecs>
static bool	setInfoSVEStN (const AArch64TargetLowering &TLI, const DataLayout &DL, AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI)
	Set the IntrinsicInfo for the aarch64_sve_st<N> intrinsics.
static bool	isSplatShuffle (Value *V)
static bool	areExtractShuffleVectors (Value *Op1, Value *Op2, bool AllowSplat=false)
	Check if both Op1 and Op2 are shufflevector extracts of either the lower or upper half of the vector elements.
static bool	areExtractExts (Value *Ext1, Value *Ext2)
	Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.
static bool	isOperandOfVmullHighP64 (Value *Op)
	Check if Op could be used with vmull_high_p64 intrinsic.
static bool	areOperandsOfVmullHighP64 (Value *Op1, Value *Op2)
	Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic.
static bool	createTblShuffleForZExt (ZExtInst *ZExt, FixedVectorType *DstTy, bool IsLittleEndian)
static void	createTblForTrunc (TruncInst *TI, bool IsLittleEndian)
static ScalableVectorType *	getSVEContainerIRType (FixedVectorType *VTy)
static Function *	getStructuredLoadFunction (Module *M, unsigned Factor, bool Scalable, Type *LDVTy, Type *PtrTy)
static Function *	getStructuredStoreFunction (Module *M, unsigned Factor, bool Scalable, Type *STVTy, Type *PtrTy)
static SDValue	foldVectorXorShiftIntoCmp (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
	Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0.
static SDValue	performVecReduceAddCombineWithUADDLP (SDNode *N, SelectionDAG &DAG)
static SDValue	performVecReduceAddCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *ST)
static SDValue	performUADDVAddCombine (SDValue A, SelectionDAG &DAG)
static SDValue	performUADDVCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performXorCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static std::optional< unsigned >	IsSVECntIntrinsic (SDValue S)
static EVT	calculatePreExtendType (SDValue Extend)
	Calculates what the pre-extend type is, based on the extension operation node provided by Extend.
static SDValue	performBuildShuffleExtendCombine (SDValue BV, SelectionDAG &DAG)
	Combines a buildvector(sext/zext) or shuffle(sext/zext, undef) node pattern into sext/zext(buildvector) or sext/zext(shuffle) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt.
static SDValue	performMulVectorExtendCombine (SDNode *Mul, SelectionDAG &DAG)
	Combines a mul(dup(sext/zext)) node pattern into mul(sext/zext(dup)) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt.
static SDValue	performMulVectorCmpZeroCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performIntToFpCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performFpToIntCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
	Fold a floating-point multiply by power of two into floating-point to fixed-point conversion.
static SDValue	performFDivCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
	Fold a floating-point divide by power of two into fixed-point to floating-point conversion.
static SDValue	tryCombineToBSL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64TargetLowering &TLI)
static SDValue	performANDORCSELCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static bool	isConstantSplatVectorMaskForType (SDNode *N, EVT MemVT)
static bool	isAllInactivePredicate (SDValue N)
static bool	isAllActivePredicate (SelectionDAG &DAG, SDValue N)
static SDValue	performReinterpretCastCombine (SDNode *N)
static SDValue	performSVEAndCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performANDSETCCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performFADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool	hasPairwiseAdd (unsigned Opcode, EVT VT, bool FullFP16)
static SDValue	getPTest (SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, AArch64CC::CondCode Cond)
static bool	isPredicateCCSettingOp (SDValue N)
static SDValue	performFirstTrueTestVectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performLastTrueTestVectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performExtractVectorEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performConcatVectorsCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performExtractSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryCombineFixedPointConvert (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryExtendDUPToExtractHigh (SDValue N, SelectionDAG &DAG)
static bool	isEssentiallyExtractHighSubvector (SDValue N)
static bool	isSetCC (SDValue Op, SetCCInfoAndKind &SetCCInfo)
	Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one.
static bool	isSetCCOrZExtSetCC (const SDValue &Op, SetCCInfoAndKind &Info)
static SDValue	performSetccAddFolding (SDNode *Op, SelectionDAG &DAG)
static SDValue	performAddUADDVCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performAddCSelIntoCSinc (SDNode *N, SelectionDAG &DAG)
	Perform the scalar expression combine in the form of: CSEL(c, 1, cc) + b => CSINC(b+c, b, cc) CSNEG(c, -1, cc) + b => CSINC(b+c, b, cc)
static SDValue	performAddDotCombine (SDNode *N, SelectionDAG &DAG)
static bool	isNegatedInteger (SDValue Op)
static SDValue	getNegatedInteger (SDValue Op, SelectionDAG &DAG)
static SDValue	performNegCSelCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performAddSubLongCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool	isCMP (SDValue Op)
static std::optional< AArch64CC::CondCode >	getCSETCondCode (SDValue Op)
static SDValue	foldOverflowCheck (SDNode *Op, SelectionDAG &DAG, bool IsAdd)
static SDValue	foldADCToCINC (SDNode *N, SelectionDAG &DAG)
static SDValue	performVectorAddSubExtCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performBuildVectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performTruncateCombine (SDNode *N, SelectionDAG &DAG)
static bool	isExtendOrShiftOperand (SDValue N)
static SDValue	performAddCombineSubShift (SDNode *N, SDValue SUB, SDValue Z, SelectionDAG &DAG)
static SDValue	performAddCombineForShiftedOperands (SDNode *N, SelectionDAG &DAG)
static SDValue	performSubAddMULCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performSVEMulAddSubCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performAddSubIntoVectorOp (SDNode *N, SelectionDAG &DAG)
static bool	isLoadOrMultipleLoads (SDValue B, SmallVector< LoadSDNode * > &Loads)
static bool	areLoadedOffsetButOtherwiseSame (SDValue Op0, SDValue Op1, SelectionDAG &DAG, unsigned &NumSubLoads)
static SDValue	performExtBinopLoadFold (SDNode *N, SelectionDAG &DAG)
static SDValue	performAddSubCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	tryCombineLongOpWithDup (unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryCombineShiftImm (unsigned IID, SDNode *N, SelectionDAG &DAG)
static SDValue	tryCombineCRC32 (unsigned Mask, SDNode *N, SelectionDAG &DAG)
static SDValue	combineAcrossLanesIntrinsic (unsigned Opc, SDNode *N, SelectionDAG &DAG)
static SDValue	LowerSVEIntrinsicIndex (SDNode *N, SelectionDAG &DAG)
static SDValue	LowerSVEIntrinsicDUP (SDNode *N, SelectionDAG &DAG)
static SDValue	LowerSVEIntrinsicEXT (SDNode *N, SelectionDAG &DAG)
static SDValue	tryConvertSVEWideCompare (SDNode *N, ISD::CondCode CC, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	combineSVEReductionInt (SDNode *N, unsigned Opc, SelectionDAG &DAG)
static SDValue	combineSVEReductionFP (SDNode *N, unsigned Opc, SelectionDAG &DAG)
static SDValue	combineSVEReductionOrderedFP (SDNode *N, unsigned Opc, SelectionDAG &DAG)
static SDValue	convertMergedOpToPredOp (SDNode *N, unsigned Opc, SelectionDAG &DAG, bool UnpredOp=false, bool SwapOperands=false)
static SDValue	performIntrinsicCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static bool	isCheapToExtend (const SDValue &N)
static SDValue	performSignExtendSetCCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	splitStoreSplat (SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts)
static SDValue	performLD1Combine (SDNode *N, SelectionDAG &DAG, unsigned Opc)
static SDValue	performLDNT1Combine (SDNode *N, SelectionDAG &DAG)
template<unsigned Opcode>
static SDValue	performLD1ReplicateCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performST1Combine (SDNode *N, SelectionDAG &DAG)
static SDValue	performSTNT1Combine (SDNode *N, SelectionDAG &DAG)
static SDValue	replaceZeroVectorStore (SelectionDAG &DAG, StoreSDNode &St)
	Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.
static SDValue	replaceSplatVectorStore (SelectionDAG &DAG, StoreSDNode &St)
	Replace a splat of a scalar to a vector store by scalar stores of the scalar value.
static SDValue	splitStores (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performSpliceCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performUnpackCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	trySimplifySrlAddToRshrnb (SDValue Srl, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performUzpCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performGLD1Combine (SDNode *N, SelectionDAG &DAG)
static SDValue	performVectorShiftCombine (SDNode *N, const AArch64TargetLowering &TLI, TargetLowering::DAGCombinerInfo &DCI)
	Optimize a vector shift instruction and its operand if shifted out bits are not used.
static SDValue	performSunpkloCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performPostLD1Combine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp)
	Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R.
static bool	performTBISimplification (SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
	Simplify Addr given that the top byte of it is ignored by HW during address translation.
static SDValue	foldTruncStoreOfExt (SelectionDAG &DAG, SDNode *N)
static SDValue	performLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static EVT	tryGetOriginalBoolVectorType (SDValue Op, int Depth=0)
static SDValue	vectorToScalarBitmask (SDNode *N, SelectionDAG &DAG)
static SDValue	combineBoolVectorAndTruncateStore (SelectionDAG &DAG, StoreSDNode *Store)
static SDValue	performSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performMSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static bool	foldIndexIntoBase (SDValue &BasePtr, SDValue &Index, SDValue Scale, SDLoc DL, SelectionDAG &DAG)
static bool	findMoreOptimalIndexType (const MaskedGatherScatterSDNode *N, SDValue &BasePtr, SDValue &Index, SelectionDAG &DAG)
static SDValue	performMaskedGatherScatterCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performNEONPostLDSTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
	Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.
static bool	checkValueWidth (SDValue V, unsigned width, ISD::LoadExtType &ExtType)
static bool	isEquivalentMaskless (unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant)
static SDValue	performSubsToAndsCombine (SDNode *N, SDNode *SubsNode, SDNode *AndNode, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex, unsigned CC)
static SDValue	performCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex)
static SDValue	performBRCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	foldCSELofCTTZ (SDNode *N, SelectionDAG &DAG)
static SDValue	foldCSELOfCSEL (SDNode *Op, SelectionDAG &DAG)
static SDValue	performCSELCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryToWidenSetCCOperands (SDNode *Op, SelectionDAG &DAG)
static SDValue	performVecReduceBitwiseCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performSETCCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performFlagSettingCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, unsigned GenericOpcode)
static SDValue	performSetCCPunpkCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performSetccMergeZeroCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	getTestBitOperand (SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG)
static SDValue	performTBZCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	trySwapVSelectOperands (SDNode *N, SelectionDAG &DAG)
static SDValue	performVSelectCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performSelectCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar.
static SDValue	performDUPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performNVCASTCombine (SDNode *N)
	Get rid of unnecessary NVCASTs (that don't change the type).
static SDValue	performGlobalAddressCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM)
static SDValue	performCTLZCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	getScaledOffsetForBitWidth (SelectionDAG &DAG, SDValue Offset, SDLoc DL, unsigned BitWidth)
static bool	isValidImmForSVEVecImmAddrMode (unsigned OffsetInBytes, unsigned ScalarSizeInBytes)
	Check if the value of OffsetInBytes can be used as an immediate for the gather load/prefetch and scatter store instructions with vector base and immediate offset addressing mode:
static bool	isValidImmForSVEVecImmAddrMode (SDValue Offset, unsigned ScalarSizeInBytes)
	Check if the value of Offset represents a valid immediate for the SVE gather load/prefetch and scatter store instructiona with vector base and immediate offset addressing mode:
static SDValue	performScatterStoreCombine (SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets=true)
static SDValue	performGatherLoadCombine (SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets=true)
static SDValue	performSignExtendInRegCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	legalizeSVEGatherPrefetchOffsVec (SDNode *N, SelectionDAG &DAG)
	Legalize the gather prefetch (scalar + vector addressing mode) when the offset vector is an unpacked 32-bit scalable vector.
static SDValue	combineSVEPrefetchVecBaseImmOff (SDNode *N, SelectionDAG &DAG, unsigned ScalarSizeInBytes)
	Combines a node carrying the intrinsic aarch64_sve_prf<T>_gather_scalar_offset into a node that uses aarch64_sve_prfb_gather_uxtw_index when the scalar offset passed to aarch64_sve_prf<T>_gather_scalar_offset is not a valid immediate for the sve gather prefetch instruction with vector plus immediate addressing mode.
static bool	isLanes1toNKnownZero (SDValue Op)
static SDValue	removeRedundantInsertVectorElt (SDNode *N)
static SDValue	performInsertVectorEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performSVESpliceCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performFPExtendCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performBSPExpandForSVE (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performDupLane128Combine (SDNode *N, SelectionDAG &DAG)
static SDValue	tryCombineMULLWithUZP1 (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performMULLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performScalarToVectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static void	replaceBoolVectorBitcast (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static void	CustomNonLegalBITCASTResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, EVT ExtendVT, EVT CastVT)
static void	ReplaceAddWithADDP (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static void	ReplaceReductionResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp)
static SDValue	createGPRPairNode (SelectionDAG &DAG, SDValue V)
static void	ReplaceCMP_SWAP_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static unsigned	getAtomicLoad128Opcode (unsigned ISDOpcode, AtomicOrdering Ordering)
static void	ReplaceATOMIC_LOAD_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static Value *	UseTlsOffset (IRBuilderBase &IRB, unsigned Offset)
static SDValue	getPredicateForFixedLengthVector (SelectionDAG &DAG, SDLoc &DL, EVT VT)
static SDValue	getPredicateForVector (SelectionDAG &DAG, SDLoc &DL, EVT VT)
static SDValue	emitConditionalComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG)
	can be transformed to: not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" which can be implemented as: cmp C ccmp D, inv(CD), CC ccmp A, CA, inv(CD) ccmp B, CB, inv(CA) check for CB flags
static bool	canEmitConjunction (const SDValue Val, bool &CanNegate, bool &MustBeFirst, bool WillNegate, unsigned Depth=0)
	Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction.
static SDValue	emitConjunctionRec (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate)
	Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops.
static SDValue	emitConjunction (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC)
	Emit expression as a conjunction (a series of CCMP/CFCMP ops).

Variables
cl::opt< bool >	EnableAArch64ELFLocalDynamicTLSGeneration ("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false))
static cl::opt< bool >	EnableOptimizeLogicalImm ("aarch64-enable-logical-imm", cl::Hidden, cl::desc("Enable AArch64 logical imm instruction " "optimization"), cl::init(true))
static cl::opt< bool >	EnableCombineMGatherIntrinsics ("aarch64-enable-mgather-combine", cl::Hidden, cl::desc("Combine extends of AArch64 masked " "gather intrinsics"), cl::init(true))
static cl::opt< unsigned >	MaxXors ("aarch64-max-xors", cl::init(16), cl::Hidden, cl::desc("Maximum of xors"))
static const MVT	MVT_CC = MVT::i32
	Value type used for condition codes.
static const MCPhysReg	GPRArgRegs []
static const MCPhysReg	FPRArgRegs []

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-lower"

Definition at line 104 of file AArch64ISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 9775 of file AArch64ISelLowering.cpp.

LCALLNAME4

#define LCALLNAME4	(		A,
			B
	)

Value:

  LCALLNAMES(A, B, 1)                                                          \
  LCALLNAMES(A, B, 2) LCALLNAMES(A, B, 4) LCALLNAMES(A, B, 8)

LCALLNAME5

#define LCALLNAME5	(		A,
			B
	)

Value:

  LCALLNAMES(A, B, 1)                                                          \
  LCALLNAMES(A, B, 2)                                                          \
  LCALLNAMES(A, B, 4) LCALLNAMES(A, B, 8) LCALLNAMES(A, B, 16)

LCALLNAMES

#define LCALLNAMES	(		A,
			B,
			N
	)

Value:

  setLibcallName(A##N##_RELAX, #B #N "_relax");                                \
  setLibcallName(A##N##_ACQ, #B #N "_acq");                                    \
  setLibcallName(A##N##_REL, #B #N "_rel");                                    \
  setLibcallName(A##N##_ACQ_REL, #B #N "_acq_rel");

MAKE_CASE

#define MAKE_CASE

(

V

)

Value:

  case V:                                                                      \
    return #V;

Enumeration Type Documentation

PredicateConstraint

enum PredicateConstraint

Enumerator
Uph
Upl
Upa
Invalid

Definition at line 10055 of file AArch64ISelLowering.cpp.

Function Documentation

addRequiredExtensionForVectorMULL()

static SDValue addRequiredExtensionForVectorMULL ( SDValue  N, SelectionDAG &  DAG, const EVT &  OrigTy, const EVT &  ExtTy, unsigned  ExtOpcode  )

static

Definition at line 4365 of file AArch64ISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.

Referenced by skipExtensionForVectorMULL().

analyzeCallOperands()

static void analyzeCallOperands ( const AArch64TargetLowering &  TLI, const AArch64Subtarget *  Subtarget, const TargetLowering::CallLoweringInfo &  CLI, CCState &  CCInfo  )

static

Definition at line 6963 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::CallLoweringInfo::Args, assert(), llvm::TargetLowering::CallLoweringInfo::CallConv, llvm::AArch64TargetLowering::CCAssignFnForCall(), llvm::TargetLowering::CallLoweringInfo::DAG, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::getValueType(), llvm::AArch64Subtarget::isCallingConvWin64(), llvm::EVT::isSimple(), llvm::TargetLowering::CallLoweringInfo::IsVarArg, llvm::TargetLowering::CallLoweringInfo::Outs, and llvm::SmallVectorBase< Size_T >::size().

areExtractExts()

static bool areExtractExts ( Value *  Ext1, Value *  Ext2  )

static

Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.

Definition at line 14352 of file AArch64ISelLowering.cpp.

References llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().

Referenced by llvm::AArch64TargetLowering::shouldSinkOperands(), and llvm::ARMTargetLowering::shouldSinkOperands().

areExtractShuffleVectors()

static bool areExtractShuffleVectors ( Value *  Op1, Value *  Op2, bool  AllowSplat = false  )

static

Check if both Op1 and Op2 are shufflevector extracts of either the lower or upper half of the vector elements.

Definition at line 14296 of file AArch64ISelLowering.cpp.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::ShuffleVectorInst::isExtractSubvectorMask(), isSplatShuffle(), llvm::M1(), llvm::PatternMatch::m_Shuffle(), llvm::PatternMatch::m_Undef(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().

Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().

areLoadedOffsetButOtherwiseSame()

static bool areLoadedOffsetButOtherwiseSame ( SDValue  Op0, SDValue  Op1, SelectionDAG &  DAG, unsigned &  NumSubLoads  )

static

Definition at line 18741 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::all_of(), llvm::ISD::ANY_EXTEND, areLoadedOffsetButOtherwiseSame(), llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), isLoadOrMultipleLoads(), llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase< Size_T >::size(), Size, llvm::ISD::SUB, llvm::ISD::ZERO_EXTEND, and llvm::zip().

Referenced by areLoadedOffsetButOtherwiseSame(), and performExtBinopLoadFold().

areOperandsOfVmullHighP64()

static bool areOperandsOfVmullHighP64 ( Value *  Op1, Value *  Op2  )

static

Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic.

Definition at line 14379 of file AArch64ISelLowering.cpp.

References isOperandOfVmullHighP64().

Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().

calculatePreExtendType()

static EVT calculatePreExtendType ( SDValue  Extend )

static

Calculates what the pre-extend type is, based on the extension operation node provided by Extend.

In the case that Extend is a SIGN_EXTEND or a ZERO_EXTEND, the pre-extend type is pulled directly from the operand, while other extend operations need a bit more inspection to get this information.

Parameters

Extend

The SDNode from the DAG that represents the extend operation

Returns

The type representing the Extend source type, or MVT::Other if no valid type can be determined

Definition at line 16244 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::VTSDNode::getVT(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::ZERO_EXTEND.

Referenced by performBuildShuffleExtendCombine().

canEmitConjunction()

static bool canEmitConjunction ( const SDValue  Val, bool &  CanNegate, bool &  MustBeFirst, bool  WillNegate, unsigned  Depth = 0  )

static

Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction.

See CMP;CCMP matching.

Parameters

CanNegate	Set to true if we can negate the whole sub-tree just by changing the conditions on the SETCC tests. (this means we can call emitConjunctionRec() with Negate==true on this sub-tree)
MustBeFirst	Set to true if this subtree needs to be negated and we cannot do the negation naturally. We are required to emit the subtree first in this case.
WillNegate	Is true if are called when the result of this subexpression must be negated. This happens when the outer expression is an OR. We can use this fact to know that we have a double negation (or (or ...) ...) that can be implemented for free.

Definition at line 3230 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, assert(), canEmitConjunction(), llvm::Depth, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::OR, and llvm::ISD::SETCC.

Referenced by canEmitConjunction(), emitConjunction(), and emitConjunctionRec().

canGuaranteeTCO()

static bool canGuaranteeTCO ( CallingConv::ID  CC, bool  GuaranteeTailCalls  )

static

Return true if the calling convention is one that we can guarantee TCO for.

Definition at line 6941 of file AArch64ISelLowering.cpp.

References CC, llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.

Referenced by llvm::AArch64CallLowering::isEligibleForTailCallOptimization(), llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), mayTailCallThisCC(), and shouldGuaranteeTCO().

carryFlagToValue()

static SDValue carryFlagToValue ( SDValue  Glue, EVT  VT, SelectionDAG &  DAG, bool  Invert  )

static

Definition at line 3772 of file AArch64ISelLowering.cpp.

References assert(), CC, Cond, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getResNo(), llvm::AArch64CC::HS, and llvm::AArch64CC::LO.

Referenced by lowerADDSUBO_CARRY().

changeFPCCToAArch64CC()

static void changeFPCCToAArch64CC ( ISD::CondCode  CC, AArch64CC::CondCode &  CondCode, AArch64CC::CondCode &  CondCode2  )

static

changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.

Definition at line 2910 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, CC, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by changeFPCCToANDAArch64CC(), and changeVectorFPCCToAArch64CC().

changeFPCCToANDAArch64CC()

static void changeFPCCToANDAArch64CC ( ISD::CondCode  CC, AArch64CC::CondCode &  CondCode, AArch64CC::CondCode &  CondCode2  )

static

Convert a DAG fp condition code to an AArch64 CC.

This differs from changeFPCCToAArch64CC in that it returns cond codes that should be AND'ed instead of OR'ed.

Definition at line 2973 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, assert(), CC, changeFPCCToAArch64CC(), llvm::AArch64CC::LE, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETONE, llvm::ISD::SETUEQ, and llvm::AArch64CC::VC.

Referenced by emitConjunctionRec().

changeIntCCToAArch64CC()

static AArch64CC::CondCode changeIntCCToAArch64CC ( ISD::CondCode  CC )

static

changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC

Definition at line 2882 of file AArch64ISelLowering.cpp.

References CC, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by emitConjunctionRec(), and getAArch64Cmp().

changeVectorFPCCToAArch64CC()

static void changeVectorFPCCToAArch64CC ( ISD::CondCode  CC, AArch64CC::CondCode &  CondCode, AArch64CC::CondCode &  CondCode2, bool &  Invert  )

static

changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions.

Fewer operations are available without a real NZCV register, so we have to use less efficient combinations to get the same effect.

Definition at line 3003 of file AArch64ISelLowering.cpp.

References CC, changeFPCCToAArch64CC(), llvm::AArch64CC::GE, llvm::AArch64CC::MI, llvm::ISD::SETO, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.

checkValueWidth()

static bool checkValueWidth ( SDValue  V, unsigned  width, ISD::LoadExtType &  ExtType  )

static

Definition at line 21256 of file AArch64ISelLowering.cpp.

References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::Constant, llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::VTSDNode::getVT(), llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::TargetConstant, and llvm::ISD::ZEXTLOAD.

Referenced by performCONDCombine().

checkZExtBool()

static bool checkZExtBool ( SDValue  Arg, const SelectionDAG &  DAG  )

static

Definition at line 7203 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::EVT::getSizeInBits(), and llvm::SDValue::getValueType().

combineAcrossLanesIntrinsic()

static SDValue combineAcrossLanesIntrinsic ( unsigned  Opc, SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19084 of file AArch64ISelLowering.cpp.

References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and N.

Referenced by performIntrinsicCombine().

combineBoolVectorAndTruncateStore()

static SDValue combineBoolVectorAndTruncateStore ( SelectionDAG &  DAG, StoreSDNode *  Store  )

static

Definition at line 20828 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::EVT::isVector(), llvm::ISD::TRUNCATE, and vectorToScalarBitmask().

Referenced by performSTORECombine().

combineSVEPrefetchVecBaseImmOff()

static SDValue combineSVEPrefetchVecBaseImmOff ( SDNode *  N, SelectionDAG &  DAG, unsigned  ScalarSizeInBytes  )

static

Combines a node carrying the intrinsic aarch64_sve_prf<T>_gather_scalar_offset into a node that uses aarch64_sve_prfb_gather_uxtw_index when the scalar offset passed to aarch64_sve_prf<T>_gather_scalar_offset is not a valid immediate for the sve gather prefetch instruction with vector plus immediate addressing mode.

Definition at line 22788 of file AArch64ISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), isValidImmForSVEVecImmAddrMode(), N, and std::swap().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

combineSVEReductionFP()

static SDValue combineSVEReductionFP ( SDNode *  N, unsigned  Opc, SelectionDAG &  DAG  )

static

Definition at line 19271 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), and N.

Referenced by performIntrinsicCombine().

combineSVEReductionInt()

static SDValue combineSVEReductionInt ( SDNode *  N, unsigned  Opc, SelectionDAG &  DAG  )

static

Definition at line 19252 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getPackedSVEVectorVT(), and N.

Referenced by performIntrinsicCombine().

combineSVEReductionOrderedFP()

static SDValue combineSVEReductionOrderedFP ( SDNode *  N, unsigned  Opc, SelectionDAG &  DAG  )

static

Definition at line 19288 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, and N.

Referenced by performIntrinsicCombine().

ConstantBuildVector()

static SDValue ConstantBuildVector ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 12406 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::FMOV, llvm::EVT::getSizeInBits(), llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, resolveBuildVector(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), and tryAdvSIMDModImmFP().

constructDup()

static SDValue constructDup ( SDValue  V, int  Lane, SDLoc  dl, EVT  VT, unsigned  Opcode, SelectionDAG &  DAG  )

static

Definition at line 11538 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), Idx, llvm::EVT::is128BitVector(), and WidenVector().

convertFixedMaskToScalableVector()

static SDValue convertFixedMaskToScalableVector ( SDValue  Mask, SelectionDAG &  DAG  )

static

Definition at line 25115 of file AArch64ISelLowering.cpp.

References convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getNode(), getPredicateForFixedLengthVector(), llvm::SDValue::getValueType(), llvm::ISD::isBuildVectorAllOnes(), and llvm::AArch64ISD::SETCC_MERGE_ZERO.

convertFromScalableVector()

static SDValue convertFromScalableVector ( SelectionDAG &  DAG, EVT  VT, SDValue  V  )

static

Definition at line 25065 of file AArch64ISelLowering.cpp.

References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::EVT::isFixedLengthVector().

Referenced by convertLocVTToValVT(), getDeinterleaveViaVNSRL(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performFP_TO_INTCombine(), and performSVEMulAddSubCombine().

convertMergedOpToPredOp()

static SDValue convertMergedOpToPredOp ( SDNode *  N, unsigned  Opc, SelectionDAG &  DAG, bool  UnpredOp = false, bool  SwapOperands = false  )

static

Definition at line 19314 of file AArch64ISelLowering.cpp.

References assert(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, isAllActivePredicate(), and N.

Referenced by performIntrinsicCombine().

convertToScalableVector()

static SDValue convertToScalableVector ( SelectionDAG &  DAG, EVT  VT, SDValue  V  )

static

Definition at line 25054 of file AArch64ISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_SUBVECTOR, and llvm::EVT::isScalableVector().

Referenced by convertFixedMaskToScalableVector(), convertValVTToLocVT(), getDeinterleaveViaVNSRL(), getWideningInterleave(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarInsert(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performFP_TO_INTCombine(), performSVEMulAddSubCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

createGPRPairNode()

static SDValue createGPRPairNode ( SelectionDAG &  DAG, SDValue  V  )

static

Definition at line 23838 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::DataLayout::isBigEndian(), llvm::ISD::SRL, and std::swap().

Referenced by ReplaceCMP_SWAP_128Results(), and ReplaceCMP_SWAP_64Results().

createTblForTrunc()

static void createTblForTrunc ( TruncInst *  TI, bool  IsLittleEndian  )

static

Definition at line 14671 of file AArch64ISelLowering.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), Builder, llvm::SmallVectorImpl< T >::clear(), llvm::SmallVectorBase< Size_T >::empty(), llvm::Function::empty(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::Instruction::eraseFromParent(), F, llvm::ConstantVector::get(), llvm::FixedVectorType::get(), llvm::Intrinsic::getDeclaration(), llvm::Instruction::getModule(), llvm::User::getOperand(), llvm::Value::getType(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::Value::replaceAllUsesWith(), Results, llvm::SmallVectorBase< Size_T >::size(), and llvm::Function::size().

Referenced by llvm::AArch64TargetLowering::optimizeExtendOrTruncateConversion().

createTblShuffleForZExt()

static bool createTblShuffleForZExt ( ZExtInst *  ZExt, FixedVectorType *  DstTy, bool  IsLittleEndian  )

static

Definition at line 14627 of file AArch64ISelLowering.cpp.

References assert(), Builder, llvm::Instruction::eraseFromParent(), llvm::PoisonValue::get(), llvm::VectorType::getElementType(), llvm::User::getOperand(), llvm::Value::getType(), and llvm::Value::replaceAllUsesWith().

Referenced by llvm::AArch64TargetLowering::optimizeExtendOrTruncateConversion().

CustomNonLegalBITCASTResults()

static void CustomNonLegalBITCASTResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, EVT  ExtendVT, EVT  CastVT  )

static

Definition at line 23675 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), N, Results, and llvm::ISD::SCALAR_TO_VECTOR.

emitComparison()

static SDValue emitComparison ( SDValue  LHS, SDValue  RHS, ISD::CondCode  CC, const SDLoc &  dl, SelectionDAG &  DAG  )

static

Definition at line 3078 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADDS, llvm::ISD::AND, llvm::AArch64ISD::ANDS, assert(), CC, llvm::AArch64ISD::FCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), isCMN(), llvm::EVT::isFloatingPoint(), llvm::isNullConstant(), LHS, MVT_CC, llvm::SelectionDAG::ReplaceAllUsesWith(), RHS, and llvm::AArch64ISD::SUBS.

Referenced by emitConjunctionRec(), and getAArch64Cmp().

emitConditionalComparison()

static SDValue emitConditionalComparison ( SDValue  LHS, SDValue  RHS, ISD::CondCode  CC, SDValue  CCOp, AArch64CC::CondCode  Predicate, AArch64CC::CondCode  OutCC, const SDLoc &  DL, SelectionDAG &  DAG  )

static

can be transformed to: not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" which can be implemented as: cmp C ccmp D, inv(CD), CC ccmp A, CA, inv(CD) ccmp B, CB, inv(CA) check for CB flags

A counterexample is "or (and A B) (and C D)" which translates to not (and (not (and (not A) (not B))) (not (and (not C) (not D)))), we can only implement 1 of the inner (not) operations, but not both! Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.

Definition at line 3183 of file AArch64ISelLowering.cpp.

References assert(), CC, llvm::AArch64ISD::CCMN, llvm::AArch64ISD::CCMP, DL, llvm::AArch64ISD::FCCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::AArch64CC::getNZCVToSatisfyCondCode(), llvm::SelectionDAG::getSubtarget(), llvm::isNullConstant(), LHS, MVT_CC, RHS, llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.

Referenced by emitConjunctionRec().

emitConjunction()

static SDValue emitConjunction ( SelectionDAG &  DAG, SDValue  Val, AArch64CC::CondCode &  OutCC  )

static

Emit expression as a conjunction (a series of CCMP/CFCMP ops).

In some cases this is even possible with OR operations in the expression. See CMP;CCMP matching.

See also

emitConjunctionRec().

Definition at line 3404 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, canEmitConjunction(), and emitConjunctionRec().

Referenced by getAArch64Cmp(), LowerBRCOND(), and performANDSETCCCombine().

emitConjunctionRec()

static SDValue emitConjunctionRec ( SelectionDAG &  DAG, SDValue  Val, AArch64CC::CondCode &  OutCC, bool  Negate, SDValue  CCOp, AArch64CC::CondCode  Predicate  )

static

Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops.

See CMP;CCMP matching. Tries to transform the given i1 producing node Val to a series compare and conditional compare operations.

Returns

an NZCV flags producing node and sets OutCC to the flags that should be tested or returns SDValue() if transformation was not possible. Negate is true if we want this sub-tree being negated just by changing SETCC conditions.

Definition at line 3292 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, llvm::ISD::AND, assert(), canEmitConjunction(), CC, changeFPCCToANDAArch64CC(), changeIntCCToAArch64CC(), DL, emitComparison(), emitConditionalComparison(), emitConjunctionRec(), llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), LHS, llvm::ISD::OR, RHS, llvm::ISD::SETCC, and std::swap().

Referenced by emitConjunction(), and emitConjunctionRec().

emitStrictFPComparison()

static SDValue emitStrictFPComparison ( SDValue  LHS, SDValue  RHS, const SDLoc &  dl, SelectionDAG &  DAG, SDValue  Chain, bool  IsSignaling  )

static

Definition at line 3057 of file AArch64ISelLowering.cpp.

References assert(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), LHS, RHS, llvm::AArch64ISD::STRICT_FCMP, llvm::AArch64ISD::STRICT_FCMPE, and llvm::ISD::STRICT_FP_EXTEND.

EmitVectorComparison()

static SDValue EmitVectorComparison ( SDValue  LHS, SDValue  RHS, AArch64CC::CondCode  CC, bool  NoNans, EVT  VT, const SDLoc &  dl, SelectionDAG &  DAG  )

static

Definition at line 13394 of file AArch64ISelLowering.cpp.

References assert(), CC, llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::AArch64CC::EQ, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::AArch64CC::GE, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::EVT::isFloatingPoint(), llvm::AArch64CC::LE, LHS, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, resolveBuildVector(), and RHS.

findMoreOptimalIndexType()

static bool findMoreOptimalIndexType ( const MaskedGatherScatterSDNode *  N, SDValue &  BasePtr, SDValue &  Index, SelectionDAG &  DAG  )

static

Definition at line 21009 of file AArch64ISelLowering.cpp.

References llvm::EVT::changeVectorElementType(), foldIndexIntoBase(), llvm::SDValue::getConstantOperandVal(), llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getStepVector(), llvm::SelectionDAG::getSubtarget(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::isFixedLengthVector(), llvm::ISD::isVectorShrinkable(), N, RHS, llvm::ISD::SHL, llvm::ISD::STEP_VECTOR, llvm::AArch64::SVEBitsPerBlock, and llvm::ISD::TRUNCATE.

Referenced by performMaskedGatherScatterCombine().

foldADCToCINC()

static SDValue foldADCToCINC ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18343 of file AArch64ISelLowering.cpp.

References CC, Cond, llvm::AArch64ISD::CSINC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isNullConstant(), LHS, llvm::AArch64CC::LO, N, and RHS.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

foldCSELOfCSEL()

static SDValue foldCSELOfCSEL ( SDNode *  Op, SelectionDAG &  DAG  )

static

Definition at line 21671 of file AArch64ISelLowering.cpp.

References CC, Cond, llvm::AArch64ISD::CSEL, DL, llvm::AArch64CC::EQ, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), isCMP(), llvm::AArch64CC::NE, std::swap(), X, and Y.

Referenced by performCSELCombine().

foldCSELofCTTZ()

static SDValue foldCSELofCTTZ ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 21623 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::BitWidth, CC, llvm::ISD::CTTZ, llvm::AArch64CC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isNullConstant(), N, llvm::AArch64CC::NE, llvm::AArch64ISD::SUBS, llvm::ISD::TRUNCATE, and X.

Referenced by performCSELCombine().

foldIndexIntoBase()

static bool foldIndexIntoBase ( SDValue &  BasePtr, SDValue &  Index, SDValue  Scale, SDLoc  DL, SelectionDAG &  DAG  )

static

Returns

true if part of the index was folded into the Base.

Definition at line 20959 of file AArch64ISelLowering.cpp.

References llvm::Add, llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSplatValue(), llvm::EVT::getVectorElementType(), llvm::EVT::isVector(), llvm::ISD::MUL, llvm::Offset, and llvm::ISD::SHL.

Referenced by findMoreOptimalIndexType().

foldOverflowCheck()

static SDValue foldOverflowCheck ( SDNode *  Op, SelectionDAG &  DAG, bool  IsAdd  )

static

Definition at line 18319 of file AArch64ISelLowering.cpp.

References CC, getCSETCondCode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::AArch64CC::HS, isCMP(), llvm::isNullConstant(), llvm::isOneConstant(), and llvm::AArch64CC::LO.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

foldTruncStoreOfExt()

static SDValue foldTruncStoreOfExt ( SelectionDAG &  DAG, SDNode *  N  )

static

Definition at line 20620 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValueType(), llvm::ISD::MSTORE, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::STORE, and llvm::ISD::ZERO_EXTEND.

Referenced by performSTORECombine().

foldVectorXorShiftIntoCmp()

static SDValue foldVectorXorShiftIntoCmp ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0.

Definition at line 15827 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::CMGEz, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SDValue::hasOneUse(), llvm::ISD::isBuildVectorAllOnes(), llvm::EVT::isVector(), N, and llvm::AArch64ISD::VASHR.

Referenced by combineXor(), and performXorCombine().

GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle ( unsigned  ID, SDValue  V1, SDValue  V2, unsigned  PFEntry, SDValue  LHS, SDValue  RHS, SelectionDAG &  DAG, const SDLoc &  dl  )

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

ID is the perfect-shuffle

Definition at line 11290 of file AArch64ISelLowering.cpp.

References assert(), llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getExtFactor(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::ISD::INSERT_VECTOR_ELT, LHS, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, RHS, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.

Referenced by GeneratePerfectShuffle(), and LowerVECTOR_SHUFFLE().

GenerateTBL()

static SDValue GenerateTBL ( SDValue  Op, ArrayRef< int >  ShuffleMask, SelectionDAG &  DAG  )

static

Definition at line 11451 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorTemplateCommon< T, typename >::data(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::SDValue::isUndef(), isZerosVector(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and std::swap().

getAArch64Cmp()

static SDValue getAArch64Cmp ( SDValue  LHS, SDValue  RHS, ISD::CondCode  CC, SDValue &  AArch64cc, SelectionDAG &  DAG, const SDLoc &  dl  )

static

Definition at line 3452 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, CC, changeIntCCToAArch64CC(), emitComparison(), emitConjunction(), getCmpOperandFoldingProfit(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getValueType(), llvm::ConstantSDNode::getZExtValue(), INT64_MAX, isCMN(), isLegalArithImmed(), llvm::ConstantSDNode::isOne(), llvm::ConstantSDNode::isZero(), LHS, MVT_CC, RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND_INREG, std::swap(), UINT64_MAX, and llvm::ISD::ZEXTLOAD.

Referenced by performSetccAddFolding().

getAArch64XALUOOp()

static std::pair< SDValue, SDValue > getAArch64XALUOOp ( AArch64CC::CondCode &  CC, SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 3584 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADDS, llvm::AArch64ISD::ANDS, assert(), CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::AArch64CC::HS, LHS, llvm_unreachable, llvm::AArch64CC::LO, llvm::Mul, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, MVT_CC, llvm::AArch64CC::NE, RHS, llvm::ISD::SADDO, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SSUBO, llvm::AArch64ISD::SUBS, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::AArch64CC::VS, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerXALUO().

getAtomicLoad128Opcode()

static unsigned getAtomicLoad128Opcode ( unsigned  ISDOpcode, AtomicOrdering  Ordering  )

static

Definition at line 23943 of file AArch64ISelLowering.cpp.

References llvm::Acquire, llvm::AcquireRelease, assert(), llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_SWAP, llvm_unreachable, llvm::Monotonic, llvm::Release, and llvm::SequentiallyConsistent.

Referenced by ReplaceATOMIC_LOAD_128Results().

getCmpOperandFoldingProfit()

static unsigned getCmpOperandFoldingProfit ( SDValue  Op )

static

Returns how profitable it is to fold a comparison's operand's shift and/or extension operations.

Definition at line 3418 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by getAArch64Cmp().

getConstantLaneNumOfExtractHalfOperand()

static std::optional< uint64_t > getConstantLaneNumOfExtractHalfOperand ( SDValue &  Op )

static

Definition at line 4385 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

getContainerForFixedLengthVector()

static EVT getContainerForFixedLengthVector ( SelectionDAG &  DAG, EVT  VT  )

static

Definition at line 24969 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by convertFixedMaskToScalableVector(), getContainerForFixedLengthVector(), getDeinterleaveViaVNSRL(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), lowerScalarInsert(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), and performFP_TO_INTCombine().

getCSETCondCode()

static std::optional< AArch64CC::CondCode > getCSETCondCode ( SDValue  Op )

static

Definition at line 18301 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, CC, llvm::AArch64ISD::CSEL, llvm::isNullConstant(), llvm::isOneConstant(), and llvm::AArch64CC::NV.

Referenced by foldOverflowCheck().

getDUPLANEOp()

static unsigned getDUPLANEOp ( EVT  EltType )

static

Definition at line 11525 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, and llvm_unreachable.

Referenced by performDUPCombine().

getEstimate()

static SDValue getEstimate ( const AArch64Subtarget *  ST, unsigned  Opcode, SDValue  Operand, SelectionDAG &  DAG, int &  ExtraSteps  )

static

Definition at line 9906 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), and llvm::TargetLoweringBase::Unspecified.

getExtensionTo64Bits()

static EVT getExtensionTo64Bits ( const EVT &  OrigVT )

static

Definition at line 4348 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by addRequiredExtensionForVectorMULL(), AddRequiredExtensionForVMULL(), and SkipLoadExtensionForVMULL().

getExtFactor()

static unsigned getExtFactor ( SDValue &  V )

static

getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.

Definition at line 10491 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits().

Referenced by GeneratePerfectShuffle(), and llvm::AArch64TargetLowering::ReconstructShuffle().

getGatherVecOpcode()

unsigned getGatherVecOpcode	(	bool	IsScaled,
		bool	IsSigned,
		bool	NeedsExtend
	)

Definition at line 5397 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, and llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO.

Referenced by performGLD1Combine().

getIntrinsicID()

static unsigned getIntrinsicID ( const SDNode *  N )

static

Definition at line 6281 of file AArch64ISelLowering.cpp.

References llvm::ISD::INTRINSIC_WO_CHAIN, N, and llvm::Intrinsic::not_intrinsic.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), collectBitParts(), llvm::SITargetLowering::computeKnownBitsForTargetInstr(), FindPreallocatedCall(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::VPRecipeBuilder::handleReplication(), llvm::SITargetLowering::isCanonicalized(), isFPIntrinsic(), llvm::AArch64TargetLowering::isReassocProfitable(), IsSVECntIntrinsic(), performIntrinsicCombine(), tryConvertSVEWideCompare(), and valueIsKnownNeverF32Denorm().

getNegatedInteger()

static SDValue getNegatedInteger ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 18202 of file AArch64ISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::ISD::SUB.

Referenced by performNegCSelCombine().

getPackedSVEVectorVT() [1/2]

static EVT getPackedSVEVectorVT ( ElementCount  EC )

inlinestatic

Definition at line 179 of file AArch64ISelLowering.cpp.

References llvm_unreachable.

getPackedSVEVectorVT() [2/2]

static EVT getPackedSVEVectorVT ( EVT  VT )

inlinestatic

Definition at line 154 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by combineSVEReductionInt(), performDupLane128Combine(), and performSVESpliceCombine().

getPredicateForFixedLengthVector()

static SDValue getPredicateForFixedLengthVector ( SelectionDAG &  DAG, SDLoc &  DL, EVT  VT  )

static

Definition at line 24994 of file AArch64ISelLowering.cpp.

References assert(), DL, llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), getPTrue(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getSubtarget(), llvm::getSVEPredPatternFromNumElements(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by convertFixedMaskToScalableVector(), and getPredicateForVector().

getPredicateForScalableVector()

static SDValue getPredicateForScalableVector ( SelectionDAG &  DAG, SDLoc &  DL, EVT  VT  )

static

Definition at line 25038 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::changeVectorElementType(), DL, getPTrue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::isScalableVector(), and llvm::TargetLoweringBase::isTypeLegal().

Referenced by getPredicateForVector().

getPredicateForVector()

static SDValue getPredicateForVector ( SelectionDAG &  DAG, SDLoc &  DL, EVT  VT  )

static

Definition at line 25046 of file AArch64ISelLowering.cpp.

References DL, getPredicateForFixedLengthVector(), getPredicateForScalableVector(), and llvm::EVT::isFixedLengthVector().

getPredicateRegisterClass()

static const TargetRegisterClass * getPredicateRegisterClass ( PredicateConstraint  Constraint, EVT  VT  )

static

Definition at line 10066 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorElementType(), and llvm::EVT::isScalableVector().

getPromotedVTForPredicate()

static EVT getPromotedVTForPredicate ( EVT  VT )

inlinestatic

Definition at line 194 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::isScalableVector(), and llvm_unreachable.

Referenced by performIntrinsicCombine().

getPTest()

static SDValue getPTest ( SelectionDAG &  DAG, EVT  VT, SDValue  Pg, SDValue  Op, AArch64CC::CondCode  Cond  )

static

Definition at line 19214 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::ANY_ACTIVE, assert(), CC, Cond, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), getSVEPredicateBitCast(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::TargetLoweringBase::isTypeLegal(), isZeroingInactiveLanes(), llvm::AArch64CC::NONE_ACTIVE, llvm::AArch64ISD::PTEST, llvm::AArch64ISD::PTEST_ANY, llvm::AArch64ISD::REINTERPRET_CAST, and llvm::Test.

Referenced by performFirstTrueTestVectorCombine(), performIntrinsicCombine(), and performLastTrueTestVectorCombine().

getPTrue()

static SDValue getPTrue ( SelectionDAG &  DAG, SDLoc  DL, EVT  VT, int  Pattern  )

inlinestatic

Definition at line 4714 of file AArch64ISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), and llvm::AArch64ISD::PTRUE.

Referenced by getPredicateForFixedLengthVector(), getPredicateForScalableVector(), optimizeWhile(), performFirstTrueTestVectorCombine(), performLastTrueTestVectorCombine(), performMSTORECombine(), and performUnpackCombine().

getReductionSDNode()

static SDValue getReductionSDNode ( unsigned  Op, SDLoc  DL, SDValue  ScalarOp, SelectionDAG &  DAG  )

static

Definition at line 13564 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), and llvm::SDValue::getValueType().

getScaledOffsetForBitWidth()

static SDValue getScaledOffsetForBitWidth ( SelectionDAG &  DAG, SDValue  Offset, SDLoc  DL, unsigned  BitWidth  )

static

Definition at line 22382 of file AArch64ISelLowering.cpp.

References assert(), llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Log2_32(), llvm::Offset, llvm::ISD::SHL, and llvm::ISD::SPLAT_VECTOR.

Referenced by performGatherLoadCombine(), and performScatterStoreCombine().

getSETCC()

static SDValue getSETCC ( AArch64CC::CondCode  CC, SDValue  NZCV, const SDLoc &  DL, SelectionDAG &  DAG  )

static

Helper function to create 'CSET', which is equivalent to 'CSINC <Wd>, WZR, WZR, invert(<cond>)'.

Definition at line 10108 of file AArch64ISelLowering.cpp.

References CC, llvm::AArch64ISD::CSINC, DL, llvm::SelectionDAG::getConstant(), and llvm::SelectionDAG::getNode().

Referenced by combineAnd(), combineCMov(), combineM68kSetCC(), combineOr(), combinePredicateReduction(), combineSetCC(), combineSubSetcc(), combineVectorSizedSetCCEquality(), combineX86SetCC(), foldXor1SetCC(), LowerADDSUBO_CARRY(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerCMP_SWAP(), LowerINTRINSIC_W_CHAIN(), LowerPARITY(), LowerXALUO(), and llvm::X86TargetLowering::ReplaceNodeResults().

getSignExtendedGatherOpcode()

unsigned getSignExtendedGatherOpcode

(

unsigned

Opcode

)

Definition at line 5420 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, and llvm_unreachable.

Referenced by performGLD1Combine().

getStructuredLoadFunction()

static Function * getStructuredLoadFunction ( Module *  M, unsigned  Factor, bool  Scalable, Type *  LDVTy, Type *  PtrTy  )

static

Definition at line 14988 of file AArch64ISelLowering.cpp.

References assert(), and llvm::Intrinsic::getDeclaration().

Referenced by llvm::AArch64TargetLowering::lowerDeinterleaveIntrinsicToLoad(), and llvm::AArch64TargetLowering::lowerInterleavedLoad().

getStructuredStoreFunction()

static Function * getStructuredStoreFunction ( Module *  M, unsigned  Factor, bool  Scalable, Type *  STVTy, Type *  PtrTy  )

static

Definition at line 15004 of file AArch64ISelLowering.cpp.

References assert(), and llvm::Intrinsic::getDeclaration().

Referenced by llvm::AArch64TargetLowering::lowerInterleavedStore(), and llvm::AArch64TargetLowering::lowerInterleaveIntrinsicToStore().

getSVEContainerIRType()

static ScalableVectorType * getSVEContainerIRType ( FixedVectorType *  VTy )

static

Definition at line 14960 of file AArch64ISelLowering.cpp.

References llvm::ScalableVectorType::get(), llvm::Type::getBFloatTy(), llvm::Type::getContext(), llvm::Type::getDoubleTy(), llvm::VectorType::getElementType(), llvm::Type::getFloatTy(), llvm::Type::getHalfTy(), llvm::Type::getInt16Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), llvm::Type::getInt8Ty(), and llvm_unreachable.

Referenced by llvm::AArch64TargetLowering::lowerInterleavedLoad(), and llvm::AArch64TargetLowering::lowerInterleavedStore().

getSVEContainerType()

static MVT getSVEContainerType ( EVT  ContentTy )

static

Definition at line 19795 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by performGatherLoadCombine(), performLD1Combine(), performScatterStoreCombine(), and performST1Combine().

getSVEPredicateBitCast()

static SDValue getSVEPredicateBitCast ( EVT  VT, SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 4763 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::EVT::bitsGT(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), isZeroingInactiveLanes(), and llvm::AArch64ISD::REINTERPRET_CAST.

Referenced by getPTest().

getTestBitOperand()

static SDValue getTestBitOperand ( SDValue  Op, unsigned &  Bit, bool &  Invert, SelectionDAG &  DAG  )

static

Definition at line 21991 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::CallingConv::C, llvm::DWARFExpression::Operation::getNumOperands(), getTestBitOperand(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.

Referenced by getTestBitOperand(), and performTBZCombine().

getVectorBitwiseReduce()

static SDValue getVectorBitwiseReduce ( unsigned  Opcode, SDValue  Vec, EVT  VT, SDLoc  DL, SelectionDAG &  DAG  )

static

Definition at line 13572 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::EVT::changeVectorElementType(), DL, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), getVectorBitwiseReduce(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::EVT::isFixedLengthVector(), llvm::EVT::isPow2VectorType(), llvm_unreachable, llvm::Lo, llvm::ISD::OR, llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SplitVector(), llvm::ISD::SRL, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::XOR.

Referenced by getVectorBitwiseReduce(), and performVecReduceBitwiseCombine().

getVShiftImm()

static bool getVShiftImm ( SDValue  Op, unsigned  ElementBits, int64_t &  Cnt  )

static

getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 13273 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

hasPairwiseAdd()

static bool hasPairwiseAdd ( unsigned  Opcode, EVT  VT, bool  FullFP16  )

static

Definition at line 17326 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::FADD, and llvm::ISD::STRICT_FADD.

Referenced by performExtractVectorEltCombine().

isAddSubSExt()

static bool isAddSubSExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 4460 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.

Referenced by LowerMUL(), and selectUmullSmull().

isAddSubZExt()

static bool isAddSubZExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 4471 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.

Referenced by LowerMUL(), and selectUmullSmull().

isAllActivePredicate()

static bool isAllActivePredicate ( SelectionDAG &  DAG, SDValue  N  )

static

Definition at line 17025 of file AArch64ISelLowering.cpp.

References llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::getNumElementsFromSVEPredPattern(), llvm::SelectionDAG::getSubtarget(), llvm::ISD::isConstantSplatVectorAllOnes(), N, llvm::AArch64ISD::PTRUE, llvm::AArch64ISD::REINTERPRET_CAST, and llvm::AArch64::SVEBitsPerBlock.

Referenced by convertMergedOpToPredOp(), instCombineSVELD1(), instCombineSVESrshl(), instCombineSVEST1(), performSetccMergeZeroCombine(), performSVEAndCombine(), and performVSelectCombine().

isAllConstantBuildVector()

static bool isAllConstantBuildVector ( const SDValue &  PotentialBVec, uint64_t &  ConstVal  )

static

Definition at line 12223 of file AArch64ISelLowering.cpp.

References llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::ConstantSDNode::getZExtValue().

Referenced by isPow2Splat(), and tryLowerToSLI().

isAllInactivePredicate()

static bool isAllInactivePredicate ( SDValue  N )

static

Definition at line 17017 of file AArch64ISelLowering.cpp.

References llvm::ISD::isConstantSplatVectorAllZeros(), N, and llvm::AArch64ISD::REINTERPRET_CAST.

Referenced by performVSelectCombine().

isCheapToExtend()

static bool isCheapToExtend ( const SDValue &  N )

static

Definition at line 19680 of file AArch64ISelLowering.cpp.

References llvm::ISD::isConstantSplatVectorAllZeros(), llvm::ISD::LOAD, llvm::ISD::MLOAD, and N.

Referenced by performSignExtendSetCCCombine().

isCMN()

static bool isCMN ( SDValue  Op, ISD::CondCode  CC  )

static

Definition at line 3052 of file AArch64ISelLowering.cpp.

References CC, llvm::isNullConstant(), llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.

Referenced by emitComparison(), and getAArch64Cmp().

isCMP()

static bool isCMP ( SDValue  Op )

static

Definition at line 18294 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::SUBS.

Referenced by foldCSELOfCSEL(), and foldOverflowCheck().

isConcatMask()

static bool isConcatMask ( ArrayRef< int >  Mask, EVT  VT, bool  SplitLHS  )

static

Definition at line 11237 of file AArch64ISelLowering.cpp.

References E, llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), I, and llvm::Offset.

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal(), and tryFormConcatFromShuffle().

isConstantSplatVectorMaskForType()

static bool isConstantSplatVectorMaskForType ( SDNode *  N, EVT  MemVT  )

static

Definition at line 16990 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::DUP, llvm::EVT::getSimpleVT(), llvm::EVT::getVectorElementType(), llvm::EVT::isSimple(), N, llvm::MVT::SimpleTy, and llvm::ISD::SPLAT_VECTOR.

isEquivalentMaskless()

static bool isEquivalentMaskless ( unsigned  CC, unsigned  width, ISD::LoadExtType  ExtType, int  AddConstant, int  CompConstant  )

static

Definition at line 21359 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, CC, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::NV, llvm::AArch64CC::PL, llvm::ISD::SEXTLOAD, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by performCONDCombine().

isEssentiallyExtractHighSubvector()

static bool isEssentiallyExtractHighSubvector ( SDValue  N )

static

Definition at line 17917 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, and N.

Referenced by performAddSubLongCombine(), tryCombineLongOpWithDup(), and tryCombineMULLWithUZP1().

isExtendedBUILD_VECTOR()

static bool isExtendedBUILD_VECTOR ( SDNode *  N, SelectionDAG &  DAG, bool  isSigned  )

static

Definition at line 4398 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::EVT::getScalarSizeInBits(), llvm::isIntN(), isSigned(), llvm::isUIntN(), and N.

Referenced by isSignExtended(), isZeroExtended(), and selectUmullSmull().

isExtendOrShiftOperand()

static bool isExtendOrShiftOperand ( SDValue  N )

static

Definition at line 18458 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ConstantSDNode::getZExtValue(), llvm::ISD::isExtOpcode(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by performAddCombineSubShift().

isEXTMask()

static bool isEXTMask ( ArrayRef< int >  M, EVT  VT, bool &  ReverseEXT, unsigned &  Imm  )

static

Definition at line 11035 of file AArch64ISelLowering.cpp.

References llvm::find_if(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZExtValue(), and llvm::APInt::logBase2().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isINSMask()

static bool isINSMask ( ArrayRef< int >  M, int  NumInputElements, bool &  DstIsLeft, int &  Anomaly  )

static

Definition at line 11198 of file AArch64ISelLowering.cpp.

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isIntImmediate()

static bool isIntImmediate ( const SDNode *  N, uint64_t &  Imm  )

static

Definition at line 1932 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, and N.

isLanes1toNKnownZero()

static bool isLanes1toNKnownZero ( SDValue  Op )

static

Definition at line 22809 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ANDV_PRED, llvm::AArch64ISD::EORV_PRED, llvm::AArch64ISD::FADDA_PRED, llvm::AArch64ISD::FADDV_PRED, llvm::AArch64ISD::FMAXNMV_PRED, llvm::AArch64ISD::FMAXV_PRED, llvm::AArch64ISD::FMINNMV_PRED, llvm::AArch64ISD::FMINV_PRED, llvm::AArch64ISD::ORV_PRED, llvm::AArch64ISD::SADDV_PRED, llvm::AArch64ISD::SMAXV_PRED, llvm::AArch64ISD::SMINV_PRED, llvm::AArch64ISD::UADDV_PRED, llvm::AArch64ISD::UMAXV_PRED, and llvm::AArch64ISD::UMINV_PRED.

Referenced by removeRedundantInsertVectorElt().

isLegalArithImmed()

static bool isLegalArithImmed ( uint64_t  C )

static

Definition at line 3034 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, llvm::dbgs(), and LLVM_DEBUG.

Referenced by getAArch64Cmp().

isLoadOrMultipleLoads()

static bool isLoadOrMultipleLoads ( SDValue  B, SmallVector< LoadSDNode * > &  Loads  )

static

Definition at line 18670 of file AArch64ISelLowering.cpp.

References B, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), I, llvm::peekThroughOneUseBitcasts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::VECTOR_SHUFFLE.

Referenced by areLoadedOffsetButOtherwiseSame(), and performExtBinopLoadFold().

isMergePassthruOpcode()

static bool isMergePassthruOpcode ( unsigned  Opc )

static

Definition at line 225 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ABS_MERGE_PASSTHRU, llvm::AArch64ISD::BITREVERSE_MERGE_PASSTHRU, llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU, llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU, llvm::AArch64ISD::CTPOP_MERGE_PASSTHRU, llvm::AArch64ISD::DUP_MERGE_PASSTHRU, llvm::AArch64ISD::FABS_MERGE_PASSTHRU, llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU, llvm::AArch64ISD::FCVTZS_MERGE_PASSTHRU, llvm::AArch64ISD::FCVTZU_MERGE_PASSTHRU, llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU, llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU, llvm::AArch64ISD::FNEG_MERGE_PASSTHRU, llvm::AArch64ISD::FP_EXTEND_MERGE_PASSTHRU, llvm::AArch64ISD::FP_ROUND_MERGE_PASSTHRU, llvm::AArch64ISD::FRECPX_MERGE_PASSTHRU, llvm::AArch64ISD::FRINT_MERGE_PASSTHRU, llvm::AArch64ISD::FROUND_MERGE_PASSTHRU, llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU, llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU, llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU, llvm::AArch64ISD::NEG_MERGE_PASSTHRU, llvm::AArch64ISD::REVD_MERGE_PASSTHRU, llvm::AArch64ISD::REVH_MERGE_PASSTHRU, llvm::AArch64ISD::REVW_MERGE_PASSTHRU, llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, llvm::AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU, llvm::AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU, and llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU.

isNegatedInteger()

static bool isNegatedInteger ( SDValue  Op )

static

Definition at line 18198 of file AArch64ISelLowering.cpp.

References llvm::isNullConstant(), and llvm::ISD::SUB.

Referenced by performNegCSelCombine().

isOpcWithIntImmediate()

static bool isOpcWithIntImmediate ( const SDNode *  N, unsigned  Opc, uint64_t &  Imm  )

static

Definition at line 1943 of file AArch64ISelLowering.cpp.

References isIntImmediate(), and N.

isOperandOfVmullHighP64()

static bool isOperandOfVmullHighP64 ( Value *  Op )

static

Check if Op could be used with vmull_high_p64 intrinsic.

Definition at line 14368 of file AArch64ISelLowering.cpp.

References llvm::Value::getType(), llvm::ConstantInt::getValue(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_ExtractElt(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().

Referenced by areOperandsOfVmullHighP64().

isOrXorChain()

static bool isOrXorChain ( SDValue  N, unsigned &  Num, SmallVector< std::pair< SDValue, SDValue >, 16 > &  WorkList  )

static

Definition at line 8920 of file AArch64ISelLowering.cpp.

References isOrXorChain(), MaxXors, N, llvm::ISD::OR, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by isOrXorChain(), and performOrXorChainCombine().

isPackedVectorType()

static bool isPackedVectorType ( EVT  VT, SelectionDAG &  DAG  )

inlinestatic

Returns true if VT's elements occupy the lowest bit positions of its associated register class without any intervening space.

For example, nxv2f16, nxv4f16 and nxv8f16 are legal types that belong to the same register class, but only nxv8f16 can be treated as a packed vector.

Definition at line 216 of file AArch64ISelLowering.cpp.

References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and llvm::AArch64::SVEBitsPerBlock.

isPow2Splat()

static bool isPow2Splat ( SDValue  Op, uint64_t &  SplatVal, bool &  Negated  )

static

Definition at line 13155 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::AArch64ISD::DUP, isAllConstantBuildVector(), llvm::isPowerOf2_64(), and llvm::ISD::SPLAT_VECTOR.

isPredicateCCSettingOp()

static bool isPredicateCCSettingOp ( SDValue  N )

static

Definition at line 17341 of file AArch64ISelLowering.cpp.

References llvm::ISD::INTRINSIC_WO_CHAIN, N, and llvm::ISD::SETCC.

Referenced by performFirstTrueTestVectorCombine().

isREVMask()

static bool isREVMask ( ArrayRef< int >  M, EVT  VT, unsigned  BlockSize  )

static

isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.

(The order of the elements within each block of the vector is reversed.)

Definition at line 11077 of file AArch64ISelLowering.cpp.

References assert(), BlockSize, llvm::EVT::getScalarSizeInBits(), and llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isSetCC()

static bool isSetCC ( SDValue  Op, SetCCInfoAndKind &  SetCCInfo  )

static

Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one.

SetCCInfo is filled accordingly.

Postcondition

SetCCInfo is meanginfull only when this function returns true.

Returns

True when Op is a kind of SET_CC operation.

Definition at line 17961 of file AArch64ISelLowering.cpp.

References SetCCInfo::AArch64, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, llvm::AArch64CC::getInvertedCondCode(), llvm::ConstantSDNode::isOne(), llvm::ConstantSDNode::isZero(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, llvm::ISD::SETCC, and std::swap().

Referenced by isSetCCOrZExtSetCC().

isSetCCOrZExtSetCC()

static bool isSetCCOrZExtSetCC ( const SDValue &  Op, SetCCInfoAndKind &  Info  )

static

Definition at line 18004 of file AArch64ISelLowering.cpp.

References Info, isSetCC(), and llvm::ISD::ZERO_EXTEND.

Referenced by performSetccAddFolding().

isSignExtended()

static bool isSignExtended ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 4448 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), N, and llvm::ISD::SIGN_EXTEND.

Referenced by llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), isAddSubSExt(), LowerMUL(), performMulCombine(), and selectUmullSmull().

isSingletonEXTMask()

static bool isSingletonEXTMask ( ArrayRef< int >  M, EVT  VT, unsigned &  Imm  )

static

Definition at line 10879 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

isSplatShuffle()

static bool isSplatShuffle ( Value *  V )

static

Definition at line 14288 of file AArch64ISelLowering.cpp.

References llvm::all_equal().

Referenced by areExtractShuffleVectors(), and llvm::AArch64TargetLowering::shouldSinkOperands().

IsSVECntIntrinsic()

static std::optional< unsigned > IsSVECntIntrinsic ( SDValue  S )

static

Definition at line 16217 of file AArch64ISelLowering.cpp.

References getIntrinsicID(), and llvm::SDValue::getNode().

Referenced by performMulCombine().

isTRN_v_undef_Mask()

static bool isTRN_v_undef_Mask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 11185 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isTRNMask()

static bool isTRNMask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

Definition at line 11131 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isUZP_v_undef_Mask()

static bool isUZP_v_undef_Mask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 11166 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and Idx.

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isUZPMask()

static bool isUZPMask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

Definition at line 11118 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isValidImmForSVEVecImmAddrMode() [1/2]

static bool isValidImmForSVEVecImmAddrMode ( SDValue  Offset, unsigned  ScalarSizeInBytes  )

static

Check if the value of Offset represents a valid immediate for the SVE gather load/prefetch and scatter store instructiona with vector base and immediate offset addressing mode:

 [<Zn>.[S|D]{, #<imm>}]

where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.

Definition at line 22420 of file AArch64ISelLowering.cpp.

References llvm::ConstantSDNode::getZExtValue(), isValidImmForSVEVecImmAddrMode(), and llvm::Offset.

isValidImmForSVEVecImmAddrMode() [2/2]

static bool isValidImmForSVEVecImmAddrMode ( unsigned  OffsetInBytes, unsigned  ScalarSizeInBytes  )

inlinestatic

Check if the value of OffsetInBytes can be used as an immediate for the gather load/prefetch and scatter store instructions with vector base and immediate offset addressing mode:

 [<Zn>.[S|D]{, #<imm>}]

where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.

Definition at line 22400 of file AArch64ISelLowering.cpp.

Referenced by combineSVEPrefetchVecBaseImmOff(), isValidImmForSVEVecImmAddrMode(), performGatherLoadCombine(), and performScatterStoreCombine().

isVShiftLImm()

static bool isVShiftLImm ( SDValue  Op, EVT  VT, bool  isLong, int64_t &  Cnt  )

static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 13293 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by LowerShift(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), and PerformShiftCombine().

isVShiftRImm()

static bool isVShiftRImm ( SDValue  Op, EVT  VT, bool  isNarrow, int64_t &  Cnt  )

static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

The value must be in the range: 1 <= Value <= ElementBits for a right shift; or

Definition at line 13304 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by LowerShift(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), and PerformShiftCombine().

isWideDUPMask()

static bool isWideDUPMask ( ArrayRef< int >  M, EVT  VT, unsigned  BlockSize, unsigned &  DupLaneOp  )

static

Check if a vector shuffle corresponds to a DUP instructions with a larger element width than the vector lane type.

If that is the case the function returns true and writes the value of the DUP instruction lane operand into DupLaneOp

Definition at line 10962 of file AArch64ISelLowering.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), BlockSize, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::find_if(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), and I.

isWideTypeMask()

static bool isWideTypeMask ( ArrayRef< int >  M, EVT  VT, SmallVectorImpl< int > &  NewMask  )

static

Definition at line 11600 of file AArch64ISelLowering.cpp.

References assert(), llvm::SmallVectorImpl< T >::clear(), llvm::EVT::getVectorNumElements(), llvm::M0(), llvm::M1(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by tryWidenMaskForShuffle().

isZeroExtended()

static bool isZeroExtended ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 4454 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), N, and llvm::ISD::ZERO_EXTEND.

Referenced by isAddSubZExt(), LowerMUL(), performMulCombine(), and selectUmullSmull().

isZeroingInactiveLanes()

static bool isZeroingInactiveLanes ( SDValue  Op )

static

Definition at line 263 of file AArch64ISelLowering.cpp.

References llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::isConstantSplatVectorAllOnes(), llvm::AArch64ISD::PTRUE, and llvm::AArch64ISD::SETCC_MERGE_ZERO.

Referenced by getPTest(), and getSVEPredicateBitCast().

isZerosVector()

static bool isZerosVector ( const SDNode *  N )

static

isZerosVector - Check whether SDNode N is a zero-filled vector.

Definition at line 2865 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::AArch64ISD::DUP, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::isNullConstant(), llvm::isNullFPConstant(), and N.

Referenced by GenerateTBL(), performAddDotCombine(), performSetccMergeZeroCombine(), performSetCCPunpkCombine(), and performUnpackCombine().

isZIP_v_undef_Mask()

static bool isZIP_v_undef_Mask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 11147 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and Idx.

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

isZIPMask()

static bool isZIPMask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

Definition at line 11102 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and Idx.

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

legalizeSVEGatherPrefetchOffsVec()

static SDValue legalizeSVEGatherPrefetchOffsVec ( SDNode *  N, SelectionDAG &  DAG  )

static

Legalize the gather prefetch (scalar + vector addressing mode) when the offset vector is an unpacked 32-bit scalable vector.

The other cases (Offset != nxv2i32) do not need legalization.

Definition at line 22765 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), N, and llvm::Offset.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

lookThroughSignExtension()

std::pair< SDValue, uint64_t > lookThroughSignExtension

(

SDValue

Val

)

Definition at line 8480 of file AArch64ISelLowering.cpp.

References llvm::EVT::getFixedSizeInBits(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::SIGN_EXTEND_INREG.

lowerADDSUBO_CARRY()

static SDValue lowerADDSUBO_CARRY ( SDValue  Op, SelectionDAG &  DAG, unsigned  Opcode, bool  IsSigned  )

static

Definition at line 3795 of file AArch64ISelLowering.cpp.

References carryFlagToValue(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ISD::MERGE_VALUES, overflowFlagToValue(), llvm::AArch64ISD::SBCS, and valueToCarryFlag().

Referenced by llvm::AArch64TargetLowering::LowerOperation().

LowerBRCOND()

static SDValue LowerBRCOND ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 5864 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::BRCOND, CC, Cond, emitConjunction(), llvm::SelectionDAG::getConstant(), and llvm::SelectionDAG::getNode().

Referenced by llvm::AArch64TargetLowering::LowerOperation().

LowerFunnelShift()

static SDValue LowerFunnelShift ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 5882 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::SelectionDAG::getConstant(), llvm::MVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getValueType().

Referenced by llvm::AArch64TargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerPREFETCH()

static SDValue LowerPREFETCH ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 3852 of file AArch64ISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), and llvm::AArch64ISD::PREFETCH.

Referenced by llvm::AArch64TargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerSVEIntrinsicDUP()

static SDValue LowerSVEIntrinsicDUP ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19110 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::AArch64ISD::DUP_MERGE_PASSTHRU, llvm::SelectionDAG::getNode(), and N.

Referenced by performIntrinsicCombine().

LowerSVEIntrinsicEXT()

static SDValue LowerSVEIntrinsicEXT ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19124 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::AArch64ISD::EXT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getNode(), llvm::ElementCount::getScalable(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::EVT::isScalableVector(), llvm::ISD::MUL, N, and llvm::AArch64::SVEBitsPerBlock.

Referenced by performIntrinsicCombine().

LowerSVEIntrinsicIndex()

static SDValue LowerSVEIntrinsicIndex ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19094 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::sampleprof::Base, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getStepVector(), llvm::SDValue::getValueType(), llvm::Mul, llvm::ISD::MUL, N, and llvm::ISD::SPLAT_VECTOR.

Referenced by performIntrinsicCombine().

LowerTruncateVectorStore()

static SDValue LowerTruncateVectorStore ( SDLoc  DL, StoreSDNode *  ST, EVT  VT, EVT  MemVT, SelectionDAG &  DAG  )

static

Definition at line 5651 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::isVector(), and llvm::ISD::TRUNCATE.

LowerXALUO()

static SDValue LowerXALUO ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 3821 of file AArch64ISelLowering.cpp.

References CC, llvm::AArch64ISD::CSEL, getAArch64XALUOOp(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getVTList(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::ISD::MERGE_VALUES.

Referenced by LowerMULO(), llvm::AArch64TargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

mayTailCallThisCC()

static bool mayTailCallThisCC ( CallingConv::ID  CC )

static

Return true if we might ever do TCO for calls with this calling convention.

Definition at line 6947 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::AArch64_SVE_VectorCall, llvm::CallingConv::C, CC, llvm::CallingConv::Fast, llvm::CallingConv::PreserveAll, llvm::CallingConv::PreserveMost, llvm::CallingConv::Swift, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.

Referenced by llvm::AArch64CallLowering::isEligibleForTailCallOptimization(), llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), and llvm::SITargetLowering::isEligibleForTailCallOptimization().

NormalizeBuildVector()

static SDValue NormalizeBuildVector ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 12375 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::EVT::isFloatingPoint(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

optimizeLogicalImm()

static bool optimizeLogicalImm ( SDValue  Op, unsigned  Size, uint64_t  Imm, const APInt &  Demanded, TargetLowering::TargetLoweringOpt &  TLO, unsigned  NewOpc  )

static

Definition at line 1949 of file AArch64ISelLowering.cpp.

References assert(), llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, DL, llvm::AArch64_AM::encodeLogicalImmediate(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi, llvm::AArch64_AM::isLogicalImmediate(), llvm::isShiftedMask_64(), and Size.

Referenced by llvm::AArch64TargetLowering::targetShrinkDemandedConstant().

optimizeWhile()

static SDValue optimizeWhile ( SDValue  Op, SelectionDAG &  DAG, bool  IsSigned, bool  IsLess, bool  IsEqual  )

static

Definition at line 4722 of file AArch64ISelLowering.cpp.

References llvm::APInt::getBitWidth(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), getPTrue(), llvm::SelectionDAG::getSubtarget(), llvm::getSVEPredPatternFromNumElements(), llvm::APInt::getZExtValue(), llvm::APInt::sadd_ov(), llvm::APInt::uadd_ov(), X, and Y.

overflowFlagToValue()

static SDValue overflowFlagToValue ( SDValue  Glue, EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 3784 of file AArch64ISelLowering.cpp.

References assert(), CC, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getResNo(), and llvm::AArch64CC::VS.

Referenced by lowerADDSUBO_CARRY().

parseConstraintCode()

static AArch64CC::CondCode parseConstraintCode ( llvm::StringRef  Constraint )

static

Definition at line 10084 of file AArch64ISelLowering.cpp.

References llvm::StringSwitch< T, R >::Case(), Cond, llvm::StringSwitch< T, R >::Default(), llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by llvm::X86TargetLowering::getConstraintType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), and llvm::X86TargetLowering::LowerAsmOutputForConstraint().

parsePredicateConstraint()

static PredicateConstraint parsePredicateConstraint ( StringRef  Constraint )

static

Definition at line 10057 of file AArch64ISelLowering.cpp.

References llvm::StringSwitch< T, R >::Case(), and llvm::StringSwitch< T, R >::Default().

performAddCombineForShiftedOperands()

static SDValue performAddCombineForShiftedOperands ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18511 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::Value::hasOneUse(), isOpcWithIntImmediate(), LHS, N, performAddCombineSubShift(), RHS, and llvm::ISD::SHL.

Referenced by performAddSubCombine().

performAddCombineSubShift()

static SDValue performAddCombineSubShift ( SDNode *  N, SDValue  SUB, SDValue  Z, SelectionDAG &  DAG  )

static

Definition at line 18483 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), isExtendOrShiftOperand(), N, llvm::ISD::SUB, and Y.

Referenced by performAddCombineForShiftedOperands().

performAddCSelIntoCSinc()

static SDValue performAddCSelIntoCSinc ( SDNode *  N, SelectionDAG &  DAG  )

static

Perform the scalar expression combine in the form of: CSEL(c, 1, cc) + b => CSINC(b+c, b, cc) CSNEG(c, -1, cc) + b => CSINC(b+c, b, cc)

Definition at line 18103 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::CallingConv::C, llvm::AArch64ISD::CSEL, llvm::AArch64ISD::CSINC, llvm::AArch64ISD::CSNEG, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Value::hasOneUse(), llvm::ConstantSDNode::isAllOnes(), llvm::TargetLoweringBase::isLegalAddImmediate(), llvm::ConstantSDNode::isOne(), llvm::EVT::isScalarInteger(), LHS, N, RHS, and std::swap().

Referenced by performAddSubCombine().

performAddDotCombine()

static SDValue performAddDotCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18176 of file AArch64ISelLowering.cpp.

References A, llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), isZerosVector(), N, llvm::AArch64ISD::SDOT, std::swap(), and llvm::AArch64ISD::UDOT.

Referenced by performAddSubCombine().

performAddSubCombine()

static SDValue performAddSubCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 18914 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, N, performAddCombineForShiftedOperands(), performAddCSelIntoCSinc(), performAddDotCombine(), performAddSubIntoVectorOp(), performAddSubLongCombine(), performAddUADDVCombine(), performExtBinopLoadFold(), performNegCSelCombine(), performSubAddMULCombine(), performSVEMulAddSubCombine(), and performVectorAddSubExtCombine().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performAddSubIntoVectorOp()

static SDValue performAddSubIntoVectorOp ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18637 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::LOAD, N, and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by performAddSubCombine().

performAddSubLongCombine()

static SDValue performAddSubLongCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 18252 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::MVT::is128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractHighSubvector(), LHS, N, performSetccAddFolding(), RHS, llvm::ISD::SIGN_EXTEND, tryExtendDUPToExtractHigh(), and llvm::ISD::ZERO_EXTEND.

Referenced by performAddSubCombine().

performAddUADDVCombine()

static SDValue performAddUADDVCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18064 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::isScalarInteger(), LHS, N, RHS, and llvm::AArch64ISD::UADDV.

Referenced by performAddSubCombine().

performANDCombine()

static SDValue performANDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17227 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::BICi, llvm::SelectionDAG::computeKnownBits(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getBitWidth(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), I, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), LHS, N, performANDORCSELCombine(), performANDSETCCCombine(), performSVEAndCombine(), resolveBuildVector(), RHS, tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), llvm::KnownBits::Zero, and llvm::APInt::zext().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::LoongArchTargetLowering::PerformDAGCombine(), llvm::MipsTargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

performANDORCSELCombine()

static SDValue performANDORCSELCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 16904 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::AArch64ISD::CCMN, llvm::AArch64ISD::CCMP, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::AArch64CC::getNZCVToSatisfyCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::isNullConstant(), llvm::isOneConstant(), MVT_CC, N, llvm::AArch64ISD::SUBS, and std::swap().

Referenced by performANDCombine(), and performORCombine().

performANDSETCCCombine()

static SDValue performANDSETCCCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17188 of file AArch64ISelLowering.cpp.

References CC, llvm::AArch64ISD::CSINC, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, emitConjunction(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), N, llvm::ISD::SELECT, and llvm::ISD::SETCC.

Referenced by performANDCombine().

performBRCONDCombine()

static SDValue performBRCONDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 21561 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADDS, assert(), llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, CC, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::AArch64CC::EQ, llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::Function::hasFnAttribute(), llvm::isNullConstant(), LHS, N, llvm::AArch64CC::NE, performCONDCombine(), RHS, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::AArch64ISD::SUBS, and std::swap().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performBSPExpandForSVE()

static SDValue performBSPExpandForSVE ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 22936 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::isScalableVector(), N, and llvm::ISD::OR.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performBuildShuffleExtendCombine()

static SDValue performBuildShuffleExtendCombine ( SDValue  BV, SelectionDAG &  DAG  )

static

Combines a buildvector(sext/zext) or shuffle(sext/zext, undef) node pattern into sext/zext(buildvector) or sext/zext(shuffle) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt.

Definition at line 16282 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BUILD_VECTOR, calculatePreExtendType(), llvm::EVT::changeVectorElementType(), DL, llvm::drop_begin(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDValue::isUndef(), llvm::SDNode::ops(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::ZERO_EXTEND.

Referenced by performMulVectorExtendCombine().

performBuildVectorCombine()

static SDValue performBuildVectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 18394 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::EVT::changeVectorElementType(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorMinNumElements(), llvm::TargetLoweringBase::isTypeLegal(), and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performConcatVectorsCombine()

static SDValue performConcatVectorsCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 17495 of file AArch64ISelLowering.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::all_of(), assert(), llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::BITCAST, CC, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE64, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::SDNode::isOnlyUserOf(), llvm::EVT::isScalableVector(), llvm::SDNode::isUndef(), llvm::MVT::isVector(), LLVM_DEBUG, llvm::AArch64ISD::MOVIshift, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), RHS, llvm::ISD::TRUNCATE, llvm::AArch64ISD::VLSHR, WidenVector(), X, llvm::ISD::XOR, Y, llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performCONDCombine()

static SDValue performCONDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG, unsigned  CCIndex, unsigned  CmpIndex  )

static

Definition at line 21483 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, CC, checkValueWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasAnyUseOfValue(), isEquivalentMaskless(), N, performSubsToAndsCombine(), llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.

Referenced by performBRCONDCombine(), and performCSELCombine().

performCSELCombine()

static SDValue performCSELCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 21725 of file AArch64ISelLowering.cpp.

References foldCSELOfCSEL(), foldCSELofCTTZ(), N, and performCONDCombine().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performCTLZCombine()

static SDValue performCTLZCombine ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 22369 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITREVERSE, llvm::ISD::CTTZ, DL, llvm::SelectionDAG::getNode(), and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performDUPCombine()

static SDValue performDUPCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 22266 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::DUP, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), getDUPLANEOp(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNodeIfExists(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), N, and performPostLD1Combine().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performDupLane128Combine()

static SDValue performDupLane128Combine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 22956 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::AArch64ISD::DUPLANE128, llvm::SelectionDAG::getNode(), getPackedSVEVectorVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::is128BitVector(), and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performExtBinopLoadFold()

static SDValue performExtBinopLoadFold ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18796 of file AArch64ISelLowering.cpp.

References areLoadedOffsetButOtherwiseSame(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::Hi, llvm::ISD::isConstantSplatVector(), llvm::ISD::isExtOpcode(), llvm::EVT::isFixedLengthVector(), isLoadOrMultipleLoads(), llvm::TargetLoweringBase::isTypeLegal(), llvm::Lo, llvm::SelectionDAG::makeEquivalentMemoryOrdering(), N, llvm::SDNode::op_values(), llvm::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SHL, llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::SUB, std::swap(), and llvm::zip().

Referenced by performAddSubCombine().

performExtendCombine()

static SDValue performExtendCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 19726 of file AArch64ISelLowering.cpp.

References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::Intrinsic::not_intrinsic, performSignExtendSetCCCombine(), llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, tryCombineLongOpWithDup(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performExtractSubvectorCombine()

static SDValue performExtractSubvectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 17749 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isScalableVector(), N, and llvm::ISD::SPLAT_VECTOR.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performExtractVectorEltCombine()

static SDValue performExtractVectorEltCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 17426 of file AArch64ISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::DUP, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), hasPairwiseAdd(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::SDNode::isStrictFPOpcode(), N, llvm::Other, performFirstTrueTestVectorCombine(), performLastTrueTestVectorCombine(), and llvm::SelectionDAG::ReplaceAllUsesOfValueWith().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performFADDCombine()

static SDValue performFADDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17290 of file AArch64ISelLowering.cpp.

References A, B, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, N, RHS, and llvm::SDNode::setFlags().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performFDivCombine()

static SDValue performFDivCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Fold a floating-point divide by power of two into fixed-point to floating-point conversion.

Definition at line 16734 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, DL, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performFirstTrueTestVectorCombine()

static SDValue performFirstTrueTestVectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 17362 of file AArch64ISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::AArch64CC::FIRST_ACTIVE, getPTest(), getPTrue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::isNullConstant(), isPredicateCCSettingOp(), llvm::EVT::isScalableVector(), and N.

Referenced by performExtractVectorEltCombine().

performFlagSettingCombine()

static SDValue performFlagSettingCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, unsigned  GenericOpcode  )

static

Definition at line 21883 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, Generic, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNodeIfExists(), llvm::SelectionDAG::getVTList(), LHS, N, and RHS.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performFPExtendCombine()

static SDValue performFPExtendCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 22898 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::ISD::EXTLOAD, llvm::ISD::FP_ROUND, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getExtLoad(), llvm::EVT::getFixedSizeInBits(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isFixedLengthVector(), llvm::ISD::isNormalLoad(), N, and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performFpToIntCombine()

static SDValue performFpToIntCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Fold a floating-point multiply by power of two into floating-point to fixed-point conversion.

Definition at line 16663 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, DL, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64Subtarget::isNeonAvailable(), llvm::TargetLoweringBase::isTypeLegal(), N, and llvm::ISD::TRUNCATE.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performGatherLoadCombine()

static SDValue performGatherLoadCombine ( SDNode *  N, SelectionDAG &  DAG, unsigned  Opcode, bool  OnlyPackedOffsets = true  )

static

Definition at line 22531 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::sampleprof::Base, llvm::ISD::BITCAST, DL, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getScaledOffsetForBitWidth(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), isValidImmForSVEVecImmAddrMode(), N, llvm::Offset, llvm::AArch64::SVEBitsPerBlock, std::swap(), and llvm::ISD::TRUNCATE.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performGLD1Combine()

static SDValue performGLD1Combine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 20383 of file AArch64ISelLowering.cpp.

References assert(), llvm::sampleprof::Base, DL, getGatherVecOpcode(), llvm::SelectionDAG::getNode(), getSignExtendedGatherOpcode(), llvm::EVT::getVectorElementType(), llvm::VTSDNode::getVT(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, N, llvm::Offset, Scaled, llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, Signed, and llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performGlobalAddressCombine()

static SDValue performGlobalAddressCombine ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget, const TargetMachine &  TM  )

static

Definition at line 22318 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::CallingConv::C, llvm::AArch64Subtarget::ClassifyGlobalReference(), DL, llvm::SelectionDAG::getConstant(), llvm::Module::getDataLayout(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getGlobalAddress(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::GlobalValue::getParent(), llvm::DataLayout::getTypeAllocSize(), llvm::GlobalValue::getValueType(), llvm::AArch64II::MO_NO_FLAG, N, llvm::Offset, llvm::ISD::SUB, TM, and llvm::SDNode::uses().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performInsertSubvectorCombine()

static SDValue performInsertSubvectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 17772 of file AArch64ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::Lo, and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performInsertVectorEltCombine()

static SDValue performInsertVectorEltCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 22869 of file AArch64ISelLowering.cpp.

References N, performPostLD1Combine(), and removeRedundantInsertVectorElt().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performIntrinsicCombine()

static SDValue performIntrinsicCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 19335 of file AArch64ISelLowering.cpp.

References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::Add, llvm::ISD::ADD, llvm::ISD::AND, llvm::AArch64ISD::ANDV_PRED, llvm::AArch64CC::ANY_ACTIVE, llvm::AArch64ISD::BIC, combineAcrossLanesIntrinsic(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), convertMergedOpToPredOp(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::EORV_PRED, llvm::ISD::EXTRACT_SUBVECTOR, llvm::AArch64ISD::FADD_PRED, llvm::AArch64ISD::FADDA_PRED, llvm::AArch64ISD::FADDV_PRED, llvm::AArch64ISD::FDIV_PRED, llvm::AArch64CC::FIRST_ACTIVE, llvm::AArch64ISD::FMA_PRED, llvm::AArch64ISD::FMAX_PRED, llvm::ISD::FMAXIMUM, llvm::AArch64ISD::FMAXNM_PRED, llvm::AArch64ISD::FMAXNMV_PRED, llvm::ISD::FMAXNUM, llvm::AArch64ISD::FMAXV_PRED, llvm::AArch64ISD::FMIN_PRED, llvm::ISD::FMINIMUM, llvm::AArch64ISD::FMINNM_PRED, llvm::AArch64ISD::FMINNMV_PRED, llvm::ISD::FMINNUM, llvm::AArch64ISD::FMINV_PRED, llvm::AArch64ISD::FMUL_PRED, llvm::AArch64ISD::FSUB_PRED, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getIntrinsicID(), llvm::SelectionDAG::getNode(), getPromotedVTForPredicate(), getPTest(), llvm::ElementCount::getScalable(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isFixedLengthVector(), llvm::AArch64CC::LAST_ACTIVE, LowerSVEIntrinsicDUP(), LowerSVEIntrinsicEXT(), LowerSVEIntrinsicIndex(), llvm::AArch64ISD::MUL_PRED, llvm::AArch64ISD::MULHS_PRED, llvm::AArch64ISD::MULHU_PRED, N, llvm::ISD::OR, llvm::AArch64ISD::ORV_PRED, llvm::AArch64ISD::PMULL, llvm::ISD::SADDSAT, llvm::AArch64ISD::SADDV, llvm::AArch64ISD::SADDV_PRED, llvm::AArch64ISD::SDIV_PRED, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUO, llvm::AArch64ISD::SHL_PRED, llvm::ISD::SIGN_EXTEND, llvm::AArch64ISD::SMAX_PRED, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMAXV_PRED, llvm::AArch64ISD::SMIN_PRED, llvm::AArch64ISD::SMINV, llvm::AArch64ISD::SMINV_PRED, llvm::AArch64ISD::SMULL, llvm::ISD::SPLAT_VECTOR, llvm::AArch64ISD::SRA_PRED, llvm::AArch64ISD::SRAD_MERGE_OP1, llvm::ISD::SRL, llvm::AArch64ISD::SRL_PRED, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::TRUNCATE, tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineShiftImm(), tryConvertSVEWideCompare(), llvm::ISD::UADDSAT, llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UADDV_PRED, llvm::AArch64ISD::UDIV_PRED, llvm::AArch64ISD::UMAX_PRED, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMAXV_PRED, llvm::AArch64ISD::UMIN_PRED, llvm::AArch64ISD::UMINV, llvm::AArch64ISD::UMINV_PRED, llvm::AArch64ISD::UMULL, llvm::ISD::USUBSAT, llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performIntToFpCombine()

static SDValue performIntToFpCombine ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 16621 of file AArch64ISelLowering.cpp.

References llvm::MemSDNode::getAlign(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::AArch64Subtarget::isNeonAvailable(), llvm::ISD::isNormalLoad(), N, performVectorCompareAndMaskUnaryOpCombine(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SINT_TO_FP, llvm::AArch64ISD::SITOF, and llvm::AArch64ISD::UITOF.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performLastTrueTestVectorCombine()

static SDValue performLastTrueTestVectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 17392 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getPTest(), getPTrue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), Idx, llvm::isAllOnesConstant(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isScalableVector(), llvm::AArch64CC::LAST_ACTIVE, N, and llvm::ISD::VSCALE.

Referenced by performExtractVectorEltCombine().

performLD1Combine()

static SDValue performLD1Combine ( SDNode *  N, SelectionDAG &  DAG, unsigned  Opc  )

static

Definition at line 19823 of file AArch64ISelLowering.cpp.

References DL, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), llvm::EVT::isInteger(), N, llvm::AArch64::SVEBitsPerBlock, and llvm::ISD::TRUNCATE.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performLD1ReplicateCombine()

template<unsigned Opcode>

static SDValue performLD1ReplicateCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19875 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::isFloatingPoint(), llvm::AArch64ISD::LD1RO_MERGE_ZERO, llvm::AArch64ISD::LD1RQ_MERGE_ZERO, and N.

performLDNT1Combine()

static SDValue performLDNT1Combine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19849 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::isFloatingPoint(), N, llvm::ISD::NON_EXTLOAD, and llvm::ISD::UNINDEXED.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performLOADCombine()

static SDValue performLOADCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 20645 of file AArch64ISelLowering.cpp.

References llvm::commonAlignment(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), I, llvm::ISD::INSERT_SUBVECTOR, llvm::AArch64Subtarget::isLittleEndian(), llvm::EVT::isScalableVector(), N, performTBISimplification(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AArch64Subtarget::supportsAddressTopByteIgnored(), and llvm::ISD::TokenFactor.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performMaskedGatherScatterCombine()

static SDValue performMaskedGatherScatterCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 21079 of file AArch64ISelLowering.cpp.

References assert(), llvm::Data, DL, findMoreOptimalIndexType(), llvm::MaskedGatherScatterSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MaskedGatherSDNode::getExtensionType(), llvm::MaskedGatherScatterSDNode::getIndex(), llvm::MaskedGatherScatterSDNode::getIndexType(), llvm::MaskedGatherScatterSDNode::getMask(), llvm::SelectionDAG::getMaskedGather(), llvm::SelectionDAG::getMaskedScatter(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::MaskedGatherSDNode::getPassThru(), llvm::MaskedGatherScatterSDNode::getScale(), llvm::MaskedScatterSDNode::getValue(), llvm::SelectionDAG::getVTList(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::MaskedScatterSDNode::isTruncatingStore(), and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performMSTORECombine()

static SDValue performMSTORECombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 20914 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::changeVectorElementType(), DL, llvm::MaskedLoadStoreSDNode::getAddressingMode(), llvm::MaskedStoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::MaskedStoreSDNode::getMask(), llvm::SelectionDAG::getMaskedStore(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::getNumElementsFromSVEPredPattern(), llvm::MaskedStoreSDNode::getOffset(), getPTrue(), llvm::EVT::getSizeInBits(), llvm::MaskedStoreSDNode::getValue(), llvm::EVT::getVectorElementType(), llvm::Value::hasOneUse(), llvm::MaskedLoadStoreSDNode::isUnindexed(), N, llvm::AArch64ISD::PTRUE, llvm::AArch64ISD::UZP1, and llvm::EVT::widenIntegerVectorElementType().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performMulCombine()

static SDValue performMulCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 16399 of file AArch64ISelLowering.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::APInt::ashr(), llvm::BitWidth, llvm::CallingConv::C, llvm::APInt::countr_zero(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), isSignExtended(), IsSVECntIntrinsic(), isZeroExtended(), llvm::APInt::logBase2(), llvm::ISD::MUL, N, performMulVectorCmpZeroCombine(), performMulVectorExtendCombine(), RHS, llvm::APInt::sdivrem(), llvm::APInt::sge(), llvm::ISD::SHL, llvm::APInt::sle(), llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, and X.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performMULLCombine()

static SDValue performMULLCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 23125 of file AArch64ISelLowering.cpp.

References N, llvm::Intrinsic::not_intrinsic, tryCombineLongOpWithDup(), and tryCombineMULLWithUZP1().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performMulVectorCmpZeroCombine()

static SDValue performMulVectorCmpZeroCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 16366 of file AArch64ISelLowering.cpp.

References llvm::And, llvm::ISD::AND, llvm::AArch64ISD::CMLTz, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isConstantSplatVector(), llvm::APInt::isMask(), N, llvm::AArch64ISD::NVCAST, and llvm::ISD::SRL.

Referenced by performMulCombine().

performMulVectorExtendCombine()

static SDValue performMulVectorExtendCombine ( SDNode *  Mul, SelectionDAG &  DAG  )

static

Combines a mul(dup(sext/zext)) node pattern into mul(sext/zext(dup)) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt.

Definition at line 16346 of file AArch64ISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::Mul, and performBuildShuffleExtendCombine().

Referenced by performMulCombine().

performNegCSelCombine()

static SDValue performNegCSelCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18216 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::CSEL, DL, getNegatedInteger(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), isNegatedInteger(), and N.

Referenced by performAddSubCombine().

performNEONPostLDSTCombine()

static SDValue performNEONPostLDSTCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.

Definition at line 21117 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::SelectionDAG::getRegister(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm_unreachable, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, and llvm::AArch64ISD::ST4post.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performNVCASTCombine()

static SDValue performNVCASTCombine ( SDNode *  N )

static

Get rid of unnecessary NVCASTs (that don't change the type).

Definition at line 22308 of file AArch64ISelLowering.cpp.

References N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performORCombine()

static SDValue performORCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget, const AArch64TargetLowering &  TLI  )

static

Definition at line 16972 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::isTypeLegal(), N, performANDORCSELCombine(), and tryCombineToBSL().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::LoongArchTargetLowering::PerformDAGCombine(), llvm::MipsTargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

performOrXorChainCombine()

static SDValue performOrXorChainCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 8947 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, Cond, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::Value::hasOneUse(), I, llvm::isNullConstant(), isOrXorChain(), LHS, N, llvm::ISD::OR, RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::SmallVectorBase< Size_T >::size().

Referenced by performSETCCCombine().

performPostLD1Combine()

static SDValue performPostLD1Combine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, bool  IsLaneOp  )

static

Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R.

Definition at line 20489 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::SelectionDAG::getRegister(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::ISD::LOAD, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::Vector.

Referenced by performDUPCombine(), and performInsertVectorEltCombine().

performReinterpretCastCombine()

static SDValue performReinterpretCastCombine ( SDNode *  N )

static

Definition at line 17064 of file AArch64ISelLowering.cpp.

References llvm::SDValue::getValueType(), N, and llvm::AArch64ISD::REINTERPRET_CAST.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performScalarToVectorCombine()

static SDValue performScalarToVectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 23139 of file AArch64ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isNullConstant(), N, llvm::AArch64ISD::NVCAST, llvm::AArch64ISD::UADDLV, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performScatterStoreCombine()

static SDValue performScatterStoreCombine ( SDNode *  N, SelectionDAG &  DAG, unsigned  Opcode, bool  OnlyPackedOffsets = true  )

static

Definition at line 22427 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::sampleprof::Base, llvm::ISD::BITCAST, DL, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getScaledOffsetForBitWidth(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::isFloatingPoint(), llvm::EVT::isFloatingPoint(), llvm::EVT::isScalableVector(), isValidImmForSVEVecImmAddrMode(), N, llvm::Offset, llvm::AArch64ISD::SST1_IMM_PRED, llvm::AArch64ISD::SST1_PRED, llvm::AArch64ISD::SST1_UXTW_PRED, llvm::AArch64ISD::SSTNT1_INDEX_PRED, llvm::AArch64ISD::SSTNT1_PRED, llvm::AArch64::SVEBitsPerBlock, and std::swap().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSelectCombine()

static SDValue performSelectCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar.

This replaces any scalar setcc in the above pattern with a vector one followed by a DUP shuffle on the result.

Definition at line 22203 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isScalableVT(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), LHS, N, RHS, llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::SETCC.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSetccAddFolding()

static SDValue performSetccAddFolding ( SDNode *  Op, SelectionDAG &  DAG  )

static

Definition at line 18017 of file AArch64ISelLowering.cpp.

References SetCCInfo::AArch64, llvm::ISD::ADD, assert(), GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, isSetCCOrZExtSetCC(), LHS, GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, RHS, and std::swap().

Referenced by performAddSubLongCombine().

performSETCCCombine()

static SDValue performSETCCCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 21807 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::ISD::BITCAST, Cond, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::EVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::Value::hasOneUse(), llvm::isAllOnesConstant(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVector(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), LHS, N, performOrXorChainCombine(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, tryToWidenSetCCOperands(), llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_OR, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

performSetccMergeZeroCombine()

static SDValue performSetccMergeZeroCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 21945 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, assert(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), isAllActivePredicate(), isZerosVector(), LHS, N, performSetCCPunpkCombine(), RHS, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SETNE, and llvm::ISD::SIGN_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSetCCPunpkCombine()

static SDValue performSetCCPunpkCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 21906 of file AArch64ISelLowering.cpp.

References Cond, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), isZerosVector(), LHS, N, llvm::AArch64ISD::PTRUE, RHS, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SETNE, and llvm::ISD::SIGN_EXTEND.

Referenced by performSetccMergeZeroCombine().

performSignExtendInRegCombine()

static SDValue performSignExtendInRegCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 22633 of file AArch64ISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, EnableCombineMGatherIntrinsics, llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::AArch64ISD::GLDNT1S_MERGE_ZERO, I, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LD1S_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDFF1S_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1S_MERGE_ZERO, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64ISD::SUNPKHI, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::UUNPKHI, and llvm::AArch64ISD::UUNPKLO.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSignExtendSetCCCombine()

static SDValue performSignExtendSetCCCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 19687 of file AArch64ISelLowering.cpp.

References assert(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDNode::getValueType(), isCheapToExtend(), llvm::EVT::isInteger(), N, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by performExtendCombine().

performSpliceCombine()

static SDValue performSpliceCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 20145 of file AArch64ISelLowering.cpp.

References assert(), N, and llvm::AArch64ISD::SPLICE.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performST1Combine()

static SDValue performST1Combine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19896 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::Data, DL, llvm::SelectionDAG::getNode(), getSVEContainerType(), llvm::SelectionDAG::getValueType(), llvm::EVT::isFloatingPoint(), N, and llvm::AArch64ISD::ST1_PRED.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSTNT1Combine()

static SDValue performSTNT1Combine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 19922 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), llvm::Data, DL, llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::isFloatingPoint(), N, and llvm::ISD::UNINDEXED.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSTORECombine()

static SDValue performSTORECombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 20859 of file AArch64ISelLowering.cpp.

References combineBoolVectorAndTruncateStore(), foldTruncStoreOfExt(), llvm::ISD::FP_ROUND, llvm::EVT::getFixedSizeInBits(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::EVT::getVectorElementType(), llvm::Value::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isFixedLengthVector(), N, performTBISimplification(), Ptr, splitStores(), llvm::AArch64Subtarget::supportsAddressTopByteIgnored(), trySimplifySrlAddToRshrnb(), and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSubAddMULCombine()

static SDValue performSubAddMULCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18552 of file AArch64ISelLowering.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::M1(), llvm::ISD::MUL, N, llvm::peekThroughBitcasts(), llvm::AArch64ISD::SMULL, llvm::ISD::SUB, llvm::AArch64ISD::UMULL, and X.

Referenced by performAddSubCombine().

performSubsToAndsCombine()

static SDValue performSubsToAndsCombine ( SDNode *  N, SDNode *  SubsNode, SDNode *  AndNode, SelectionDAG &  DAG, unsigned  CCIndex, unsigned  CmpIndex, unsigned  CC  )

static

Definition at line 21436 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ANDS, assert(), CC, DL, llvm::AArch64CC::EQ, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::AArch64CC::HI, llvm::APInt::isMask(), llvm::APInt::isPowerOf2(), llvm::AArch64CC::LO, N, and llvm::AArch64CC::NE.

Referenced by performCONDCombine().

performSunpkloCombine()

static SDValue performSunpkloCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 20470 of file AArch64ISelLowering.cpp.

References CC, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), N, and llvm::ISD::SIGN_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performSVEAndCombine()

static SDValue performSVEAndCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17075 of file AArch64ISelLowering.cpp.

References llvm::And, llvm::ISD::AND, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, EnableCombineMGatherIntrinsics, llvm::ISD::EXTLOAD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, isAllActivePredicate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isConstantSplatVectorMaskForType(), llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, N, llvm::ISD::SPLAT_VECTOR, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, and llvm::ISD::ZEXTLOAD.

Referenced by performANDCombine().

performSVEMulAddSubCombine()

static SDValue performSVEMulAddSubCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 18588 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::EVT::isScalableVector(), llvm::AArch64ISD::MUL_PRED, N, and llvm::ISD::SUB.

Referenced by performAddSubCombine().

performSVESpliceCombine()

static SDValue performSVESpliceCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 22876 of file AArch64ISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), getPackedSVEVectorVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), Idx, llvm::EVT::isInteger(), LHS, N, RHS, and llvm::ISD::VECTOR_SPLICE.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performTBISimplification()

static bool performTBISimplification ( SDValue  Addr, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Simplify Addr given that the top byte of it is ignored by HW during address translation.

Definition at line 20605 of file AArch64ISelLowering.cpp.

References Addr, llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and llvm::TargetLowering::SimplifyDemandedBits().

Referenced by performLOADCombine(), and performSTORECombine().

performTBZCombine()

static SDValue performTBZCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 22064 of file AArch64ISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getTestBitOperand(), N, llvm::AArch64ISD::TBNZ, and llvm::AArch64ISD::TBZ.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performTruncateCombine()

static SDValue performTruncateCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18441 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::DUP, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::is64BitVector(), llvm::EVT::isFixedLengthVector(), N, and llvm::ISD::TRUNCATE.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performUADDVAddCombine()

static SDValue performUADDVAddCombine ( SDValue  A, SelectionDAG &  DAG  )

static

Definition at line 16049 of file AArch64ISelLowering.cpp.

References A, llvm::ISD::ADD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), performUADDVAddCombine(), llvm::AArch64ISD::SADDLP, llvm::ISD::SIGN_EXTEND, llvm::AArch64ISD::UADDLP, and llvm::ISD::ZERO_EXTEND.

Referenced by performUADDVAddCombine(), and performUADDVCombine().

performUADDVCombine()

static SDValue performUADDVCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 16097 of file AArch64ISelLowering.cpp.

References A, llvm::ISD::ADD, llvm::SelectionDAG::getNode(), N, and performUADDVAddCombine().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performUnpackCombine()

static SDValue performUnpackCombine ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 20155 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::changeVectorElementType(), DL, llvm::MaskedLoadStoreSDNode::getAddressingMode(), llvm::MaskedLoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::MaskedLoadSDNode::getExtensionType(), llvm::MaskedLoadSDNode::getMask(), llvm::SelectionDAG::getMaskedLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::SDValue::getNode(), llvm::getNumElementsFromSVEPredPattern(), llvm::MaskedLoadSDNode::getOffset(), llvm::MaskedLoadSDNode::getPassThru(), getPTrue(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::EVT::getVectorElementType(), llvm::SDNode::isUndef(), llvm::MaskedLoadStoreSDNode::isUnindexed(), isZerosVector(), llvm::ISD::MLOAD, N, llvm::AArch64ISD::PTRUE, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, and llvm::ISD::ZEXTLOAD.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performUzpCombine()

static SDValue performUzpCombine ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 20255 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::DataLayout::isLittleEndian(), llvm::EVT::isSimple(), llvm_unreachable, N, llvm::MVT::SimpleTy, llvm::ISD::TRUNCATE, trySimplifySrlAddToRshrnb(), llvm::ISD::UNDEF, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, llvm::AArch64ISD::UZP1, and X.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performVecReduceAddCombine()

static SDValue performVecReduceAddCombine ( SDNode *  N, SelectionDAG &  DAG, const AArch64Subtarget *  ST  )

static

Definition at line 15946 of file AArch64ISelLowering.cpp.

References A, llvm::ISD::ADD, B, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), I, llvm::EVT::isScalableVT(), llvm::ISD::MUL, N, performVecReduceAddCombineWithUADDLP(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AArch64ISD::SDOT, llvm::ISD::SIGN_EXTEND, llvm::AArch64ISD::UDOT, llvm::ISD::VECREDUCE_ADD, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performVecReduceAddCombineWithUADDLP()

static SDValue performVecReduceAddCombineWithUADDLP ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 15865 of file AArch64ISelLowering.cpp.

References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ABS, llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, llvm::AArch64ISD::UADDLP, llvm::ISD::VECREDUCE_ADD, and llvm::ISD::ZERO_EXTEND.

Referenced by performVecReduceAddCombine().

performVecReduceBitwiseCombine()

static SDValue performVecReduceBitwiseCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG  )

static

Definition at line 21792 of file AArch64ISelLowering.cpp.

References DL, llvm::SDValue::getValueType(), getVectorBitwiseReduce(), llvm::EVT::getVectorElementType(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isPow2VectorType(), and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performVectorAddSubExtCombine()

static SDValue performVectorAddSubExtCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18363 of file AArch64ISelLowering.cpp.

References DL, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::EVT::isFixedLengthVector(), N, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by performAddSubCombine().

performVectorCompareAndMaskUnaryOpCombine()

static SDValue performVectorCompareAndMaskUnaryOpCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 16575 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::isVector(), N, and llvm::ISD::SETCC.

Referenced by performIntToFpCombine().

performVectorShiftCombine()

static SDValue performVectorShiftCombine ( SDNode *  N, const AArch64TargetLowering &  TLI, TargetLowering::DAGCombinerInfo &  DCI  )

static

Optimize a vector shift instruction and its operand if shifted out bits are not used.

Definition at line 20442 of file AArch64ISelLowering.cpp.

References assert(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getLowBitsSet(), N, llvm::TargetLowering::SimplifyDemandedBits(), llvm::AArch64ISD::VASHR, llvm::AArch64ISD::VLSHR, and llvm::AArch64ISD::VSHL.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performVSelectCombine()

static SDValue performVSelectCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 22133 of file AArch64ISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::ElementCount::getFixed(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::is_contained(), isAllActivePredicate(), isAllInactivePredicate(), llvm::ISD::isConstantSplatVector(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::APInt::isOne(), llvm::EVT::isSimple(), N, llvm::Or, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::MVT::SimpleTy, llvm::ISD::SRA, trySwapVSelectOperands(), and llvm::ISD::VSELECT.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

performXorCombine()

static SDValue performXorCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const AArch64Subtarget *  Subtarget  )

static

Definition at line 16105 of file AArch64ISelLowering.cpp.

References foldVectorXorShiftIntoCmp(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and N.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

ReconstructShuffleWithRuntimeMask()

SDValue ReconstructShuffleWithRuntimeMask	(	SDValue	Op,
		SelectionDAG &	DAG
	)

Definition at line 10499 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorBase< Size_T >::empty(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isScalableVector(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

ReconstructTruncateFromBuildVector()

static SDValue ReconstructTruncateFromBuildVector ( SDValue  V, SelectionDAG &  DAG  )

static

Definition at line 10911 of file AArch64ISelLowering.cpp.

References assert(), llvm::sampleprof::Base, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::TRUNCATE, X, and Y.

removeRedundantInsertVectorElt()

static SDValue removeRedundantInsertVectorElt ( SDNode *  N )

static

Definition at line 22832 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isConstantSplatVectorAllZeros(), isLanes1toNKnownZero(), llvm::isNullConstant(), and N.

Referenced by performInsertVectorEltCombine().

ReplaceAddWithADDP()

static void ReplaceAddWithADDP ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 23742 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADDP, assert(), llvm::ISD::CONCAT_VECTORS, DL, E, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::EVT::is256BitVector(), llvm::EVT::isFloatingPoint(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Results, llvm::SelectionDAG::SplitVector(), and X.

ReplaceATOMIC_LOAD_128Results()

static void ReplaceATOMIC_LOAD_128Results ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 24018 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::BUILD_PAIR, getAtomicLoad128Opcode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::DataLayout::isBigEndian(), llvm::Lo, N, Ptr, Results, llvm::SelectionDAG::setNodeMemRefs(), llvm::SelectionDAG::SplitScalar(), std::swap(), and llvm::ISD::XOR.

replaceBoolVectorBitcast()

static void replaceBoolVectorBitcast ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG  )

static

Definition at line 23648 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::DWARFExpression::Operation::getNumOperands(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::EVT::isVector(), N, Results, and vectorToScalarBitmask().

ReplaceCMP_SWAP_128Results()

static void ReplaceCMP_SWAP_128Results ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 23855 of file AArch64ISelLowering.cpp.

References llvm::Acquire, llvm::AcquireRelease, assert(), llvm::ISD::BUILD_PAIR, createGPRPairNode(), DL, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::DataLayout::isBigEndian(), llvm_unreachable, llvm::Lo, llvm::Monotonic, N, llvm::Release, Results, llvm::SequentiallyConsistent, llvm::SelectionDAG::setNodeMemRefs(), llvm::SelectionDAG::SplitScalar(), and std::swap().

ReplaceReductionResults()

static void ReplaceReductionResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, unsigned  InterOp, unsigned  AcrossOp  )

static

Definition at line 23789 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::Hi, llvm::Lo, N, Results, and llvm::SelectionDAG::SplitVectorOperand().

replaceSplatVectorStore()

static SDValue replaceSplatVectorStore ( SelectionDAG &  DAG, StoreSDNode &  St  )

static

Replace a splat of a scalar to a vector store by scalar stores of the scalar value.

The load store optimizer pass will merge them to store pair stores. This has better performance than a splat of the scalar followed by a split vector store. Even if the stores are not merged it is four stores vs a dup, followed by an ext.b and two stores.

Definition at line 20021 of file AArch64ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::StoreSDNode::isTruncatingStore(), and splitStoreSplat().

Referenced by splitStores().

replaceZeroVectorStore()

static SDValue replaceZeroVectorStore ( SelectionDAG &  DAG, StoreSDNode &  St  )

static

Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.

The load store optimizer pass will merge them to store pair stores. This should be better than a movi to create the vector zero followed by a vector store if the zero constant is not re-used, since one instructions and one register live range will be removed.

For example, the final generated code should be:

stp xzr, xzr, [x0]

instead of:

movi v0.2d, #0 str q0, [x0]

Definition at line 19954 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, DL, llvm::StoreSDNode::getBasePtr(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), I, llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isNullConstant(), llvm::isNullFPConstant(), llvm::EVT::isScalableVector(), llvm::StoreSDNode::isTruncatingStore(), llvm::Offset, and splitStoreSplat().

Referenced by splitStores().

resolveBuildVector()

static bool resolveBuildVector ( BuildVectorSDNode *  BVN, APInt &  CnstBits, APInt &  UndefBits  )

static

Definition at line 11996 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::BuildVectorSDNode::isConstantSplat(), and llvm::APInt::zextOrTrunc().

Referenced by ConstantBuildVector(), EmitVectorComparison(), and performANDCombine().

selectUmullSmull()

static unsigned selectUmullSmull ( SDNode *&  N0, SDNode *&  N1, SelectionDAG &  DAG, SDLoc  DL, bool &  IsMLA  )

static

Definition at line 4549 of file AArch64ISelLowering.cpp.

References DL, llvm::APInt::getHighBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), isAddSubSExt(), isAddSubZExt(), isExtendedBUILD_VECTOR(), isSignExtended(), isZeroExtended(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::SelectionDAG::SignBitIsZero(), llvm::MVT::SimpleTy, llvm::AArch64ISD::SMULL, std::swap(), llvm::ISD::TRUNCATE, and llvm::AArch64ISD::UMULL.

setInfoSVEStN()

template<unsigned NumVecs>

static bool setInfoSVEStN ( const AArch64TargetLowering &  TLI, const DataLayout &  DL, AArch64TargetLowering::IntrinsicInfo &  Info, const CallInst &  CI  )

static

Set the IntrinsicInfo for the aarch64_sve_st<N> intrinsics.

Definition at line 13905 of file AArch64ISelLowering.cpp.

References llvm::CallBase::arg_size(), assert(), DL, llvm::CallBase::getArgOperand(), llvm::Type::getContext(), llvm::TargetLoweringBase::getMemValueType(), llvm::EVT::getScalarType(), llvm::Value::getType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), I, Info, llvm::ISD::INTRINSIC_VOID, and llvm::MachineMemOperand::MOStore.

skipExtensionForVectorMULL()

static SDValue skipExtensionForVectorMULL ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 4424 of file AArch64ISelLowering.cpp.

References addRequiredExtensionForVectorMULL(), assert(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ISD::isExtOpcode(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::APInt::zextOrTrunc().

splitStores()

static SDValue splitStores ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, SelectionDAG &  DAG, const AArch64Subtarget *  Subtarget  )

static

Definition at line 20074 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::MachineFunction::getFunction(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::StoreSDNode::getValue(),