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LLVM
14.0.0git
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#include "AArch64ISelLowering.h"#include "AArch64CallingConvention.h"#include "AArch64ExpandImm.h"#include "AArch64MachineFunctionInfo.h"#include "AArch64PerfectShuffle.h"#include "AArch64RegisterInfo.h"#include "AArch64Subtarget.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "Utils/AArch64BaseInfo.h"#include "llvm/ADT/APFloat.h"#include "llvm/ADT/APInt.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/StringRef.h"#include "llvm/ADT/Triple.h"#include "llvm/ADT/Twine.h"#include "llvm/Analysis/ObjCARCUtil.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/Analysis.h"#include "llvm/CodeGen/CallingConvLower.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/RuntimeLibcalls.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/CodeGen/TargetCallingConv.h"#include "llvm/CodeGen/TargetInstrInfo.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/Attributes.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DebugLoc.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/GetElementPtrTypeIterator.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/Instruction.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/IntrinsicInst.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/IntrinsicsAArch64.h"#include "llvm/IR/Module.h"#include "llvm/IR/OperandTraits.h"#include "llvm/IR/PatternMatch.h"#include "llvm/IR/Type.h"#include "llvm/IR/Use.h"#include "llvm/IR/Value.h"#include "llvm/MC/MCRegisterInfo.h"#include "llvm/Support/Casting.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MachineValueType.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetOptions.h"#include <algorithm>#include <bitset>#include <cassert>#include <cctype>#include <cstdint>#include <cstdlib>#include <iterator>#include <limits>#include <tuple>#include <utility>#include <vector>#include "AArch64GenAsmMatcher.inc"Go to the source code of this file.
Classes | |
| struct | GenericSetCCInfo |
| Helper structure to keep track of ISD::SET_CC operands. More... | |
| struct | AArch64SetCCInfo |
| Helper structure to keep track of a SET_CC lowered into AArch64 code. More... | |
| union | SetCCInfo |
| Helper structure to keep track of SetCC information. More... | |
| struct | SetCCInfoAndKind |
| Helper structure to be able to read SetCC information. More... | |
Macros | |
| #define | DEBUG_TYPE "aarch64-lower" |
| #define | LCALLNAMES(A, B, N) |
| #define | LCALLNAME4(A, B) |
| #define | LCALLNAME5(A, B) |
| #define | MAKE_CASE(V) |
| #define | GET_REGISTER_MATCHER |
Enumerations | |
| enum | PredicateConstraint { Upl, Upa, Invalid } |
Functions | |
| STATISTIC (NumTailCalls, "Number of tail calls") | |
| STATISTIC (NumShiftInserts, "Number of vector shift inserts") | |
| STATISTIC (NumOptimizedImms, "Number of times immediates were optimized") | |
| static EVT | getPackedSVEVectorVT (EVT VT) |
| static EVT | getPackedSVEVectorVT (ElementCount EC) |
| static EVT | getPromotedVTForPredicate (EVT VT) |
| static bool | isPackedVectorType (EVT VT, SelectionDAG &DAG) |
| Returns true if VT's elements occupy the lowest bit positions of its associated register class without any intervening space. More... | |
| static bool | isMergePassthruOpcode (unsigned Opc) |
| static bool | optimizeLogicalImm (SDValue Op, unsigned Size, uint64_t Imm, const APInt &Demanded, TargetLowering::TargetLoweringOpt &TLO, unsigned NewOpc) |
| static EVT | getContainerForFixedLengthVector (SelectionDAG &DAG, EVT VT) |
| static SDValue | convertToScalableVector (SelectionDAG &DAG, EVT VT, SDValue V) |
| static SDValue | convertFromScalableVector (SelectionDAG &DAG, EVT VT, SDValue V) |
| static SDValue | convertFixedMaskToScalableVector (SDValue Mask, SelectionDAG &DAG) |
| static bool | isZerosVector (const SDNode *N) |
| isZerosVector - Check whether SDNode N is a zero-filled vector. More... | |
| static AArch64CC::CondCode | changeIntCCToAArch64CC (ISD::CondCode CC) |
| changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC More... | |
| static void | changeFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2) |
| changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. More... | |
| static void | changeFPCCToANDAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2) |
| Convert a DAG fp condition code to an AArch64 CC. More... | |
| static void | changeVectorFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) |
| changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions. More... | |
| static bool | isLegalArithImmed (uint64_t C) |
| static bool | isCMN (SDValue Op, ISD::CondCode CC) |
| static SDValue | emitStrictFPComparison (SDValue LHS, SDValue RHS, const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, bool IsSignaling) |
| static SDValue | emitComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) |
| static unsigned | getCmpOperandFoldingProfit (SDValue Op) |
| Returns how profitable it is to fold a comparison's operand's shift and/or extension operations. More... | |
| static SDValue | getAArch64Cmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) |
| static std::pair< SDValue, SDValue > | getAArch64XALUOOp (AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerXALUO (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerPREFETCH (SDValue Op, SelectionDAG &DAG) |
| static MVT | getSVEContainerType (EVT ContentTy) |
| static EVT | getExtensionTo64Bits (const EVT &OrigVT) |
| static SDValue | addRequiredExtensionForVectorMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) |
| static bool | isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned) |
| static SDValue | skipExtensionForVectorMULL (SDNode *N, SelectionDAG &DAG) |
| static bool | isSignExtended (SDNode *N, SelectionDAG &DAG) |
| static bool | isZeroExtended (SDNode *N, SelectionDAG &DAG) |
| static bool | isAddSubSExt (SDNode *N, SelectionDAG &DAG) |
| static bool | isAddSubZExt (SDNode *N, SelectionDAG &DAG) |
| static SDValue | getPTrue (SelectionDAG &DAG, SDLoc DL, EVT VT, int Pattern) |
| static SDValue | lowerConvertToSVBool (SDValue Op, SelectionDAG &DAG) |
| unsigned | getGatherVecOpcode (bool IsScaled, bool IsSigned, bool NeedsExtend) |
| unsigned | getScatterVecOpcode (bool IsScaled, bool IsSigned, bool NeedsExtend) |
| unsigned | getSignExtendedGatherOpcode (unsigned Opcode) |
| bool | getGatherScatterIndexIsExtended (SDValue Index) |
| void | selectGatherScatterAddrMode (SDValue &BasePtr, SDValue &Index, EVT MemVT, unsigned &Opcode, bool IsGather, SelectionDAG &DAG) |
| static SDValue | LowerTruncateVectorStore (SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG) |
| static bool | canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls) |
| Return true if the calling convention is one that we can guarantee TCO for. More... | |
| static bool | mayTailCallThisCC (CallingConv::ID CC) |
| Return true if we might ever do TCO for calls with this calling convention. More... | |
| std::pair< SDValue, uint64_t > | lookThroughSignExtension (SDValue Val) |
| static SDValue | getEstimate (const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps) |
| static PredicateConstraint | parsePredicateConstraint (StringRef Constraint) |
| static SDValue | WidenVector (SDValue V64Reg, SelectionDAG &DAG) |
| WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class. More... | |
| static unsigned | getExtFactor (SDValue &V) |
| getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction. More... | |
| static SDValue | NarrowVector (SDValue V128Reg, SelectionDAG &DAG) |
| NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. More... | |
| static bool | isSingletonEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm) |
| static bool | isWideDUPMask (ArrayRef< int > M, EVT VT, unsigned BlockSize, unsigned &DupLaneOp) |
| Check if a vector shuffle corresponds to a DUP instructions with a larger element width than the vector lane type. More... | |
| static bool | isEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm) |
| static bool | isREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize) |
| isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize. More... | |
| static bool | isZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isINSMask (ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly) |
| static bool | isConcatMask (ArrayRef< int > Mask, EVT VT, bool SplitLHS) |
| static SDValue | tryFormConcatFromShuffle (SDValue Op, SelectionDAG &DAG) |
| static SDValue | GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) |
| GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More... | |
| static SDValue | GenerateTBL (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG) |
| static unsigned | getDUPLANEOp (EVT EltType) |
| static SDValue | constructDup (SDValue V, int Lane, SDLoc dl, EVT VT, unsigned Opcode, SelectionDAG &DAG) |
| static bool | resolveBuildVector (BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits) |
| static SDValue | tryAdvSIMDModImm64 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static SDValue | tryAdvSIMDModImm32 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr) |
| static SDValue | tryAdvSIMDModImm16 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr) |
| static SDValue | tryAdvSIMDModImm321s (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static SDValue | tryAdvSIMDModImm8 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static SDValue | tryAdvSIMDModImmFP (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static bool | isAllConstantBuildVector (const SDValue &PotentialBVec, uint64_t &ConstVal) |
| static unsigned | getIntrinsicID (const SDNode *N) |
| static SDValue | tryLowerToSLI (SDNode *N, SelectionDAG &DAG) |
| static SDValue | NormalizeBuildVector (SDValue Op, SelectionDAG &DAG) |
| static SDValue | ConstantBuildVector (SDValue Op, SelectionDAG &DAG) |
| static bool | getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt) |
| getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More... | |
| static bool | isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt) |
| isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More... | |
| static bool | isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) |
| isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More... | |
| static SDValue | EmitVectorComparison (SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) |
| static SDValue | getReductionSDNode (unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG) |
| template<unsigned NumVecs> | |
| static bool | setInfoSVEStN (const AArch64TargetLowering &TLI, const DataLayout &DL, AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI) |
Set the IntrinsicInfo for the aarch64_sve_st<N> intrinsics. More... | |
| static bool | areExtractShuffleVectors (Value *Op1, Value *Op2) |
| Check if both Op1 and Op2 are shufflevector extracts of either the lower or upper half of the vector elements. More... | |
| static bool | areExtractExts (Value *Ext1, Value *Ext2) |
| Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements. More... | |
| static bool | isOperandOfVmullHighP64 (Value *Op) |
| Check if Op could be used with vmull_high_p64 intrinsic. More... | |
| static bool | areOperandsOfVmullHighP64 (Value *Op1, Value *Op2) |
| Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic. More... | |
| static SDValue | foldVectorXorShiftIntoCmp (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0. More... | |
| static SDValue | performVecReduceAddCombineWithUADDLP (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performVecReduceAddCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *ST) |
| static SDValue | performXorCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static bool | IsSVECntIntrinsic (SDValue S) |
| static EVT | calculatePreExtendType (SDValue Extend, SelectionDAG &DAG) |
Calculates what the pre-extend type is, based on the extension operation node provided by Extend. More... | |
| static SDValue | performCommonVectorExtendCombine (SDValue VectorShuffle, SelectionDAG &DAG) |
| Combines a dup(sext/zext) node pattern into sext/zext(dup) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt. More... | |
| static SDValue | performMulVectorExtendCombine (SDNode *Mul, SelectionDAG &DAG) |
| Combines a mul(dup(sext/zext)) node pattern into mul(sext/zext(dup)) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt. More... | |
| static SDValue | performMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performIntToFpCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performFpToIntCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| Fold a floating-point multiply by power of two into floating-point to fixed-point conversion. More... | |
| static SDValue | performFDivCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| Fold a floating-point divide by power of two into fixed-point to floating-point conversion. More... | |
| static bool | findEXTRHalf (SDValue N, SDValue &Src, uint32_t &ShiftAmount, bool &FromHi) |
| An EXTR instruction is made up of two shifts, ORed together. More... | |
| static SDValue | tryCombineToEXTR (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair. More... | |
| static SDValue | tryCombineToBSL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static bool | isConstantSplatVectorMaskForType (SDNode *N, EVT MemVT) |
| static SDValue | performSVEAndCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performSRLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performVectorTruncateCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static bool | hasPairwiseAdd (unsigned Opcode, EVT VT, bool FullFP16) |
| static SDValue | performExtractVectorEltCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performConcatVectorsCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineFixedPointConvert (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryExtendDUPToExtractHigh (SDValue N, SelectionDAG &DAG) |
| static bool | isEssentiallyExtractHighSubvector (SDValue N) |
| static bool | isSetCC (SDValue Op, SetCCInfoAndKind &SetCCInfo) |
Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one. More... | |
| static bool | isSetCCOrZExtSetCC (const SDValue &Op, SetCCInfoAndKind &Info) |
| static SDValue | performSetccAddFolding (SDNode *Op, SelectionDAG &DAG) |
| static SDValue | performUADDVCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performAddDotCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performAddSubLongCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performAddSubCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineLongOpWithDup (unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineShiftImm (unsigned IID, SDNode *N, SelectionDAG &DAG) |
| static SDValue | tryCombineCRC32 (unsigned Mask, SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineAcrossLanesIntrinsic (unsigned Opc, SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntrinsicIndex (SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntrinsicDUP (SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntrinsicEXT (SDNode *N, SelectionDAG &DAG) |
| static SDValue | tryConvertSVEWideCompare (SDNode *N, ISD::CondCode CC, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | getPTest (SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, AArch64CC::CondCode Cond) |
| static SDValue | combineSVEReductionInt (SDNode *N, unsigned Opc, SelectionDAG &DAG) |
| static SDValue | combineSVEReductionFP (SDNode *N, unsigned Opc, SelectionDAG &DAG) |
| static SDValue | combineSVEReductionOrderedFP (SDNode *N, unsigned Opc, SelectionDAG &DAG) |
| static bool | isAllActivePredicate (SDValue N) |
| static SDValue | convertMergedOpToPredOp (SDNode *N, unsigned Opc, SelectionDAG &DAG, bool UnpredOp=false, bool SwapOperands=false) |
| static SDValue | performIntrinsicCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | splitStoreSplat (SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts) |
| static SDValue | performLD1Combine (SDNode *N, SelectionDAG &DAG, unsigned Opc) |
| static SDValue | performLDNT1Combine (SDNode *N, SelectionDAG &DAG) |
| template<unsigned Opcode> | |
| static SDValue | performLD1ReplicateCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performST1Combine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performSTNT1Combine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | replaceZeroVectorStore (SelectionDAG &DAG, StoreSDNode &St) |
| Replace a splat of zeros to a vector store by scalar stores of WZR/XZR. More... | |
| static SDValue | replaceSplatVectorStore (SelectionDAG &DAG, StoreSDNode &St) |
| Replace a splat of a scalar to a vector store by scalar stores of the scalar value. More... | |
| static SDValue | splitStores (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performSpliceCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performUzpCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performGLD1Combine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performVectorShiftCombine (SDNode *N, const AArch64TargetLowering &TLI, TargetLowering::DAGCombinerInfo &DCI) |
| Optimize a vector shift instruction and its operand if shifted out bits are not used. More... | |
| static SDValue | performPostLD1Combine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp) |
| Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R. More... | |
| static bool | performTBISimplification (SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
Simplify Addr given that the top byte of it is ignored by HW during address translation. More... | |
| static SDValue | foldTruncStoreOfExt (SelectionDAG &DAG, SDNode *N) |
| static SDValue | performSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performNEONPostLDSTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates. More... | |
| static bool | checkValueWidth (SDValue V, unsigned width, ISD::LoadExtType &ExtType) |
| static bool | isEquivalentMaskless (unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant) |
| static SDValue | performCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) |
| static SDValue | performBRCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performCSELCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performSETCCCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performSetccMergeZeroCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | getTestBitOperand (SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) |
| static SDValue | performTBZCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performVSelectCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performSelectCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar. More... | |
| static SDValue | performNVCASTCombine (SDNode *N) |
| Get rid of unnecessary NVCASTs (that don't change the type). More... | |
| static SDValue | performGlobalAddressCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM) |
| static SDValue | getScaledOffsetForBitWidth (SelectionDAG &DAG, SDValue Offset, SDLoc DL, unsigned BitWidth) |
| static bool | isValidImmForSVEVecImmAddrMode (unsigned OffsetInBytes, unsigned ScalarSizeInBytes) |
Check if the value of OffsetInBytes can be used as an immediate for the gather load/prefetch and scatter store instructions with vector base and immediate offset addressing mode: More... | |
| static bool | isValidImmForSVEVecImmAddrMode (SDValue Offset, unsigned ScalarSizeInBytes) |
Check if the value of Offset represents a valid immediate for the SVE gather load/prefetch and scatter store instructiona with vector base and immediate offset addressing mode: More... | |
| static SDValue | performScatterStoreCombine (SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets=true) |
| static SDValue | performGatherLoadCombine (SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets=true) |
| static SDValue | performSignExtendInRegCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | legalizeSVEGatherPrefetchOffsVec (SDNode *N, SelectionDAG &DAG) |
| Legalize the gather prefetch (scalar + vector addressing mode) when the offset vector is an unpacked 32-bit scalable vector. More... | |
| static SDValue | combineSVEPrefetchVecBaseImmOff (SDNode *N, SelectionDAG &DAG, unsigned ScalarSizeInBytes) |
Combines a node carrying the intrinsic aarch64_sve_prf<T>_gather_scalar_offset into a node that uses aarch64_sve_prfb_gather_uxtw_index when the scalar offset passed to aarch64_sve_prf<T>_gather_scalar_offset is not a valid immediate for the sve gather prefetch instruction with vector plus immediate addressing mode. More... | |
| static bool | isLanes1toNKnownZero (SDValue Op) |
| static SDValue | removeRedundantInsertVectorElt (SDNode *N) |
| static SDValue | performInsertVectorEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| SDValue | performSVESpliceCombine (SDNode *N, SelectionDAG &DAG) |
| static void | ReplaceReductionResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp) |
| static std::pair< SDValue, SDValue > | splitInt128 (SDValue N, SelectionDAG &DAG) |
| static SDValue | createGPRPairNode (SelectionDAG &DAG, SDValue V) |
| static void | ReplaceCMP_SWAP_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static Value * | UseTlsOffset (IRBuilderBase &IRB, unsigned Offset) |
| static SDValue | getPredicateForFixedLengthVector (SelectionDAG &DAG, SDLoc &DL, EVT VT) |
| static SDValue | getPredicateForScalableVector (SelectionDAG &DAG, SDLoc &DL, EVT VT) |
| static SDValue | getPredicateForVector (SelectionDAG &DAG, SDLoc &DL, EVT VT) |
| static SDValue | emitConditionalComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) |
| can be transformed to: not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" which can be implemented as: cmp C ccmp D, inv(CD), CC ccmp A, CA, inv(CD) ccmp B, CB, inv(CA) check for CB flags More... | |
| static bool | canEmitConjunction (const SDValue Val, bool &CanNegate, bool &MustBeFirst, bool WillNegate, unsigned Depth=0) |
Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction. More... | |
| static SDValue | emitConjunctionRec (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) |
| Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops. More... | |
| static SDValue | emitConjunction (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC) |
| Emit expression as a conjunction (a series of CCMP/CFCMP ops). More... | |
Variables | |
| cl::opt< bool > | EnableAArch64ELFLocalDynamicTLSGeneration ("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false)) |
| static cl::opt< bool > | EnableOptimizeLogicalImm ("aarch64-enable-logical-imm", cl::Hidden, cl::desc("Enable AArch64 logical imm instruction " "optimization"), cl::init(true)) |
| static cl::opt< bool > | EnableCombineMGatherIntrinsics ("aarch64-enable-mgather-combine", cl::Hidden, cl::desc("Combine extends of AArch64 masked " "gather intrinsics"), cl::init(true)) |
| static const MVT | MVT_CC = MVT::i32 |
| Value type used for condition codes. More... | |
| #define DEBUG_TYPE "aarch64-lower" |
Definition at line 97 of file AArch64ISelLowering.cpp.
| #define GET_REGISTER_MATCHER |
Definition at line 8011 of file AArch64ISelLowering.cpp.
| #define MAKE_CASE | ( | V | ) |
| enum PredicateConstraint |
| Enumerator | |
|---|---|
| Upl | |
| Upa | |
| Invalid | |
Definition at line 8288 of file AArch64ISelLowering.cpp.
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Definition at line 3647 of file AArch64ISelLowering.cpp.
References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.
Referenced by skipExtensionForVectorMULL().
Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.
Definition at line 11668 of file AArch64ISelLowering.cpp.
References llvm::MipsISD::Ext, llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().
Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().
Check if both Op1 and Op2 are shufflevector extracts of either the lower or upper half of the vector elements.
Definition at line 11627 of file AArch64ISelLowering.cpp.
References llvm::TypeSize::getFixedSize(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::ShuffleVectorInst::isExtractSubvectorMask(), llvm::M1(), llvm::PatternMatch::m_Shuffle(), llvm::PatternMatch::m_Undef(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().
Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().
Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic.
Definition at line 11695 of file AArch64ISelLowering.cpp.
References isOperandOfVmullHighP64().
Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().
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Calculates what the pre-extend type is, based on the extension operation node provided by Extend.
In the case that Extend is a SIGN_EXTEND or a ZERO_EXTEND, the pre-extend type is pulled directly from the operand, while other extend operations need a bit more inspection to get this information.
| Extend | The SDNode from the DAG that represents the extend operation |
| DAG | The SelectionDAG hosting the Extend node |
Extend source type, or MVT::Other if no valid type can be determined Definition at line 12667 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::VTSDNode::getVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::ZERO_EXTEND.
Referenced by performCommonVectorExtendCombine().
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Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction.
See CMP;CCMP matching.
| CanNegate | Set to true if we can negate the whole sub-tree just by changing the conditions on the SETCC tests. (this means we can call emitConjunctionRec() with Negate==true on this sub-tree) |
| MustBeFirst | Set to true if this subtree needs to be negated and we cannot do the negation naturally. We are required to emit the subtree first in this case. |
| WillNegate | Is true if are called when the result of this subexpression must be negated. This happens when the outer expression is an OR. We can use this fact to know that we have a double negation (or (or ...) ...) that can be implemented for free. |
Definition at line 2663 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::Depth, llvm::MVT::f128, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::OR, and llvm::ISD::SETCC.
Referenced by emitConjunction(), and emitConjunctionRec().
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Return true if the calling convention is one that we can guarantee TCO for.
Definition at line 5605 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.
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changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
Definition at line 2351 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by changeFPCCToANDAArch64CC(), and changeVectorFPCCToAArch64CC().
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Convert a DAG fp condition code to an AArch64 CC.
This differs from changeFPCCToAArch64CC in that it returns cond codes that should be AND'ed instead of OR'ed.
Definition at line 2414 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, assert(), changeFPCCToAArch64CC(), llvm::AArch64CC::LE, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETONE, llvm::ISD::SETUEQ, and llvm::AArch64CC::VC.
Referenced by emitConjunctionRec().
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changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC
Definition at line 2323 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by emitConjunctionRec(), and getAArch64Cmp().
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changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions.
Fewer operations are available without a real NZCV register, so we have to use less efficient combinations to get the same effect.
Definition at line 2444 of file AArch64ISelLowering.cpp.
References changeFPCCToAArch64CC(), llvm::MVT::f32, llvm::AArch64CC::GE, llvm::ISD::getSetCCInverse(), LLVM_FALLTHROUGH, llvm::AArch64CC::MI, llvm::ISD::SETO, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.
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Definition at line 15647 of file AArch64ISelLowering.cpp.
References llvm::abs(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::Constant, llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::VTSDNode::getVT(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::TargetConstant, and llvm::ISD::ZEXTLOAD.
Referenced by performCONDCombine().
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Definition at line 14307 of file AArch64ISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i64, and N.
Referenced by performIntrinsicCombine().
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Combines a node carrying the intrinsic aarch64_sve_prf<T>_gather_scalar_offset into a node that uses aarch64_sve_prfb_gather_uxtw_index when the scalar offset passed to aarch64_sve_prf<T>_gather_scalar_offset is not a valid immediate for the sve gather prefetch instruction with vector plus immediate addressing mode.
Definition at line 16725 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, isValidImmForSVEVecImmAddrMode(), N, llvm::MVT::Other, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14480 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i64, and N.
Referenced by performIntrinsicCombine().
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Definition at line 14461 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getPackedSVEVectorVT(), llvm::MVT::i64, and N.
Referenced by performIntrinsicCombine().
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Definition at line 14497 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, and N.
Referenced by performIntrinsicCombine().
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Definition at line 10169 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::FMOV, llvm::EVT::getSizeInBits(), llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, resolveBuildVector(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), and tryAdvSIMDModImmFP().
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Definition at line 9430 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, int, and WidenVector().
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Definition at line 18208 of file AArch64ISelLowering.cpp.
References convertToScalableVector(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getNode(), getPredicateForFixedLengthVector(), llvm::BitmaskEnumDetail::Mask(), llvm::AArch64ISD::SETCC_MERGE_ZERO, and llvm::ISD::SETNE.
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Definition at line 18178 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().
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Definition at line 14545 of file AArch64ISelLowering.cpp.
References assert(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, isAllActivePredicate(), and N.
Referenced by performIntrinsicCombine().
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Definition at line 18167 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().
Referenced by convertFixedMaskToScalableVector().
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Definition at line 17380 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), llvm::ISD::SRL, std::swap(), and llvm::MVT::Untyped.
Referenced by ReplaceCMP_SWAP_128Results().
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Definition at line 2509 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, llvm::ISD::AND, llvm::AArch64ISD::ANDS, assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::AArch64ISD::FCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), isCMN(), llvm::EVT::isFloatingPoint(), llvm::isNullConstant(), llvm::ISD::isUnsignedIntSetCC(), MVT_CC, llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.
Referenced by emitConjunctionRec(), and getAArch64Cmp().
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can be transformed to: not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" which can be implemented as: cmp C ccmp D, inv(CD), CC ccmp A, CA, inv(CD) ccmp B, CB, inv(CA) check for CB flags
A counterexample is "or (and A B) (and C D)" which translates to not (and (not (and (not A) (not B))) (not (and (not C) (not D)))), we can only implement 1 of the inner (not) operations, but not both! Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
Definition at line 2615 of file AArch64ISelLowering.cpp.
References assert(), llvm::AArch64ISD::CCMN, llvm::AArch64ISD::CCMP, DL, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::AArch64ISD::FCCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::AArch64CC::getNZCVToSatisfyCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), llvm::isNullConstant(), MVT_CC, llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.
Referenced by emitConjunctionRec().
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Emit expression as a conjunction (a series of CCMP/CFCMP ops).
In some cases this is even possible with OR operations in the expression. See CMP;CCMP matching.
Definition at line 2837 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, canEmitConjunction(), and emitConjunctionRec().
Referenced by getAArch64Cmp().
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Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops.
See CMP;CCMP matching. Tries to transform the given i1 producing node Val to a series compare and conditional compare operations.
OutCC to the flags that should be tested or returns SDValue() if transformation was not possible. Negate is true if we want this sub-tree being negated just by changing SETCC conditions. Definition at line 2725 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::ISD::AND, assert(), canEmitConjunction(), changeFPCCToANDAArch64CC(), changeIntCCToAArch64CC(), DL, emitComparison(), emitConditionalComparison(), llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::yaml::isInteger(), llvm::ISD::OR, llvm::ISD::SETCC, and std::swap().
Referenced by emitConjunction().
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Definition at line 2498 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::Other, llvm::AArch64ISD::STRICT_FCMP, and llvm::AArch64ISD::STRICT_FCMPE.
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Definition at line 10940 of file AArch64ISelLowering.cpp.
References assert(), llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::AArch64CC::EQ, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::AArch64CC::GE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::EVT::isFloatingPoint(), llvm::AArch64CC::LE, LLVM_FALLTHROUGH, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, and resolveBuildVector().
An EXTR instruction is made up of two shifts, ORed together.
This helper searches for and classifies those shifts.
Definition at line 13143 of file AArch64ISelLowering.cpp.
References N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryCombineToEXTR().
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Definition at line 15467 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MipsISD::Ext, llvm::SelectionDAG::getStore(), llvm::SDValue::getValueType(), llvm::ISD::MSTORE, N, llvm::ISD::SIGN_EXTEND, llvm::SPII::Store, llvm::ISD::STORE, and llvm::ISD::ZERO_EXTEND.
Referenced by performSTORECombine().
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Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0.
Definition at line 12429 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CMGEz, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::AArch64Subtarget::hasNEON(), llvm::ISD::isBuildVectorAllOnes(), llvm::EVT::isVector(), N, Shift, and llvm::AArch64ISD::VASHR.
Referenced by performXorCombine().
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GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 9252 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::bf16, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), getExtFactor(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
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Definition at line 9355 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::makeArrayRef(), Offset, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v8i8.
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Definition at line 2885 of file AArch64ISelLowering.cpp.
References changeIntCCToAArch64CC(), emitComparison(), emitConjunction(), getCmpOperandFoldingProfit(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, INT64_MAX, isCMN(), isLegalArithImmed(), llvm::ConstantSDNode::isOne(), llvm::ConstantSDNode::isZero(), MVT_CC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND_INREG, std::swap(), UINT64_MAX, and llvm::ISD::ZEXTLOAD.
Referenced by performSetccAddFolding().
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Definition at line 3017 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, llvm::AArch64ISD::ANDS, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::AArch64CC::HS, llvm::MVT::i32, llvm::MVT::i64, llvm_unreachable, llvm::AArch64CC::LO, llvm::Mul, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, MVT_CC, llvm::AArch64CC::NE, llvm::ISD::SADDO, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SSUBO, llvm::AArch64ISD::SUBS, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::AArch64CC::VS, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerXALUO().
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Returns how profitable it is to fold a comparison's operand's shift and/or extension operations.
Definition at line 2851 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::MVT::i32, llvm::MVT::i64, llvm::BitmaskEnumDetail::Mask(), Shift, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by getAArch64Cmp().
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Definition at line 18081 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2f64, llvm::MVT::nxv2i64, llvm::MVT::nxv4f32, llvm::MVT::nxv4i32, llvm::MVT::nxv8f16, llvm::MVT::nxv8i16, and llvm::MVT::SimpleTy.
Referenced by convertFixedMaskToScalableVector().
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Definition at line 9417 of file AArch64ISelLowering.cpp.
References llvm::MVT::bf16, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, and llvm_unreachable.
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Definition at line 8141 of file AArch64ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::ARM_MB::ST, llvm::MVT::v1f32, llvm::MVT::v1f64, llvm::MVT::v2f32, llvm::MVT::v2f64, and llvm::MVT::v4f32.
Definition at line 3630 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.
Referenced by addRequiredExtensionForVectorMULL().
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getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.
Definition at line 8648 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::EVT::getVectorElementType().
Referenced by GeneratePerfectShuffle(), and llvm::AArch64TargetLowering::ReconstructShuffle().
| bool getGatherScatterIndexIsExtended | ( | SDValue | Index | ) |
Definition at line 4313 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), Index, llvm::BitmaskEnumDetail::Mask(), llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::SPLAT_VECTOR.
| unsigned getGatherVecOpcode | ( | bool | IsScaled, |
| bool | IsSigned, | ||
| bool | NeedsExtend | ||
| ) |
Definition at line 4245 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, and llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO.
Referenced by performGLD1Combine().
Definition at line 9990 of file AArch64ISelLowering.cpp.
References llvm::ISD::INTRINSIC_WO_CHAIN, N, and llvm::Intrinsic::not_intrinsic.
Referenced by collectBitParts(), FindPreallocatedCall(), llvm::VPRecipeBuilder::handleReplication(), IsSVECntIntrinsic(), performIntrinsicCombine(), and tryConvertSVEWideCompare().
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Definition at line 155 of file AArch64ISelLowering.cpp.
References llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2i64, llvm::MVT::nxv4i32, and llvm::MVT::nxv8i16.
Definition at line 130 of file AArch64ISelLowering.cpp.
References llvm::MVT::bf16, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2f64, llvm::MVT::nxv2i64, llvm::MVT::nxv4f32, llvm::MVT::nxv4i32, llvm::MVT::nxv8bf16, llvm::MVT::nxv8f16, llvm::MVT::nxv8i16, and llvm::MVT::SimpleTy.
Referenced by combineSVEReductionInt(), and performSVESpliceCombine().
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Definition at line 18106 of file AArch64ISelLowering.cpp.
References llvm::LegalityPredicates::all(), assert(), DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), getPTrue(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getSubtarget(), llvm::getSVEPredPatternFromNumElements(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::MVT::nxv16i1, llvm::MVT::nxv2i1, llvm::MVT::nxv4i1, llvm::MVT::nxv8i1, and llvm::MVT::SimpleTy.
Referenced by convertFixedMaskToScalableVector(), and getPredicateForVector().
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Definition at line 18151 of file AArch64ISelLowering.cpp.
References llvm::LegalityPredicates::all(), assert(), llvm::EVT::changeVectorElementType(), DL, getPTrue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i1, llvm::EVT::isScalableVector(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by getPredicateForVector().
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Definition at line 18159 of file AArch64ISelLowering.cpp.
References DL, getPredicateForFixedLengthVector(), getPredicateForScalableVector(), and llvm::EVT::isFixedLengthVector().
Definition at line 170 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::MVT::i1, llvm::EVT::isScalableVector(), llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2i64, llvm::MVT::nxv4i32, and llvm::MVT::nxv8i16.
Referenced by llvm::AArch64TargetLowering::getPromotedVTForPredicate().
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Definition at line 14437 of file AArch64ISelLowering.cpp.
References assert(), Cond, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::Other, llvm::AArch64ISD::PTEST, and llvm::Test.
Referenced by performIntrinsicCombine().
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Definition at line 3892 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, and llvm::AArch64ISD::PTRUE.
Referenced by getPredicateForFixedLengthVector(), getPredicateForScalableVector(), and lowerConvertToSVBool().
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Definition at line 11105 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::getValueType(), and llvm::MVT::i64.
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Definition at line 16319 of file AArch64ISelLowering.cpp.
References assert(), llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i64, llvm::Log2_32(), llvm::MVT::nxv2i64, Offset, Shift, llvm::ISD::SHL, and llvm::ISD::SPLAT_VECTOR.
Referenced by performGatherLoadCombine(), and performScatterStoreCombine().
| unsigned getScatterVecOpcode | ( | bool | IsScaled, |
| bool | IsSigned, | ||
| bool | NeedsExtend | ||
| ) |
| unsigned getSignExtendedGatherOpcode | ( | unsigned | Opcode | ) |
Definition at line 4291 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, and llvm_unreachable.
Referenced by performGLD1Combine().
Definition at line 14863 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2f32, llvm::MVT::nxv2f64, llvm::MVT::nxv2i16, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv2i8, llvm::MVT::nxv4f32, llvm::MVT::nxv4i16, llvm::MVT::nxv4i32, llvm::MVT::nxv4i8, llvm::MVT::nxv8bf16, llvm::MVT::nxv8f16, llvm::MVT::nxv8i16, llvm::MVT::nxv8i8, and llvm::MVT::SimpleTy.
Referenced by performGatherLoadCombine(), performLD1Combine(), performScatterStoreCombine(), and performST1Combine().
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Definition at line 16027 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::tgtok::Bit, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.
Referenced by performTBZCombine().
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getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
Definition at line 10819 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().
Referenced by isVShiftLImm(), and isVShiftRImm().
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Definition at line 13591 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FADD, and llvm::MVT::i64.
Referenced by performExtractVectorEltCombine().
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Definition at line 3727 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.
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Definition at line 3738 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.
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Definition at line 14520 of file AArch64ISelLowering.cpp.
References llvm::LegalityPredicates::all(), N, llvm::AArch64ISD::PTRUE, and llvm::AArch64ISD::REINTERPRET_CAST.
Referenced by convertMergedOpToPredOp(), and llvm::AArch64TargetLowering::isAllActivePredicate().
Definition at line 9973 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), and i.
Referenced by performVectorTruncateCombine(), and tryLowerToSLI().
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Definition at line 2493 of file AArch64ISelLowering.cpp.
References llvm::isNullConstant(), llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.
Referenced by emitComparison(), getAArch64Cmp(), and trySwapICmpOperands().
Definition at line 9202 of file AArch64ISelLowering.cpp.
References E, llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), I, llvm::BitmaskEnumDetail::Mask(), and Offset.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal(), and tryFormConcatFromShuffle().
Definition at line 13313 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::DUP, llvm::EVT::getSimpleVT(), llvm::EVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isSimple(), N, llvm::MVT::SimpleTy, and llvm::ISD::SPLAT_VECTOR.
Referenced by performSVEAndCombine().
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Definition at line 15750 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::NV, llvm::AArch64CC::PL, llvm::ISD::SEXTLOAD, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by performCONDCombine().
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Definition at line 13913 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, and N.
Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().
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Definition at line 3664 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::EVT::getScalarSizeInBits(), llvm::isIntN(), llvm::isUIntN(), and N.
Referenced by isSignExtended(), and isZeroExtended().
Definition at line 8999 of file AArch64ISelLowering.cpp.
References llvm::find_if(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZExtValue(), llvm::APInt::logBase2(), and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 9163 of file AArch64ISelLowering.cpp.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 16746 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ANDV_PRED, llvm::AArch64ISD::EORV_PRED, llvm::AArch64ISD::FADDA_PRED, llvm::AArch64ISD::FADDV_PRED, llvm::AArch64ISD::FMAXNMV_PRED, llvm::AArch64ISD::FMAXV_PRED, llvm::AArch64ISD::FMINNMV_PRED, llvm::AArch64ISD::FMINV_PRED, llvm::AArch64ISD::ORV_PRED, llvm::AArch64ISD::SADDV_PRED, llvm::AArch64ISD::SMAXV_PRED, llvm::AArch64ISD::SMINV_PRED, llvm::AArch64ISD::UADDV_PRED, llvm::AArch64ISD::UMAXV_PRED, and llvm::AArch64ISD::UMINV_PRED.
Referenced by removeRedundantInsertVectorElt().
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Definition at line 2475 of file AArch64ISelLowering.cpp.
References llvm::dbgs(), and LLVM_DEBUG.
Referenced by getAArch64Cmp(), tryAdjustICmpImmAndPred(), and trySwapICmpOperands().
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Definition at line 201 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ABS_MERGE_PASSTHRU, llvm::AArch64ISD::BITREVERSE_MERGE_PASSTHRU, llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU, llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU, llvm::AArch64ISD::CTPOP_MERGE_PASSTHRU, llvm::AArch64ISD::DUP_MERGE_PASSTHRU, llvm::AArch64ISD::FABS_MERGE_PASSTHRU, llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU, llvm::AArch64ISD::FCVTZS_MERGE_PASSTHRU, llvm::AArch64ISD::FCVTZU_MERGE_PASSTHRU, llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU, llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU, llvm::AArch64ISD::FNEG_MERGE_PASSTHRU, llvm::AArch64ISD::FP_EXTEND_MERGE_PASSTHRU, llvm::AArch64ISD::FP_ROUND_MERGE_PASSTHRU, llvm::AArch64ISD::FRECPX_MERGE_PASSTHRU, llvm::AArch64ISD::FRINT_MERGE_PASSTHRU, llvm::AArch64ISD::FROUND_MERGE_PASSTHRU, llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU, llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU, llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU, llvm::AArch64ISD::NEG_MERGE_PASSTHRU, llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, llvm::AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU, llvm::AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU, and llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU.
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Check if Op could be used with vmull_high_p64 intrinsic.
Definition at line 11684 of file AArch64ISelLowering.cpp.
References llvm::Value::getType(), llvm::ConstantInt::getValue(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_ExtractElt(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().
Referenced by areOperandsOfVmullHighP64().
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Returns true if VT's elements occupy the lowest bit positions of its associated register class without any intervening space.
For example, nxv2f16, nxv4f16 and nxv8f16 are legal types that belong to the same register class, but only nxv8f16 can be treated as a packed vector.
Definition at line 192 of file AArch64ISelLowering.cpp.
References assert(), llvm::TypeSize::getKnownMinSize(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and llvm::AArch64::SVEBitsPerBlock.
isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.
(The order of the elements within each block of the vector is reversed.)
Definition at line 9040 of file AArch64ISelLowering.cpp.
References assert(), BlockSize, llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one.
SetCCInfo is filled accordingly.
Definition at line 13957 of file AArch64ISelLowering.cpp.
References SetCCInfo::AArch64, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, llvm::AArch64CC::getInvertedCondCode(), llvm::ConstantSDNode::isOne(), llvm::ConstantSDNode::isZero(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, llvm::ISD::SETCC, and std::swap().
Referenced by isSetCCOrZExtSetCC().
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Definition at line 14000 of file AArch64ISelLowering.cpp.
References Info, isSetCC(), and llvm::ISD::ZERO_EXTEND.
Referenced by performSetccAddFolding().
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Definition at line 3715 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), N, and llvm::ISD::SIGN_EXTEND.
Referenced by isAddSubSExt(), and performMulCombine().
Definition at line 8893 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
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Definition at line 12642 of file AArch64ISelLowering.cpp.
References getIntrinsicID(), and S.
Referenced by performMulCombine().
isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
Definition at line 9150 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 9096 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
Definition at line 9131 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, j(), and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 9083 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Check if the value of Offset represents a valid immediate for the SVE gather load/prefetch and scatter store instructiona with vector base and immediate offset addressing mode:
[<Zn>.[S|D]{, #<imm>}]
where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
Definition at line 16357 of file AArch64ISelLowering.cpp.
References llvm::ConstantSDNode::getZExtValue(), isValidImmForSVEVecImmAddrMode(), and Offset.
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Check if the value of OffsetInBytes can be used as an immediate for the gather load/prefetch and scatter store instructions with vector base and immediate offset addressing mode:
[<Zn>.[S|D]{, #<imm>}]
where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
Definition at line 16337 of file AArch64ISelLowering.cpp.
Referenced by combineSVEPrefetchVecBaseImmOff(), isValidImmForSVEVecImmAddrMode(), performGatherLoadCombine(), and performScatterStoreCombine().
isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.
Definition at line 10839 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
The value must be in the range: 1 <= Value <= ElementBits for a right shift; or
Definition at line 10850 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
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Check if a vector shuffle corresponds to a DUP instructions with a larger element width than the vector lane type.
If that is the case the function returns true and writes the value of the DUP instruction lane operand into DupLaneOp
Definition at line 8926 of file AArch64ISelLowering.cpp.
References assert(), BlockSize, llvm::find_if(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), I, and M.
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Definition at line 3721 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), N, and llvm::ISD::ZERO_EXTEND.
Referenced by isAddSubZExt(), and performMulCombine().
isZerosVector - Check whether SDNode N is a zero-filled vector.
Definition at line 2304 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::AArch64ISD::DUP, llvm::ISD::isConstantSplatVectorAllZeros(), and N.
Referenced by performAddDotCombine(), and performSetccMergeZeroCombine().
isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
Definition at line 9112 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 9067 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Legalize the gather prefetch (scalar + vector addressing mode) when the offset vector is an unpacked 32-bit scalable vector.
The other cases (Offset != nxv2i32) do not need legalization.
Definition at line 16702 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), N, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, Offset, and llvm::MVT::Other.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
Definition at line 6913 of file AArch64ISelLowering.cpp.
References llvm::EVT::getFixedSizeInBits(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::SIGN_EXTEND_INREG.
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Definition at line 3189 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADCS, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::AArch64ISD::ADDS, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::AArch64ISD::SBCS, llvm::ISD::SUBC, llvm::ISD::SUBE, and llvm::AArch64ISD::SUBS.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 3898 of file AArch64ISelLowering.cpp.
References llvm::LegalityPredicates::all(), llvm::ISD::AND, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), getPTrue(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::BitmaskEnumDetail::Mask(), llvm::AArch64ISD::REINTERPRET_CAST, and llvm::AArch64ISD::SETCC_MERGE_ZERO.
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Definition at line 3256 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::MVT::Other, and llvm::AArch64ISD::PREFETCH.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 14333 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::AArch64ISD::DUP_MERGE_PASSTHRU, llvm::SelectionDAG::getNode(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, and N.
Referenced by performIntrinsicCombine().
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Definition at line 14347 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::AArch64ISD::EXT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getNode(), llvm::LinearPolySize< ElementCount >::getScalable(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isScalableVector(), llvm::ISD::MUL, N, and llvm::AArch64::SVEBitsPerBlock.
Referenced by performIntrinsicCombine().
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Definition at line 14317 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::sampleprof::Base, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getStepVector(), llvm::SDValue::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::Mul, llvm::ISD::MUL, N, and llvm::ISD::SPLAT_VECTOR.
Referenced by performIntrinsicCombine().
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Definition at line 4603 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::isVector(), llvm::ARM_MB::ST, llvm::ISD::TRUNCATE, llvm::RegState::Undef, llvm::MVT::v2i32, llvm::MVT::v4i16, llvm::MVT::v4i8, llvm::MVT::v8i16, and llvm::MVT::v8i8.
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Definition at line 3225 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CSEL, getAArch64XALUOOp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), and llvm::ISD::MERGE_VALUES.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Return true if we might ever do TCO for calls with this calling convention.
Definition at line 5611 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::AArch64_SVE_VectorCall, llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::CallingConv::PreserveMost, llvm::CallingConv::Swift, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.
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NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
Definition at line 8655 of file AArch64ISelLowering.cpp.
References DL, llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().
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Definition at line 10138 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, and llvm::EVT::isFloatingPoint().
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Definition at line 1641 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, DL, llvm::AArch64_AM::encodeLogicalImmediate(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::MipsISD::Hi, llvm::AArch64_AM::isLogicalImmediate(), llvm::isShiftedMask_64(), llvm::BitmaskEnumDetail::Mask(), and llvm::Check::Size.
Referenced by llvm::AArch64TargetLowering::targetShrinkDemandedConstant().
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Definition at line 14097 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), isZerosVector(), N, llvm::AArch64ISD::SDOT, std::swap(), and llvm::AArch64ISD::UDOT.
Referenced by performAddSubCombine().
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Definition at line 14172 of file AArch64ISelLowering.cpp.
References N, performAddDotCombine(), performAddSubLongCombine(), and performUADDVCombine().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14130 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::is128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractHighSubvector(), N, performSetccAddFolding(), llvm::ISD::SIGN_EXTEND, tryExtendDUPToExtractHigh(), and llvm::ISD::ZERO_EXTEND.
Referenced by performAddSubCombine().
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Definition at line 13432 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::BICi, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, performSVEAndCombine(), resolveBuildVector(), tryAdvSIMDModImm16(), and tryAdvSIMDModImm32().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 15900 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, assert(), llvm::ISD::BR, llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::AArch64CC::EQ, llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::Function::hasFnAttribute(), llvm::MVT::i32, llvm::MVT::i64, llvm::isNullConstant(), N, llvm::AArch64CC::NE, llvm::MVT::Other, performCONDCombine(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::AArch64ISD::SUBS, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Combines a dup(sext/zext) node pattern into sext/zext(dup) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt.
Definition at line 12706 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::AssertSext, llvm::ISD::AssertZext, calculatePreExtendType(), llvm::EVT::changeVectorElementType(), DL, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::UnivariateLinearPolyBase< LeafTy >::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ShuffleVectorSDNode::isSplat(), llvm::MVT::Other, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::ISD::ZERO_EXTEND.
Referenced by performMulVectorExtendCombine().
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Definition at line 13645 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::dbgs(), llvm::AArch64ISD::DUPLANE64, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), i, llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MVT::isVector(), LLVM_DEBUG, llvm::BitmaskEnumDetail::Mask(), N, llvm::AArch64ISD::SHADD, llvm::AArch64ISD::SRHADD, llvm::ISD::TRUNCATE, llvm::AArch64ISD::UHADD, llvm::AArch64ISD::URHADD, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v8i16, and WidenVector().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 15826 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, checkValueWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), isEquivalentMaskless(), N, llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.
Referenced by performBRCONDCombine(), and performCSELCombine().
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Definition at line 15963 of file AArch64ISelLowering.cpp.
References N, and performCONDCombine().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14800 of file AArch64ISelLowering.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::Intrinsic::not_intrinsic, tryCombineLongOpWithDup(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13602 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::ConstantSDNode::getZExtValue(), hasPairwiseAdd(), llvm::MVT::i64, N, and Other.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Fold a floating-point divide by power of two into fixed-point to floating-point conversion.
Definition at line 13074 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v4i64, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Fold a floating-point multiply by power of two into floating-point to fixed-point conversion.
Definition at line 12999 of file AArch64ISelLowering.cpp.
References assert(), llvm::tgtok::Bits, DL, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::ISD::TRUNCATE, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i32, and llvm::MVT::v4i64.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 16468 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::sampleprof::Base, llvm::ISD::BITCAST, DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getScaledOffsetForBitWidth(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), isValidImmForSVEVecImmAddrMode(), llvm::SPII::Load, N, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv4i32, Offset, llvm::MVT::Other, llvm::AArch64::SVEBitsPerBlock, std::swap(), and llvm::ISD::TRUNCATE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 15263 of file AArch64ISelLowering.cpp.
References assert(), llvm::sampleprof::Base, DL, getGatherVecOpcode(), llvm::SelectionDAG::getNode(), getSignExtendedGatherOpcode(), llvm::EVT::getVectorElementType(), llvm::VTSDNode::getVT(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::MVT::i32, N, Offset, llvm::MVT::Other, Scaled, llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, Signed, and llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 16267 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::AArch64Subtarget::ClassifyGlobalReference(), DL, llvm::SelectionDAG::getConstant(), llvm::Module::getDataLayout(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getGlobalAddress(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::GlobalValue::getParent(), llvm::DataLayout::getTypeAllocSize(), llvm::GlobalValue::getValueType(), llvm::MVT::i64, llvm::min(), llvm::AArch64II::MO_NO_FLAG, N, Offset, llvm::ISD::SUB, TM, and llvm::SDNode::uses().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13775 of file AArch64ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MipsISD::Hi, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::MipsISD::Lo, and N.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 16806 of file AArch64ISelLowering.cpp.
References N, performPostLD1Combine(), and removeRedundantInsertVectorElt().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14566 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::AArch64ISD::ANDV_PRED, llvm::AArch64CC::ANY_ACTIVE, llvm::AArch64ISD::BIC, combineAcrossLanesIntrinsic(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), convertMergedOpToPredOp(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::EORV_PRED, llvm::AArch64ISD::FADD_PRED, llvm::AArch64ISD::FADDA_PRED, llvm::AArch64ISD::FADDV_PRED, llvm::AArch64CC::FIRST_ACTIVE, llvm::ISD::FMAXIMUM, llvm::AArch64ISD::FMAXNMV_PRED, llvm::ISD::FMAXNUM, llvm::AArch64ISD::FMAXV_PRED, llvm::ISD::FMINIMUM, llvm::AArch64ISD::FMINNMV_PRED, llvm::ISD::FMINNUM, llvm::AArch64ISD::FMINV_PRED, llvm::AArch64ISD::FMUL_PRED, llvm::AArch64ISD::FSUB_PRED, llvm::SelectionDAG::getCondCode(), getIntrinsicID(), llvm::SelectionDAG::getNode(), getPTest(), llvm::MVT::i64, llvm::AArch64CC::LAST_ACTIVE, LowerSVEIntrinsicDUP(), LowerSVEIntrinsicEXT(), LowerSVEIntrinsicIndex(), llvm::AArch64ISD::MUL_PRED, llvm::AArch64ISD::MULHS_PRED, llvm::AArch64ISD::MULHU_PRED, N, llvm::ISD::OR, llvm::AArch64ISD::ORV_PRED, llvm::ISD::SADDSAT, llvm::AArch64ISD::SADDV, llvm::AArch64ISD::SADDV_PRED, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUO, llvm::AArch64ISD::SHL_PRED, llvm::AArch64ISD::SMAX_PRED, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMAXV_PRED, llvm::AArch64ISD::SMIN_PRED, llvm::AArch64ISD::SMINV, llvm::AArch64ISD::SMINV_PRED, llvm::ISD::SPLAT_VECTOR, llvm::AArch64ISD::SRA_PRED, llvm::AArch64ISD::SRL_PRED, llvm::ISD::SSUBSAT, llvm::ISD::SUB, tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineShiftImm(), tryConvertSVEWideCompare(), llvm::ISD::UADDSAT, llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UADDV_PRED, llvm::AArch64ISD::UMAX_PRED, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMAXV_PRED, llvm::AArch64ISD::UMIN_PRED, llvm::AArch64ISD::UMINV, llvm::AArch64ISD::UMINV_PRED, llvm::ISD::USUBSAT, llvm::ISD::VSELECT, and llvm::ISD::XOR.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12958 of file AArch64ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::AArch64Subtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalLoad(), llvm::SPII::Load, N, performVectorCompareAndMaskUnaryOpCombine(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SINT_TO_FP, llvm::AArch64ISD::SITOF, and llvm::AArch64ISD::UITOF.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14891 of file AArch64ISelLowering.cpp.
References DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), llvm::EVT::isInteger(), llvm::SPII::Load, N, llvm::MVT::Other, llvm::AArch64::SVEBitsPerBlock, and llvm::ISD::TRUNCATE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14947 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::AArch64Subtarget::hasBF16(), llvm::EVT::isFloatingPoint(), llvm::AArch64ISD::LD1RO_MERGE_ZERO, llvm::AArch64ISD::LD1RQ_MERGE_ZERO, llvm::SPII::Load, N, llvm::MVT::nxv8bf16, and llvm::MVT::Other.
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Definition at line 14917 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::AArch64Subtarget::hasBF16(), llvm::EVT::isFloatingPoint(), N, llvm::ISD::NON_EXTLOAD, llvm::MVT::nxv8bf16, and llvm::ISD::UNINDEXED.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12799 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::APInt::ashr(), assert(), llvm::APInt::countTrailingZeros(), DL, llvm::MipsISD::Ext, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), isSignExtended(), IsSVECntIntrinsic(), isZeroExtended(), llvm::APInt::logBase2(), N, performMulVectorExtendCombine(), llvm::APInt::sge(), llvm::ISD::SHL, llvm::APInt::sle(), llvm::ISD::SUB, and llvm::ISD::TRUNCATE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Combines a mul(dup(sext/zext)) node pattern into mul(sext/zext(dup)) making use of the vector SExt/ZExt rather than the scalar SExt/ZExt.
Definition at line 12781 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::Mul, and performCommonVectorExtendCombine().
Referenced by performMulCombine().
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Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.
Definition at line 15508 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::SelectionDAG::getRegister(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), i, llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm_unreachable, llvm::makeArrayRef(), n, N, llvm::MVT::Other, llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, and llvm::AArch64ISD::ST4post.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
Get rid of unnecessary NVCASTs (that don't change the type).
Definition at line 16257 of file AArch64ISelLowering.cpp.
References N.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13295 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::isTypeLegal(), N, tryCombineToBSL(), and tryCombineToEXTR().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R.
Definition at line 15345 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::SelectionDAG::getRegister(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isScalableVector(), llvm::ARM_MB::LD, llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::ISD::LOAD, N, llvm::MVT::Other, and Vector.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), and performInsertVectorEltCombine().
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Definition at line 16364 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::sampleprof::Base, llvm::ISD::BITCAST, DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getScaledOffsetForBitWidth(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::EVT::isScalableVector(), isValidImmForSVEVecImmAddrMode(), N, llvm::MVT::nxv2f64, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv4f32, llvm::MVT::nxv4i32, Offset, llvm::MVT::Other, llvm::AArch64ISD::SST1_IMM_PRED, llvm::AArch64ISD::SST1_PRED, llvm::AArch64ISD::SST1_UXTW_PRED, llvm::AArch64ISD::SSTNT1_INDEX_PRED, llvm::AArch64ISD::SSTNT1_PRED, llvm::AArch64::SVEBitsPerBlock, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar.
This replaces any scalar setcc in the above pattern with a vector one followed by a DUP shuffle on the result.
Definition at line 16193 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::SETCC.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14013 of file AArch64ISelLowering.cpp.
References SetCCInfo::AArch64, llvm::ISD::ADD, assert(), GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, isSetCCOrZExtSetCC(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, and std::swap().
Referenced by performAddSubLongCombine().
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Definition at line 15973 of file AArch64ISelLowering.cpp.
References assert(), Cond, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::isNullConstant(), llvm::isOneConstant(), N, llvm::ISD::SETCC, and llvm::ISD::SETNE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 16002 of file AArch64ISelLowering.cpp.
References assert(), Cond, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), isZerosVector(), N, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SETNE, and llvm::ISD::SIGN_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 16570 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, EnableCombineMGatherIntrinsics, llvm::MipsISD::Ext, llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::AArch64ISD::GLDNT1S_MERGE_ZERO, I, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LD1S_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDFF1S_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1S_MERGE_ZERO, N, llvm::MVT::Other, llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64ISD::SUNPKHI, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::UUNPKHI, and llvm::AArch64ISD::UUNPKLO.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 15228 of file AArch64ISelLowering.cpp.
References assert(), N, and llvm::AArch64ISD::SPLICE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13480 of file AArch64ISelLowering.cpp.
References llvm::ISD::BSWAP, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::MaskedValueIsZero(), N, and llvm::ISD::ROTR.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14971 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::Data, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), getSVEContainerType(), llvm::SelectionDAG::getValueType(), llvm::AArch64Subtarget::hasBF16(), llvm::EVT::isFloatingPoint(), N, llvm::MVT::nxv8bf16, and llvm::AArch64ISD::ST1_PRED.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 15001 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), llvm::Data, DL, llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::AArch64Subtarget::hasBF16(), llvm::EVT::isFloatingPoint(), N, llvm::MVT::nxv8bf16, and llvm::ISD::UNINDEXED.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 15489 of file AArch64ISelLowering.cpp.
References foldTruncStoreOfExt(), N, performTBISimplification(), splitStores(), llvm::SPII::Store, and llvm::AArch64Subtarget::supportsAddressTopByteIgnored().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13340 of file AArch64ISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::DUP, EnableCombineMGatherIntrinsics, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isConstantSplatVectorMaskForType(), llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::BitmaskEnumDetail::Mask(), N, llvm::AArch64ISD::UUNPKHI, and llvm::AArch64ISD::UUNPKLO.
Referenced by performANDCombine().
| SDValue performSVESpliceCombine | ( | SDNode * | N, |
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Definition at line 16813 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), getPackedSVEVectorVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::isInteger(), N, and llvm::ISD::VECTOR_SPLICE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Simplify Addr given that the top byte of it is ignored by HW during address translation.
Definition at line 15452 of file AArch64ISelLowering.cpp.
References Addr, llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and llvm::TargetLowering::SimplifyDemandedBits().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), and performSTORECombine().
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Definition at line 16100 of file AArch64ISelLowering.cpp.
References assert(), llvm::tgtok::Bit, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getTestBitOperand(), llvm::MVT::i64, N, llvm::MVT::Other, llvm::AArch64ISD::TBNZ, and llvm::AArch64ISD::TBZ.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14060 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i64, llvm::EVT::isScalarInteger(), N, and llvm::AArch64ISD::UADDV.
Referenced by performAddSubCombine().
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Definition at line 15238 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), N, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, llvm::AArch64ISD::UZP1, and X.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12545 of file AArch64ISelLowering.cpp.
References B, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::ISD::MUL, N, performVecReduceAddCombineWithUADDLP(), llvm::AArch64ISD::SDOT, llvm::ISD::SIGN_EXTEND, llvm::ARM_MB::ST, llvm::AArch64ISD::UDOT, llvm::MVT::v16i8, llvm::MVT::v2i32, llvm::MVT::v4i32, llvm::MVT::v8i8, llvm::ISD::VECREDUCE_ADD, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12467 of file AArch64ISelLowering.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ABS, llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, llvm::AArch64ISD::UADDLP, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VECREDUCE_ADD, and llvm::ISD::ZERO_EXTEND.
Referenced by performVecReduceAddCombine().
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Definition at line 12912 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::isVector(), N, and llvm::ISD::SETCC.
Referenced by performIntToFpCombine().
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Optimize a vector shift instruction and its operand if shifted out bits are not used.
Definition at line 15322 of file AArch64ISelLowering.cpp.
References assert(), llvm::APInt::getLowBitsSet(), N, llvm::TargetLowering::SimplifyDemandedBits(), llvm::AArch64ISD::VASHR, and llvm::AArch64ISD::VLSHR.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13520 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::APInt::getAllOnes(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), isAllConstantBuildVector(), N, llvm::AArch64ISD::SHADD, Shift, llvm::ISD::SIGN_EXTEND, llvm::AArch64ISD::SRHADD, llvm::ISD::SUB, llvm::AArch64ISD::UHADD, llvm::AArch64ISD::URHADD, llvm::AArch64ISD::VLSHR, llvm::Xor, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 16131 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::LinearPolySize< ElementCount >::getFixed(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, llvm::is_contained(), llvm::ISD::isConstantSplatVector(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::APInt::isOneValue(), llvm::EVT::isSimple(), llvm::makeArrayRef(), N, llvm::Or, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETGT, Shift, llvm::MVT::SimpleTy, llvm::ISD::SRA, llvm::MVT::v16i8, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::VSELECT.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12590 of file AArch64ISelLowering.cpp.
References foldVectorXorShiftIntoCmp(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and N.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
Definition at line 16769 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isConstantSplatVectorAllZeros(), isLanes1toNKnownZero(), llvm::isNullConstant(), and N.
Referenced by performInsertVectorEltCombine().
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Definition at line 17397 of file AArch64ISelLowering.cpp.
References llvm::Acquire, llvm::AcquireRelease, assert(), llvm::ISD::BUILD_PAIR, createGPRPairNode(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getVTList(), llvm::AArch64Subtarget::hasLSE(), llvm::MipsISD::Hi, llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), llvm_unreachable, llvm::MipsISD::Lo, llvm::Monotonic, N, llvm::MVT::Other, llvm::AArch64Subtarget::outlineAtomics(), llvm::Release, Results, llvm::SequentiallyConsistent, llvm::SelectionDAG::setNodeMemRefs(), splitInt128(), std::swap(), and llvm::MVT::Untyped.
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Definition at line 17322 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, N, Results, and llvm::SelectionDAG::SplitVectorOperand().
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Replace a splat of a scalar to a vector store by scalar stores of the scalar value.
The load store optimizer pass will merge them to store pair stores. This has better performance than a splat of the scalar followed by a split vector store. Even if the stores are not merged it is four stores vs a dup, followed by an ext.b and two stores.
Definition at line 15104 of file AArch64ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::StoreSDNode::isTruncatingStore(), and splitStoreSplat().
Referenced by splitStores().
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Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.
The load store optimizer pass will merge them to store pair stores. This should be better than a movi to create the vector zero followed by a vector store if the zero constant is not re-used, since one instructions and one register live range will be removed.
For example, the final generated code should be:
stp xzr, xzr, [x0]
instead of:
movi v0.2d, #0 str q0, [x0]
Definition at line 15037 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DL, llvm::StoreSDNode::getBasePtr(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isNullConstant(), llvm::isNullFPConstant(), llvm::EVT::isScalableVector(), llvm::StoreSDNode::isTruncatingStore(), Offset, and splitStoreSplat().
Referenced by splitStores().
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Definition at line 9756 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), i, llvm::BuildVectorSDNode::isConstantSplat(), and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector(), EmitVectorComparison(), and performANDCombine().
| void selectGatherScatterAddrMode | ( | SDValue & | BasePtr, |
| SDValue & | Index, | ||
| EVT | MemVT, | ||
| unsigned & | Opcode, | ||
| bool | IsGather, | ||
| SelectionDAG & | DAG | ||
| ) |
Definition at line 4340 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::MVT::i64, Index, llvm::isNullConstant(), Offset, llvm::AArch64ISD::SST1_IMM_PRED, and std::swap().
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Set the IntrinsicInfo for the aarch64_sve_st<N> intrinsics.
Definition at line 11311 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::CallBase::getArgOperand(), llvm::Type::getContext(), llvm::TargetLoweringBase::getMemValueType(), llvm::CallBase::getNumArgOperands(), llvm::EVT::getScalarType(), llvm::Value::getType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), I, Info, llvm::ISD::INTRINSIC_VOID, and llvm::MachineMemOperand::MOStore.
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Definition at line 3690 of file AArch64ISelLowering.cpp.
References addRequiredExtensionForVectorMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), i, llvm::MVT::i32, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().
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Definition at line 17336 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MipsISD::Hi, llvm::MVT::i128, llvm::MVT::i64, llvm::MipsISD::Lo, N, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by ReplaceCMP_SWAP_128Results().
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Definition at line 15157 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::Function::hasMinSize(), llvm::MVT::i64, llvm::EVT::isFixedLengthVector(), llvm::AArch64Subtarget::isMisaligned128StoreSlow(), N, replaceSplatVectorStore(), replaceZeroVectorStore(), S, and llvm::MVT::v2i64.
Referenced by performSTORECombine().
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Definition at line 14821 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::MVT::i64, llvm::StoreSDNode::isTruncatingStore(), llvm::MinAlign(), and Offset.
Referenced by replaceSplatVectorStore(), and replaceZeroVectorStore().
| STATISTIC | ( | NumOptimizedImms | , |
| "Number of times immediates were optimized" | |||
| ) |
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Definition at line 9848 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::AArch64_AM::encodeAdvSIMDModImmType5(), llvm::AArch64_AM::encodeAdvSIMDModImmType6(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType5(), llvm::AArch64_AM::isAdvSIMDModImmType6(), llvm::AArch64ISD::NVCAST, Shift, llvm::MVT::v4i16, and llvm::MVT::v8i16.
Referenced by ConstantBuildVector(), and performANDCombine().
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Definition at line 9800 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::AArch64_AM::encodeAdvSIMDModImmType1(), llvm::AArch64_AM::encodeAdvSIMDModImmType2(), llvm::AArch64_AM::encodeAdvSIMDModImmType3(), llvm::AArch64_AM::encodeAdvSIMDModImmType4(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType1(), llvm::AArch64_AM::isAdvSIMDModImmType2(), llvm::AArch64_AM::isAdvSIMDModImmType3(), llvm::AArch64_AM::isAdvSIMDModImmType4(), llvm::AArch64ISD::NVCAST, Shift, llvm::MVT::v2i32, and llvm::MVT::v4i32.
Referenced by ConstantBuildVector(), and performANDCombine().
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Definition at line 9888 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::AArch64_AM::encodeAdvSIMDModImmType7(), llvm::AArch64_AM::encodeAdvSIMDModImmType8(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType7(), llvm::AArch64_AM::isAdvSIMDModImmType8(), llvm::AArch64ISD::NVCAST, Shift, llvm::MVT::v2i32, and llvm::MVT::v4i32.
Referenced by ConstantBuildVector().
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Definition at line 9779 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::AArch64_AM::encodeAdvSIMDModImmType10(), llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType10(), llvm::AArch64ISD::NVCAST, and llvm::MVT::v2i64.
Referenced by ConstantBuildVector().
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Definition at line 9919 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::AArch64_AM::encodeAdvSIMDModImmType9(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType9(), llvm::AArch64ISD::NVCAST, llvm::MVT::v16i8, and llvm::MVT::v8i8.
Referenced by ConstantBuildVector().
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Definition at line 9940 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::AArch64_AM::encodeAdvSIMDModImmType11(), llvm::AArch64_AM::encodeAdvSIMDModImmType12(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType11(), llvm::AArch64_AM::isAdvSIMDModImmType12(), llvm::AArch64ISD::NVCAST, llvm::MVT::v2f32, llvm::MVT::v2f64, and llvm::MVT::v4f32.
Referenced by ConstantBuildVector().
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Definition at line 14294 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::BitmaskEnumDetail::Mask(), and N.
Referenced by performIntrinsicCombine().
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Definition at line 13816 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm_unreachable, N, Shift, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.
Referenced by performIntrinsicCombine().
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Definition at line 14191 of file AArch64ISelLowering.cpp.
References assert(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractHighSubvector(), N, llvm::Intrinsic::not_intrinsic, and tryExtendDUPToExtractHigh().
Referenced by performExtendCombine(), and performIntrinsicCombine().
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Definition at line 14223 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSExtValue(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::BuildVectorSDNode::isConstantSplat(), llvm_unreachable, N, llvm::AArch64ISD::SQSHL_I, llvm::AArch64ISD::SQSHLU_I, llvm::AArch64ISD::SRSHR_I, llvm::AArch64ISD::UQSHL_I, llvm::AArch64ISD::URSHR_I, and llvm::AArch64ISD::VSHL.
Referenced by performIntrinsicCombine().
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Definition at line 13205 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::tgtok::Bits, llvm::AArch64ISD::BSP, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), i, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isVector(), j(), N, and llvm::ISD::SUB.
Referenced by performORCombine().
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EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair.
This function looks for the pattern: (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an EXTR. Can't quite be done in TableGen because the two immediates aren't independent.
Definition at line 13165 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::EXTR, findEXTRHalf(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::OR, and std::swap().
Referenced by performORCombine().
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Definition at line 14373 of file AArch64ISelLowering.cpp.
References DL, llvm::AArch64ISD::DUP, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), getIntrinsicID(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm_unreachable, N, llvm::AArch64ISD::SETCC_MERGE_ZERO, and llvm::ISD::SPLAT_VECTOR.
Referenced by performIntrinsicCombine().
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Definition at line 13878 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, llvm::MVT::is64BitVector(), llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, and N.
Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().
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Definition at line 9222 of file AArch64ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i64, isConcatMask(), and llvm::BitmaskEnumDetail::Mask().
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Definition at line 10010 of file AArch64ISelLowering.cpp.
References llvm::And, llvm::ISD::AND, assert(), llvm::AArch64ISD::BICi, C1, llvm::dbgs(), DL, llvm::SDNode::dump(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getZExtValue(), isAllConstantBuildVector(), llvm::EVT::isVector(), LLVM_DEBUG, N, Shift, llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, llvm::AArch64ISD::VSLI, llvm::AArch64ISD::VSRI, X, and Y.
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Definition at line 17846 of file AArch64ISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::CreatePointerCast(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8PtrTy(), llvm::IRBuilderBase::getInt8Ty(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPointerTo(), M, and Offset.
Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), and llvm::AArch64TargetLowering::getSafeStackPointerLocation().
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WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class.
Definition at line 8635 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, and llvm::ISD::INSERT_SUBVECTOR.
Referenced by constructDup(), GeneratePerfectShuffle(), and performConcatVectorsCombine().
| cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false)) |
Referenced by llvm::AArch64MCInstLower::lowerSymbolOperandELF().
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Referenced by performSignExtendInRegCombine(), and performSVEAndCombine().
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Referenced by llvm::AArch64TargetLowering::targetShrinkDemandedConstant().
Value type used for condition codes.
Definition at line 128 of file AArch64ISelLowering.cpp.
Referenced by emitComparison(), emitConditionalComparison(), getAArch64Cmp(), and getAArch64XALUOOp().
1.8.17