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LLVM
12.0.0git
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#include "AArch64ISelLowering.h"#include "AArch64CallingConvention.h"#include "AArch64ExpandImm.h"#include "AArch64MachineFunctionInfo.h"#include "AArch64PerfectShuffle.h"#include "AArch64RegisterInfo.h"#include "AArch64Subtarget.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "Utils/AArch64BaseInfo.h"#include "llvm/ADT/APFloat.h"#include "llvm/ADT/APInt.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/StringRef.h"#include "llvm/ADT/StringSwitch.h"#include "llvm/ADT/Triple.h"#include "llvm/ADT/Twine.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/CallingConvLower.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/RuntimeLibcalls.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/CodeGen/TargetCallingConv.h"#include "llvm/CodeGen/TargetInstrInfo.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/Attributes.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DebugLoc.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/GetElementPtrTypeIterator.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/Instruction.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/IntrinsicInst.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/IntrinsicsAArch64.h"#include "llvm/IR/Module.h"#include "llvm/IR/OperandTraits.h"#include "llvm/IR/PatternMatch.h"#include "llvm/IR/Type.h"#include "llvm/IR/Use.h"#include "llvm/IR/Value.h"#include "llvm/MC/MCRegisterInfo.h"#include "llvm/Support/Casting.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MachineValueType.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetOptions.h"#include <algorithm>#include <bitset>#include <cassert>#include <cctype>#include <cstdint>#include <cstdlib>#include <iterator>#include <limits>#include <tuple>#include <utility>#include <vector>#include "AArch64GenAsmMatcher.inc"Go to the source code of this file.
Classes | |
| struct | GenericSetCCInfo |
| Helper structure to keep track of ISD::SET_CC operands. More... | |
| struct | AArch64SetCCInfo |
| Helper structure to keep track of a SET_CC lowered into AArch64 code. More... | |
| union | SetCCInfo |
| Helper structure to keep track of SetCC information. More... | |
| struct | SetCCInfoAndKind |
| Helper structure to be able to read SetCC information. More... | |
Macros | |
| #define | DEBUG_TYPE "aarch64-lower" |
| #define | MAKE_CASE(V) |
| #define | GET_REGISTER_MATCHER |
Enumerations | |
| enum | PredicateConstraint { Upl, Upa, Invalid } |
Functions | |
| STATISTIC (NumTailCalls, "Number of tail calls") | |
| STATISTIC (NumShiftInserts, "Number of vector shift inserts") | |
| STATISTIC (NumOptimizedImms, "Number of times immediates were optimized") | |
| static bool | isPackedVectorType (EVT VT, SelectionDAG &DAG) |
| Returns true if VT's elements occupy the lowest bit positions of its associated register class without any intervening space. More... | |
| static bool | optimizeLogicalImm (SDValue Op, unsigned Size, uint64_t Imm, const APInt &Demanded, TargetLowering::TargetLoweringOpt &TLO, unsigned NewOpc) |
| static AArch64CC::CondCode | changeIntCCToAArch64CC (ISD::CondCode CC) |
| changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC More... | |
| static void | changeFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2) |
| changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. More... | |
| static void | changeFPCCToANDAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2) |
| Convert a DAG fp condition code to an AArch64 CC. More... | |
| static void | changeVectorFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) |
| changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions. More... | |
| static bool | isLegalArithImmed (uint64_t C) |
| static bool | isCMN (SDValue Op, ISD::CondCode CC) |
| static SDValue | emitStrictFPComparison (SDValue LHS, SDValue RHS, const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, bool IsSignaling) |
| static SDValue | emitComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) |
| static unsigned | getCmpOperandFoldingProfit (SDValue Op) |
| Returns how profitable it is to fold a comparison's operand's shift and/or extension operations. More... | |
| static SDValue | getAArch64Cmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) |
| static std::pair< SDValue, SDValue > | getAArch64XALUOOp (AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerXOR (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerXALUO (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerPREFETCH (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerBITCAST (SDValue Op, SelectionDAG &DAG) |
| static EVT | getExtensionTo64Bits (const EVT &OrigVT) |
| static SDValue | addRequiredExtensionForVectorMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) |
| static bool | isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned) |
| static SDValue | skipExtensionForVectorMULL (SDNode *N, SelectionDAG &DAG) |
| static bool | isSignExtended (SDNode *N, SelectionDAG &DAG) |
| static bool | isZeroExtended (SDNode *N, SelectionDAG &DAG) |
| static bool | isAddSubSExt (SDNode *N, SelectionDAG &DAG) |
| static bool | isAddSubZExt (SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerMUL (SDValue Op, SelectionDAG &DAG) |
| static SDValue | getPTrue (SelectionDAG &DAG, SDLoc DL, EVT VT, int Pattern) |
| static SDValue | LowerTruncateVectorStore (SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG) |
| static bool | canGuaranteeTCO (CallingConv::ID CC) |
| Return true if the calling convention is one that we can guarantee TCO for. More... | |
| static bool | mayTailCallThisCC (CallingConv::ID CC) |
| Return true if we might ever do TCO for calls with this calling convention. More... | |
| static SDValue | getEstimate (const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps) |
| static PredicateConstraint | parsePredicateConstraint (StringRef Constraint) |
| static SDValue | WidenVector (SDValue V64Reg, SelectionDAG &DAG) |
| WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class. More... | |
| static unsigned | getExtFactor (SDValue &V) |
| getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction. More... | |
| static SDValue | NarrowVector (SDValue V128Reg, SelectionDAG &DAG) |
| NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. More... | |
| static bool | isSingletonEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm) |
| static bool | isEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm) |
| static bool | isREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize) |
| isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize. More... | |
| static bool | isZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isINSMask (ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly) |
| static bool | isConcatMask (ArrayRef< int > Mask, EVT VT, bool SplitLHS) |
| static SDValue | tryFormConcatFromShuffle (SDValue Op, SelectionDAG &DAG) |
| static SDValue | GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) |
| GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More... | |
| static SDValue | GenerateTBL (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG) |
| static unsigned | getDUPLANEOp (EVT EltType) |
| static bool | resolveBuildVector (BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits) |
| static SDValue | tryAdvSIMDModImm64 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static SDValue | tryAdvSIMDModImm32 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr) |
| static SDValue | tryAdvSIMDModImm16 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr) |
| static SDValue | tryAdvSIMDModImm321s (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static SDValue | tryAdvSIMDModImm8 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static SDValue | tryAdvSIMDModImmFP (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) |
| static bool | isAllConstantBuildVector (const SDValue &PotentialBVec, uint64_t &ConstVal) |
| static unsigned | getIntrinsicID (const SDNode *N) |
| static SDValue | tryLowerToSLI (SDNode *N, SelectionDAG &DAG) |
| static SDValue | NormalizeBuildVector (SDValue Op, SelectionDAG &DAG) |
| static SDValue | ConstantBuildVector (SDValue Op, SelectionDAG &DAG) |
| static bool | getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt) |
| getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More... | |
| static bool | isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt) |
| isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More... | |
| static bool | isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) |
| isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More... | |
| static SDValue | EmitVectorComparison (SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) |
| static SDValue | getReductionSDNode (unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG) |
| template<unsigned NumVecs> | |
| static bool | setInfoSVEStN (AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI) |
Set the IntrinsicInfo for the aarch64_sve_st<N> intrinsics. More... | |
| static bool | areExtractShuffleVectors (Value *Op1, Value *Op2) |
| Check if both Op1 and Op2 are shufflevector extracts of either the lower or upper half of the vector elements. More... | |
| static bool | areExtractExts (Value *Ext1, Value *Ext2) |
| Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements. More... | |
| static bool | isOperandOfVmullHighP64 (Value *Op) |
| Check if Op could be used with vmull_high_p64 intrinsic. More... | |
| static bool | areOperandsOfVmullHighP64 (Value *Op1, Value *Op2) |
| Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic. More... | |
| static SDValue | foldVectorXorShiftIntoCmp (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0. More... | |
| static SDValue | performIntegerAbsCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performXorCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static bool | IsSVECntIntrinsic (SDValue S) |
| static SDValue | performMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performIntToFpCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performFpToIntCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| Fold a floating-point multiply by power of two into floating-point to fixed-point conversion. More... | |
| static SDValue | performFDivCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| Fold a floating-point divide by power of two into fixed-point to floating-point conversion. More... | |
| static bool | findEXTRHalf (SDValue N, SDValue &Src, uint32_t &ShiftAmount, bool &FromHi) |
| An EXTR instruction is made up of two shifts, ORed together. More... | |
| static SDValue | tryCombineToEXTR (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair. More... | |
| static SDValue | tryCombineToBSL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static bool | isConstantSplatVectorMaskForType (SDNode *N, EVT MemVT) |
| static SDValue | performSVEAndCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performSRLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performConcatVectorsCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineFixedPointConvert (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryExtendDUPToExtractHigh (SDValue N, SelectionDAG &DAG) |
| static bool | isEssentiallyExtractHighSubvector (SDValue N) |
| static bool | isSetCC (SDValue Op, SetCCInfoAndKind &SetCCInfo) |
Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one. More... | |
| static bool | isSetCCOrZExtSetCC (const SDValue &Op, SetCCInfoAndKind &Info) |
| static SDValue | performSetccAddFolding (SDNode *Op, SelectionDAG &DAG) |
| static SDValue | performAddSubLongCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineLongOpWithDup (unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineShiftImm (unsigned IID, SDNode *N, SelectionDAG &DAG) |
| static SDValue | tryCombineCRC32 (unsigned Mask, SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineAcrossLanesIntrinsic (unsigned Opc, SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntReduction (SDNode *N, unsigned Opc, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntrinsicIndex (SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntrinsicDUP (SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerSVEIntrinsicEXT (SDNode *N, SelectionDAG &DAG) |
| static SDValue | tryConvertSVEWideCompare (SDNode *N, ISD::CondCode CC, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | getPTest (SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, AArch64CC::CondCode Cond) |
| static SDValue | combineSVEReductionFP (SDNode *N, unsigned Opc, SelectionDAG &DAG) |
| static SDValue | combineSVEReductionOrderedFP (SDNode *N, unsigned Opc, SelectionDAG &DAG) |
| static SDValue | performIntrinsicCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | splitStoreSplat (SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts) |
| static MVT | getSVEContainerType (EVT ContentTy) |
| static SDValue | performLD1Combine (SDNode *N, SelectionDAG &DAG, unsigned Opc) |
| static SDValue | performLDNT1Combine (SDNode *N, SelectionDAG &DAG) |
| template<unsigned Opcode> | |
| static SDValue | performLD1ReplicateCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performST1Combine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performSTNT1Combine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | replaceZeroVectorStore (SelectionDAG &DAG, StoreSDNode &St) |
| Replace a splat of zeros to a vector store by scalar stores of WZR/XZR. More... | |
| static SDValue | replaceSplatVectorStore (SelectionDAG &DAG, StoreSDNode &St) |
| Replace a splat of a scalar to a vector store by scalar stores of the scalar value. More... | |
| static SDValue | splitStores (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performPostLD1Combine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp) |
| Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R. More... | |
| static bool | performTBISimplification (SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
Simplify Addr given that the top byte of it is ignored by HW during address translation. More... | |
| static SDValue | performSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performNEONPostLDSTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates. More... | |
| static bool | checkValueWidth (SDValue V, unsigned width, ISD::LoadExtType &ExtType) |
| static bool | isEquivalentMaskless (unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant) |
| static SDValue | performCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) |
| static SDValue | performBRCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | getTestBitOperand (SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) |
| static SDValue | performTBZCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performVSelectCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performSelectCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar. More... | |
| static SDValue | performNVCASTCombine (SDNode *N) |
| Get rid of unnecessary NVCASTs (that don't change the type). More... | |
| static SDValue | performGlobalAddressCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM) |
| static SDValue | getScaledOffsetForBitWidth (SelectionDAG &DAG, SDValue Offset, SDLoc DL, unsigned BitWidth) |
| static bool | isValidImmForSVEVecImmAddrMode (unsigned OffsetInBytes, unsigned ScalarSizeInBytes) |
Check if the value of OffsetInBytes can be used as an immediate for the gather load/prefetch and scatter store instructions with vector base and immediate offset addressing mode: More... | |
| static bool | isValidImmForSVEVecImmAddrMode (SDValue Offset, unsigned ScalarSizeInBytes) |
Check if the value of Offset represents a valid immediate for the SVE gather load/prefetch and scatter store instructiona with vector base and immediate offset addressing mode: More... | |
| static SDValue | performScatterStoreCombine (SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets=true) |
| static SDValue | performGatherLoadCombine (SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets=true) |
| static SDValue | performSignExtendInRegCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | legalizeSVEGatherPrefetchOffsVec (SDNode *N, SelectionDAG &DAG) |
| Legalize the gather prefetch (scalar + vector addressing mode) when the offset vector is an unpacked 32-bit scalable vector. More... | |
| static SDValue | combineSVEPrefetchVecBaseImmOff (SDNode *N, SelectionDAG &DAG, unsigned ScalarSizeInBytes) |
Combines a node carrying the intrinsic aarch64_sve_prf<T>_gather_scalar_offset into a node that uses aarch64_sve_prfb_gather_uxtw_index when the scalar offset passed to aarch64_sve_prf<T>_gather_scalar_offset is not a valid immediate for the sve gather prefetch instruction with vector plus immediate addressing mode. More... | |
| static void | ReplaceBITCASTResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) |
| static void | ReplaceReductionResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp) |
| static std::pair< SDValue, SDValue > | splitInt128 (SDValue N, SelectionDAG &DAG) |
| static SDValue | createGPRPairNode (SelectionDAG &DAG, SDValue V) |
| static void | ReplaceCMP_SWAP_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static Value * | UseTlsOffset (IRBuilder<> &IRB, unsigned Offset) |
| static EVT | getContainerForFixedLengthVector (SelectionDAG &DAG, EVT VT) |
| static SDValue | getPredicateForFixedLengthVector (SelectionDAG &DAG, SDLoc &DL, EVT VT) |
| static SDValue | getPredicateForScalableVector (SelectionDAG &DAG, SDLoc &DL, EVT VT) |
| static SDValue | getPredicateForVector (SelectionDAG &DAG, SDLoc &DL, EVT VT) |
| static SDValue | convertToScalableVector (SelectionDAG &DAG, EVT VT, SDValue V) |
| static SDValue | convertFromScalableVector (SelectionDAG &DAG, EVT VT, SDValue V) |
| static SDValue | emitConditionalComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) |
| can be transformed to: not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" which can be implemented as: cmp C ccmp D, inv(CD), CC ccmp A, CA, inv(CD) ccmp B, CB, inv(CA) check for CB flags More... | |
| static bool | canEmitConjunction (const SDValue Val, bool &CanNegate, bool &MustBeFirst, bool WillNegate, unsigned Depth=0) |
Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction. More... | |
| static SDValue | emitConjunctionRec (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) |
| Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops. More... | |
| static SDValue | emitConjunction (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC) |
| Emit expression as a conjunction (a series of CCMP/CFCMP ops). More... | |
Variables | |
| cl::opt< bool > | EnableAArch64ELFLocalDynamicTLSGeneration ("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false)) |
| static cl::opt< bool > | EnableOptimizeLogicalImm ("aarch64-enable-logical-imm", cl::Hidden, cl::desc("Enable AArch64 logical imm instruction " "optimization"), cl::init(true)) |
| static const MVT | MVT_CC = MVT::i32 |
| Value type used for condition codes. More... | |
| #define DEBUG_TYPE "aarch64-lower" |
Definition at line 96 of file AArch64ISelLowering.cpp.
| #define GET_REGISTER_MATCHER |
Definition at line 6236 of file AArch64ISelLowering.cpp.
| #define MAKE_CASE | ( | V | ) |
Referenced by llvm::AArch64TargetLowering::getTargetNodeName().
| enum PredicateConstraint |
| Enumerator | |
|---|---|
| Upl | |
| Upa | |
| Invalid | |
Definition at line 6588 of file AArch64ISelLowering.cpp.
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Definition at line 2949 of file AArch64ISelLowering.cpp.
References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), and llvm::EVT::is128BitVector().
Referenced by skipExtensionForVectorMULL().
Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.
Definition at line 9670 of file AArch64ISelLowering.cpp.
References llvm::MipsISD::Ext, llvm::User::getOperand(), llvm::Type::getScalarSizeInBits(), llvm::Value::getType(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().
Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().
Check if both Op1 and Op2 are shufflevector extracts of either the lower or upper half of the vector elements.
Definition at line 9629 of file AArch64ISelLowering.cpp.
References llvm::TypeSize::getFixedSize(), getNumElements(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::ShuffleVectorInst::isExtractSubvectorMask(), llvm::M1(), llvm::PatternMatch::m_Shuffle(), llvm::PatternMatch::m_Undef(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().
Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().
Check if Op1 and Op2 could be used with vmull_high_p64 intrinsic.
Definition at line 9697 of file AArch64ISelLowering.cpp.
References isOperandOfVmullHighP64().
Referenced by llvm::AArch64TargetLowering::shouldSinkOperands().
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Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction.
See CMP;CCMP matching.
| CanNegate | Set to true if we can negate the whole sub-tree just by changing the conditions on the SETCC tests. (this means we can call emitConjunctionRec() with Negate==true on this sub-tree) |
| MustBeFirst | Set to true if this subtree needs to be negated and we cannot do the negation naturally. We are required to emit the subtree first in this case. |
| WillNegate | Is true if are called when the result of this subexpression must be negated. This happens when the outer expression is an OR. We can use this fact to know that we have a double negation (or (or ...) ...) that can be implemented for free. |
Definition at line 2049 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::Depth, llvm::MVT::f128, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::OR, and llvm::ISD::SETCC.
Referenced by emitConjunction(), and emitConjunctionRec().
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Return true if the calling convention is one that we can guarantee TCO for.
Definition at line 4099 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast.
Referenced by mayTailCallThisCC().
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changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
Definition at line 1737 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by changeFPCCToANDAArch64CC(), changeVectorFPCCToAArch64CC(), and mayTailCallThisCC().
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Convert a DAG fp condition code to an AArch64 CC.
This differs from changeFPCCToAArch64CC in that it returns cond codes that should be AND'ed instead of OR'ed.
Definition at line 1800 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, assert(), changeFPCCToAArch64CC(), llvm::AArch64CC::LE, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETONE, llvm::ISD::SETUEQ, and llvm::AArch64CC::VC.
Referenced by emitConjunctionRec().
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changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC
Definition at line 1709 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by emitConjunctionRec(), EmitVectorComparison(), getAArch64Cmp(), and mayTailCallThisCC().
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changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions.
Fewer operations are available without a real NZCV register, so we have to use less efficient combinations to get the same effect.
Definition at line 1830 of file AArch64ISelLowering.cpp.
References changeFPCCToAArch64CC(), llvm::MVT::f32, llvm::AArch64CC::GE, llvm::ISD::getSetCCInverse(), LLVM_FALLTHROUGH, llvm::AArch64CC::MI, llvm::ISD::SETO, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.
Referenced by EmitVectorComparison().
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Definition at line 12843 of file AArch64ISelLowering.cpp.
References llvm::abs(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::Constant, llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::VTSDNode::getVT(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::TargetConstant, and llvm::ISD::ZEXTLOAD.
Referenced by performCONDCombine().
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Definition at line 11662 of file AArch64ISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getValueType(), and llvm::MVT::i64.
Referenced by performIntrinsicCombine().
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Combines a node carrying the intrinsic aarch64_sve_prf<T>_gather_scalar_offset into a node that uses aarch64_sve_prfb_gather_uxtw_index when the scalar offset passed to aarch64_sve_prf<T>_gather_scalar_offset is not a valid immediate for the sve gather prefetch instruction with vector plus immediate addressing mode.
Definition at line 13824 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, isValidImmForSVEVecImmAddrMode(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::MVT::Other, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 11842 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), and llvm::MVT::i64.
Referenced by performIntrinsicCombine().
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Definition at line 11859 of file AArch64ISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i64, and llvm::ISD::INSERT_VECTOR_ELT.
Referenced by performIntrinsicCombine().
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Definition at line 8321 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::bf16, llvm::ISD::BITCAST, llvm::dbgs(), DL, llvm::AArch64ISD::DUP, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::AArch64ISD::FMOV, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::BuildVectorSDNode::getConstantSplatNode(), llvm::SelectionDAG::getContext(), getDUPLANEOp(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, llvm::BuildVectorSDNode::isConstant(), isConstant(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), LLVM_DEBUG, llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, NormalizeBuildVector(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::SelectionDAG::ReplaceAllUsesWith(), resolveBuildVector(), llvm::ISD::SCALAR_TO_VECTOR, llvm::shuffle(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4bf16, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8bf16, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::Vector, and WidenVector().
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Definition at line 15036 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getPredicateForFixedLengthVector(), getPredicateForVector(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isFixedLengthVector(), llvm::EVT::isScalableVector(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::SPII::Load, llvm::MVT::nxv16i8, llvm::MVT::nxv2i64, llvm::MVT::nxv4i32, llvm::MVT::nxv8i16, llvm::SDNode::op_values(), Operands, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MVT::SimpleTy, llvm::SPII::Store, and llvm::AArch64ISD::UZP1.
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Definition at line 15025 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::isFixedLengthVector(), and llvm::EVT::isScalableVector().
Referenced by convertFromScalableVector().
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Definition at line 14324 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), llvm::ISD::SRL, std::swap(), and llvm::MVT::Untyped.
Referenced by getAL(), getARClassRegisterMask(), getContiguousRangeOfSetBits(), ReplaceCMP_SWAP_128Results(), and SDValueToConstBool().
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Definition at line 1895 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, llvm::ISD::AND, llvm::AArch64ISD::ANDS, assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::AArch64ISD::FCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), isCMN(), llvm::EVT::isFloatingPoint(), llvm::isNullConstant(), llvm::ISD::isUnsignedIntSetCC(), llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.
Referenced by emitConjunctionRec(), getAArch64Cmp(), and mayTailCallThisCC().
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can be transformed to: not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" which can be implemented as: cmp C ccmp D, inv(CD), CC ccmp A, CA, inv(CD) ccmp B, CB, inv(CA) check for CB flags
A counterexample is "or (and A B) (and C D)" which translates to not (and (not (and (not A) (not B))) (not (and (not C) (not D)))), we can only implement 1 of the inner (not) operations, but not both!Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
Definition at line 2001 of file AArch64ISelLowering.cpp.
References assert(), llvm::AArch64ISD::CCMN, llvm::AArch64ISD::CCMP, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::AArch64ISD::FCCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::AArch64CC::getNZCVToSatisfyCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), llvm::isNullConstant(), llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.
Referenced by emitConjunctionRec().
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Emit expression as a conjunction (a series of CCMP/CFCMP ops).
In some cases this is even possible with OR operations in the expression. See CMP;CCMP matching.
Definition at line 2223 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, canEmitConjunction(), and emitConjunctionRec().
Referenced by getAArch64Cmp().
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Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops.
See CMP;CCMP matching. Tries to transform the given i1 producing node Val to a series compare and conditional compare operations.
OutCC to the flags that should be tested or returns SDValue() if transformation was not possible. Negate is true if we want this sub-tree being negated just by changing SETCC conditions. Definition at line 2111 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::ISD::AND, assert(), canEmitConjunction(), changeFPCCToANDAArch64CC(), changeIntCCToAArch64CC(), DL, emitComparison(), emitConditionalComparison(), llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::ISD::OR, llvm::ISD::SETCC, and std::swap().
Referenced by emitConjunction().
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Definition at line 1884 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::Other, llvm::AArch64ISD::STRICT_FCMP, and llvm::AArch64ISD::STRICT_FCMPE.
Referenced by mayTailCallThisCC().
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Definition at line 8982 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, assert(), changeIntCCToAArch64CC(), llvm::EVT::changeVectorElementTypeToInteger(), changeVectorFPCCToAArch64CC(), llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::dyn_cast(), llvm::AArch64CC::EQ, llvm::MVT::f128, llvm::MVT::f16, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::ISD::FP_EXTEND, llvm::AArch64CC::GE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getSubtarget(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::AArch64CC::LE, LLVM_FALLTHROUGH, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::bitc::NoNaNs, llvm::TargetOptions::NoNaNsFPMath, llvm::AArch64ISD::NOT, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::SelectionDAG::ReplaceAllUsesWith(), resolveBuildVector(), llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.
An EXTR instruction is made up of two shifts, ORed together.
This helper searches for and classifies those shifts.
Definition at line 10816 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryCombineToEXTR().
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Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0.
Definition at line 10358 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CMGEz, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64Subtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::ISD::isBuildVectorAllOnes(), llvm::EVT::isVector(), and llvm::AArch64ISD::VASHR.
Referenced by performXorCombine().
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GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 7446 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::bf16, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), getExtFactor(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
Referenced by getDUPLANEOp().
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Definition at line 7549 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorTemplateCommon< T >::data(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::SDNode::isUndef(), llvm::makeArrayRef(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v8i8.
Referenced by getDUPLANEOp().
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Definition at line 2271 of file AArch64ISelLowering.cpp.
References C, changeIntCCToAArch64CC(), emitComparison(), emitConjunction(), getCmpOperandFoldingProfit(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, INT64_MAX, isCMN(), isLegalArithImmed(), llvm::ConstantSDNode::isNullValue(), llvm::ConstantSDNode::isOne(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND_INREG, std::swap(), UINT64_MAX, and llvm::ISD::ZEXTLOAD.
Referenced by LowerXOR(), mayTailCallThisCC(), performSetccAddFolding(), and performXorCombine().
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Definition at line 2403 of file AArch64ISelLowering.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::AArch64ISD::ADDS, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64CC::HS, llvm::MVT::i32, llvm::MVT::i64, llvm::SDNode::isStrictFPOpcode(), llvm_unreachable, llvm::AArch64CC::LO, llvm::TargetLowering::makeLibCall(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::AArch64CC::NE, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::ISD::SADDO, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::AArch64ISD::SUBS, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::AArch64CC::VS, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerXALUO(), LowerXOR(), and mayTailCallThisCC().
Returns how profitable it is to fold a comparison's operand's shift and/or extension operations.
Definition at line 2237 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::BitmaskEnumDetail::Mask(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by getAArch64Cmp().
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Definition at line 14916 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2f64, llvm::MVT::nxv2i64, llvm::MVT::nxv4f32, llvm::MVT::nxv4i32, llvm::MVT::nxv8f16, llvm::MVT::nxv8i16, and llvm::MVT::SimpleTy.
Referenced by convertFromScalableVector().
Definition at line 7611 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::LegalityPredicates::all(), llvm::ISD::AND, llvm::MVT::bf16, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, Concat, llvm::ISD::CONCAT_VECTORS, DL, llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::dyn_cast(), llvm::AArch64ISD::EXT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, GeneratePerfectShuffle(), GenerateTBL(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), getExtFactor(), llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMachineNode(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPTrue(), llvm::EVT::getScalarType(), llvm::MVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::AArch64ISD::INDEX_VECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, isEXTMask(), isINSMask(), llvm::EVT::isInteger(), isREVMask(), llvm::EVT::isScalableVector(), isSingletonEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), isTRN_v_undef_Mask(), isTRNMask(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDNode::isUndef(), isUZP_v_undef_Mask(), isUZPMask(), isZIP_v_undef_Mask(), isZIPMask(), llvm_unreachable, llvm::MVT::nxv2i64, PerfectShuffleTable, llvm::report_fatal_error(), llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, llvm::ISD::SPLAT_VECTOR, llvm::AArch64::SVEBitsPerBlock, std::swap(), llvm::AArch64ISD::TBL, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, tryFormConcatFromShuffle(), llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::NVPTX::PTXLdStInstCode::V2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
Referenced by ConstantBuildVector().
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Definition at line 6448 of file AArch64ISelLowering.cpp.
References DL, Enabled, llvm::TargetLoweringBase::Enabled, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FMUL, llvm::AArch64ISD::FRECPE, llvm::AArch64ISD::FRECPS, llvm::AArch64ISD::FRSQRTE, llvm::AArch64ISD::FRSQRTS, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::AArch64Subtarget::hasFPARMv8(), llvm::AArch64Subtarget::hasNEON(), llvm::EVT::isFloatingPoint(), llvm::EVT::isVector(), llvm::ISD::SELECT, llvm::SDNodeFlags::setAllowReassociation(), llvm::ISD::SETEQ, llvm::AArch64Subtarget::useRSqrt(), llvm::MVT::v1f32, llvm::MVT::v1f64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v4f32, and llvm::ISD::VSELECT.
Definition at line 2932 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.
Referenced by addRequiredExtensionForVectorMULL().
getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.
Definition at line 6933 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::EVT::getVectorElementType().
Referenced by GeneratePerfectShuffle(), getDUPLANEOp(), and llvm::AArch64TargetLowering::ReconstructShuffle().
Definition at line 8145 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::Intrinsic::not_intrinsic.
Referenced by FindPreallocatedCall(), llvm::CallBase::getCaller(), isBrevLdIntrinsic(), llvm::Function::isConstrainedFPIntrinsic(), IsSVECntIntrinsic(), performExtendCombine(), performIntrinsicCombine(), propagateMetadata(), SimplifyFCmpInst(), and tryConvertSVEWideCompare().
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Definition at line 14941 of file AArch64ISelLowering.cpp.
References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::MVT::nxv16i1, llvm::MVT::nxv2i1, llvm::MVT::nxv4i1, llvm::MVT::nxv8i1, llvm::AArch64ISD::PTRUE, and llvm::MVT::SimpleTy.
Referenced by convertFromScalableVector(), and getPredicateForVector().
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Definition at line 15009 of file AArch64ISelLowering.cpp.
References llvm::LegalityPredicates::all(), assert(), llvm::EVT::changeVectorElementType(), getPTrue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i1, llvm::EVT::isScalableVector(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by getPredicateForVector().
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Definition at line 15017 of file AArch64ISelLowering.cpp.
References getPredicateForFixedLengthVector(), getPredicateForScalableVector(), and llvm::EVT::isFixedLengthVector().
Referenced by convertFromScalableVector().
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Definition at line 11818 of file AArch64ISelLowering.cpp.
References assert(), llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::i32, llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::Other, llvm::AArch64ISD::PTEST, and llvm::Test.
Referenced by performIntrinsicCombine().
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Definition at line 3140 of file AArch64ISelLowering.cpp.
References llvm::ISD::ABS, llvm::LegalityPredicates::all(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::AArch64ISD::CLASTA_N, llvm::AArch64ISD::CLASTB_N, llvm::dyn_cast(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::AArch64TargetLowering::getPointerTy(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::AArch64ISD::INSR, llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::AArch64ISD::LASTA, llvm::AArch64ISD::LASTB, llvm::BitmaskEnumDetail::Mask(), llvm::AArch64ISD::PTRUE, Reg, llvm::AArch64ISD::REINTERPRET_CAST, llvm::report_fatal_error(), llvm::AArch64ISD::REV, llvm::NVPTX::PTXLdStInstCode::Scalar, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::AArch64ISD::SRHADD, llvm::AArch64ISD::SUNPKHI, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::TBL, llvm::AArch64ISD::THREAD_POINTER, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::AArch64ISD::URHADD, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::MVT::v1i64, llvm::AArch64ISD::VSLI, llvm::AArch64ISD::VSRI, llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
Referenced by getDUPLANEOp(), and getPredicateForScalableVector().
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Definition at line 9147 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_CLR, llvm::AArch64ISD::CALL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::AArch64TargetLowering::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getRegisterMask(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64RegisterInfo::getWindowsStackProbePreservedMask(), llvm::MVT::Glue, llvm::SDNodeFlags::hasNoNaNs(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SHL, Size, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMINV, llvm::ISD::SRL, llvm::ISD::SUB, llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMINV, llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask(), llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::XOR.
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Definition at line 13418 of file AArch64ISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::EVT::isScalableVector(), llvm::Log2_32(), llvm::MVT::nxv2i64, llvm::ISD::SHL, and llvm::ISD::SPLAT_VECTOR.
Referenced by performGatherLoadCombine(), and performScatterStoreCombine().
Definition at line 12201 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::nxv16i8, llvm::MVT::nxv2f32, llvm::MVT::nxv2f64, llvm::MVT::nxv2i16, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv2i8, llvm::MVT::nxv4f32, llvm::MVT::nxv4i16, llvm::MVT::nxv4i32, llvm::MVT::nxv4i8, llvm::MVT::nxv8bf16, llvm::MVT::nxv8f16, llvm::MVT::nxv8i16, llvm::MVT::nxv8i8, and llvm::MVT::SimpleTy.
Referenced by performGatherLoadCombine(), performLD1Combine(), performScatterStoreCombine(), and performST1Combine().
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Definition at line 13162 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::tgtok::Bit, C, llvm::dyn_cast(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.
Referenced by performTBZCombine().
getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
Definition at line 8810 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().
Referenced by isVShiftLImm(), and isVShiftRImm().
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Definition at line 3026 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isSignExtended(), and llvm::ISD::SUB.
Referenced by LowerMUL().
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Definition at line 3037 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, isZeroExtended(), llvm::MVT::Other, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.
Referenced by LowerMUL().
Definition at line 8128 of file AArch64ISelLowering.cpp.
References llvm::dyn_cast(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::ConstantSDNode::getZExtValue().
Referenced by isVShiftRImm(), and tryLowerToSLI().
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Definition at line 1879 of file AArch64ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isNullConstant(), llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.
Referenced by emitComparison(), and getAArch64Cmp().
Definition at line 7396 of file AArch64ISelLowering.cpp.
References E, llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), and I.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal(), and tryFormConcatFromShuffle().
Definition at line 10943 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::DUP, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::EVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isSimple(), llvm::MVT::SimpleTy, and llvm::ISD::SPLAT_VECTOR.
Referenced by performSVEAndCombine().
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Definition at line 12946 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::NV, llvm::AArch64CC::PL, llvm::ISD::SEXTLOAD, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by performCONDCombine().
Definition at line 11352 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::EVT::getVectorNumElements().
Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().
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Definition at line 2966 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, C, llvm::SDNode::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::isIntN(), llvm::isUIntN(), and llvm::SDNode::op_values().
Referenced by isSignExtended(), and isZeroExtended().
Definition at line 7193 of file AArch64ISelLowering.cpp.
References llvm::ArrayRef< T >::end(), llvm::find_if(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZExtValue(), and llvm::APInt::logBase2().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 7357 of file AArch64ISelLowering.cpp.
References llvm::ArrayRef< T >::size().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 1861 of file AArch64ISelLowering.cpp.
References llvm::dbgs(), and LLVM_DEBUG.
Referenced by getAArch64Cmp().
Check if Op could be used with vmull_high_p64 intrinsic.
Definition at line 9686 of file AArch64ISelLowering.cpp.
References getNumElements(), llvm::Value::getType(), llvm::ConstantInt::getValue(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_ExtractElt(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().
Referenced by areOperandsOfVmullHighP64().
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Returns true if VT's elements occupy the lowest bit positions of its associated register class without any intervening space.
For example, nxv2f16, nxv4f16 and nxv8f16 are legal types that belong to the same register class, but only nxv8f16 can be treated as a packed vector.
Definition at line 124 of file AArch64ISelLowering.cpp.
References assert(), llvm::TypeSize::getKnownMinSize(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and llvm::AArch64::SVEBitsPerBlock.
isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.
(The order of the elements within each block of the vector is reversed.)
Definition at line 7234 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), and llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one.
SetCCInfo is filled accordingly.
Definition at line 11394 of file AArch64ISelLowering.cpp.
References SetCCInfo::AArch64, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, llvm::dyn_cast(), SetCCInfo::Generic, llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, llvm::ConstantSDNode::isOne(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, llvm::ISD::SETCC, and std::swap().
Referenced by isSetCCOrZExtSetCC().
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Definition at line 11437 of file AArch64ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), Info, isSetCC(), and llvm::ISD::ZERO_EXTEND.
Referenced by performSetccAddFolding().
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Definition at line 3016 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), and llvm::ISD::SIGN_EXTEND.
Referenced by isAddSubSExt(), LowerMUL(), and performMulCombine().
Definition at line 7162 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp().
Definition at line 10464 of file AArch64ISelLowering.cpp.
References getIntrinsicID(), and llvm::SDValue::getNode().
Referenced by performMulCombine().
isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
Definition at line 7344 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 7290 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
Definition at line 7325 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 7277 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Check if the value of OffsetInBytes can be used as an immediate for the gather load/prefetch and scatter store instructions with vector base and immediate offset addressing mode:
[<Zn>.[S|D]{, #<imm>}]
where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
Definition at line 13437 of file AArch64ISelLowering.cpp.
Referenced by combineSVEPrefetchVecBaseImmOff(), isValidImmForSVEVecImmAddrMode(), performGatherLoadCombine(), and performScatterStoreCombine().
Check if the value of Offset represents a valid immediate for the SVE gather load/prefetch and scatter store instructiona with vector base and immediate offset addressing mode:
[<Zn>.[S|D]{, #<imm>}]
where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
Definition at line 13457 of file AArch64ISelLowering.cpp.
References llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::ConstantSDNode::getZExtValue(), and isValidImmForSVEVecImmAddrMode().
isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.
Definition at line 8830 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
Referenced by isVShiftRImm().
isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
The value must be in the range: 1 <= Value <= ElementBits for a right shift; or
Definition at line 8841 of file AArch64ISelLowering.cpp.
References assert(), C, DL, llvm::APInt::getAllOnesValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), getVShiftImm(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, isAllConstantBuildVector(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), isVShiftLImm(), llvm_unreachable, llvm::AArch64ISD::NEG, llvm::ISD::SHL, llvm::AArch64ISD::SHL_MERGE_OP1, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRA, llvm::AArch64ISD::SRA_MERGE_OP1, llvm::AArch64ISD::SRHADD, llvm::ISD::SRL, llvm::AArch64ISD::SRL_MERGE_OP1, llvm::ISD::SUB, llvm::AArch64ISD::URHADD, llvm::AArch64ISD::VASHR, llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
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Definition at line 3021 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), and llvm::ISD::ZERO_EXTEND.
Referenced by isAddSubZExt(), LowerMUL(), and performMulCombine().
isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
Definition at line 7306 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 7261 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Legalize the gather prefetch (scalar + vector addressing mode) when the offset vector is an unpacked 32-bit scalable vector.
The other cases (Offset != nxv2i32) do not need legalization.
Definition at line 13801 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::MVT::Other, and llvm::MVT::SimpleTy.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 2611 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADCS, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::AArch64ISD::ADDS, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::AArch64ISD::SBCS, llvm::ISD::SUBC, llvm::ISD::SUBE, and llvm::AArch64ISD::SUBS.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 2916 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bf16, llvm::ISD::BITCAST, DL, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i16, and llvm::MVT::i32.
Referenced by llvm::PPCTargetLowering::CallFlags::CallFlags(), llvm::HexagonTargetLowering::isCtlzFast(), and llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 3071 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), skipExtensionForVectorMULL(), llvm::AArch64ISD::SMULL, std::swap(), llvm::AArch64ISD::UMULL, and llvm::MVT::v2i64.
Referenced by llvm::PPCTargetLowering::CallFlags::CallFlags(), and llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 2678 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::changeVectorElementTypeToInteger(), DL, llvm::MipsISD::Ext, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::MVT::getFloatingPointVT(), llvm::RTLIB::getFPEXT(), llvm::RTLIB::getFPROUND(), llvm::RTLIB::getFPTOSINT(), llvm::RTLIB::getFPTOUINT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::AArch64Subtarget::hasFullFP16(), llvm::MVT::i32, llvm::SDNode::isStrictFPOpcode(), llvm::EVT::isVector(), llvm::TargetLowering::makeLibCall(), llvm::MVT::Other, llvm::AArch64ISD::PREFETCH, llvm::ISD::STRICT_FP_TO_SINT, and llvm::ISD::TRUNCATE.
Referenced by llvm::HexagonTargetLowering::isCtlzFast(), and llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 11672 of file AArch64ISelLowering.cpp.
References llvm::Data, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::AArch64::NeonBitsPerVector.
Referenced by performIntrinsicCombine().
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Definition at line 11715 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::AArch64ISD::DUP_MERGE_PASSTHRU, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, and llvm::NVPTX::PTXLdStInstCode::Scalar.
Referenced by performIntrinsicCombine().
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Definition at line 11729 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::AArch64ISD::EXT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isScalableVector(), llvm::ISD::MUL, and llvm::AArch64::SVEBitsPerBlock.
Referenced by performIntrinsicCombine().
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Definition at line 11700 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, and llvm::AArch64ISD::INDEX_VECTOR.
Referenced by performIntrinsicCombine().
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Definition at line 3316 of file AArch64ISelLowering.cpp.
References llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(), assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementCount(), llvm::SelectionDAG::getVTList(), llvm::MipsISD::Hi, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MemSDNode::isNonTemporal(), llvm::StoreSDNode::isTruncatingStore(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::MipsISD::Lo, llvm::ElementCount::Min, llvm::MVT::Other, llvm::TargetLowering::scalarizeVectorStore(), llvm::AArch64ISD::STNP, llvm::AArch64ISD::STP, llvm::ISD::TRUNCATE, llvm::RegState::Undef, llvm::MVT::v2i32, llvm::MVT::v4i16, llvm::MVT::v4i8, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::Align::value().
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Definition at line 2816 of file AArch64ISelLowering.cpp.
References Arg, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::EVT::changeVectorElementTypeToInteger(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getContext(), llvm::MVT::getFloatingPointVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::RTLIB::getSINTTOFP(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::RTLIB::getUINTTOFP(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::AArch64Subtarget::hasFullFP16(), llvm::MVT::i128, llvm::tgtok::In, llvm::SDNode::isStrictFPOpcode(), llvm::EVT::isVector(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::STRICT_SINT_TO_FP, and llvm::ISD::ZERO_EXTEND.
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Definition at line 2647 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CSEL, getAArch64XALUOOp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), and llvm::ISD::MERGE_VALUES.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 2531 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CSEL, llvm::dyn_cast(), getAArch64Cmp(), getAArch64XALUOOp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ConstantSDNode::isAllOnesValue(), llvm::ConstantSDNode::isNullValue(), llvm::isOneConstant(), llvm::ISD::isOverflowIntrOpRes(), llvm::TargetLoweringBase::isTypeLegal(), llvm::Other, llvm::ISD::SELECT_CC, std::swap(), and llvm::ISD::XOR.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Return true if we might ever do TCO for calls with this calling convention.
Definition at line 4104 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::AArch64_SVE_VectorCall, llvm::ISD::ADD, llvm::SelectionDAG::addCallSiteInfo(), llvm::AArch64ISD::ADDlow, llvm::SelectionDAG::addNoMergeSiteInfo(), llvm::AArch64ISD::ADR, llvm::AArch64ISD::ADRP, llvm::CCValAssign::AExt, llvm::CCValAssign::AExtUpper, llvm::AArch64CC::AL, llvm::alignTo(), llvm::CCState::AnalyzeCallOperands(), llvm::CCState::AnalyzeReturn(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::any_of(), Arg, llvm::Function::arg_begin(), llvm::Function::arg_end(), assert(), llvm::CCValAssign::BCvt, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MVT::bf16, llvm::AArch64ISD::BIT, llvm::ISD::BITCAST, llvm::tgtok::Bits, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::AArch64ISD::BRCOND, llvm::CallingConv::C, C, llvm::AArch64ISD::CALL, Callee, canGuaranteeTCO(), llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::AArch64TargetLowering::CCAssignFnForCall(), changeFPCCToAArch64CC(), changeIntCCToAArch64CC(), llvm::CCState::CheckReturn(), llvm::AArch64Subtarget::classifyGlobalFunctionReference(), llvm::AArch64Subtarget::ClassifyGlobalReference(), contains(), Context, llvm::SmallSet< T, N, C >::count(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::AArch64ISD::CSEL, llvm::AArch64ISD::CSINC, llvm::AArch64ISD::CSINV, llvm::AArch64ISD::CSNEG, llvm::ISD::CTPOP, llvm::dbgs(), DL, llvm::dyn_cast(), llvm::numbers::e, llvm::TargetOptions::EmitCallSiteInfo, emitComparison(), llvm::AArch64RegisterInfo::emitReservedArgRegCallError(), emitStrictFPComparison(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< SmallVectorSizeType< T > >::empty(), EnableAArch64ELFLocalDynamicTLSGeneration, llvm::SmallVectorTemplateCommon< T >::end(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::AArch64CC::EQ, llvm::SmallVectorImpl< T >::erase(), F(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CallingConv::Fast, llvm::find_if(), llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::CCValAssign::FPExt, llvm::CCValAssign::Full, G, llvm::TLSModel::GeneralDynamic, getAArch64Cmp(), getAArch64XALUOOp(), llvm::ConstantPoolSDNode::getAlign(), llvm::SelectionDAG::getBitcast(), llvm::BlockAddressSDNode::getBlockAddress(), llvm::AArch64FunctionInfo::getBytesInStackArgArea(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::AArch64RegisterInfo::getCalleeSavedRegsViaCopy(), llvm::Function::getCallingConv(), llvm::AArch64RegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCALLSEQ_START(), llvm::codegen::getCodeModel(), llvm::TargetMachine::getCodeModel(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::ConstantPoolSDNode::getConstVal(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MVT::getFloatingPointVT(), llvm::AArch64FunctionInfo::getForwardedMustTailRegParms(), llvm::SelectionDAG::getFrameIndex(), llvm::TargetLoweringBase::getFrameIndexTy(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::GlobalAddressSDNode::getGlobal(), llvm::MachinePointerInfo::getGOT(), llvm::JumpTableSDNode::getIndex(), llvm::MachineFunction::getInfo(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMergeValues(), llvm::CCState::getNextStackOffset(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::ISD::ArgFlagsTy::getNonZeroByValAlign(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::getOffset(), llvm::GlobalAddressSDNode::getOffset(), llvm::ConstantPoolSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::AArch64TargetLowering::getPointerTy(), llvm::DataLayout::getPrefTypeAlign(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::EVT::getScalarSizeInBits(), llvm::ISD::getSetCCInverse(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::MachinePointerInfo::getStack(), llvm::SelectionDAG::getStore(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SelectionDAG::getTargetInsertSubreg(), llvm::SelectionDAG::getTargetJumpTable(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetMachine::getTargetTriple(), llvm::AArch64RegisterInfo::getThisReturnPreservedMask(), llvm::AArch64RegisterInfo::getTLSCallPreservedMask(), llvm::TargetMachine::getTLSModel(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::CCValAssign::getValVT(), llvm::EVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::TargetOptions::GuaranteedTailCallOpt, llvm::AArch64Subtarget::hasCustomCallingConv(), llvm::GlobalValue::hasExternalWeakLinkage(), llvm::Function::hasFnAttribute(), llvm::AArch64Subtarget::hasFullFP16(), llvm::AArch64Subtarget::hasNEON(), llvm::MipsISD::Hi, I, llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::tgtok::In, llvm::AArch64FunctionInfo::incNumLocalDynamicTLSAccesses(), llvm::CCValAssign::Indirect, llvm::TLSModel::InitialExec, llvm::SmallSet< T, N, C >::insert(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), llvm::isAllOnesConstant(), llvm::ConstantSDNode::isAllOnesValue(), llvm::AArch64RegisterInfo::isAnyArgRegReserved(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegs(), llvm::EVT::isInteger(), llvm::AArch64Subtarget::isLittleEndian(), llvm::CCValAssign::isMemLoc(), llvm::isNullConstant(), llvm::ConstantSDNode::isNullValue(), llvm::ConstantSDNode::isOne(), llvm::isOneConstant(), llvm::Triple::isOSBinFormatELF(), llvm::Triple::isOSBinFormatMachO(), llvm::Triple::isOSWindows(), llvm::ISD::isOverflowIntrOpRes(), llvm::isPowerOf2_64(), llvm::CCValAssign::isRegLoc(), llvm::ISD::ArgFlagsTy::isReturned(), llvm::EVT::isScalableVector(), llvm::MVT::isScalableVector(), llvm::EVT::isSimple(), llvm::SDNode::isStrictFPOpcode(), llvm::ISD::ArgFlagsTy::isSwiftSelf(), llvm::AArch64Subtarget::isTargetDarwin(), llvm::AArch64Subtarget::isTargetELF(), llvm::AArch64Subtarget::isTargetMachO(), llvm::AArch64Subtarget::isTargetWindows(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::ConstantFPSDNode::isZero(), llvm::HexagonISD::JT, llvm::CodeModel::Large, LLVM_DEBUG, llvm_unreachable, llvm::MipsISD::Lo, llvm::AArch64ISD::LOADgot, llvm::TLSModel::LocalDynamic, llvm::TLSModel::LocalExec, llvm::Log2_64(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::BitmaskEnumDetail::Mask(), llvm::AArch64II::MO_COFFSTUB, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_HI12, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_NO_FLAG, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::AArch64II::MO_TLS, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, MRI, N, llvm::AArch64CC::NE, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLowering::parametersInCSRMatch(), llvm::CallingConv::PreserveMost, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::remove_if(), llvm::report_fatal_error(), llvm::CCState::resultsCompatible(), llvm::MipsISD::Ret, llvm::AArch64ISD::RET_FLAG, llvm::RetCC_AArch64_AAPCS(), llvm::RetCC_AArch64_WebKit_JS(), llvm::MachineFrameInfo::setAdjustsStack(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::MachineFrameInfo::setHasTailCall(), llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUNE, llvm::CCValAssign::SExt, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase< SmallVectorSizeType< T > >::size(), llvm::TargetLowering::softenSetCCOperands(), llvm::ISD::SPLAT_VECTOR, llvm::SPII::Store, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, llvm::TargetStackID::SVEVector, std::swap(), llvm::CallingConv::Swift, llvm::AArch64ISD::TBNZ, llvm::AArch64ISD::TBZ, llvm::AArch64ISD::TC_RETURN, llvm::Test, llvm::AArch64ISD::THREAD_POINTER, llvm::CodeModel::Tiny, llvm::AArch64ISD::TLSDESC_CALLSEQ, llvm::TargetOptions::TLSSize, llvm::ISD::TokenFactor, TRI, llvm::CCValAssign::Trunc, llvm::ISD::TRUNCATE, llvm::TargetOptions::UnsafeFPMath, llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask(), llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::TargetMachine::useEmulatedTLS(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VSELECT, llvm::ISD::InputArg::VT, llvm::ISD::OutputArg::VT, llvm::CallingConv::WebKit_JS, llvm::CallingConv::Win64, llvm::AArch64ISD::WrapperLarge, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::CCValAssign::ZExt.
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NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
Definition at line 6940 of file AArch64ISelLowering.cpp.
References DL, llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().
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Definition at line 8290 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), llvm::SDNode::ops(), and llvm::SmallVectorTemplateBase< T >::push_back().
Referenced by ConstantBuildVector().
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Definition at line 1097 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, DL, llvm::AArch64_AM::encodeLogicalImmediate(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MipsISD::Hi, llvm::AArch64_AM::isLogicalImmediate(), llvm::isShiftedMask_64(), llvm::BitmaskEnumDetail::Mask(), and Size.
Referenced by llvm::AArch64TargetLowering::targetShrinkDemandedConstant().
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Definition at line 6594 of file AArch64ISelLowering.cpp.
References assert(), C, llvm::TargetLowering::C_Immediate, llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_Other, llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::dyn_cast(), llvm::Failed(), llvm::StringRef::getAsInteger(), llvm::TargetLowering::getConstraintType(), llvm::SDValue::getNode(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::SelectionDAG::getRegister(), llvm::ConstantSDNode::getSExtValue(), llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::Value::getType(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::AArch64Subtarget::hasFPARMv8(), llvm::MVT::i32, llvm::MVT::i64, info, llvm::Invalid, llvm::Type::isFloatingPointTy(), llvm::AArch64_AM::isLogicalImmediate(), llvm::isNullConstant(), llvm::MVT::isScalableVector(), llvm::isUInt< 32 >(), llvm::Type::isVectorTy(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::MVT::Other, P, Size, llvm::StringRef::size(), llvm::StringRef::slice(), TRI, Upa, and Upl.
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Definition at line 11500 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::is128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractHighSubvector(), performSetccAddFolding(), llvm::ISD::SIGN_EXTEND, tryExtendDUPToExtractHigh(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 11056 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::BICi, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), performSVEAndCombine(), resolveBuildVector(), tryAdvSIMDModImm16(), and tryAdvSIMDModImm32().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13096 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, assert(), llvm::ISD::BR, llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::AArch64CC::EQ, llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::Function::hasFnAttribute(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i32, llvm::MVT::i64, llvm::isNullConstant(), llvm::AArch64CC::NE, llvm::MVT::Other, performCONDCombine(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::AArch64ISD::SUBS, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 11127 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::dbgs(), llvm::AArch64ISD::DUPLANE64, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MVT::isVector(), LLVM_DEBUG, llvm::BitmaskEnumDetail::Mask(), llvm::AArch64ISD::SRHADD, llvm::ISD::TRUNCATE, llvm::AArch64ISD::URHADD, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v8i16, and WidenVector().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13022 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, checkValueWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), isEquivalentMaskless(), llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.
Referenced by performBRCONDCombine(), and llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12064 of file AArch64ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::MVT::getIntegerVT(), getIntrinsicID(), llvm::TypeSize::getKnownMinSize(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::MipsISD::Hi, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MipsISD::Lo, tryCombineLongOpWithDup(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Fold a floating-point divide by power of two into fixed-point to floating-point conversion.
Definition at line 10747 of file AArch64ISelLowering.cpp.
References C, DL, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v4i64, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Fold a floating-point multiply by power of two into floating-point to fixed-point conversion.
Definition at line 10672 of file AArch64ISelLowering.cpp.
References assert(), llvm::tgtok::Bits, C, DL, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::TRUNCATE, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i32, and llvm::MVT::v4i64.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13568 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), getScaledOffsetForBitWidth(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), isValidImmForSVEVecImmAddrMode(), llvm::EVT::isVector(), llvm::SPII::Load, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv4i32, llvm::MVT::Other, llvm::MVT::SimpleTy, llvm::AArch64::SVEBitsPerBlock, std::swap(), and llvm::ISD::TRUNCATE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13366 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, C, llvm::AArch64Subtarget::ClassifyGlobalReference(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::Module::getDataLayout(), llvm::SelectionDAG::getGlobalAddress(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::GlobalValue::getParent(), llvm::DataLayout::getTypeAllocSize(), llvm::GlobalValue::getValueType(), llvm::MVT::i64, llvm::Type::isSized(), llvm::min(), llvm::AArch64II::MO_NO_FLAG, N, llvm::ISD::SUB, and llvm::SDNode::uses().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10382 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::AArch64ISD::CSEL, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::AArch64CC::PL, llvm::ISD::SRA, llvm::ISD::SUB, llvm::AArch64ISD::SUBS, and llvm::ISD::XOR.
Referenced by performXorCombine().
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Definition at line 11882 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ANDV_PRED, llvm::AArch64CC::ANY_ACTIVE, combineAcrossLanesIntrinsic(), combineSVEReductionFP(), combineSVEReductionOrderedFP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::EORV_PRED, llvm::AArch64ISD::FADDA_PRED, llvm::AArch64ISD::FADDV_PRED, llvm::AArch64CC::FIRST_ACTIVE, llvm::ISD::FMAXIMUM, llvm::AArch64ISD::FMAXNMV_PRED, llvm::ISD::FMAXNUM, llvm::AArch64ISD::FMAXV_PRED, llvm::ISD::FMINIMUM, llvm::AArch64ISD::FMINNMV_PRED, llvm::ISD::FMINNUM, llvm::AArch64ISD::FMINV_PRED, llvm::SelectionDAG::getCondCode(), getIntrinsicID(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), getPTest(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::isFloatingPoint(), llvm::AArch64CC::LAST_ACTIVE, LowerSVEIntReduction(), LowerSVEIntrinsicDUP(), LowerSVEIntrinsicEXT(), LowerSVEIntrinsicIndex(), llvm::AArch64ISD::ORV_PRED, llvm::AArch64ISD::SADDV, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::AArch64ISD::SHL_MERGE_OP1, llvm::AArch64ISD::SMAX_MERGE_OP1, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMAXV_PRED, llvm::AArch64ISD::SMIN_MERGE_OP1, llvm::AArch64ISD::SMINV, llvm::AArch64ISD::SMINV_PRED, llvm::ISD::SPLAT_VECTOR, llvm::AArch64ISD::SRA_MERGE_OP1, llvm::AArch64ISD::SRL_MERGE_OP1, tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineShiftImm(), tryConvertSVEWideCompare(), llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UMAX_MERGE_OP1, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMAXV_PRED, llvm::AArch64ISD::UMIN_MERGE_OP1, llvm::AArch64ISD::UMINV, llvm::AArch64ISD::UMINV_PRED, and llvm::ISD::VSELECT.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10631 of file AArch64ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::AArch64Subtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalLoad(), isVolatile(), llvm::SPII::Load, performVectorCompareAndMaskUnaryOpCombine(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SINT_TO_FP, llvm::AArch64ISD::SITOF, and llvm::AArch64ISD::UITOF.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12229 of file AArch64ISelLowering.cpp.
References DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), getSVEContainerType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::EVT::isInteger(), llvm::SPII::Load, llvm::MVT::Other, llvm::AArch64::SVEBitsPerBlock, and llvm::ISD::TRUNCATE.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12285 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::isFloatingPoint(), llvm::AArch64ISD::LD1RO_MERGE_ZERO, llvm::AArch64ISD::LD1RQ_MERGE_ZERO, llvm::SPII::Load, and llvm::MVT::Other.
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Definition at line 12255 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::isFloatingPoint(), N, llvm::ISD::NON_EXTLOAD, llvm::MVT::nxv8bf16, and llvm::ISD::UNINDEXED.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10477 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::APInt::ashr(), assert(), C, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::APInt::isPowerOf2(), isSignExtended(), IsSVECntIntrinsic(), isZeroExtended(), llvm::APInt::logBase2(), llvm::ISD::SHL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::SDNode::use_begin().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.
Definition at line 12704 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm_unreachable, llvm::makeArrayRef(), N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, llvm::AArch64ISD::ST4post, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
Get rid of unnecessary NVCASTs (that don't change the type).
Definition at line 13356 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), and llvm::SDNode::getValueType().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10925 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::isTypeLegal(), tryCombineToBSL(), and tryCombineToEXTR().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R.
Definition at line 12565 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isScalableVector(), llvm::ARM_MB::LD, llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::ISD::LOAD, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and llvm::Vector.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 13464 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), getScaledOffsetForBitWidth(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getSVEContainerType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::EVT::isScalableVector(), isValidImmForSVEVecImmAddrMode(), llvm::EVT::isVector(), llvm::MVT::nxv2f64, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv4f32, llvm::MVT::nxv4i32, llvm::MVT::Other, llvm::MVT::SimpleTy, llvm::AArch64ISD::SST1_IMM_PRED, llvm::AArch64ISD::SST1_PRED, llvm::AArch64ISD::SST1_UXTW_PRED, llvm::AArch64ISD::SSTNT1_INDEX_PRED, llvm::AArch64ISD::SSTNT1_PRED, llvm::AArch64::SVEBitsPerBlock, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar.
This replaces any scalar setcc in the above pattern with a vector one followed by a DUP shuffle on the result.
Definition at line 13295 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::SETCC.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 11450 of file AArch64ISelLowering.cpp.
References SetCCInfo::AArch64, llvm::ISD::ADD, assert(), GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, isSetCCOrZExtSetCC(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, and std::swap().
Referenced by performAddSubLongCombine().
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Definition at line 13670 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, llvm::MipsISD::Ext, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::AArch64ISD::GLDNT1S_MERGE_ZERO, llvm::SDValue::hasOneUse(), I, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LD1S_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDFF1S_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1S_MERGE_ZERO, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64ISD::SUNPKHI, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::UUNPKHI, and llvm::AArch64ISD::UUNPKLO.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 11099 of file AArch64ISelLowering.cpp.
References llvm::ISD::BSWAP, C, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::MaskedValueIsZero(), and llvm::ISD::ROTR.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12306 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::Data, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), getSVEContainerType(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::isFloatingPoint(), llvm::MVT::nxv8bf16, and llvm::AArch64ISD::ST1_PRED.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12336 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), llvm::Data, DL, llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::isFloatingPoint(), N, llvm::MVT::nxv8bf16, and llvm::ISD::UNINDEXED.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 12687 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOperand(), performTBISimplification(), splitStores(), and llvm::AArch64Subtarget::supportsAddressTopByteIgnored().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10970 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, C, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::DUP, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::ConstantSDNode::getZExtValue(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isConstantSplatVectorMaskForType(), llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::BitmaskEnumDetail::Mask(), llvm::APInt::trunc(), llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, and llvm::APInt::zextOrTrunc().
Referenced by performANDCombine().
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Simplify Addr given that the top byte of it is ignored by HW during address translation.
Definition at line 12672 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), and performSTORECombine().
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Definition at line 13235 of file AArch64ISelLowering.cpp.
References assert(), llvm::tgtok::Bit, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getTestBitOperand(), llvm::MVT::i64, llvm::MVT::Other, llvm::AArch64ISD::TBNZ, and llvm::AArch64ISD::TBZ.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10585 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::isVector(), and llvm::ISD::SETCC.
Referenced by performIntToFpCombine().
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Definition at line 13266 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, llvm::ISD::SETCC, and llvm::ISD::VSELECT.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10409 of file AArch64ISelLowering.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::APInt::countTrailingZeros(), llvm::AArch64ISD::CSEL, DL, foldVectorXorShiftIntoCmp(), getAArch64Cmp(), llvm::Function::getAttributes(), llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::AArch64TargetLowering::isIntDivCheap(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), performIntegerAbsCombine(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SETLT, llvm::ISD::SRA, and llvm::ISD::SUB.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 14248 of file AArch64ISelLowering.cpp.
References llvm::MVT::bf16, llvm::ISD::BITCAST, DL, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::TRUNCATE.
Referenced by ReplaceCMP_SWAP_128Results().
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Definition at line 14341 of file AArch64ISelLowering.cpp.
References llvm::Acquire, llvm::AcquireRelease, llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, llvm::SmallVectorImpl< T >::append(), assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::BITCAST, llvm::ISD::BUILD_PAIR, llvm::AArch64ISD::CLASTA_N, llvm::AArch64ISD::CLASTB_N, createGPRPairNode(), llvm::ISD::CTPOP, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineMemOperand::getOrdering(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::AArch64Subtarget::hasLSE(), llvm::MipsISD::Hi, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::DataLayout::isBigEndian(), llvm::MemSDNode::isVolatile(), llvm::AArch64ISD::LASTA, llvm::AArch64ISD::LASTB, llvm::AArch64ISD::LDP, llvm_unreachable, llvm::MipsISD::Lo, llvm::ISD::LOAD, llvm::Monotonic, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::Release, ReplaceBITCASTResults(), ReplaceReductionResults(), llvm::AArch64ISD::SADDV, llvm::SequentiallyConsistent, llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::SMAX, llvm::AArch64ISD::SMAXV, llvm::ISD::SMIN, llvm::AArch64ISD::SMINV, splitInt128(), std::swap(), llvm::ISD::TRUNCATE, llvm::AArch64ISD::UADDV, llvm::ISD::UMAX, llvm::AArch64ISD::UMAXV, llvm::ISD::UMIN, llvm::AArch64ISD::UMINV, llvm::MVT::Untyped, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, and llvm::ISD::VECREDUCE_UMIN.
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Definition at line 14266 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDNode::getValueType(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::SelectionDAG::SplitVectorOperand().
Referenced by ReplaceCMP_SWAP_128Results().
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Replace a splat of a scalar to a vector store by scalar stores of the scalar value.
The load store optimizer pass will merge them to store pair stores. This has better performance than a splat of the scalar followed by a split vector store. Even if the stores are not merged it is four stores vs a dup, followed by an ext.b and two stores.
Definition at line 12439 of file AArch64ISelLowering.cpp.
References llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::StoreSDNode::isTruncatingStore(), and splitStoreSplat().
Referenced by splitStores().
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Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.
The load store optimizer pass will merge them to store pair stores. This should be better than a movi to create the vector zero followed by a vector store if the zero constant is not re-used, since one instructions and one register live range will be removed.
For example, the final generated code should be:
stp xzr, xzr, [x0]
instead of:
movi v0.2d, #0 str q0, [x0]
Definition at line 12372 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DL, llvm::StoreSDNode::getBasePtr(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isNullConstant(), llvm::isNullFPConstant(), llvm::EVT::isScalableVector(), llvm::StoreSDNode::isTruncatingStore(), and splitStoreSplat().
Referenced by splitStores().
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Definition at line 7911 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::BuildVectorSDNode::isConstantSplat(), and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector(), EmitVectorComparison(), performANDCombine(), and tryLowerToSLI().
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Set the IntrinsicInfo for the aarch64_sve_st<N> intrinsics.
Definition at line 9309 of file AArch64ISelLowering.cpp.
References assert(), llvm::CallBase::getArgOperand(), llvm::Type::getContext(), llvm::EVT::getEVT(), llvm::CallBase::getNumArgOperands(), llvm::EVT::getScalarType(), llvm::Value::getType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), I, llvm::ISD::INTRINSIC_VOID, and llvm::MachineMemOperand::MOStore.
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Definition at line 2992 of file AArch64ISelLowering.cpp.
References addRequiredExtensionForVectorMULL(), assert(), llvm::ISD::BUILD_VECTOR, C, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerMUL().
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Definition at line 14280 of file AArch64ISelLowering.cpp.
References DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementCount(), llvm::MipsISD::Hi, llvm::MVT::i128, llvm::MVT::i64, llvm::tgtok::In, llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::MipsISD::Lo, llvm::ElementCount::Min, llvm::SmallVectorTemplateBase< T >::push_back(), Results, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, and llvm::EVT::widenIntegerVectorElementType().
Referenced by ReplaceCMP_SWAP_128Results().
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Definition at line 12492 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::MachineFunction::getFunction(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::Function::hasMinSize(), llvm::MVT::i64, llvm::EVT::isFixedLengthVector(), llvm::LSBaseSDNode::isIndexed(), llvm::AArch64Subtarget::isMisaligned128StoreSlow(), llvm::MemSDNode::isVolatile(), N, replaceSplatVectorStore(), replaceZeroVectorStore(), and llvm::MVT::v2i64.
Referenced by performSTORECombine().
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Definition at line 12159 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::StoreSDNode::isTruncatingStore(), and llvm::MinAlign().
Referenced by replaceSplatVectorStore(), and replaceZeroVectorStore().
| STATISTIC | ( | NumTailCalls | , |
| "Number of tail calls" | |||
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| STATISTIC | ( | NumShiftInserts | , |
| "Number of vector shift inserts" | |||
| ) |
| STATISTIC | ( | NumOptimizedImms | , |
| "Number of times immediates were optimized" | |||
| ) |
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Definition at line 8003 of file AArch64ISelLowering.cpp.
References llvm::AArch64_AM::encodeAdvSIMDModImmType5(), llvm::AArch64_AM::encodeAdvSIMDModImmType6(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType5(), llvm::AArch64_AM::isAdvSIMDModImmType6(), llvm::AArch64ISD::NVCAST, llvm::MVT::v4i16, llvm::MVT::v8i16, and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector(), performANDCombine(), and tryLowerToSLI().
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Definition at line 7955 of file AArch64ISelLowering.cpp.
References llvm::AArch64_AM::encodeAdvSIMDModImmType1(), llvm::AArch64_AM::encodeAdvSIMDModImmType2(), llvm::AArch64_AM::encodeAdvSIMDModImmType3(), llvm::AArch64_AM::encodeAdvSIMDModImmType4(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType1(), llvm::AArch64_AM::isAdvSIMDModImmType2(), llvm::AArch64_AM::isAdvSIMDModImmType3(), llvm::AArch64_AM::isAdvSIMDModImmType4(), llvm::AArch64ISD::NVCAST, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector(), performANDCombine(), and tryLowerToSLI().
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Definition at line 8043 of file AArch64ISelLowering.cpp.
References llvm::AArch64_AM::encodeAdvSIMDModImmType7(), llvm::AArch64_AM::encodeAdvSIMDModImmType8(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType7(), llvm::AArch64_AM::isAdvSIMDModImmType8(), llvm::AArch64ISD::NVCAST, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector().
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Definition at line 7934 of file AArch64ISelLowering.cpp.
References llvm::AArch64_AM::encodeAdvSIMDModImmType10(), llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType10(), llvm::AArch64ISD::NVCAST, llvm::MVT::v2i64, and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector().
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Definition at line 8074 of file AArch64ISelLowering.cpp.
References llvm::AArch64_AM::encodeAdvSIMDModImmType9(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType9(), llvm::AArch64ISD::NVCAST, llvm::MVT::v16i8, llvm::MVT::v8i8, and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector().
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Definition at line 8095 of file AArch64ISelLowering.cpp.
References llvm::AArch64_AM::encodeAdvSIMDModImmType11(), llvm::AArch64_AM::encodeAdvSIMDModImmType12(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::AArch64_AM::isAdvSIMDModImmType11(), llvm::AArch64_AM::isAdvSIMDModImmType12(), llvm::AArch64ISD::NVCAST, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v4f32, and llvm::APInt::zextOrTrunc().
Referenced by ConstantBuildVector().
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Definition at line 11649 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::BitmaskEnumDetail::Mask().
Referenced by performIntrinsicCombine().
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Definition at line 11255 of file AArch64ISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm_unreachable, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.
Referenced by performIntrinsicCombine().
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Definition at line 11549 of file AArch64ISelLowering.cpp.
References assert(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractHighSubvector(), and tryExtendDUPToExtractHigh().
Referenced by performExtendCombine(), and performIntrinsicCombine().
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Definition at line 11578 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm_unreachable, llvm::AArch64ISD::SQSHL_I, llvm::AArch64ISD::SQSHLU_I, llvm::AArch64ISD::SRSHR_I, llvm::AArch64ISD::UQSHL_I, llvm::AArch64ISD::URSHR_I, and llvm::AArch64ISD::VSHL.
Referenced by performIntrinsicCombine().
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Definition at line 10878 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::tgtok::Bits, llvm::AArch64ISD::BSP, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), and llvm::EVT::isVector().
Referenced by performORCombine().
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EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair.
This function looks for the pattern: (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an EXTR. Can't quite be done in TableGen because the two immediates aren't independent.
Definition at line 10838 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::AArch64ISD::EXTR, findEXTRHalf(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::OR, and std::swap().
Referenced by performORCombine().
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Definition at line 11754 of file AArch64ISelLowering.cpp.
References DL, llvm::AArch64ISD::DUP, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), getIntrinsicID(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm_unreachable, llvm::AArch64ISD::SETCC_MERGE_ZERO, and llvm::ISD::SPLAT_VECTOR.
Referenced by performIntrinsicCombine().
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Definition at line 11317 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, llvm::MVT::is64BitVector(), llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, and llvm::SDNode::ops().
Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().
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Definition at line 7416 of file AArch64ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i64, isConcatMask(), and llvm::BitmaskEnumDetail::Mask().
Referenced by getDUPLANEOp().
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Definition at line 8165 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::AArch64ISD::BICi, llvm::dbgs(), DL, llvm::SDNode::dump(), llvm::dyn_cast(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), isAllConstantBuildVector(), llvm::EVT::isVector(), LLVM_DEBUG, llvm::AArch64ISD::ORRi, resolveBuildVector(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, llvm::AArch64ISD::VSLI, llvm::AArch64ISD::VSRI, X, and Y.
Definition at line 14687 of file AArch64ISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::CreatePointerCast(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt8PtrTy(), llvm::IRBuilderBase::getInt8Ty(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), and llvm::Type::getPointerTo().
Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), and llvm::AArch64TargetLowering::getSafeStackPointerLocation().
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WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class.
Definition at line 6920 of file AArch64ISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i32, and llvm::ISD::INSERT_SUBVECTOR.
Referenced by ConstantBuildVector(), GeneratePerfectShuffle(), getDUPLANEOp(), NarrowVector(), performConcatVectorsCombine(), and llvm::SelectionDAG::SplitVectorOperand().
| cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false)) |
Referenced by mayTailCallThisCC().
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Referenced by llvm::AArch64TargetLowering::targetShrinkDemandedConstant().
Value type used for condition codes.
Definition at line 117 of file AArch64ISelLowering.cpp.
1.8.13