20#define GET_TARGET_REGBANK_IMPL
21#include "X86GenRegisterBank.inc"
25#define GET_TARGET_REGBANK_INFO_IMPL
26#include "X86GenRegisterBankInfo.def"
33 assert(&X86::GPRRegBank == &RBGPR &&
"Incorrect RegBanks inizalization.");
38 "Subclass not added?");
39 assert(RBGPR.
getSize() == 64 &&
"GPRs should hold up to 64-bit");
46 if (X86::GR8RegClass.hasSubClassEq(&RC) ||
47 X86::GR16RegClass.hasSubClassEq(&RC) ||
48 X86::GR32RegClass.hasSubClassEq(&RC) ||
49 X86::GR64RegClass.hasSubClassEq(&RC) ||
50 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) ||
51 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC))
54 if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
55 X86::FR64XRegClass.hasSubClassEq(&RC) ||
56 X86::VR128XRegClass.hasSubClassEq(&RC) ||
57 X86::VR256XRegClass.hasSubClassEq(&RC) ||
58 X86::VR512RegClass.hasSubClassEq(&RC))
64X86GenRegisterBankInfo::PartialMappingIdx
110void X86RegisterBankInfo::getInstrPartialMappingIdxs(
114 unsigned NumOperands =
MI.getNumOperands();
115 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
116 auto &MO =
MI.getOperand(
Idx);
117 if (!MO.isReg() || !MO.getReg())
118 OpRegBankIdx[
Idx] = PMI_None;
124bool X86RegisterBankInfo::getInstrValueMapping(
129 unsigned NumOperands =
MI.getNumOperands();
130 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
131 if (!
MI.getOperand(
Idx).isReg())
133 if (!
MI.getOperand(
Idx).getReg())
137 if (!Mapping->isValid())
140 OpdsMapping[
Idx] = Mapping;
146X86RegisterBankInfo::getSameOperandsMapping(
const MachineInstr &
MI,
151 unsigned NumOperands =
MI.getNumOperands();
152 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
154 if (NumOperands != 3 || (Ty !=
MRI.getType(
MI.getOperand(1).getReg())) ||
155 (Ty !=
MRI.getType(
MI.getOperand(2).getReg())))
166 unsigned Opc =
MI.getOpcode();
177 case TargetOpcode::G_ADD:
178 case TargetOpcode::G_SUB:
179 case TargetOpcode::G_MUL:
180 return getSameOperandsMapping(
MI,
false);
181 case TargetOpcode::G_FADD:
182 case TargetOpcode::G_FSUB:
183 case TargetOpcode::G_FMUL:
184 case TargetOpcode::G_FDIV:
185 return getSameOperandsMapping(
MI,
true);
186 case TargetOpcode::G_SHL:
187 case TargetOpcode::G_LSHR:
188 case TargetOpcode::G_ASHR: {
189 unsigned NumOperands =
MI.getNumOperands();
190 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
200 unsigned NumOperands =
MI.getNumOperands();
204 case TargetOpcode::G_FPEXT:
205 case TargetOpcode::G_FPTRUNC:
206 case TargetOpcode::G_FCONSTANT:
208 getInstrPartialMappingIdxs(
MI,
MRI,
true, OpRegBankIdx);
210 case TargetOpcode::G_SITOFP:
211 case TargetOpcode::G_FPTOSI: {
214 auto &Op0 =
MI.getOperand(0);
215 auto &Op1 =
MI.getOperand(1);
216 const LLT Ty0 =
MRI.getType(Op0.getReg());
217 const LLT Ty1 =
MRI.getType(Op1.getReg());
219 bool FirstArgIsFP = Opc == TargetOpcode::G_SITOFP;
220 bool SecondArgIsFP = Opc == TargetOpcode::G_FPTOSI;
225 case TargetOpcode::G_FCMP: {
226 LLT Ty1 =
MRI.getType(
MI.getOperand(2).getReg());
227 LLT Ty2 =
MRI.getType(
MI.getOperand(3).getReg());
230 "Mismatched operand sizes for G_FCMP");
234 assert((
Size == 32 ||
Size == 64) &&
"Unsupported size for G_FCMP");
237 OpRegBankIdx = {PMI_GPR8,
238 PMI_None, FpRegBank, FpRegBank};
241 case TargetOpcode::G_TRUNC:
242 case TargetOpcode::G_ANYEXT: {
243 auto &Op0 =
MI.getOperand(0);
244 auto &Op1 =
MI.getOperand(1);
245 const LLT Ty0 =
MRI.getType(Op0.getReg());
246 const LLT Ty1 =
MRI.getType(Op1.getReg());
253 Opc == TargetOpcode::G_ANYEXT;
255 getInstrPartialMappingIdxs(
MI,
MRI, isFPTrunc || isFPAnyExt,
260 getInstrPartialMappingIdxs(
MI,
MRI,
false, OpRegBankIdx);
266 if (!getInstrValueMapping(
MI, OpRegBankIdx, OpdsMapping))
286 switch (
MI.getOpcode()) {
287 case TargetOpcode::G_LOAD:
288 case TargetOpcode::G_STORE:
289 case TargetOpcode::G_IMPLICIT_DEF: {
295 unsigned NumOperands =
MI.getNumOperands();
299 getInstrPartialMappingIdxs(
MI,
MRI,
true, OpRegBankIdx);
303 if (!getInstrValueMapping(
MI, OpRegBankIdx, OpdsMapping))
unsigned const MachineRegisterInfo * MRI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file declares the targeting of the RegisterBankInfo class for X86.
constexpr bool isScalar() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP)
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx Idx, unsigned NumOperands)
X86RegisterBankInfo(const TargetRegisterInfo &TRI)
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.