22#include "llvm/Config/llvm-config.h"
28#define DEBUG_TYPE "registerbankinfo"
33 "Number of partial mappings dynamically created");
35 "Number of partial mappings dynamically accessed");
37 "Number of value mappings dynamically created");
39 "Number of value mappings dynamically accessed");
41 "Number of operands mappings dynamically created");
43 "Number of operands mappings dynamically accessed");
45 "Number of instruction mappings dynamically created");
47 "Number of instruction mappings dynamically accessed");
57 : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
71 "ID does not match the index in the array");
82 if (!Reg.isVirtual()) {
100 assert(Reg.isPhysical() &&
"Reg must be a physreg");
103 return RegRCIt->second;
125 "The mapping of the register bank does not make sense");
133 auto &RegClassOrBank =
MRI.getRegClassOrRegBank(Reg);
135 return MRI.constrainRegClass(Reg, &RC);
139 if (RB && !RB->
covers(RC))
143 MRI.setRegClass(Reg, &RC);
154 return MI.isCopy() ||
MI.isPHI() ||
155 MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
166 unsigned NumOperandsForMapping = IsCopyLike ? 1 :
MI.getNumOperands();
177 bool CompleteMapping =
true;
180 for (
unsigned OpIdx = 0, EndIdx =
MI.getNumOperands(); OpIdx != EndIdx;
197 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank :
nullptr;
204 CompleteMapping =
false;
216 if (!OperandsMapping[0]) {
217 if (
MI.isRegSequence()) {
223 OperandsMapping[0] = ValMapping;
230 for (; OpIdx != EndIdx; ++OpIdx) {
244 CompleteMapping =
true;
248 OperandsMapping[OpIdx] = ValMapping;
251 if (IsCopyLike && !CompleteMapping) {
256 assert(CompleteMapping &&
"Setting an uncomplete mapping");
260 NumOperandsForMapping);
279 ++NumPartialMappingsAccessed;
286 ++NumPartialMappingsCreated;
289 PartMapping = std::make_unique<PartialMapping>(StartIdx,
Length, RegBank);
301 unsigned NumBreakDowns) {
305 for (
unsigned Idx = 0;
Idx != NumBreakDowns; ++
Idx)
312 unsigned NumBreakDowns)
const {
313 ++NumValueMappingsAccessed;
320 ++NumValueMappingsCreated;
323 ValMapping = std::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
327template <
typename Iterator>
331 ++NumOperandsMappingsAccessed;
340 ++NumOperandsMappingsCreated;
347 Res = std::make_unique<ValueMapping[]>(std::distance(Begin, End));
349 for (Iterator It = Begin; It != End; ++It, ++
Idx) {
365 std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
373 unsigned NumOperands) {
378RegisterBankInfo::getInstructionMappingImpl(
379 bool IsInvalid,
unsigned ID,
unsigned Cost,
381 unsigned NumOperands)
const {
383 OperandsMapping ==
nullptr && NumOperands == 0) ||
385 "Mismatch argument for invalid input");
386 ++NumInstructionMappingsAccessed;
394 ++NumInstructionMappingsCreated;
397 InstrMapping = std::make_unique<InstructionMapping>(
398 ID, Cost, OperandsMapping, NumOperands);
399 return *InstrMapping;
414 if (Mapping.isValid()) {
424 assert(Mapping->verify(
MI) &&
"Mapping is invalid");
426 return PossibleMappings;
439 for (
unsigned OpIdx = 0,
441 OpIdx != EndIdx; ++OpIdx) {
460 "This mapping is too complex for this function");
463 if (NewRegs.
empty()) {
464 LLVM_DEBUG(
dbgs() <<
" has not been repaired, nothing to be done\n");
475 LLT OrigTy =
MRI.getType(OrigReg);
476 LLT NewTy =
MRI.getType(NewReg);
477 if (OrigTy != NewTy) {
483 "Types with difference size cannot be handled by the default "
485 LLVM_DEBUG(
dbgs() <<
"\nChange type of new opd from " << NewTy <<
" to "
487 MRI.setType(NewReg, OrigTy);
496 if (Reg.isPhysical()) {
502 assert(RC &&
"Expecting Register class");
503 return TRI.getRegSizeInBits(*RC);
505 return TRI.getRegSizeInBits(Reg,
MRI);
511#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
519 assert(RegBank &&
"Register bank not set");
521 assert((StartIdx <= getHighBitIdx()) &&
"Overflow, switch to APInt?");
523 assert(RegBank->getSize() >=
Length &&
"Register bank too small for Mask");
528 OS <<
"[" << StartIdx <<
", " << getHighBitIdx() <<
"], RegBank = ";
536 if (NumBreakDowns < 2)
540 for (
const PartialMapping *Part = First + 1; Part != end(); ++Part) {
541 if (Part->Length != First->Length || Part->RegBank != First->RegBank)
549 assert(NumBreakDowns &&
"Value mapped nowhere?!");
550 unsigned OrigValueBitWidth = 0;
554 assert(PartMap.
verify() &&
"Partial mapping is invalid");
560 assert(OrigValueBitWidth >= MeaningfulBitWidth &&
561 "Meaningful bits not covered by the mapping");
562 APInt ValueMask(OrigValueBitWidth, 0);
569 ValueMask ^= PartMapMask;
570 assert((ValueMask & PartMapMask) == PartMapMask &&
571 "Some partial mappings overlap");
577#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
585 OS <<
"#BreakDown: " << NumBreakDowns <<
" ";
590 OS <<
'[' << PartMap <<
']';
601 "NumOperands must match, see constructor");
603 "MI must be connected to a MachineFunction");
609 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
613 "We should not care about non-reg mapping");
619 LLT Ty =
MRI.getType(Reg);
623 "We must have a mapping for reg operands");
630 "Value mapping is invalid");
635#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
643 OS <<
"ID: " << getID() <<
" Cost: " << getCost() <<
" Mapping: ";
645 for (
unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
646 const ValueMapping &ValMapping = getOperandMapping(OpIdx);
649 OS <<
"{ Idx: " << OpIdx <<
" Map: " << ValMapping <<
'}';
653const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
658 :
MRI(
MRI),
MI(
MI), InstrMapping(InstrMapping) {
660 OpToNewVRegIdx.
resize(NumOpds, OperandsMapper::DontKnowIdx);
665RegisterBankInfo::OperandsMapper::getVRegsMem(
unsigned OpIdx) {
667 unsigned NumPartialVal =
669 int StartIdx = OpToNewVRegIdx[OpIdx];
671 if (StartIdx == OperandsMapper::DontKnowIdx) {
675 StartIdx = NewVRegs.size();
676 OpToNewVRegIdx[OpIdx] = StartIdx;
677 for (
unsigned i = 0; i < NumPartialVal; ++i)
678 NewVRegs.push_back(0);
681 getNewVRegsEnd(StartIdx, NumPartialVal);
687RegisterBankInfo::OperandsMapper::getNewVRegsEnd(
unsigned StartIdx,
688 unsigned NumVal)
const {
689 return const_cast<OperandsMapper *
>(
this)->getNewVRegsEnd(StartIdx, NumVal);
692RegisterBankInfo::OperandsMapper::getNewVRegsEnd(
unsigned StartIdx,
694 assert((NewVRegs.size() == StartIdx + NumVal ||
695 NewVRegs.size() > StartIdx + NumVal) &&
696 "NewVRegs too small to contain all the partial mapping");
697 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
698 : &NewVRegs[StartIdx + NumVal];
707 for (
Register &NewVReg : NewVRegsForOpIdx) {
708 assert(PartMap != ValMapping.
end() &&
"Out-of-bound access");
709 assert(NewVReg == 0 &&
"Register has already been created");
722 unsigned PartialMapIdx,
727 "Out-of-bound access for partial mapping");
729 (void)getVRegsMem(OpIdx);
730 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
731 "This value is already set");
732 NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
737 bool ForDebug)
const {
740 int StartIdx = OpToNewVRegIdx[OpIdx];
742 if (StartIdx == OperandsMapper::DontKnowIdx)
743 return make_range(NewVRegs.end(), NewVRegs.end());
745 unsigned PartMapSize =
748 getNewVRegsEnd(StartIdx, PartMapSize);
753 assert((VReg || ForDebug) &&
"Some registers are uninitialized");
758#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
766 bool ForDebug)
const {
771 OS <<
"Populated indices (CellNumber, IndexInNewVRegs): ";
773 for (
unsigned Idx = 0;
Idx != NumOpds; ++
Idx) {
774 if (OpToNewVRegIdx[
Idx] != DontKnowIdx) {
777 OS <<
'(' <<
Idx <<
", " << OpToNewVRegIdx[
Idx] <<
')';
785 OS <<
"Operand Mapping: ";
789 getMI().getParent() && getMI().getMF()
790 ? getMI().getMF()->getSubtarget().getRegisterInfo()
793 for (
unsigned Idx = 0;
Idx != NumOpds; ++
Idx) {
794 if (OpToNewVRegIdx[
Idx] == DontKnowIdx)
800 bool IsFirstNewVReg =
true;
804 IsFirstNewVReg =
false;
unsigned const MachineRegisterInfo * MRI
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
#define LLVM_LIKELY(EXPR)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)
Hashing function for PartialMapping.
static bool isCopyLike(const MachineInstr &MI)
Check whether or not MI should be treated like a copy for the mappings.
static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)
static hash_code hashInstructionMapping(unsigned ID, unsigned Cost, const RegisterBankInfo::ValueMapping *OperandsMapping, unsigned NumOperands)
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Class for arbitrary precision integers.
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getNumOperands() const
Get the number of operands.
unsigned getID() const
Get the ID.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
void dump() const
Print this on dbgs() stream.
void print(raw_ostream &OS) const
Print this on OS;.
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
MachineInstr & getMI() const
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
void dump() const
Print this operands mapper on dbgs() stream.
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Holds all the information related to register banks.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
RegisterBankInfo()
This constructor is meaningless.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const TargetRegisterClass * getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
unsigned getNumRegBanks() const
Get the total number of register banks.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints,...
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
RegisterBank ** RegBanks
Hold the set of supported register banks.
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
typename SuperClass::const_iterator const_iterator
typename SuperClass::iterator iterator
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
An opaque object representing a hash code.
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
hash_code hash_value(const FixedPointSemantics &Val)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Helper struct that represents how a value is partially mapped into a register.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
unsigned getHighBitIdx() const
void dump() const
Print this partial mapping on dbgs() stream.
bool verify() const
Check that the Mask is compatible with the RegBank.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned Length
Length of this mapping in bits.
Helper struct that represents how a value is mapped through different register banks.
const PartialMapping * begin() const
Iterators through the PartialMappings.
const PartialMapping * end() const
void print(raw_ostream &OS) const
Print this on OS;.
bool partsAllUniform() const
unsigned NumBreakDowns
Number of partial mapping to break down this value.
void dump() const
Print this on dbgs() stream.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.