LLVM 19.0.0git
AArch64RegisterBankInfo.cpp
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1//===- AArch64RegisterBankInfo.cpp ----------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the RegisterBankInfo class for
10/// AArch64.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
15#include "AArch64RegisterInfo.h"
17#include "llvm/ADT/STLExtras.h"
31#include "llvm/IR/IntrinsicsAArch64.h"
34#include <algorithm>
35#include <cassert>
36
37#define GET_TARGET_REGBANK_IMPL
38#include "AArch64GenRegisterBank.inc"
39
40// This file will be TableGen'ed at some point.
41#include "AArch64GenRegisterBankInfo.def"
42
43using namespace llvm;
44
46 const TargetRegisterInfo &TRI) {
47 static llvm::once_flag InitializeRegisterBankFlag;
48
49 static auto InitializeRegisterBankOnce = [&]() {
50 // We have only one set of register banks, whatever the subtarget
51 // is. Therefore, the initialization of the RegBanks table should be
52 // done only once. Indeed the table of all register banks
53 // (AArch64::RegBanks) is unique in the compiler. At some point, it
54 // will get tablegen'ed and the whole constructor becomes empty.
55
56 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
57 (void)RBGPR;
58 assert(&AArch64::GPRRegBank == &RBGPR &&
59 "The order in RegBanks is messed up");
60
61 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
62 (void)RBFPR;
63 assert(&AArch64::FPRRegBank == &RBFPR &&
64 "The order in RegBanks is messed up");
65
66 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
67 (void)RBCCR;
68 assert(&AArch64::CCRegBank == &RBCCR &&
69 "The order in RegBanks is messed up");
70
71 // The GPR register bank is fully defined by all the registers in
72 // GR64all + its subclasses.
73 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
74 "Subclass not added?");
75 assert(getMaximumSize(RBGPR.getID()) == 128 &&
76 "GPRs should hold up to 128-bit");
77
78 // The FPR register bank is fully defined by all the registers in
79 // GR64all + its subclasses.
80 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
81 "Subclass not added?");
82 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
83 "Subclass not added?");
84 assert(getMaximumSize(RBFPR.getID()) == 512 &&
85 "FPRs should hold up to 512-bit via QQQQ sequence");
86
87 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
88 "Class not added?");
89 assert(getMaximumSize(RBCCR.getID()) == 32 &&
90 "CCR should hold up to 32-bit");
91
92 // Check that the TableGen'ed like file is in sync we our expectations.
93 // First, the Idx.
96 "PartialMappingIdx's are incorrectly ordered");
100 "PartialMappingIdx's are incorrectly ordered");
101// Now, the content.
102// Check partial mapping.
103#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
104 do { \
105 assert( \
106 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
107 #Idx " is incorrectly initialized"); \
108 } while (false)
109
110 CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
111 CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
112 CHECK_PARTIALMAP(PMI_GPR128, 0, 128, RBGPR);
113 CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
114 CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
115 CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
116 CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
117 CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
118 CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
119
120// Check value mapping.
121#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
122 do { \
123 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
124 PartialMappingIdx::PMI_First##RBName, Size, \
125 Offset) && \
126 #RBName #Size " " #Offset " is incorrectly initialized"); \
127 } while (false)
128
129#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
130
131 CHECK_VALUEMAP(GPR, 32);
132 CHECK_VALUEMAP(GPR, 64);
133 CHECK_VALUEMAP(GPR, 128);
134 CHECK_VALUEMAP(FPR, 16);
135 CHECK_VALUEMAP(FPR, 32);
136 CHECK_VALUEMAP(FPR, 64);
137 CHECK_VALUEMAP(FPR, 128);
138 CHECK_VALUEMAP(FPR, 256);
139 CHECK_VALUEMAP(FPR, 512);
140
141// Check the value mapping for 3-operands instructions where all the operands
142// map to the same value mapping.
143#define CHECK_VALUEMAP_3OPS(RBName, Size) \
144 do { \
145 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
146 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
147 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
148 } while (false)
149
150 CHECK_VALUEMAP_3OPS(GPR, 32);
151 CHECK_VALUEMAP_3OPS(GPR, 64);
152 CHECK_VALUEMAP_3OPS(GPR, 128);
158
159#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
160 do { \
161 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
162 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
163 (void)PartialMapDstIdx; \
164 (void)PartialMapSrcIdx; \
165 const ValueMapping *Map = getCopyMapping( \
166 AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
167 (void)Map; \
168 assert(Map[0].BreakDown == \
169 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
170 Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
171 " Dst is incorrectly initialized"); \
172 assert(Map[1].BreakDown == \
173 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
174 Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
175 " Src is incorrectly initialized"); \
176 \
177 } while (false)
178
179 CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
181 CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
187
188#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
189 do { \
190 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
191 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
192 (void)PartialMapDstIdx; \
193 (void)PartialMapSrcIdx; \
194 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
195 (void)Map; \
196 assert(Map[0].BreakDown == \
197 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
198 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
199 " Dst is incorrectly initialized"); \
200 assert(Map[1].BreakDown == \
201 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
202 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
203 " Src is incorrectly initialized"); \
204 \
205 } while (false)
206
207 CHECK_VALUEMAP_FPEXT(32, 16);
208 CHECK_VALUEMAP_FPEXT(64, 16);
209 CHECK_VALUEMAP_FPEXT(64, 32);
210 CHECK_VALUEMAP_FPEXT(128, 64);
211
212 assert(verify(TRI) && "Invalid register bank information");
213 };
214
215 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
216}
217
219 const RegisterBank &B,
220 TypeSize Size) const {
221 // What do we do with different size?
222 // copy are same size.
223 // Will introduce other hooks for different size:
224 // * extract cost.
225 // * build_sequence cost.
226
227 // Copy from (resp. to) GPR to (resp. from) FPR involves FMOV.
228 // FIXME: This should be deduced from the scheduling model.
229 if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)
230 // FMOVXDr or FMOVWSr.
231 return 5;
232 if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)
233 // FMOVDXr or FMOVSWr.
234 return 4;
235
237}
238
239const RegisterBank &
241 LLT) const {
242 switch (RC.getID()) {
243 case AArch64::FPR8RegClassID:
244 case AArch64::FPR16RegClassID:
245 case AArch64::FPR16_loRegClassID:
246 case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
247 case AArch64::FPR32RegClassID:
248 case AArch64::FPR64RegClassID:
249 case AArch64::FPR128RegClassID:
250 case AArch64::FPR64_loRegClassID:
251 case AArch64::FPR128_loRegClassID:
252 case AArch64::FPR128_0to7RegClassID:
253 case AArch64::DDRegClassID:
254 case AArch64::DDDRegClassID:
255 case AArch64::DDDDRegClassID:
256 case AArch64::QQRegClassID:
257 case AArch64::QQQRegClassID:
258 case AArch64::QQQQRegClassID:
259 return getRegBank(AArch64::FPRRegBankID);
260 case AArch64::GPR32commonRegClassID:
261 case AArch64::GPR32RegClassID:
262 case AArch64::GPR32spRegClassID:
263 case AArch64::GPR32sponlyRegClassID:
264 case AArch64::GPR32argRegClassID:
265 case AArch64::GPR32allRegClassID:
266 case AArch64::GPR64commonRegClassID:
267 case AArch64::GPR64RegClassID:
268 case AArch64::GPR64spRegClassID:
269 case AArch64::GPR64sponlyRegClassID:
270 case AArch64::GPR64argRegClassID:
271 case AArch64::GPR64allRegClassID:
272 case AArch64::GPR64noipRegClassID:
273 case AArch64::GPR64common_and_GPR64noipRegClassID:
274 case AArch64::GPR64noip_and_tcGPR64RegClassID:
275 case AArch64::tcGPR64RegClassID:
276 case AArch64::tcGPRx16x17RegClassID:
277 case AArch64::tcGPRx17RegClassID:
278 case AArch64::tcGPRnotx16RegClassID:
279 case AArch64::WSeqPairsClassRegClassID:
280 case AArch64::XSeqPairsClassRegClassID:
281 case AArch64::MatrixIndexGPR32_8_11RegClassID:
282 case AArch64::MatrixIndexGPR32_12_15RegClassID:
283 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID:
284 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
285 return getRegBank(AArch64::GPRRegBankID);
286 case AArch64::CCRRegClassID:
287 return getRegBank(AArch64::CCRegBankID);
288 default:
289 llvm_unreachable("Register class not supported");
290 }
291}
292
295 const MachineInstr &MI) const {
296 const MachineFunction &MF = *MI.getParent()->getParent();
297 const TargetSubtargetInfo &STI = MF.getSubtarget();
298 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
299 const MachineRegisterInfo &MRI = MF.getRegInfo();
300
301 switch (MI.getOpcode()) {
302 case TargetOpcode::G_OR: {
303 // 32 and 64-bit or can be mapped on either FPR or
304 // GPR for the same cost.
305 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
306 if (Size != 32 && Size != 64)
307 break;
308
309 // If the instruction has any implicit-defs or uses,
310 // do not mess with it.
311 if (MI.getNumOperands() != 3)
312 break;
313 InstructionMappings AltMappings;
314 const InstructionMapping &GPRMapping = getInstructionMapping(
315 /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size),
316 /*NumOperands*/ 3);
317 const InstructionMapping &FPRMapping = getInstructionMapping(
318 /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size),
319 /*NumOperands*/ 3);
320
321 AltMappings.push_back(&GPRMapping);
322 AltMappings.push_back(&FPRMapping);
323 return AltMappings;
324 }
325 case TargetOpcode::G_BITCAST: {
326 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
327 if (Size != 32 && Size != 64)
328 break;
329
330 // If the instruction has any implicit-defs or uses,
331 // do not mess with it.
332 if (MI.getNumOperands() != 2)
333 break;
334
335 InstructionMappings AltMappings;
336 const InstructionMapping &GPRMapping = getInstructionMapping(
337 /*ID*/ 1, /*Cost*/ 1,
338 getCopyMapping(AArch64::GPRRegBankID, AArch64::GPRRegBankID, Size),
339 /*NumOperands*/ 2);
340 const InstructionMapping &FPRMapping = getInstructionMapping(
341 /*ID*/ 2, /*Cost*/ 1,
342 getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size),
343 /*NumOperands*/ 2);
344 const InstructionMapping &GPRToFPRMapping = getInstructionMapping(
345 /*ID*/ 3,
346 /*Cost*/
347 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
349 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size),
350 /*NumOperands*/ 2);
351 const InstructionMapping &FPRToGPRMapping = getInstructionMapping(
352 /*ID*/ 3,
353 /*Cost*/
354 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
356 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size),
357 /*NumOperands*/ 2);
358
359 AltMappings.push_back(&GPRMapping);
360 AltMappings.push_back(&FPRMapping);
361 AltMappings.push_back(&GPRToFPRMapping);
362 AltMappings.push_back(&FPRToGPRMapping);
363 return AltMappings;
364 }
365 case TargetOpcode::G_LOAD: {
366 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
367 if (Size != 64)
368 break;
369
370 // If the instruction has any implicit-defs or uses,
371 // do not mess with it.
372 if (MI.getNumOperands() != 2)
373 break;
374
375 InstructionMappings AltMappings;
376 const InstructionMapping &GPRMapping = getInstructionMapping(
377 /*ID*/ 1, /*Cost*/ 1,
379 // Addresses are GPR 64-bit.
381 /*NumOperands*/ 2);
382 const InstructionMapping &FPRMapping = getInstructionMapping(
383 /*ID*/ 2, /*Cost*/ 1,
385 // Addresses are GPR 64-bit.
387 /*NumOperands*/ 2);
388
389 AltMappings.push_back(&GPRMapping);
390 AltMappings.push_back(&FPRMapping);
391 return AltMappings;
392 }
393 default:
394 break;
395 }
397}
398
399void AArch64RegisterBankInfo::applyMappingImpl(
400 MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const {
401 switch (OpdMapper.getMI().getOpcode()) {
402 case TargetOpcode::G_OR:
403 case TargetOpcode::G_BITCAST:
404 case TargetOpcode::G_LOAD:
405 // Those ID must match getInstrAlternativeMappings.
406 assert((OpdMapper.getInstrMapping().getID() >= 1 &&
407 OpdMapper.getInstrMapping().getID() <= 4) &&
408 "Don't know how to handle that ID");
409 return applyDefaultMapping(OpdMapper);
410 default:
411 llvm_unreachable("Don't know how to handle that operation");
412 }
413}
414
415/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
416/// having only floating-point operands.
417static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
418 switch (Opc) {
419 case TargetOpcode::G_FADD:
420 case TargetOpcode::G_FSUB:
421 case TargetOpcode::G_FMUL:
422 case TargetOpcode::G_FMA:
423 case TargetOpcode::G_FDIV:
424 case TargetOpcode::G_FCONSTANT:
425 case TargetOpcode::G_FPEXT:
426 case TargetOpcode::G_FPTRUNC:
427 case TargetOpcode::G_FCEIL:
428 case TargetOpcode::G_FFLOOR:
429 case TargetOpcode::G_FNEARBYINT:
430 case TargetOpcode::G_FNEG:
431 case TargetOpcode::G_FCOS:
432 case TargetOpcode::G_FSIN:
433 case TargetOpcode::G_FLOG10:
434 case TargetOpcode::G_FLOG:
435 case TargetOpcode::G_FLOG2:
436 case TargetOpcode::G_FSQRT:
437 case TargetOpcode::G_FABS:
438 case TargetOpcode::G_FEXP:
439 case TargetOpcode::G_FRINT:
440 case TargetOpcode::G_INTRINSIC_TRUNC:
441 case TargetOpcode::G_INTRINSIC_ROUND:
442 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
443 case TargetOpcode::G_FMAXNUM:
444 case TargetOpcode::G_FMINNUM:
445 case TargetOpcode::G_FMAXIMUM:
446 case TargetOpcode::G_FMINIMUM:
447 return true;
448 }
449 return false;
450}
451
453AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
454 const MachineInstr &MI) const {
455 const unsigned Opc = MI.getOpcode();
456 const MachineFunction &MF = *MI.getParent()->getParent();
457 const MachineRegisterInfo &MRI = MF.getRegInfo();
458
459 unsigned NumOperands = MI.getNumOperands();
460 assert(NumOperands <= 3 &&
461 "This code is for instructions with 3 or less operands");
462
463 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
464 unsigned Size = Ty.getSizeInBits();
465 bool IsFPR = Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
466
468
469#ifndef NDEBUG
470 // Make sure all the operands are using similar size and type.
471 // Should probably be checked by the machine verifier.
472 // This code won't catch cases where the number of lanes is
473 // different between the operands.
474 // If we want to go to that level of details, it is probably
475 // best to check that the types are the same, period.
476 // Currently, we just check that the register banks are the same
477 // for each types.
478 for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {
479 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
480 assert(
482 RBIdx, OpTy.getSizeInBits()) ==
484 "Operand has incompatible size");
485 bool OpIsFPR = OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
486 (void)OpIsFPR;
487 assert(IsFPR == OpIsFPR && "Operand has incompatible type");
488 }
489#endif // End NDEBUG.
490
492 getValueMapping(RBIdx, Size), NumOperands);
493}
494
495/// \returns true if a given intrinsic only uses and defines FPRs.
497 const MachineInstr &MI) {
498 // TODO: Add more intrinsics.
499 switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
500 default:
501 return false;
502 case Intrinsic::aarch64_neon_uaddlv:
503 case Intrinsic::aarch64_neon_uaddv:
504 case Intrinsic::aarch64_neon_saddv:
505 case Intrinsic::aarch64_neon_umaxv:
506 case Intrinsic::aarch64_neon_smaxv:
507 case Intrinsic::aarch64_neon_uminv:
508 case Intrinsic::aarch64_neon_sminv:
509 case Intrinsic::aarch64_neon_faddv:
510 case Intrinsic::aarch64_neon_fmaxv:
511 case Intrinsic::aarch64_neon_fminv:
512 case Intrinsic::aarch64_neon_fmaxnmv:
513 case Intrinsic::aarch64_neon_fminnmv:
514 return true;
515 case Intrinsic::aarch64_neon_saddlv: {
516 const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
517 return SrcTy.getElementType().getSizeInBits() >= 16 &&
518 SrcTy.getElementCount().getFixedValue() >= 4;
519 }
520 }
521}
522
523bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,
525 const TargetRegisterInfo &TRI,
526 unsigned Depth) const {
527 unsigned Op = MI.getOpcode();
528 if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(MRI, MI))
529 return true;
530
531 // Do we have an explicit floating point instruction?
533 return true;
534
535 // No. Check if we have a copy-like instruction. If we do, then we could
536 // still be fed by floating point instructions.
537 if (Op != TargetOpcode::COPY && !MI.isPHI() &&
539 return false;
540
541 // Check if we already know the register bank.
542 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI);
543 if (RB == &AArch64::FPRRegBank)
544 return true;
545 if (RB == &AArch64::GPRRegBank)
546 return false;
547
548 // We don't know anything.
549 //
550 // If we have a phi, we may be able to infer that it will be assigned a FPR
551 // based off of its inputs.
552 if (!MI.isPHI() || Depth > MaxFPRSearchDepth)
553 return false;
554
555 return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {
556 return Op.isReg() &&
557 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
558 });
559}
560
561bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
563 const TargetRegisterInfo &TRI,
564 unsigned Depth) const {
565 switch (MI.getOpcode()) {
566 case TargetOpcode::G_FPTOSI:
567 case TargetOpcode::G_FPTOUI:
568 case TargetOpcode::G_FCMP:
569 case TargetOpcode::G_LROUND:
570 case TargetOpcode::G_LLROUND:
571 return true;
572 default:
573 break;
574 }
575 return hasFPConstraints(MI, MRI, TRI, Depth);
576}
577
578bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
580 const TargetRegisterInfo &TRI,
581 unsigned Depth) const {
582 switch (MI.getOpcode()) {
583 case AArch64::G_DUP:
584 case TargetOpcode::G_SITOFP:
585 case TargetOpcode::G_UITOFP:
586 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
587 case TargetOpcode::G_INSERT_VECTOR_ELT:
588 case TargetOpcode::G_BUILD_VECTOR:
589 case TargetOpcode::G_BUILD_VECTOR_TRUNC:
590 return true;
591 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
592 switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
593 case Intrinsic::aarch64_neon_ld1x2:
594 case Intrinsic::aarch64_neon_ld1x3:
595 case Intrinsic::aarch64_neon_ld1x4:
596 case Intrinsic::aarch64_neon_ld2:
597 case Intrinsic::aarch64_neon_ld2lane:
598 case Intrinsic::aarch64_neon_ld2r:
599 case Intrinsic::aarch64_neon_ld3:
600 case Intrinsic::aarch64_neon_ld3lane:
601 case Intrinsic::aarch64_neon_ld3r:
602 case Intrinsic::aarch64_neon_ld4:
603 case Intrinsic::aarch64_neon_ld4lane:
604 case Intrinsic::aarch64_neon_ld4r:
605 return true;
606 default:
607 break;
608 }
609 break;
610 default:
611 break;
612 }
613 return hasFPConstraints(MI, MRI, TRI, Depth);
614}
615
616bool AArch64RegisterBankInfo::isLoadFromFPType(const MachineInstr &MI) const {
617 // GMemOperation because we also want to match indexed loads.
618 auto *MemOp = cast<GMemOperation>(&MI);
619 const Value *LdVal = MemOp->getMMO().getValue();
620 if (!LdVal)
621 return false;
622
623 Type *EltTy = nullptr;
624 if (const GlobalValue *GV = dyn_cast<GlobalValue>(LdVal)) {
625 EltTy = GV->getValueType();
626 // Look at the first element of the struct to determine the type we are
627 // loading
628 while (StructType *StructEltTy = dyn_cast<StructType>(EltTy))
629 EltTy = StructEltTy->getTypeAtIndex(0U);
630 // Look at the first element of the array to determine its type
631 if (isa<ArrayType>(EltTy))
632 EltTy = EltTy->getArrayElementType();
633 } else {
634 // FIXME: grubbing around uses is pretty ugly, but with no more
635 // `getPointerElementType` there's not much else we can do.
636 for (const auto *LdUser : LdVal->users()) {
637 if (isa<LoadInst>(LdUser)) {
638 EltTy = LdUser->getType();
639 break;
640 }
641 if (isa<StoreInst>(LdUser) && LdUser->getOperand(1) == LdVal) {
642 EltTy = LdUser->getOperand(0)->getType();
643 break;
644 }
645 }
646 }
647 return EltTy && EltTy->isFPOrFPVectorTy();
648}
649
652 const unsigned Opc = MI.getOpcode();
653
654 // Try the default logic for non-generic instructions that are either copies
655 // or already have some operands assigned to banks.
656 if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
657 Opc == TargetOpcode::G_PHI) {
660 if (Mapping.isValid())
661 return Mapping;
662 }
663
664 const MachineFunction &MF = *MI.getParent()->getParent();
665 const MachineRegisterInfo &MRI = MF.getRegInfo();
666 const TargetSubtargetInfo &STI = MF.getSubtarget();
667 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
668
669 switch (Opc) {
670 // G_{F|S|U}REM are not listed because they are not legal.
671 // Arithmetic ops.
672 case TargetOpcode::G_ADD:
673 case TargetOpcode::G_SUB:
674 case TargetOpcode::G_PTR_ADD:
675 case TargetOpcode::G_MUL:
676 case TargetOpcode::G_SDIV:
677 case TargetOpcode::G_UDIV:
678 // Bitwise ops.
679 case TargetOpcode::G_AND:
680 case TargetOpcode::G_OR:
681 case TargetOpcode::G_XOR:
682 // Floating point ops.
683 case TargetOpcode::G_FADD:
684 case TargetOpcode::G_FSUB:
685 case TargetOpcode::G_FMUL:
686 case TargetOpcode::G_FDIV:
687 case TargetOpcode::G_FMAXIMUM:
688 case TargetOpcode::G_FMINIMUM:
689 return getSameKindOfOperandsMapping(MI);
690 case TargetOpcode::G_FPEXT: {
691 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
692 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
694 DefaultMappingID, /*Cost*/ 1,
696 /*NumOperands*/ 2);
697 }
698 // Shifts.
699 case TargetOpcode::G_SHL:
700 case TargetOpcode::G_LSHR:
701 case TargetOpcode::G_ASHR: {
702 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());
703 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
704 if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32)
707 return getSameKindOfOperandsMapping(MI);
708 }
709 case TargetOpcode::COPY: {
710 Register DstReg = MI.getOperand(0).getReg();
711 Register SrcReg = MI.getOperand(1).getReg();
712 // Check if one of the register is not a generic register.
713 if ((DstReg.isPhysical() || !MRI.getType(DstReg).isValid()) ||
714 (SrcReg.isPhysical() || !MRI.getType(SrcReg).isValid())) {
715 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
716 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
717 if (!DstRB)
718 DstRB = SrcRB;
719 else if (!SrcRB)
720 SrcRB = DstRB;
721 // If both RB are null that means both registers are generic.
722 // We shouldn't be here.
723 assert(DstRB && SrcRB && "Both RegBank were nullptr");
724 unsigned Size = getSizeInBits(DstReg, MRI, TRI);
727 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
728 // We only care about the mapping of the destination.
729 /*NumOperands*/ 1);
730 }
731 // Both registers are generic, use G_BITCAST.
732 [[fallthrough]];
733 }
734 case TargetOpcode::G_BITCAST: {
735 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
736 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
737 unsigned Size = DstTy.getSizeInBits();
738 bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
739 bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
740 const RegisterBank &DstRB =
741 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
742 const RegisterBank &SrcRB =
743 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
746 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
747 // We only care about the mapping of the destination for COPY.
748 /*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
749 }
750 default:
751 break;
752 }
753
754 unsigned NumOperands = MI.getNumOperands();
755
756 // Track the size and bank of each register. We don't do partial mappings.
757 SmallVector<unsigned, 4> OpSize(NumOperands);
758 SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
759 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
760 auto &MO = MI.getOperand(Idx);
761 if (!MO.isReg() || !MO.getReg())
762 continue;
763
764 LLT Ty = MRI.getType(MO.getReg());
765 if (!Ty.isValid())
766 continue;
767 OpSize[Idx] = Ty.getSizeInBits();
768
769 // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
770 // For floating-point instructions, scalars go in FPRs.
772 Ty.getSizeInBits() > 64)
773 OpRegBankIdx[Idx] = PMI_FirstFPR;
774 else
775 OpRegBankIdx[Idx] = PMI_FirstGPR;
776 }
777
778 unsigned Cost = 1;
779 // Some of the floating-point instructions have mixed GPR and FPR operands:
780 // fine-tune the computed mapping.
781 switch (Opc) {
782 case AArch64::G_DUP: {
783 Register ScalarReg = MI.getOperand(1).getReg();
784 LLT ScalarTy = MRI.getType(ScalarReg);
785 auto ScalarDef = MRI.getVRegDef(ScalarReg);
786 // We want to select dup(load) into LD1R.
787 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)
788 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
789 // s8 is an exception for G_DUP, which we always want on gpr.
790 else if (ScalarTy.getSizeInBits() != 8 &&
791 (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
792 onlyDefinesFP(*ScalarDef, MRI, TRI)))
793 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
794 else
795 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
796 break;
797 }
798 case TargetOpcode::G_TRUNC: {
799 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
800 if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128)
801 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
802 break;
803 }
804 case TargetOpcode::G_SITOFP:
805 case TargetOpcode::G_UITOFP: {
806 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
807 break;
808 // Integer to FP conversions don't necessarily happen between GPR -> FPR
809 // regbanks. They can also be done within an FPR register.
810 Register SrcReg = MI.getOperand(1).getReg();
811 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank)
812 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
813 else
814 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
815 break;
816 }
817 case TargetOpcode::G_FPTOSI:
818 case TargetOpcode::G_FPTOUI:
819 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
820 break;
821 OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
822 break;
823 case TargetOpcode::G_FCMP: {
824 // If the result is a vector, it must use a FPR.
826 MRI.getType(MI.getOperand(0).getReg()).isVector() ? PMI_FirstFPR
827 : PMI_FirstGPR;
828 OpRegBankIdx = {Idx0,
829 /* Predicate */ PMI_None, PMI_FirstFPR, PMI_FirstFPR};
830 break;
831 }
832 case TargetOpcode::G_BITCAST:
833 // This is going to be a cross register bank copy and this is expensive.
834 if (OpRegBankIdx[0] != OpRegBankIdx[1])
835 Cost = copyCost(
836 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank,
837 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank,
838 TypeSize::getFixed(OpSize[0]));
839 break;
840 case TargetOpcode::G_LOAD: {
841 // Loading in vector unit is slightly more expensive.
842 // This is actually only true for the LD1R and co instructions,
843 // but anyway for the fast mode this number does not matter and
844 // for the greedy mode the cost of the cross bank copy will
845 // offset this number.
846 // FIXME: Should be derived from the scheduling model.
847 if (OpRegBankIdx[0] != PMI_FirstGPR) {
848 Cost = 2;
849 break;
850 }
851
852 if (cast<GLoad>(MI).isAtomic()) {
853 // Atomics always use GPR destinations. Don't refine any further.
854 OpRegBankIdx[0] = PMI_FirstGPR;
855 break;
856 }
857
858 // Try to guess the type of the load from the MMO.
859 if (isLoadFromFPType(MI)) {
860 OpRegBankIdx[0] = PMI_FirstFPR;
861 break;
862 }
863
864 // Check if that load feeds fp instructions.
865 // In that case, we want the default mapping to be on FPR
866 // instead of blind map every scalar to GPR.
867 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
868 [&](const MachineInstr &UseMI) {
869 // If we have at least one direct use in a FP instruction,
870 // assume this was a floating point load in the IR. If it was
871 // not, we would have had a bitcast before reaching that
872 // instruction.
873 //
874 // Int->FP conversion operations are also captured in
875 // onlyDefinesFP().
876 return onlyUsesFP(UseMI, MRI, TRI) ||
877 onlyDefinesFP(UseMI, MRI, TRI);
878 }))
879 OpRegBankIdx[0] = PMI_FirstFPR;
880 break;
881 }
882 case TargetOpcode::G_STORE:
883 // Check if that store is fed by fp instructions.
884 if (OpRegBankIdx[0] == PMI_FirstGPR) {
885 Register VReg = MI.getOperand(0).getReg();
886 if (!VReg)
887 break;
888 MachineInstr *DefMI = MRI.getVRegDef(VReg);
889 if (onlyDefinesFP(*DefMI, MRI, TRI))
890 OpRegBankIdx[0] = PMI_FirstFPR;
891 break;
892 }
893 break;
894 case TargetOpcode::G_INDEXED_STORE:
895 if (OpRegBankIdx[1] == PMI_FirstGPR) {
896 Register VReg = MI.getOperand(1).getReg();
897 if (!VReg)
898 break;
899 MachineInstr *DefMI = MRI.getVRegDef(VReg);
900 if (onlyDefinesFP(*DefMI, MRI, TRI))
901 OpRegBankIdx[1] = PMI_FirstFPR;
902 break;
903 }
904 break;
905 case TargetOpcode::G_INDEXED_SEXTLOAD:
906 case TargetOpcode::G_INDEXED_ZEXTLOAD:
907 // These should always be GPR.
908 OpRegBankIdx[0] = PMI_FirstGPR;
909 break;
910 case TargetOpcode::G_INDEXED_LOAD: {
911 if (isLoadFromFPType(MI))
912 OpRegBankIdx[0] = PMI_FirstFPR;
913 break;
914 }
915 case TargetOpcode::G_SELECT: {
916 // If the destination is FPR, preserve that.
917 if (OpRegBankIdx[0] != PMI_FirstGPR)
918 break;
919
920 // If we're taking in vectors, we have no choice but to put everything on
921 // FPRs, except for the condition. The condition must always be on a GPR.
922 LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
923 if (SrcTy.isVector()) {
925 break;
926 }
927
928 // Try to minimize the number of copies. If we have more floating point
929 // constrained values than not, then we'll put everything on FPR. Otherwise,
930 // everything has to be on GPR.
931 unsigned NumFP = 0;
932
933 // Check if the uses of the result always produce floating point values.
934 //
935 // For example:
936 //
937 // %z = G_SELECT %cond %x %y
938 // fpr = G_FOO %z ...
939 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
940 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))
941 ++NumFP;
942
943 // Check if the defs of the source values always produce floating point
944 // values.
945 //
946 // For example:
947 //
948 // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
949 // %z = G_SELECT %cond %x %y
950 //
951 // Also check whether or not the sources have already been decided to be
952 // FPR. Keep track of this.
953 //
954 // This doesn't check the condition, since it's just whatever is in NZCV.
955 // This isn't passed explicitly in a register to fcsel/csel.
956 for (unsigned Idx = 2; Idx < 4; ++Idx) {
957 Register VReg = MI.getOperand(Idx).getReg();
958 MachineInstr *DefMI = MRI.getVRegDef(VReg);
959 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank ||
960 onlyDefinesFP(*DefMI, MRI, TRI))
961 ++NumFP;
962 }
963
964 // If we have more FP constraints than not, then move everything over to
965 // FPR.
966 if (NumFP >= 2)
968
969 break;
970 }
971 case TargetOpcode::G_UNMERGE_VALUES: {
972 // If the first operand belongs to a FPR register bank, then make sure that
973 // we preserve that.
974 if (OpRegBankIdx[0] != PMI_FirstGPR)
975 break;
976
977 LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
978 // UNMERGE into scalars from a vector should always use FPR.
979 // Likewise if any of the uses are FP instructions.
980 if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
981 any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
982 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
983 // Set the register bank of every operand to FPR.
984 for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
985 Idx < NumOperands; ++Idx)
986 OpRegBankIdx[Idx] = PMI_FirstFPR;
987 }
988 break;
989 }
990 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
991 // Destination and source need to be FPRs.
992 OpRegBankIdx[0] = PMI_FirstFPR;
993 OpRegBankIdx[1] = PMI_FirstFPR;
994
995 // Index needs to be a GPR.
996 OpRegBankIdx[2] = PMI_FirstGPR;
997 break;
998 case TargetOpcode::G_INSERT_VECTOR_ELT:
999 OpRegBankIdx[0] = PMI_FirstFPR;
1000 OpRegBankIdx[1] = PMI_FirstFPR;
1001
1002 // The element may be either a GPR or FPR. Preserve that behaviour.
1003 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
1004 OpRegBankIdx[2] = PMI_FirstFPR;
1005 else
1006 OpRegBankIdx[2] = PMI_FirstGPR;
1007
1008 // Index needs to be a GPR.
1009 OpRegBankIdx[3] = PMI_FirstGPR;
1010 break;
1011 case TargetOpcode::G_EXTRACT: {
1012 // For s128 sources we have to use fpr unless we know otherwise.
1013 auto Src = MI.getOperand(1).getReg();
1014 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
1015 if (SrcTy.getSizeInBits() != 128)
1016 break;
1017 auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
1018 ? PMI_FirstGPR
1019 : PMI_FirstFPR;
1020 OpRegBankIdx[0] = Idx;
1021 OpRegBankIdx[1] = Idx;
1022 break;
1023 }
1024 case TargetOpcode::G_BUILD_VECTOR: {
1025 // If the first source operand belongs to a FPR register bank, then make
1026 // sure that we preserve that.
1027 if (OpRegBankIdx[1] != PMI_FirstGPR)
1028 break;
1029 Register VReg = MI.getOperand(1).getReg();
1030 if (!VReg)
1031 break;
1032
1033 // Get the instruction that defined the source operand reg, and check if
1034 // it's a floating point operation. Or, if it's a type like s16 which
1035 // doesn't have a exact size gpr register class. The exception is if the
1036 // build_vector has all constant operands, which may be better to leave as
1037 // gpr without copies, so it can be matched in imported patterns.
1038 MachineInstr *DefMI = MRI.getVRegDef(VReg);
1039 unsigned DefOpc = DefMI->getOpcode();
1040 const LLT SrcTy = MRI.getType(VReg);
1041 if (all_of(MI.operands(), [&](const MachineOperand &Op) {
1042 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
1043 TargetOpcode::G_CONSTANT;
1044 }))
1045 break;
1047 SrcTy.getSizeInBits() < 32 ||
1048 getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank) {
1049 // Have a floating point op.
1050 // Make sure every operand gets mapped to a FPR register class.
1051 unsigned NumOperands = MI.getNumOperands();
1052 for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
1053 OpRegBankIdx[Idx] = PMI_FirstFPR;
1054 }
1055 break;
1056 }
1057 case TargetOpcode::G_VECREDUCE_FADD:
1058 case TargetOpcode::G_VECREDUCE_FMUL:
1059 case TargetOpcode::G_VECREDUCE_FMAX:
1060 case TargetOpcode::G_VECREDUCE_FMIN:
1061 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1062 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1063 case TargetOpcode::G_VECREDUCE_ADD:
1064 case TargetOpcode::G_VECREDUCE_MUL:
1065 case TargetOpcode::G_VECREDUCE_AND:
1066 case TargetOpcode::G_VECREDUCE_OR:
1067 case TargetOpcode::G_VECREDUCE_XOR:
1068 case TargetOpcode::G_VECREDUCE_SMAX:
1069 case TargetOpcode::G_VECREDUCE_SMIN:
1070 case TargetOpcode::G_VECREDUCE_UMAX:
1071 case TargetOpcode::G_VECREDUCE_UMIN:
1072 // Reductions produce a scalar value from a vector, the scalar should be on
1073 // FPR bank.
1074 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
1075 break;
1076 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1077 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
1078 // These reductions also take a scalar accumulator input.
1079 // Assign them FPR for now.
1080 OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR, PMI_FirstFPR};
1081 break;
1082 case TargetOpcode::G_INTRINSIC:
1083 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1084 // Check if we know that the intrinsic has any constraints on its register
1085 // banks. If it does, then update the mapping accordingly.
1086 unsigned Idx = 0;
1087 if (onlyDefinesFP(MI, MRI, TRI))
1088 for (const auto &Op : MI.defs()) {
1089 if (Op.isReg())
1090 OpRegBankIdx[Idx] = PMI_FirstFPR;
1091 ++Idx;
1092 }
1093 else
1094 Idx += MI.getNumExplicitDefs();
1095
1096 if (onlyUsesFP(MI, MRI, TRI))
1097 for (const auto &Op : MI.explicit_uses()) {
1098 if (Op.isReg())
1099 OpRegBankIdx[Idx] = PMI_FirstFPR;
1100 ++Idx;
1101 }
1102 break;
1103 }
1104 case TargetOpcode::G_LROUND:
1105 case TargetOpcode::G_LLROUND: {
1106 // Source is always floating point and destination is always integer.
1107 OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
1108 break;
1109 }
1110 }
1111
1112 // Finally construct the computed mapping.
1113 SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
1114 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
1115 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
1116 LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());
1117 if (!Ty.isValid())
1118 continue;
1119 auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
1120 if (!Mapping->isValid())
1122
1123 OpdsMapping[Idx] = Mapping;
1124 }
1125 }
1126
1128 getOperandsMapping(OpdsMapping), NumOperands);
1129}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static unsigned getIntrinsicID(const SDNode *N)
#define CHECK_VALUEMAP(RBName, Size)
static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)
#define CHECK_VALUEMAP_3OPS(RBName, Size)
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
This file declares the targeting of the RegisterBankInfo class for AArch64.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
ppc ctr loops verify
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallVector class.
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
static const RegisterBankInfo::PartialMapping PartMappings[]
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
static const RegisterBankInfo::ValueMapping ValMappings[]
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
This class represents an Operation in the Expression.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr bool isValid() const
Definition: LowLevelType.h:137
constexpr bool isVector() const
Definition: LowLevelType.h:147
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:185
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:282
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:176
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Definition: RegisterBank.h:28
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:45
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Class to represent struct types.
Definition: DerivedTypes.h:216
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition: TypeSize.h:332
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Type * getArrayElementType() const
Definition: Type.h:404
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
Definition: Type.h:216
LLVM Value Representation.
Definition: Value.h:74
iterator_range< user_iterator > users()
Definition: Value.h:421
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1731
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
The llvm::once_flag structure.
Definition: Threading.h:68