31#include "llvm/IR/IntrinsicsAArch64.h"
36#define GET_TARGET_REGBANK_IMPL
37#include "AArch64GenRegisterBank.inc"
40#include "AArch64GenRegisterBankInfo.def"
48 static auto InitializeRegisterBankOnce = [&]() {
57 assert(&AArch64::GPRRegBank == &RBGPR &&
58 "The order in RegBanks is messed up");
62 assert(&AArch64::FPRRegBank == &RBFPR &&
63 "The order in RegBanks is messed up");
67 assert(&AArch64::CCRegBank == &RBCCR &&
68 "The order in RegBanks is messed up");
73 "Subclass not added?");
75 "GPRs should hold up to 128-bit");
80 "Subclass not added?");
82 "Subclass not added?");
84 "FPRs should hold up to 512-bit via QQQQ sequence");
89 "CCR should hold up to 32-bit");
95 "PartialMappingIdx's are incorrectly ordered");
99 "PartialMappingIdx's are incorrectly ordered");
102#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
105 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
106 #Idx " is incorrectly initialized"); \
120#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
122 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
123 PartialMappingIdx::PMI_First##RBName, Size, \
125 #RBName #Size " " #Offset " is incorrectly initialized"); \
128#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
142#define CHECK_VALUEMAP_3OPS(RBName, Size) \
144 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
145 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
146 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
158#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
160 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
161 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
162 (void)PartialMapDstIdx; \
163 (void)PartialMapSrcIdx; \
164 const ValueMapping *Map = getCopyMapping( \
165 AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
167 assert(Map[0].BreakDown == \
168 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
169 Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
170 " Dst is incorrectly initialized"); \
171 assert(Map[1].BreakDown == \
172 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
173 Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
174 " Src is incorrectly initialized"); \
187#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
189 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
190 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
191 (void)PartialMapDstIdx; \
192 (void)PartialMapSrcIdx; \
193 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
195 assert(Map[0].BreakDown == \
196 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
197 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
198 " Dst is incorrectly initialized"); \
199 assert(Map[1].BreakDown == \
200 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
201 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
202 " Src is incorrectly initialized"); \
214 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
219 unsigned Size)
const {
228 if (&
A == &AArch64::GPRRegBank && &
B == &AArch64::FPRRegBank)
231 if (&
A == &AArch64::FPRRegBank && &
B == &AArch64::GPRRegBank)
241 switch (RC.
getID()) {
242 case AArch64::FPR8RegClassID:
243 case AArch64::FPR16RegClassID:
244 case AArch64::FPR16_loRegClassID:
245 case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
246 case AArch64::FPR32RegClassID:
247 case AArch64::FPR64RegClassID:
248 case AArch64::FPR64_loRegClassID:
249 case AArch64::FPR128RegClassID:
250 case AArch64::FPR128_loRegClassID:
251 case AArch64::DDRegClassID:
252 case AArch64::DDDRegClassID:
253 case AArch64::DDDDRegClassID:
254 case AArch64::QQRegClassID:
255 case AArch64::QQQRegClassID:
256 case AArch64::QQQQRegClassID:
258 case AArch64::GPR32commonRegClassID:
259 case AArch64::GPR32RegClassID:
260 case AArch64::GPR32spRegClassID:
261 case AArch64::GPR32sponlyRegClassID:
262 case AArch64::GPR32argRegClassID:
263 case AArch64::GPR32allRegClassID:
264 case AArch64::GPR64commonRegClassID:
265 case AArch64::GPR64RegClassID:
266 case AArch64::GPR64spRegClassID:
267 case AArch64::GPR64sponlyRegClassID:
268 case AArch64::GPR64argRegClassID:
269 case AArch64::GPR64allRegClassID:
270 case AArch64::GPR64noipRegClassID:
271 case AArch64::GPR64common_and_GPR64noipRegClassID:
272 case AArch64::GPR64noip_and_tcGPR64RegClassID:
273 case AArch64::tcGPR64RegClassID:
274 case AArch64::rtcGPR64RegClassID:
275 case AArch64::WSeqPairsClassRegClassID:
276 case AArch64::XSeqPairsClassRegClassID:
277 case AArch64::MatrixIndexGPR32_8_11RegClassID:
278 case AArch64::MatrixIndexGPR32_12_15RegClassID:
279 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID:
280 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
282 case AArch64::CCRRegClassID:
297 switch (
MI.getOpcode()) {
298 case TargetOpcode::G_OR: {
307 if (
MI.getNumOperands() != 3)
321 case TargetOpcode::G_BITCAST: {
328 if (
MI.getNumOperands() != 2)
342 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
Size),
347 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
Size),
357 case TargetOpcode::G_LOAD: {
364 if (
MI.getNumOperands() != 2)
391void AArch64RegisterBankInfo::applyMappingImpl(
393 switch (OpdMapper.getMI().getOpcode()) {
394 case TargetOpcode::G_OR:
395 case TargetOpcode::G_BITCAST:
396 case TargetOpcode::G_LOAD:
398 assert((OpdMapper.getInstrMapping().getID() >= 1 &&
399 OpdMapper.getInstrMapping().getID() <= 4) &&
400 "Don't know how to handle that ID");
411 case TargetOpcode::G_FADD:
412 case TargetOpcode::G_FSUB:
413 case TargetOpcode::G_FMUL:
414 case TargetOpcode::G_FMA:
415 case TargetOpcode::G_FDIV:
416 case TargetOpcode::G_FCONSTANT:
417 case TargetOpcode::G_FPEXT:
418 case TargetOpcode::G_FPTRUNC:
419 case TargetOpcode::G_FCEIL:
420 case TargetOpcode::G_FFLOOR:
421 case TargetOpcode::G_FNEARBYINT:
422 case TargetOpcode::G_FNEG:
423 case TargetOpcode::G_FCOS:
424 case TargetOpcode::G_FSIN:
425 case TargetOpcode::G_FLOG10:
426 case TargetOpcode::G_FLOG:
427 case TargetOpcode::G_FLOG2:
428 case TargetOpcode::G_FSQRT:
429 case TargetOpcode::G_FABS:
430 case TargetOpcode::G_FEXP:
431 case TargetOpcode::G_FRINT:
432 case TargetOpcode::G_INTRINSIC_TRUNC:
433 case TargetOpcode::G_INTRINSIC_ROUND:
434 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
435 case TargetOpcode::G_FMAXNUM:
436 case TargetOpcode::G_FMINNUM:
437 case TargetOpcode::G_FMAXIMUM:
438 case TargetOpcode::G_FMINIMUM:
445AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
447 const unsigned Opc =
MI.getOpcode();
451 unsigned NumOperands =
MI.getNumOperands();
452 assert(NumOperands <= 3 &&
453 "This code is for instructions with 3 or less operands");
455 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
470 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
471 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
476 "Operand has incompatible size");
479 assert(IsFPR == OpIsFPR &&
"Operand has incompatible type");
494 case Intrinsic::aarch64_neon_uaddlv:
495 case Intrinsic::aarch64_neon_uaddv:
496 case Intrinsic::aarch64_neon_saddv:
497 case Intrinsic::aarch64_neon_umaxv:
498 case Intrinsic::aarch64_neon_smaxv:
499 case Intrinsic::aarch64_neon_uminv:
500 case Intrinsic::aarch64_neon_sminv:
501 case Intrinsic::aarch64_neon_faddv:
502 case Intrinsic::aarch64_neon_fmaxv:
503 case Intrinsic::aarch64_neon_fminv:
504 case Intrinsic::aarch64_neon_fmaxnmv:
505 case Intrinsic::aarch64_neon_fminnmv:
507 case Intrinsic::aarch64_neon_saddlv: {
508 const LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
515bool AArch64RegisterBankInfo::hasFPConstraints(
const MachineInstr &
MI,
518 unsigned Depth)
const {
519 unsigned Op =
MI.getOpcode();
529 if (
Op != TargetOpcode::COPY && !
MI.isPHI() &&
535 if (RB == &AArch64::FPRRegBank)
537 if (RB == &AArch64::GPRRegBank)
544 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
549 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
556 unsigned Depth)
const {
557 switch (
MI.getOpcode()) {
558 case TargetOpcode::G_FPTOSI:
559 case TargetOpcode::G_FPTOUI:
560 case TargetOpcode::G_FCMP:
561 case TargetOpcode::G_LROUND:
562 case TargetOpcode::G_LLROUND:
570bool AArch64RegisterBankInfo::onlyDefinesFP(
const MachineInstr &
MI,
573 unsigned Depth)
const {
574 switch (
MI.getOpcode()) {
576 case TargetOpcode::G_SITOFP:
577 case TargetOpcode::G_UITOFP:
578 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
579 case TargetOpcode::G_INSERT_VECTOR_ELT:
580 case TargetOpcode::G_BUILD_VECTOR:
581 case TargetOpcode::G_BUILD_VECTOR_TRUNC:
583 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
585 case Intrinsic::aarch64_neon_ld1x2:
586 case Intrinsic::aarch64_neon_ld1x3:
587 case Intrinsic::aarch64_neon_ld1x4:
588 case Intrinsic::aarch64_neon_ld2:
589 case Intrinsic::aarch64_neon_ld2lane:
590 case Intrinsic::aarch64_neon_ld2r:
591 case Intrinsic::aarch64_neon_ld3:
592 case Intrinsic::aarch64_neon_ld3lane:
593 case Intrinsic::aarch64_neon_ld3r:
594 case Intrinsic::aarch64_neon_ld4:
595 case Intrinsic::aarch64_neon_ld4lane:
596 case Intrinsic::aarch64_neon_ld4r:
610 const unsigned Opc =
MI.getOpcode();
615 Opc == TargetOpcode::G_PHI) {
630 case TargetOpcode::G_ADD:
631 case TargetOpcode::G_SUB:
632 case TargetOpcode::G_PTR_ADD:
633 case TargetOpcode::G_MUL:
634 case TargetOpcode::G_SDIV:
635 case TargetOpcode::G_UDIV:
637 case TargetOpcode::G_AND:
638 case TargetOpcode::G_OR:
639 case TargetOpcode::G_XOR:
641 case TargetOpcode::G_FADD:
642 case TargetOpcode::G_FSUB:
643 case TargetOpcode::G_FMUL:
644 case TargetOpcode::G_FDIV:
645 case TargetOpcode::G_FMAXIMUM:
646 case TargetOpcode::G_FMINIMUM:
647 return getSameKindOfOperandsMapping(
MI);
648 case TargetOpcode::G_FPEXT: {
649 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
650 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
657 case TargetOpcode::G_SHL:
658 case TargetOpcode::G_LSHR:
659 case TargetOpcode::G_ASHR: {
660 LLT ShiftAmtTy =
MRI.getType(
MI.getOperand(2).getReg());
661 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
665 return getSameKindOfOperandsMapping(
MI);
667 case TargetOpcode::COPY: {
671 if ((DstReg.
isPhysical() || !
MRI.getType(DstReg).isValid()) ||
681 assert(DstRB && SrcRB &&
"Both RegBank were nullptr");
692 case TargetOpcode::G_BITCAST: {
693 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
694 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
699 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
701 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
706 Opc == TargetOpcode::G_BITCAST ? 2 : 1);
712 unsigned NumOperands =
MI.getNumOperands();
717 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
718 auto &MO =
MI.getOperand(
Idx);
719 if (!MO.isReg() || !MO.getReg())
722 LLT Ty =
MRI.getType(MO.getReg());
740 case AArch64::G_DUP: {
741 Register ScalarReg =
MI.getOperand(1).getReg();
742 LLT ScalarTy =
MRI.getType(ScalarReg);
743 auto ScalarDef =
MRI.getVRegDef(ScalarReg);
745 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)
750 onlyDefinesFP(*ScalarDef,
MRI,
TRI)))
756 case TargetOpcode::G_TRUNC: {
757 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
762 case TargetOpcode::G_SITOFP:
763 case TargetOpcode::G_UITOFP: {
764 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
775 case TargetOpcode::G_FPTOSI:
776 case TargetOpcode::G_FPTOUI:
777 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
781 case TargetOpcode::G_FCMP: {
786 OpRegBankIdx = {Idx0,
790 case TargetOpcode::G_BITCAST:
792 if (OpRegBankIdx[0] != OpRegBankIdx[1])
798 case TargetOpcode::G_LOAD: {
810 if (cast<GLoad>(
MI).isAtomic()) {
817 const auto &MMO = **
MI.memoperands_begin();
818 const Value *LdVal = MMO.getValue();
820 Type *EltTy =
nullptr;
821 if (
const GlobalValue *GV = dyn_cast<GlobalValue>(LdVal)) {
822 EltTy = GV->getValueType();
826 for (
const auto *LdUser : LdVal->
users()) {
827 if (isa<LoadInst>(LdUser)) {
828 EltTy = LdUser->getType();
831 if (isa<StoreInst>(LdUser) && LdUser->getOperand(1) == LdVal) {
832 EltTy = LdUser->getOperand(0)->getType();
846 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
855 return onlyUsesFP(UseMI, MRI, TRI) ||
856 onlyDefinesFP(UseMI, MRI, TRI);
861 case TargetOpcode::G_STORE:
873 case TargetOpcode::G_SELECT: {
880 LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
897 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
929 case TargetOpcode::G_UNMERGE_VALUES: {
935 LLT SrcTy =
MRI.getType(
MI.getOperand(
MI.getNumOperands()-1).getReg());
939 any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
942 for (
unsigned Idx = 0, NumOperands =
MI.getNumOperands();
948 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
956 case TargetOpcode::G_INSERT_VECTOR_ELT:
969 case TargetOpcode::G_EXTRACT: {
971 auto Src =
MI.getOperand(1).getReg();
972 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
975 auto Idx =
MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
978 OpRegBankIdx[0] =
Idx;
979 OpRegBankIdx[1] =
Idx;
982 case TargetOpcode::G_BUILD_VECTOR: {
998 const LLT SrcTy =
MRI.getType(VReg);
1000 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
1001 TargetOpcode::G_CONSTANT;
1009 unsigned NumOperands =
MI.getNumOperands();
1010 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx)
1015 case TargetOpcode::G_VECREDUCE_FADD:
1016 case TargetOpcode::G_VECREDUCE_FMUL:
1017 case TargetOpcode::G_VECREDUCE_FMAX:
1018 case TargetOpcode::G_VECREDUCE_FMIN:
1019 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1020 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1021 case TargetOpcode::G_VECREDUCE_ADD:
1022 case TargetOpcode::G_VECREDUCE_MUL:
1023 case TargetOpcode::G_VECREDUCE_AND:
1024 case TargetOpcode::G_VECREDUCE_OR:
1025 case TargetOpcode::G_VECREDUCE_XOR:
1026 case TargetOpcode::G_VECREDUCE_SMAX:
1027 case TargetOpcode::G_VECREDUCE_SMIN:
1028 case TargetOpcode::G_VECREDUCE_UMAX:
1029 case TargetOpcode::G_VECREDUCE_UMIN:
1034 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1035 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
1040 case TargetOpcode::G_INTRINSIC:
1041 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1046 for (
const auto &
Op :
MI.defs()) {
1052 Idx +=
MI.getNumExplicitDefs();
1055 for (
const auto &
Op :
MI.explicit_uses()) {
1062 case TargetOpcode::G_LROUND:
1063 case TargetOpcode::G_LLROUND: {
1072 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
1073 if (
MI.getOperand(
Idx).isReg() &&
MI.getOperand(
Idx).getReg()) {
1074 LLT Ty =
MRI.getType(
MI.getOperand(
Idx).getReg());
1078 if (!Mapping->isValid())
1081 OpdsMapping[
Idx] = Mapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static unsigned getIntrinsicID(const SDNode *N)
#define CHECK_VALUEMAP(RBName, Size)
static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)
#define CHECK_VALUEMAP_3OPS(RBName, Size)
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
This file declares the targeting of the RegisterBankInfo class for AArch64.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static RegisterBankInfo::PartialMapping PartMappings[]
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
static RegisterBankInfo::ValueMapping ValMappings[]
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
This class represents an Operation in the Expression.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
LLVM Value Representation.
iterator_range< user_iterator > users()
constexpr ScalarTy getFixedValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
The llvm::once_flag structure.