LLVM  14.0.0git
AArch64RegisterBankInfo.cpp
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1 //===- AArch64RegisterBankInfo.cpp ----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the RegisterBankInfo class for
10 /// AArch64.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
15 #include "AArch64InstrInfo.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/IR/IntrinsicsAArch64.h"
32 #include <algorithm>
33 #include <cassert>
34 
35 #define GET_TARGET_REGBANK_IMPL
36 #include "AArch64GenRegisterBank.inc"
37 
38 // This file will be TableGen'ed at some point.
39 #include "AArch64GenRegisterBankInfo.def"
40 
41 using namespace llvm;
42 
45  static llvm::once_flag InitializeRegisterBankFlag;
46 
47  static auto InitializeRegisterBankOnce = [&]() {
48  // We have only one set of register banks, whatever the subtarget
49  // is. Therefore, the initialization of the RegBanks table should be
50  // done only once. Indeed the table of all register banks
51  // (AArch64::RegBanks) is unique in the compiler. At some point, it
52  // will get tablegen'ed and the whole constructor becomes empty.
53 
54  const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
55  (void)RBGPR;
56  assert(&AArch64::GPRRegBank == &RBGPR &&
57  "The order in RegBanks is messed up");
58 
59  const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
60  (void)RBFPR;
61  assert(&AArch64::FPRRegBank == &RBFPR &&
62  "The order in RegBanks is messed up");
63 
64  const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
65  (void)RBCCR;
66  assert(&AArch64::CCRegBank == &RBCCR &&
67  "The order in RegBanks is messed up");
68 
69  // The GPR register bank is fully defined by all the registers in
70  // GR64all + its subclasses.
71  assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
72  "Subclass not added?");
73  assert(RBGPR.getSize() == 128 && "GPRs should hold up to 128-bit");
74 
75  // The FPR register bank is fully defined by all the registers in
76  // GR64all + its subclasses.
77  assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
78  "Subclass not added?");
79  assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
80  "Subclass not added?");
81  assert(RBFPR.getSize() == 512 &&
82  "FPRs should hold up to 512-bit via QQQQ sequence");
83 
84  assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
85  "Class not added?");
86  assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
87 
88  // Check that the TableGen'ed like file is in sync we our expectations.
89  // First, the Idx.
92  "PartialMappingIdx's are incorrectly ordered");
96  "PartialMappingIdx's are incorrectly ordered");
97 // Now, the content.
98 // Check partial mapping.
99 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
100  do { \
101  assert( \
102  checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
103  #Idx " is incorrectly initialized"); \
104  } while (false)
105 
106  CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
107  CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
108  CHECK_PARTIALMAP(PMI_GPR128, 0, 128, RBGPR);
109  CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
110  CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
111  CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
112  CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
113  CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
114  CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
115 
116 // Check value mapping.
117 #define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
118  do { \
119  assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
120  PartialMappingIdx::PMI_First##RBName, Size, \
121  Offset) && \
122  #RBName #Size " " #Offset " is incorrectly initialized"); \
123  } while (false)
124 
125 #define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
126 
127  CHECK_VALUEMAP(GPR, 32);
128  CHECK_VALUEMAP(GPR, 64);
129  CHECK_VALUEMAP(GPR, 128);
130  CHECK_VALUEMAP(FPR, 16);
131  CHECK_VALUEMAP(FPR, 32);
132  CHECK_VALUEMAP(FPR, 64);
133  CHECK_VALUEMAP(FPR, 128);
134  CHECK_VALUEMAP(FPR, 256);
135  CHECK_VALUEMAP(FPR, 512);
136 
137 // Check the value mapping for 3-operands instructions where all the operands
138 // map to the same value mapping.
139 #define CHECK_VALUEMAP_3OPS(RBName, Size) \
140  do { \
141  CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
142  CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
143  CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
144  } while (false)
145 
146  CHECK_VALUEMAP_3OPS(GPR, 32);
147  CHECK_VALUEMAP_3OPS(GPR, 64);
148  CHECK_VALUEMAP_3OPS(GPR, 128);
151  CHECK_VALUEMAP_3OPS(FPR, 128);
152  CHECK_VALUEMAP_3OPS(FPR, 256);
153  CHECK_VALUEMAP_3OPS(FPR, 512);
154 
155 #define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
156  do { \
157  unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
158  unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
159  (void)PartialMapDstIdx; \
160  (void)PartialMapSrcIdx; \
161  const ValueMapping *Map = getCopyMapping( \
162  AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
163  (void)Map; \
164  assert(Map[0].BreakDown == \
165  &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
166  Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
167  " Dst is incorrectly initialized"); \
168  assert(Map[1].BreakDown == \
169  &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
170  Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
171  " Src is incorrectly initialized"); \
172  \
173  } while (false)
174 
175  CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
177  CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
183 
184 #define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
185  do { \
186  unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
187  unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
188  (void)PartialMapDstIdx; \
189  (void)PartialMapSrcIdx; \
190  const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
191  (void)Map; \
192  assert(Map[0].BreakDown == \
193  &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
194  Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
195  " Dst is incorrectly initialized"); \
196  assert(Map[1].BreakDown == \
197  &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
198  Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
199  " Src is incorrectly initialized"); \
200  \
201  } while (false)
202 
203  CHECK_VALUEMAP_FPEXT(32, 16);
204  CHECK_VALUEMAP_FPEXT(64, 16);
205  CHECK_VALUEMAP_FPEXT(64, 32);
206  CHECK_VALUEMAP_FPEXT(128, 64);
207 
208  assert(verify(TRI) && "Invalid register bank information");
209  };
210 
211  llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
212 }
213 
215  const RegisterBank &B,
216  unsigned Size) const {
217  // What do we do with different size?
218  // copy are same size.
219  // Will introduce other hooks for different size:
220  // * extract cost.
221  // * build_sequence cost.
222 
223  // Copy from (resp. to) GPR to (resp. from) FPR involves FMOV.
224  // FIXME: This should be deduced from the scheduling model.
225  if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)
226  // FMOVXDr or FMOVWSr.
227  return 5;
228  if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)
229  // FMOVDXr or FMOVSWr.
230  return 4;
231 
232  return RegisterBankInfo::copyCost(A, B, Size);
233 }
234 
235 const RegisterBank &
237  LLT) const {
238  switch (RC.getID()) {
239  case AArch64::FPR8RegClassID:
240  case AArch64::FPR16RegClassID:
241  case AArch64::FPR16_loRegClassID:
242  case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
243  case AArch64::FPR32RegClassID:
244  case AArch64::FPR64RegClassID:
245  case AArch64::FPR64_loRegClassID:
246  case AArch64::FPR128RegClassID:
247  case AArch64::FPR128_loRegClassID:
248  case AArch64::DDRegClassID:
249  case AArch64::DDDRegClassID:
250  case AArch64::DDDDRegClassID:
251  case AArch64::QQRegClassID:
252  case AArch64::QQQRegClassID:
253  case AArch64::QQQQRegClassID:
254  return getRegBank(AArch64::FPRRegBankID);
255  case AArch64::GPR32commonRegClassID:
256  case AArch64::GPR32RegClassID:
257  case AArch64::GPR32spRegClassID:
258  case AArch64::GPR32sponlyRegClassID:
259  case AArch64::GPR32argRegClassID:
260  case AArch64::GPR32allRegClassID:
261  case AArch64::GPR64commonRegClassID:
262  case AArch64::GPR64RegClassID:
263  case AArch64::GPR64spRegClassID:
264  case AArch64::GPR64sponlyRegClassID:
265  case AArch64::GPR64argRegClassID:
266  case AArch64::GPR64allRegClassID:
267  case AArch64::GPR64noipRegClassID:
268  case AArch64::GPR64common_and_GPR64noipRegClassID:
269  case AArch64::GPR64noip_and_tcGPR64RegClassID:
270  case AArch64::tcGPR64RegClassID:
271  case AArch64::rtcGPR64RegClassID:
272  case AArch64::WSeqPairsClassRegClassID:
273  case AArch64::XSeqPairsClassRegClassID:
274  case AArch64::MatrixIndexGPR32_12_15RegClassID:
275  return getRegBank(AArch64::GPRRegBankID);
276  case AArch64::CCRRegClassID:
277  return getRegBank(AArch64::CCRegBankID);
278  default:
279  llvm_unreachable("Register class not supported");
280  }
281 }
282 
285  const MachineInstr &MI) const {
286  const MachineFunction &MF = *MI.getParent()->getParent();
287  const TargetSubtargetInfo &STI = MF.getSubtarget();
288  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
289  const MachineRegisterInfo &MRI = MF.getRegInfo();
290 
291  switch (MI.getOpcode()) {
292  case TargetOpcode::G_OR: {
293  // 32 and 64-bit or can be mapped on either FPR or
294  // GPR for the same cost.
295  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
296  if (Size != 32 && Size != 64)
297  break;
298 
299  // If the instruction has any implicit-defs or uses,
300  // do not mess with it.
301  if (MI.getNumOperands() != 3)
302  break;
303  InstructionMappings AltMappings;
304  const InstructionMapping &GPRMapping = getInstructionMapping(
305  /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size),
306  /*NumOperands*/ 3);
307  const InstructionMapping &FPRMapping = getInstructionMapping(
308  /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size),
309  /*NumOperands*/ 3);
310 
311  AltMappings.push_back(&GPRMapping);
312  AltMappings.push_back(&FPRMapping);
313  return AltMappings;
314  }
315  case TargetOpcode::G_BITCAST: {
316  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
317  if (Size != 32 && Size != 64)
318  break;
319 
320  // If the instruction has any implicit-defs or uses,
321  // do not mess with it.
322  if (MI.getNumOperands() != 2)
323  break;
324 
325  InstructionMappings AltMappings;
326  const InstructionMapping &GPRMapping = getInstructionMapping(
327  /*ID*/ 1, /*Cost*/ 1,
328  getCopyMapping(AArch64::GPRRegBankID, AArch64::GPRRegBankID, Size),
329  /*NumOperands*/ 2);
330  const InstructionMapping &FPRMapping = getInstructionMapping(
331  /*ID*/ 2, /*Cost*/ 1,
332  getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size),
333  /*NumOperands*/ 2);
334  const InstructionMapping &GPRToFPRMapping = getInstructionMapping(
335  /*ID*/ 3,
336  /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
337  getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size),
338  /*NumOperands*/ 2);
339  const InstructionMapping &FPRToGPRMapping = getInstructionMapping(
340  /*ID*/ 3,
341  /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
342  getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size),
343  /*NumOperands*/ 2);
344 
345  AltMappings.push_back(&GPRMapping);
346  AltMappings.push_back(&FPRMapping);
347  AltMappings.push_back(&GPRToFPRMapping);
348  AltMappings.push_back(&FPRToGPRMapping);
349  return AltMappings;
350  }
351  case TargetOpcode::G_LOAD: {
352  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
353  if (Size != 64)
354  break;
355 
356  // If the instruction has any implicit-defs or uses,
357  // do not mess with it.
358  if (MI.getNumOperands() != 2)
359  break;
360 
361  InstructionMappings AltMappings;
362  const InstructionMapping &GPRMapping = getInstructionMapping(
363  /*ID*/ 1, /*Cost*/ 1,
365  // Addresses are GPR 64-bit.
367  /*NumOperands*/ 2);
368  const InstructionMapping &FPRMapping = getInstructionMapping(
369  /*ID*/ 2, /*Cost*/ 1,
371  // Addresses are GPR 64-bit.
373  /*NumOperands*/ 2);
374 
375  AltMappings.push_back(&GPRMapping);
376  AltMappings.push_back(&FPRMapping);
377  return AltMappings;
378  }
379  default:
380  break;
381  }
383 }
384 
385 void AArch64RegisterBankInfo::applyMappingImpl(
386  const OperandsMapper &OpdMapper) const {
387  switch (OpdMapper.getMI().getOpcode()) {
388  case TargetOpcode::G_OR:
389  case TargetOpcode::G_BITCAST:
390  case TargetOpcode::G_LOAD:
391  // Those ID must match getInstrAlternativeMappings.
392  assert((OpdMapper.getInstrMapping().getID() >= 1 &&
393  OpdMapper.getInstrMapping().getID() <= 4) &&
394  "Don't know how to handle that ID");
395  return applyDefaultMapping(OpdMapper);
396  default:
397  llvm_unreachable("Don't know how to handle that operation");
398  }
399 }
400 
401 /// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
402 /// having only floating-point operands.
403 static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
404  switch (Opc) {
405  case TargetOpcode::G_FADD:
406  case TargetOpcode::G_FSUB:
407  case TargetOpcode::G_FMUL:
408  case TargetOpcode::G_FMA:
409  case TargetOpcode::G_FDIV:
410  case TargetOpcode::G_FCONSTANT:
411  case TargetOpcode::G_FPEXT:
412  case TargetOpcode::G_FPTRUNC:
413  case TargetOpcode::G_FCEIL:
414  case TargetOpcode::G_FFLOOR:
415  case TargetOpcode::G_FNEARBYINT:
416  case TargetOpcode::G_FNEG:
417  case TargetOpcode::G_FCOS:
418  case TargetOpcode::G_FSIN:
419  case TargetOpcode::G_FLOG10:
420  case TargetOpcode::G_FLOG:
421  case TargetOpcode::G_FLOG2:
422  case TargetOpcode::G_FSQRT:
423  case TargetOpcode::G_FABS:
424  case TargetOpcode::G_FEXP:
425  case TargetOpcode::G_FRINT:
426  case TargetOpcode::G_INTRINSIC_TRUNC:
427  case TargetOpcode::G_INTRINSIC_ROUND:
428  case TargetOpcode::G_FMAXNUM:
429  case TargetOpcode::G_FMINNUM:
430  return true;
431  }
432  return false;
433 }
434 
436 AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
437  const MachineInstr &MI) const {
438  const unsigned Opc = MI.getOpcode();
439  const MachineFunction &MF = *MI.getParent()->getParent();
440  const MachineRegisterInfo &MRI = MF.getRegInfo();
441 
442  unsigned NumOperands = MI.getNumOperands();
443  assert(NumOperands <= 3 &&
444  "This code is for instructions with 3 or less operands");
445 
446  LLT Ty = MRI.getType(MI.getOperand(0).getReg());
447  unsigned Size = Ty.getSizeInBits();
448  bool IsFPR = Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
449 
450  PartialMappingIdx RBIdx = IsFPR ? PMI_FirstFPR : PMI_FirstGPR;
451 
452 #ifndef NDEBUG
453  // Make sure all the operands are using similar size and type.
454  // Should probably be checked by the machine verifier.
455  // This code won't catch cases where the number of lanes is
456  // different between the operands.
457  // If we want to go to that level of details, it is probably
458  // best to check that the types are the same, period.
459  // Currently, we just check that the register banks are the same
460  // for each types.
461  for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {
462  LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
463  assert(
465  RBIdx, OpTy.getSizeInBits()) ==
467  "Operand has incompatible size");
468  bool OpIsFPR = OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
469  (void)OpIsFPR;
470  assert(IsFPR == OpIsFPR && "Operand has incompatible type");
471  }
472 #endif // End NDEBUG.
473 
475  getValueMapping(RBIdx, Size), NumOperands);
476 }
477 
478 /// \returns true if a given intrinsic \p ID only uses and defines FPRs.
479 static bool isFPIntrinsic(unsigned ID) {
480  // TODO: Add more intrinsics.
481  switch (ID) {
482  default:
483  return false;
484  case Intrinsic::aarch64_neon_uaddlv:
485  return true;
486  }
487 }
488 
489 bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,
490  const MachineRegisterInfo &MRI,
491  const TargetRegisterInfo &TRI,
492  unsigned Depth) const {
493  unsigned Op = MI.getOpcode();
494  if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(MI.getIntrinsicID()))
495  return true;
496 
497  // Do we have an explicit floating point instruction?
499  return true;
500 
501  // No. Check if we have a copy-like instruction. If we do, then we could
502  // still be fed by floating point instructions.
503  if (Op != TargetOpcode::COPY && !MI.isPHI() &&
505  return false;
506 
507  // Check if we already know the register bank.
508  auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI);
509  if (RB == &AArch64::FPRRegBank)
510  return true;
511  if (RB == &AArch64::GPRRegBank)
512  return false;
513 
514  // We don't know anything.
515  //
516  // If we have a phi, we may be able to infer that it will be assigned a FPR
517  // based off of its inputs.
518  if (!MI.isPHI() || Depth > MaxFPRSearchDepth)
519  return false;
520 
521  return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {
522  return Op.isReg() &&
523  onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
524  });
525 }
526 
527 bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
528  const MachineRegisterInfo &MRI,
529  const TargetRegisterInfo &TRI,
530  unsigned Depth) const {
531  switch (MI.getOpcode()) {
532  case TargetOpcode::G_FPTOSI:
533  case TargetOpcode::G_FPTOUI:
534  case TargetOpcode::G_FCMP:
535  case TargetOpcode::G_LROUND:
536  case TargetOpcode::G_LLROUND:
537  return true;
538  default:
539  break;
540  }
541  return hasFPConstraints(MI, MRI, TRI, Depth);
542 }
543 
544 bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
545  const MachineRegisterInfo &MRI,
546  const TargetRegisterInfo &TRI,
547  unsigned Depth) const {
548  switch (MI.getOpcode()) {
549  case AArch64::G_DUP:
550  case TargetOpcode::G_SITOFP:
551  case TargetOpcode::G_UITOFP:
552  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
553  case TargetOpcode::G_INSERT_VECTOR_ELT:
554  case TargetOpcode::G_BUILD_VECTOR:
555  case TargetOpcode::G_BUILD_VECTOR_TRUNC:
556  return true;
557  default:
558  break;
559  }
560  return hasFPConstraints(MI, MRI, TRI, Depth);
561 }
562 
565  const unsigned Opc = MI.getOpcode();
566 
567  // Try the default logic for non-generic instructions that are either copies
568  // or already have some operands assigned to banks.
569  if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
570  Opc == TargetOpcode::G_PHI) {
571  const RegisterBankInfo::InstructionMapping &Mapping =
573  if (Mapping.isValid())
574  return Mapping;
575  }
576 
577  const MachineFunction &MF = *MI.getParent()->getParent();
578  const MachineRegisterInfo &MRI = MF.getRegInfo();
579  const TargetSubtargetInfo &STI = MF.getSubtarget();
580  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
581 
582  switch (Opc) {
583  // G_{F|S|U}REM are not listed because they are not legal.
584  // Arithmetic ops.
585  case TargetOpcode::G_ADD:
586  case TargetOpcode::G_SUB:
587  case TargetOpcode::G_PTR_ADD:
588  case TargetOpcode::G_MUL:
589  case TargetOpcode::G_SDIV:
590  case TargetOpcode::G_UDIV:
591  // Bitwise ops.
592  case TargetOpcode::G_AND:
593  case TargetOpcode::G_OR:
594  case TargetOpcode::G_XOR:
595  // Floating point ops.
596  case TargetOpcode::G_FADD:
597  case TargetOpcode::G_FSUB:
598  case TargetOpcode::G_FMUL:
599  case TargetOpcode::G_FDIV:
600  return getSameKindOfOperandsMapping(MI);
601  case TargetOpcode::G_FPEXT: {
602  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
603  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
604  return getInstructionMapping(
605  DefaultMappingID, /*Cost*/ 1,
606  getFPExtMapping(DstTy.getSizeInBits(), SrcTy.getSizeInBits()),
607  /*NumOperands*/ 2);
608  }
609  // Shifts.
610  case TargetOpcode::G_SHL:
611  case TargetOpcode::G_LSHR:
612  case TargetOpcode::G_ASHR: {
613  LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());
614  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
615  if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32)
617  &ValMappings[Shift64Imm], 3);
618  return getSameKindOfOperandsMapping(MI);
619  }
620  case TargetOpcode::COPY: {
621  Register DstReg = MI.getOperand(0).getReg();
622  Register SrcReg = MI.getOperand(1).getReg();
623  // Check if one of the register is not a generic register.
624  if ((Register::isPhysicalRegister(DstReg) ||
625  !MRI.getType(DstReg).isValid()) ||
626  (Register::isPhysicalRegister(SrcReg) ||
627  !MRI.getType(SrcReg).isValid())) {
628  const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
629  const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
630  if (!DstRB)
631  DstRB = SrcRB;
632  else if (!SrcRB)
633  SrcRB = DstRB;
634  // If both RB are null that means both registers are generic.
635  // We shouldn't be here.
636  assert(DstRB && SrcRB && "Both RegBank were nullptr");
637  unsigned Size = getSizeInBits(DstReg, MRI, TRI);
638  return getInstructionMapping(
639  DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
640  getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
641  // We only care about the mapping of the destination.
642  /*NumOperands*/ 1);
643  }
644  // Both registers are generic, use G_BITCAST.
646  }
647  case TargetOpcode::G_BITCAST: {
648  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
649  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
650  unsigned Size = DstTy.getSizeInBits();
651  bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
652  bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
653  const RegisterBank &DstRB =
654  DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
655  const RegisterBank &SrcRB =
656  SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
657  return getInstructionMapping(
658  DefaultMappingID, copyCost(DstRB, SrcRB, Size),
659  getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
660  // We only care about the mapping of the destination for COPY.
661  /*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
662  }
663  default:
664  break;
665  }
666 
667  unsigned NumOperands = MI.getNumOperands();
668 
669  // Track the size and bank of each register. We don't do partial mappings.
670  SmallVector<unsigned, 4> OpSize(NumOperands);
671  SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
672  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
673  auto &MO = MI.getOperand(Idx);
674  if (!MO.isReg() || !MO.getReg())
675  continue;
676 
677  LLT Ty = MRI.getType(MO.getReg());
678  OpSize[Idx] = Ty.getSizeInBits();
679 
680  // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
681  // For floating-point instructions, scalars go in FPRs.
683  Ty.getSizeInBits() > 64)
684  OpRegBankIdx[Idx] = PMI_FirstFPR;
685  else
686  OpRegBankIdx[Idx] = PMI_FirstGPR;
687  }
688 
689  unsigned Cost = 1;
690  // Some of the floating-point instructions have mixed GPR and FPR operands:
691  // fine-tune the computed mapping.
692  switch (Opc) {
693  case AArch64::G_DUP: {
694  Register ScalarReg = MI.getOperand(1).getReg();
695  LLT ScalarTy = MRI.getType(ScalarReg);
696  auto ScalarDef = MRI.getVRegDef(ScalarReg);
697  // s8 is an exception for G_DUP, which we always want on gpr.
698  if (ScalarTy.getSizeInBits() != 8 &&
699  (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
700  onlyDefinesFP(*ScalarDef, MRI, TRI)))
701  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
702  else
703  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
704  break;
705  }
706  case TargetOpcode::G_TRUNC: {
707  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
708  if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128)
709  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
710  break;
711  }
712  case TargetOpcode::G_SITOFP:
713  case TargetOpcode::G_UITOFP: {
714  if (MRI.getType(MI.getOperand(0).getReg()).isVector())
715  break;
716  // Integer to FP conversions don't necessarily happen between GPR -> FPR
717  // regbanks. They can also be done within an FPR register.
718  Register SrcReg = MI.getOperand(1).getReg();
719  if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank)
720  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
721  else
722  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
723  break;
724  }
725  case TargetOpcode::G_FPTOSI:
726  case TargetOpcode::G_FPTOUI:
727  if (MRI.getType(MI.getOperand(0).getReg()).isVector())
728  break;
729  OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
730  break;
731  case TargetOpcode::G_FCMP: {
732  // If the result is a vector, it must use a FPR.
734  MRI.getType(MI.getOperand(0).getReg()).isVector() ? PMI_FirstFPR
735  : PMI_FirstGPR;
736  OpRegBankIdx = {Idx0,
737  /* Predicate */ PMI_None, PMI_FirstFPR, PMI_FirstFPR};
738  break;
739  }
740  case TargetOpcode::G_BITCAST:
741  // This is going to be a cross register bank copy and this is expensive.
742  if (OpRegBankIdx[0] != OpRegBankIdx[1])
743  Cost = copyCost(
744  *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank,
745  *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank,
746  OpSize[0]);
747  break;
748  case TargetOpcode::G_LOAD:
749  // Loading in vector unit is slightly more expensive.
750  // This is actually only true for the LD1R and co instructions,
751  // but anyway for the fast mode this number does not matter and
752  // for the greedy mode the cost of the cross bank copy will
753  // offset this number.
754  // FIXME: Should be derived from the scheduling model.
755  if (OpRegBankIdx[0] != PMI_FirstGPR) {
756  Cost = 2;
757  break;
758  }
759 
760  if (cast<GLoad>(MI).isAtomic()) {
761  // Atomics always use GPR destinations. Don't refine any further.
762  OpRegBankIdx[0] = PMI_FirstGPR;
763  break;
764  }
765 
766  // Check if that load feeds fp instructions.
767  // In that case, we want the default mapping to be on FPR
768  // instead of blind map every scalar to GPR.
769  if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
770  [&](const MachineInstr &UseMI) {
771  // If we have at least one direct use in a FP instruction,
772  // assume this was a floating point load in the IR. If it was
773  // not, we would have had a bitcast before reaching that
774  // instruction.
775  //
776  // Int->FP conversion operations are also captured in
777  // onlyDefinesFP().
778  return onlyUsesFP(UseMI, MRI, TRI) ||
779  onlyDefinesFP(UseMI, MRI, TRI);
780  }))
781  OpRegBankIdx[0] = PMI_FirstFPR;
782  break;
783  case TargetOpcode::G_STORE:
784  // Check if that store is fed by fp instructions.
785  if (OpRegBankIdx[0] == PMI_FirstGPR) {
786  Register VReg = MI.getOperand(0).getReg();
787  if (!VReg)
788  break;
789  MachineInstr *DefMI = MRI.getVRegDef(VReg);
790  if (onlyDefinesFP(*DefMI, MRI, TRI))
791  OpRegBankIdx[0] = PMI_FirstFPR;
792  break;
793  }
794  break;
795  case TargetOpcode::G_SELECT: {
796  // If the destination is FPR, preserve that.
797  if (OpRegBankIdx[0] != PMI_FirstGPR)
798  break;
799 
800  // If we're taking in vectors, we have no choice but to put everything on
801  // FPRs, except for the condition. The condition must always be on a GPR.
802  LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
803  if (SrcTy.isVector()) {
805  break;
806  }
807 
808  // Try to minimize the number of copies. If we have more floating point
809  // constrained values than not, then we'll put everything on FPR. Otherwise,
810  // everything has to be on GPR.
811  unsigned NumFP = 0;
812 
813  // Check if the uses of the result always produce floating point values.
814  //
815  // For example:
816  //
817  // %z = G_SELECT %cond %x %y
818  // fpr = G_FOO %z ...
819  if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
820  [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))
821  ++NumFP;
822 
823  // Check if the defs of the source values always produce floating point
824  // values.
825  //
826  // For example:
827  //
828  // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
829  // %z = G_SELECT %cond %x %y
830  //
831  // Also check whether or not the sources have already been decided to be
832  // FPR. Keep track of this.
833  //
834  // This doesn't check the condition, since it's just whatever is in NZCV.
835  // This isn't passed explicitly in a register to fcsel/csel.
836  for (unsigned Idx = 2; Idx < 4; ++Idx) {
837  Register VReg = MI.getOperand(Idx).getReg();
838  MachineInstr *DefMI = MRI.getVRegDef(VReg);
839  if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank ||
840  onlyDefinesFP(*DefMI, MRI, TRI))
841  ++NumFP;
842  }
843 
844  // If we have more FP constraints than not, then move everything over to
845  // FPR.
846  if (NumFP >= 2)
848 
849  break;
850  }
851  case TargetOpcode::G_UNMERGE_VALUES: {
852  // If the first operand belongs to a FPR register bank, then make sure that
853  // we preserve that.
854  if (OpRegBankIdx[0] != PMI_FirstGPR)
855  break;
856 
857  LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
858  // UNMERGE into scalars from a vector should always use FPR.
859  // Likewise if any of the uses are FP instructions.
860  if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
861  any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
862  [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
863  // Set the register bank of every operand to FPR.
864  for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
865  Idx < NumOperands; ++Idx)
866  OpRegBankIdx[Idx] = PMI_FirstFPR;
867  }
868  break;
869  }
870  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
871  // Destination and source need to be FPRs.
872  OpRegBankIdx[0] = PMI_FirstFPR;
873  OpRegBankIdx[1] = PMI_FirstFPR;
874 
875  // Index needs to be a GPR.
876  OpRegBankIdx[2] = PMI_FirstGPR;
877  break;
878  case TargetOpcode::G_INSERT_VECTOR_ELT:
879  OpRegBankIdx[0] = PMI_FirstFPR;
880  OpRegBankIdx[1] = PMI_FirstFPR;
881 
882  // The element may be either a GPR or FPR. Preserve that behaviour.
883  if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
884  OpRegBankIdx[2] = PMI_FirstFPR;
885  else
886  OpRegBankIdx[2] = PMI_FirstGPR;
887 
888  // Index needs to be a GPR.
889  OpRegBankIdx[3] = PMI_FirstGPR;
890  break;
891  case TargetOpcode::G_EXTRACT: {
892  // For s128 sources we have to use fpr unless we know otherwise.
893  auto Src = MI.getOperand(1).getReg();
894  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
895  if (SrcTy.getSizeInBits() != 128)
896  break;
897  auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
898  ? PMI_FirstGPR
899  : PMI_FirstFPR;
900  OpRegBankIdx[0] = Idx;
901  OpRegBankIdx[1] = Idx;
902  break;
903  }
904  case TargetOpcode::G_BUILD_VECTOR: {
905  // If the first source operand belongs to a FPR register bank, then make
906  // sure that we preserve that.
907  if (OpRegBankIdx[1] != PMI_FirstGPR)
908  break;
909  Register VReg = MI.getOperand(1).getReg();
910  if (!VReg)
911  break;
912 
913  // Get the instruction that defined the source operand reg, and check if
914  // it's a floating point operation. Or, if it's a type like s16 which
915  // doesn't have a exact size gpr register class. The exception is if the
916  // build_vector has all constant operands, which may be better to leave as
917  // gpr without copies, so it can be matched in imported patterns.
918  MachineInstr *DefMI = MRI.getVRegDef(VReg);
919  unsigned DefOpc = DefMI->getOpcode();
920  const LLT SrcTy = MRI.getType(VReg);
921  if (all_of(MI.operands(), [&](const MachineOperand &Op) {
922  return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
923  TargetOpcode::G_CONSTANT;
924  }))
925  break;
927  SrcTy.getSizeInBits() < 32 ||
928  getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank) {
929  // Have a floating point op.
930  // Make sure every operand gets mapped to a FPR register class.
931  unsigned NumOperands = MI.getNumOperands();
932  for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
933  OpRegBankIdx[Idx] = PMI_FirstFPR;
934  }
935  break;
936  }
937  case TargetOpcode::G_VECREDUCE_FADD:
938  case TargetOpcode::G_VECREDUCE_FMUL:
939  case TargetOpcode::G_VECREDUCE_FMAX:
940  case TargetOpcode::G_VECREDUCE_FMIN:
941  case TargetOpcode::G_VECREDUCE_ADD:
942  case TargetOpcode::G_VECREDUCE_MUL:
943  case TargetOpcode::G_VECREDUCE_AND:
944  case TargetOpcode::G_VECREDUCE_OR:
945  case TargetOpcode::G_VECREDUCE_XOR:
946  case TargetOpcode::G_VECREDUCE_SMAX:
947  case TargetOpcode::G_VECREDUCE_SMIN:
948  case TargetOpcode::G_VECREDUCE_UMAX:
949  case TargetOpcode::G_VECREDUCE_UMIN:
950  // Reductions produce a scalar value from a vector, the scalar should be on
951  // FPR bank.
952  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
953  break;
954  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
955  case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
956  // These reductions also take a scalar accumulator input.
957  // Assign them FPR for now.
958  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR, PMI_FirstFPR};
959  break;
960  case TargetOpcode::G_INTRINSIC: {
961  // Check if we know that the intrinsic has any constraints on its register
962  // banks. If it does, then update the mapping accordingly.
963  unsigned ID = MI.getIntrinsicID();
964  unsigned Idx = 0;
965  if (!isFPIntrinsic(ID))
966  break;
967  for (const auto &Op : MI.explicit_operands()) {
968  if (Op.isReg())
969  OpRegBankIdx[Idx] = PMI_FirstFPR;
970  ++Idx;
971  }
972  break;
973  }
974  case TargetOpcode::G_LROUND:
975  case TargetOpcode::G_LLROUND: {
976  // Source is always floating point and destination is always integer.
977  OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
978  break;
979  }
980  }
981 
982  // Finally construct the computed mapping.
983  SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
984  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
985  if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
986  auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
987  if (!Mapping->isValid())
989 
990  OpdsMapping[Idx] = Mapping;
991  }
992  }
993 
995  getOperandsMapping(OpdsMapping), NumOperands);
996 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AArch64GenRegisterBankInfo::getFPExtMapping
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
CHECK_VALUEMAP_FPEXT
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:71
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
AArch64RegisterBankInfo.h
llvm::RegisterBankInfo::getInstrMappingImpl
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
Definition: RegisterBankInfo.cpp:162
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::RegisterBankInfo::verify
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
Definition: RegisterBankInfo.cpp:69
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:432
ErrorHandling.h
CHECK_VALUEMAP_CROSSREGCPY
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
RegisterBankInfo.h
llvm::RegisterBankInfo::applyDefaultMapping
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
Definition: RegisterBankInfo.cpp:438
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:543
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
isAtomic
static bool isAtomic(Instruction *I)
Definition: ThreadSanitizer.cpp:530
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
GenericMachineInstrs.h
FPR
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
Definition: PPCISelLowering.cpp:3822
isPreISelGenericFloatingPointOpcode
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Definition: AArch64RegisterBankInfo.cpp:403
STLExtras.h
llvm::RegisterBankInfo::InstructionMapping::isValid
bool isValid() const
Check whether this object is valid.
Definition: RegisterBankInfo.h:254
llvm::AArch64GenRegisterBankInfo::PMI_GPR64
@ PMI_GPR64
Definition: AArch64RegisterBankInfo.h:36
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
MachineRegisterInfo.h
llvm::AArch64GenRegisterBankInfo::PMI_LastGPR
@ PMI_LastGPR
Definition: AArch64RegisterBankInfo.h:39
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1551
llvm::AArch64RegisterBankInfo::copyCost
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Definition: AArch64RegisterBankInfo.cpp:214
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::AArch64GenRegisterBankInfo::PMI_FirstGPR
@ PMI_FirstGPR
Definition: AArch64RegisterBankInfo.h:38
AArch64InstrInfo.h
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::AArch64GenRegisterBankInfo::PMI_FPR512
@ PMI_FPR512
Definition: AArch64RegisterBankInfo.h:34
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
Utils.h
llvm::AArch64GenRegisterBankInfo::PMI_FPR32
@ PMI_FPR32
Definition: AArch64RegisterBankInfo.h:30
llvm::AArch64GenRegisterBankInfo::Shift64Imm
@ Shift64Imm
Definition: AArch64RegisterBankInfo.h:61
TargetOpcodes.h
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::RegisterBank::getID
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
llvm::AArch64GenRegisterBankInfo::checkPartialMappingIdx
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
Definition: AArch64RegisterBankInfo.cpp:284
llvm::AArch64GenRegisterBankInfo::PMI_None
@ PMI_None
Definition: AArch64RegisterBankInfo.h:28
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::RegisterBankInfo::getInstrAlternativeMappings
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
Definition: RegisterBankInfo.cpp:433
llvm::RegisterBankInfo::getSizeInBits
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
Definition: RegisterBankInfo.cpp:493
llvm::AArch64GenRegisterBankInfo::PartMappings
static RegisterBankInfo::PartialMapping PartMappings[]
Definition: AArch64RegisterBankInfo.h:45
CHECK_VALUEMAP
#define CHECK_VALUEMAP(RBName, Size)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::AArch64GenRegisterBankInfo::PartialMappingIdx
PartialMappingIdx
Definition: AArch64RegisterBankInfo.h:27
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RegisterBankInfo::InstructionMapping
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Definition: RegisterBankInfo.h:189
llvm::AArch64GenRegisterBankInfo::getValueMapping
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
llvm::AArch64GenRegisterBankInfo::PMI_FPR64
@ PMI_FPR64
Definition: AArch64RegisterBankInfo.h:31
llvm::AArch64GenRegisterBankInfo::PMI_GPR32
@ PMI_GPR32
Definition: AArch64RegisterBankInfo.h:35
llvm::RegisterBankInfo::DefaultMappingID
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
Definition: RegisterBankInfo.h:652
llvm::RegisterBankInfo::getOperandsMapping
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
Definition: RegisterBankInfo.cpp:332
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:123
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::RegisterBank::covers
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
Definition: RegisterBank.cpp:61
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::RegisterBankInfo::getInstructionMapping
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Definition: RegisterBankInfo.h:526
llvm::AArch64GenRegisterBankInfo::PMI_GPR128
@ PMI_GPR128
Definition: AArch64RegisterBankInfo.h:37
isFPIntrinsic
static bool isFPIntrinsic(unsigned ID)
Definition: AArch64RegisterBankInfo.cpp:479
llvm::AArch64RegisterBankInfo::getRegBankFromRegClass
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Definition: AArch64RegisterBankInfo.cpp:236
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1558
CHECK_PARTIALMAP
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
llvm::AArch64GenRegisterBankInfo::PMI_FPR256
@ PMI_FPR256
Definition: AArch64RegisterBankInfo.h:33
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
TargetSubtargetInfo.h
llvm::AArch64RegisterBankInfo::getInstrMapping
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Definition: AArch64RegisterBankInfo.cpp:564
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:60
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64GenRegisterBankInfo::getCopyMapping
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:90
llvm::AArch64GenRegisterBankInfo::PMI_FPR16
@ PMI_FPR16
Definition: AArch64RegisterBankInfo.h:29
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::AArch64GenRegisterBankInfo::ValMappings
static RegisterBankInfo::ValueMapping ValMappings[]
Definition: AArch64RegisterBankInfo.h:46
llvm::RegisterBank::getSize
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
llvm::AArch64GenRegisterBankInfo::PMI_FirstFPR
@ PMI_FirstFPR
Definition: AArch64RegisterBankInfo.h:40
CHECK_VALUEMAP_3OPS
#define CHECK_VALUEMAP_3OPS(RBName, Size)
llvm::RegisterBankInfo::getInvalidInstructionMapping
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
Definition: RegisterBankInfo.h:534
llvm::AArch64GenRegisterBankInfo
Definition: AArch64RegisterBankInfo.h:25
llvm::RegisterBankInfo::copyCost
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Definition: RegisterBankInfo.h:614
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
RegisterBank.h
llvm::AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::AArch64GenRegisterBankInfo::PMI_FPR128
@ PMI_FPR128
Definition: AArch64RegisterBankInfo.h:32
MachineOperand.h
MachineFunction.h
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
TargetRegisterInfo.h
llvm::AArch64GenRegisterBankInfo::PMI_LastFPR
@ PMI_LastFPR
Definition: AArch64RegisterBankInfo.h:41
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
Definition: AArch64RegisterBankInfo.cpp:43
llvm::LLT
Definition: LowLevelTypeImpl.h:40