32#include "llvm/IR/IntrinsicsAArch64.h"
38#define GET_TARGET_REGBANK_IMPL
39#include "AArch64GenRegisterBank.inc"
42#include "AArch64GenRegisterBankInfo.def"
50 static auto InitializeRegisterBankOnce = [&]() {
59 assert(&AArch64::GPRRegBank == &RBGPR &&
60 "The order in RegBanks is messed up");
64 assert(&AArch64::FPRRegBank == &RBFPR &&
65 "The order in RegBanks is messed up");
69 assert(&AArch64::CCRegBank == &RBCCR &&
70 "The order in RegBanks is messed up");
75 "Subclass not added?");
77 "GPRs should hold up to 128-bit");
82 "Subclass not added?");
84 "Subclass not added?");
86 "FPRs should hold up to 512-bit via QQQQ sequence");
91 "CCR should hold up to 32-bit");
97 "PartialMappingIdx's are incorrectly ordered");
101 "PartialMappingIdx's are incorrectly ordered");
104#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
107 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
108 #Idx " is incorrectly initialized"); \
122#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
124 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
125 PartialMappingIdx::PMI_First##RBName, Size, \
127 #RBName #Size " " #Offset " is incorrectly initialized"); \
130#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
144#define CHECK_VALUEMAP_3OPS(RBName, Size) \
146 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
147 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
148 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
160#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
162 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
163 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
164 (void)PartialMapDstIdx; \
165 (void)PartialMapSrcIdx; \
166 const ValueMapping *Map = getCopyMapping(AArch64::RBNameDst##RegBankID, \
167 AArch64::RBNameSrc##RegBankID, \
168 TypeSize::getFixed(Size)); \
170 assert(Map[0].BreakDown == \
171 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
172 Map[0].NumBreakDowns == 1 && \
173 #RBNameDst #Size " Dst is incorrectly initialized"); \
174 assert(Map[1].BreakDown == \
175 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
176 Map[1].NumBreakDowns == 1 && \
177 #RBNameSrc #Size " Src is incorrectly initialized"); \
190#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
192 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
193 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
194 (void)PartialMapDstIdx; \
195 (void)PartialMapSrcIdx; \
196 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
198 assert(Map[0].BreakDown == \
199 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
200 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
201 " Dst is incorrectly initialized"); \
202 assert(Map[1].BreakDown == \
203 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
204 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
205 " Src is incorrectly initialized"); \
217 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
231 if (&
A == &AArch64::GPRRegBank && &
B == &AArch64::FPRRegBank)
234 if (&
A == &AArch64::FPRRegBank && &
B == &AArch64::GPRRegBank)
244 switch (RC.
getID()) {
245 case AArch64::FPR8RegClassID:
246 case AArch64::FPR16RegClassID:
247 case AArch64::FPR16_loRegClassID:
248 case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
249 case AArch64::FPR32RegClassID:
250 case AArch64::FPR64RegClassID:
251 case AArch64::FPR128RegClassID:
252 case AArch64::FPR64_loRegClassID:
253 case AArch64::FPR128_loRegClassID:
254 case AArch64::FPR128_0to7RegClassID:
255 case AArch64::DDRegClassID:
256 case AArch64::DDDRegClassID:
257 case AArch64::DDDDRegClassID:
258 case AArch64::QQRegClassID:
259 case AArch64::QQQRegClassID:
260 case AArch64::QQQQRegClassID:
261 case AArch64::ZPRRegClassID:
262 case AArch64::ZPR_3bRegClassID:
264 case AArch64::GPR32commonRegClassID:
265 case AArch64::GPR32RegClassID:
266 case AArch64::GPR32spRegClassID:
267 case AArch64::GPR32sponlyRegClassID:
268 case AArch64::GPR32argRegClassID:
269 case AArch64::GPR32allRegClassID:
270 case AArch64::GPR64commonRegClassID:
271 case AArch64::GPR64RegClassID:
272 case AArch64::GPR64spRegClassID:
273 case AArch64::GPR64sponlyRegClassID:
274 case AArch64::GPR64argRegClassID:
275 case AArch64::GPR64allRegClassID:
276 case AArch64::GPR64noipRegClassID:
277 case AArch64::GPR64common_and_GPR64noipRegClassID:
278 case AArch64::GPR64noip_and_tcGPR64RegClassID:
279 case AArch64::tcGPR64RegClassID:
280 case AArch64::tcGPRx16x17RegClassID:
281 case AArch64::tcGPRx17RegClassID:
282 case AArch64::tcGPRnotx16RegClassID:
283 case AArch64::WSeqPairsClassRegClassID:
284 case AArch64::XSeqPairsClassRegClassID:
285 case AArch64::MatrixIndexGPR32_8_11RegClassID:
286 case AArch64::MatrixIndexGPR32_12_15RegClassID:
287 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID:
288 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
290 case AArch64::CCRRegClassID:
305 switch (
MI.getOpcode()) {
306 case TargetOpcode::G_OR: {
315 if (
MI.getNumOperands() != 3)
329 case TargetOpcode::G_BITCAST: {
336 if (
MI.getNumOperands() != 2)
351 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
358 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
369 case TargetOpcode::G_LOAD: {
376 if (
MI.getNumOperands() != 2)
405void AArch64RegisterBankInfo::applyMappingImpl(
410 switch (
MI.getOpcode()) {
411 case TargetOpcode::G_OR:
412 case TargetOpcode::G_BITCAST:
413 case TargetOpcode::G_LOAD:
415 assert((OpdMapper.getInstrMapping().getID() >= 1 &&
416 OpdMapper.getInstrMapping().getID() <= 4) &&
417 "Don't know how to handle that ID");
419 case TargetOpcode::G_INSERT_VECTOR_ELT: {
423 MRI.setRegBank(Ext.getReg(0),
getRegBank(AArch64::GPRRegBankID));
424 MI.getOperand(2).setReg(Ext.getReg(0));
433AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
435 const unsigned Opc =
MI.getOpcode();
439 unsigned NumOperands =
MI.getNumOperands();
440 assert(NumOperands <= 3 &&
441 "This code is for instructions with 3 or less operands");
443 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
458 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
459 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
464 "Operand has incompatible size");
467 assert(IsFPR == OpIsFPR &&
"Operand has incompatible type");
482 case Intrinsic::aarch64_neon_uaddlv:
483 case Intrinsic::aarch64_neon_uaddv:
484 case Intrinsic::aarch64_neon_saddv:
485 case Intrinsic::aarch64_neon_umaxv:
486 case Intrinsic::aarch64_neon_smaxv:
487 case Intrinsic::aarch64_neon_uminv:
488 case Intrinsic::aarch64_neon_sminv:
489 case Intrinsic::aarch64_neon_faddv:
490 case Intrinsic::aarch64_neon_fmaxv:
491 case Intrinsic::aarch64_neon_fminv:
492 case Intrinsic::aarch64_neon_fmaxnmv:
493 case Intrinsic::aarch64_neon_fminnmv:
495 case Intrinsic::aarch64_neon_saddlv: {
496 const LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
503bool AArch64RegisterBankInfo::isPHIWithFPContraints(
506 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
509 return any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
511 if (onlyUsesFP(UseMI, MRI, TRI, Depth + 1))
513 return isPHIWithFPContraints(UseMI, MRI, TRI, Depth + 1);
517bool AArch64RegisterBankInfo::hasFPConstraints(
const MachineInstr &
MI,
520 unsigned Depth)
const {
521 unsigned Op =
MI.getOpcode();
531 if (
Op != TargetOpcode::COPY && !
MI.isPHI() &&
537 if (RB == &AArch64::FPRRegBank)
539 if (RB == &AArch64::GPRRegBank)
546 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
551 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
558 unsigned Depth)
const {
559 switch (
MI.getOpcode()) {
560 case TargetOpcode::G_FPTOSI:
561 case TargetOpcode::G_FPTOUI:
562 case TargetOpcode::G_FCMP:
563 case TargetOpcode::G_LROUND:
564 case TargetOpcode::G_LLROUND:
572bool AArch64RegisterBankInfo::onlyDefinesFP(
const MachineInstr &
MI,
575 unsigned Depth)
const {
576 switch (
MI.getOpcode()) {
578 case TargetOpcode::G_SITOFP:
579 case TargetOpcode::G_UITOFP:
580 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
581 case TargetOpcode::G_INSERT_VECTOR_ELT:
582 case TargetOpcode::G_BUILD_VECTOR:
583 case TargetOpcode::G_BUILD_VECTOR_TRUNC:
585 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
587 case Intrinsic::aarch64_neon_ld1x2:
588 case Intrinsic::aarch64_neon_ld1x3:
589 case Intrinsic::aarch64_neon_ld1x4:
590 case Intrinsic::aarch64_neon_ld2:
591 case Intrinsic::aarch64_neon_ld2lane:
592 case Intrinsic::aarch64_neon_ld2r:
593 case Intrinsic::aarch64_neon_ld3:
594 case Intrinsic::aarch64_neon_ld3lane:
595 case Intrinsic::aarch64_neon_ld3r:
596 case Intrinsic::aarch64_neon_ld4:
597 case Intrinsic::aarch64_neon_ld4lane:
598 case Intrinsic::aarch64_neon_ld4r:
610bool AArch64RegisterBankInfo::isLoadFromFPType(
const MachineInstr &
MI)
const {
612 auto *
MemOp = cast<GMemOperation>(&
MI);
613 const Value *LdVal =
MemOp->getMMO().getValue();
617 Type *EltTy =
nullptr;
618 if (
const GlobalValue *GV = dyn_cast<GlobalValue>(LdVal)) {
619 EltTy = GV->getValueType();
622 while (
StructType *StructEltTy = dyn_cast<StructType>(EltTy)) {
623 if (StructEltTy->getNumElements() == 0)
625 EltTy = StructEltTy->getTypeAtIndex(0U);
628 if (isa<ArrayType>(EltTy))
633 for (
const auto *LdUser : LdVal->
users()) {
634 if (isa<LoadInst>(LdUser)) {
635 EltTy = LdUser->getType();
638 if (isa<StoreInst>(LdUser) && LdUser->getOperand(1) == LdVal) {
639 EltTy = LdUser->getOperand(0)->getType();
649 const unsigned Opc =
MI.getOpcode();
654 Opc == TargetOpcode::G_PHI) {
669 case TargetOpcode::G_ADD:
670 case TargetOpcode::G_SUB:
671 case TargetOpcode::G_PTR_ADD:
672 case TargetOpcode::G_MUL:
673 case TargetOpcode::G_SDIV:
674 case TargetOpcode::G_UDIV:
676 case TargetOpcode::G_AND:
677 case TargetOpcode::G_OR:
678 case TargetOpcode::G_XOR:
680 case TargetOpcode::G_FADD:
681 case TargetOpcode::G_FSUB:
682 case TargetOpcode::G_FMUL:
683 case TargetOpcode::G_FDIV:
684 case TargetOpcode::G_FMAXIMUM:
685 case TargetOpcode::G_FMINIMUM:
686 return getSameKindOfOperandsMapping(
MI);
687 case TargetOpcode::G_FPEXT: {
688 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
689 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
696 case TargetOpcode::G_SHL:
697 case TargetOpcode::G_LSHR:
698 case TargetOpcode::G_ASHR: {
699 LLT ShiftAmtTy =
MRI.getType(
MI.getOperand(2).getReg());
700 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
704 return getSameKindOfOperandsMapping(
MI);
706 case TargetOpcode::COPY: {
710 if ((DstReg.
isPhysical() || !
MRI.getType(DstReg).isValid()) ||
720 assert(DstRB && SrcRB &&
"Both RegBank were nullptr");
731 case TargetOpcode::G_BITCAST: {
732 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
733 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
738 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
740 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
745 Opc == TargetOpcode::G_BITCAST ? 2 : 1);
751 unsigned NumOperands =
MI.getNumOperands();
757 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
758 auto &MO =
MI.getOperand(
Idx);
759 if (!MO.isReg() || !MO.getReg())
762 LLT Ty =
MRI.getType(MO.getReg());
783 case AArch64::G_DUP: {
784 Register ScalarReg =
MI.getOperand(1).getReg();
785 LLT ScalarTy =
MRI.getType(ScalarReg);
786 auto ScalarDef =
MRI.getVRegDef(ScalarReg);
788 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)
793 onlyDefinesFP(*ScalarDef,
MRI,
TRI)))
799 case TargetOpcode::G_TRUNC: {
800 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
805 case TargetOpcode::G_SITOFP:
806 case TargetOpcode::G_UITOFP: {
807 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
818 case TargetOpcode::G_FPTOSI:
819 case TargetOpcode::G_FPTOUI:
820 case TargetOpcode::G_INTRINSIC_LRINT:
821 case TargetOpcode::G_INTRINSIC_LLRINT:
822 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
826 case TargetOpcode::G_FCMP: {
831 OpRegBankIdx = {Idx0,
835 case TargetOpcode::G_BITCAST:
837 if (OpRegBankIdx[0] != OpRegBankIdx[1])
843 case TargetOpcode::G_LOAD: {
855 if (cast<GLoad>(
MI).isAtomic()) {
862 if (isLoadFromFPType(
MI)) {
870 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
881 if (isPHIWithFPContraints(UseMI, MRI, TRI))
884 return onlyUsesFP(UseMI, MRI, TRI) ||
885 onlyDefinesFP(UseMI, MRI, TRI);
890 case TargetOpcode::G_STORE:
902 case TargetOpcode::G_INDEXED_STORE:
913 case TargetOpcode::G_INDEXED_SEXTLOAD:
914 case TargetOpcode::G_INDEXED_ZEXTLOAD:
918 case TargetOpcode::G_INDEXED_LOAD: {
919 if (isLoadFromFPType(
MI))
923 case TargetOpcode::G_SELECT: {
930 LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
947 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
979 case TargetOpcode::G_UNMERGE_VALUES: {
985 LLT SrcTy =
MRI.getType(
MI.getOperand(
MI.getNumOperands()-1).getReg());
989 any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
992 for (
unsigned Idx = 0, NumOperands =
MI.getNumOperands();
998 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1006 case TargetOpcode::G_INSERT_VECTOR_ELT:
1016 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
1025 case TargetOpcode::G_EXTRACT: {
1027 auto Src =
MI.getOperand(1).getReg();
1028 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
1031 auto Idx =
MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
1034 OpRegBankIdx[0] =
Idx;
1035 OpRegBankIdx[1] =
Idx;
1038 case TargetOpcode::G_BUILD_VECTOR: {
1054 const LLT SrcTy =
MRI.getType(VReg);
1056 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
1057 TargetOpcode::G_CONSTANT;
1065 unsigned NumOperands =
MI.getNumOperands();
1066 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx)
1071 case TargetOpcode::G_VECREDUCE_FADD:
1072 case TargetOpcode::G_VECREDUCE_FMUL:
1073 case TargetOpcode::G_VECREDUCE_FMAX:
1074 case TargetOpcode::G_VECREDUCE_FMIN:
1075 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1076 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1077 case TargetOpcode::G_VECREDUCE_ADD:
1078 case TargetOpcode::G_VECREDUCE_MUL:
1079 case TargetOpcode::G_VECREDUCE_AND:
1080 case TargetOpcode::G_VECREDUCE_OR:
1081 case TargetOpcode::G_VECREDUCE_XOR:
1082 case TargetOpcode::G_VECREDUCE_SMAX:
1083 case TargetOpcode::G_VECREDUCE_SMIN:
1084 case TargetOpcode::G_VECREDUCE_UMAX:
1085 case TargetOpcode::G_VECREDUCE_UMIN:
1090 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1091 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
1096 case TargetOpcode::G_INTRINSIC:
1097 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1102 for (
const auto &
Op :
MI.defs()) {
1108 Idx +=
MI.getNumExplicitDefs();
1111 for (
const auto &
Op :
MI.explicit_uses()) {
1118 case TargetOpcode::G_LROUND:
1119 case TargetOpcode::G_LLROUND: {
1128 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
1129 if (
MI.getOperand(
Idx).isReg() &&
MI.getOperand(
Idx).getReg()) {
1130 LLT Ty =
MRI.getType(
MI.getOperand(
Idx).getReg());
1135 if (!Mapping->isValid())
1138 OpdsMapping[
Idx] = Mapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static unsigned getIntrinsicID(const SDNode *N)
#define CHECK_VALUEMAP(RBName, Size)
static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)
#define CHECK_VALUEMAP_3OPS(RBName, Size)
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
This file declares the targeting of the RegisterBankInfo class for AArch64.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, TypeSize Size)
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, TypeSize Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
static const RegisterBankInfo::PartialMapping PartMappings[]
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, TypeSize Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
static const RegisterBankInfo::ValueMapping ValMappings[]
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
This class represents an Operation in the Expression.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Class to represent struct types.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
Type * getArrayElementType() const
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
LLVM Value Representation.
iterator_range< user_iterator > users()
constexpr ScalarTy getFixedValue() const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
The llvm::once_flag structure.