LLVM  10.0.0svn
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 
16 #include "X86FrameLowering.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86SelectionDAGInfo.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/CallingConv.h"
29 #include <climits>
30 #include <memory>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "X86GenSubtargetInfo.inc"
34 
35 namespace llvm {
36 
37 class GlobalValue;
38 
39 /// The X86 backend supports a number of different styles of PIC.
40 ///
41 namespace PICStyles {
42 
43 enum Style {
44  StubPIC, // Used on i386-darwin in pic mode.
45  GOT, // Used on 32 bit elf on when in pic mode.
46  RIPRel, // Used on X86-64 when in pic mode.
47  None // Set when not in pic mode.
48 };
49 
50 } // end namespace PICStyles
51 
52 class X86Subtarget final : public X86GenSubtargetInfo {
53 public:
54  // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
55  // are not a good idea. We should be migrating away from these.
62  IntelTRM
63  };
64 
65 protected:
66  enum X86SSEEnum {
67  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
68  };
69 
70  enum X863DNowEnum {
71  NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
72  };
73 
74  /// X86 processor family: Intel Atom, and others
75  X86ProcFamilyEnum X86ProcFamily = Others;
76 
77  /// Which PIC style to use
79 
80  const TargetMachine &TM;
81 
82  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
83  X86SSEEnum X86SSELevel = NoSSE;
84 
85  /// MMX, 3DNow, 3DNow Athlon, or none supported.
86  X863DNowEnum X863DNowLevel = NoThreeDNow;
87 
88  /// True if the processor supports X87 instructions.
89  bool HasX87 = false;
90 
91  /// True if the processor supports CMPXCHG8B.
92  bool HasCmpxchg8b = false;
93 
94  /// True if this processor has NOPL instruction
95  /// (generally pentium pro+).
96  bool HasNOPL = false;
97 
98  /// True if this processor has conditional move instructions
99  /// (generally pentium pro+).
100  bool HasCMov = false;
101 
102  /// True if the processor supports X86-64 instructions.
103  bool HasX86_64 = false;
104 
105  /// True if the processor supports POPCNT.
106  bool HasPOPCNT = false;
107 
108  /// True if the processor supports SSE4A instructions.
109  bool HasSSE4A = false;
110 
111  /// Target has AES instructions
112  bool HasAES = false;
113  bool HasVAES = false;
114 
115  /// Target has FXSAVE/FXRESTOR instructions
116  bool HasFXSR = false;
117 
118  /// Target has XSAVE instructions
119  bool HasXSAVE = false;
120 
121  /// Target has XSAVEOPT instructions
122  bool HasXSAVEOPT = false;
123 
124  /// Target has XSAVEC instructions
125  bool HasXSAVEC = false;
126 
127  /// Target has XSAVES instructions
128  bool HasXSAVES = false;
129 
130  /// Target has carry-less multiplication
131  bool HasPCLMUL = false;
132  bool HasVPCLMULQDQ = false;
133 
134  /// Target has Galois Field Arithmetic instructions
135  bool HasGFNI = false;
136 
137  /// Target has 3-operand fused multiply-add
138  bool HasFMA = false;
139 
140  /// Target has 4-operand fused multiply-add
141  bool HasFMA4 = false;
142 
143  /// Target has XOP instructions
144  bool HasXOP = false;
145 
146  /// Target has TBM instructions.
147  bool HasTBM = false;
148 
149  /// Target has LWP instructions
150  bool HasLWP = false;
151 
152  /// True if the processor has the MOVBE instruction.
153  bool HasMOVBE = false;
154 
155  /// True if the processor has the RDRAND instruction.
156  bool HasRDRAND = false;
157 
158  /// Processor has 16-bit floating point conversion instructions.
159  bool HasF16C = false;
160 
161  /// Processor has FS/GS base insturctions.
162  bool HasFSGSBase = false;
163 
164  /// Processor has LZCNT instruction.
165  bool HasLZCNT = false;
166 
167  /// Processor has BMI1 instructions.
168  bool HasBMI = false;
169 
170  /// Processor has BMI2 instructions.
171  bool HasBMI2 = false;
172 
173  /// Processor has VBMI instructions.
174  bool HasVBMI = false;
175 
176  /// Processor has VBMI2 instructions.
177  bool HasVBMI2 = false;
178 
179  /// Processor has Integer Fused Multiply Add
180  bool HasIFMA = false;
181 
182  /// Processor has RTM instructions.
183  bool HasRTM = false;
184 
185  /// Processor has ADX instructions.
186  bool HasADX = false;
187 
188  /// Processor has SHA instructions.
189  bool HasSHA = false;
190 
191  /// Processor has PRFCHW instructions.
192  bool HasPRFCHW = false;
193 
194  /// Processor has RDSEED instructions.
195  bool HasRDSEED = false;
196 
197  /// Processor has LAHF/SAHF instructions.
198  bool HasLAHFSAHF = false;
199 
200  /// Processor has MONITORX/MWAITX instructions.
201  bool HasMWAITX = false;
202 
203  /// Processor has Cache Line Zero instruction
204  bool HasCLZERO = false;
205 
206  /// Processor has Cache Line Demote instruction
207  bool HasCLDEMOTE = false;
208 
209  /// Processor has MOVDIRI instruction (direct store integer).
210  bool HasMOVDIRI = false;
211 
212  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
213  bool HasMOVDIR64B = false;
214 
215  /// Processor has ptwrite instruction.
216  bool HasPTWRITE = false;
217 
218  /// Processor has Prefetch with intent to Write instruction
219  bool HasPREFETCHWT1 = false;
220 
221  /// True if SHLD instructions are slow.
222  bool IsSHLDSlow = false;
223 
224  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
225  // PMULUDQ.
226  bool IsPMULLDSlow = false;
227 
228  /// True if the PMADDWD instruction is slow compared to PMULLD.
229  bool IsPMADDWDSlow = false;
230 
231  /// True if unaligned memory accesses of 16-bytes are slow.
232  bool IsUAMem16Slow = false;
233 
234  /// True if unaligned memory accesses of 32-bytes are slow.
235  bool IsUAMem32Slow = false;
236 
237  /// True if SSE operations can have unaligned memory operands.
238  /// This may require setting a configuration bit in the processor.
239  bool HasSSEUnalignedMem = false;
240 
241  /// True if this processor has the CMPXCHG16B instruction;
242  /// this is true for most x86-64 chips, but not the first AMD chips.
243  bool HasCmpxchg16b = false;
244 
245  /// True if the LEA instruction should be used for adjusting
246  /// the stack pointer. This is an optimization for Intel Atom processors.
247  bool UseLeaForSP = false;
248 
249  /// True if POPCNT instruction has a false dependency on the destination register.
250  bool HasPOPCNTFalseDeps = false;
251 
252  /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
253  bool HasLZCNTFalseDeps = false;
254 
255  /// True if its preferable to combine to a single shuffle using a variable
256  /// mask over multiple fixed shuffles.
257  bool HasFastVariableShuffle = false;
258 
259  /// True if there is no performance penalty to writing only the lower parts
260  /// of a YMM or ZMM register without clearing the upper part.
261  bool HasFastPartialYMMorZMMWrite = false;
262 
263  /// True if there is no performance penalty for writing NOPs with up to
264  /// 11 bytes.
265  bool HasFast11ByteNOP = false;
266 
267  /// True if there is no performance penalty for writing NOPs with up to
268  /// 15 bytes.
269  bool HasFast15ByteNOP = false;
270 
271  /// True if gather is reasonably fast. This is true for Skylake client and
272  /// all AVX-512 CPUs.
273  bool HasFastGather = false;
274 
275  /// True if hardware SQRTSS instruction is at least as fast (latency) as
276  /// RSQRTSS followed by a Newton-Raphson iteration.
277  bool HasFastScalarFSQRT = false;
278 
279  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
280  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
281  bool HasFastVectorFSQRT = false;
282 
283  /// True if 8-bit divisions are significantly faster than
284  /// 32-bit divisions and should be used when possible.
285  bool HasSlowDivide32 = false;
286 
287  /// True if 32-bit divides are significantly faster than
288  /// 64-bit divisions and should be used when possible.
289  bool HasSlowDivide64 = false;
290 
291  /// True if LZCNT instruction is fast.
292  bool HasFastLZCNT = false;
293 
294  /// True if SHLD based rotate is fast.
295  bool HasFastSHLDRotate = false;
296 
297  /// True if the processor supports macrofusion.
298  bool HasMacroFusion = false;
299 
300  /// True if the processor supports branch fusion.
301  bool HasBranchFusion = false;
302 
303  /// True if the processor has enhanced REP MOVSB/STOSB.
304  bool HasERMSB = false;
305 
306  /// True if the short functions should be padded to prevent
307  /// a stall when returning too early.
308  bool PadShortFunctions = false;
309 
310  /// True if two memory operand instructions should use a temporary register
311  /// instead.
312  bool SlowTwoMemOps = false;
313 
314  /// True if the LEA instruction inputs have to be ready at address generation
315  /// (AG) time.
316  bool LEAUsesAG = false;
317 
318  /// True if the LEA instruction with certain arguments is slow
319  bool SlowLEA = false;
320 
321  /// True if the LEA instruction has all three source operands: base, index,
322  /// and offset or if the LEA instruction uses base and index registers where
323  /// the base is EBP, RBP,or R13
324  bool Slow3OpsLEA = false;
325 
326  /// True if INC and DEC instructions are slow when writing to flags
327  bool SlowIncDec = false;
328 
329  /// Processor has AVX-512 PreFetch Instructions
330  bool HasPFI = false;
331 
332  /// Processor has AVX-512 Exponential and Reciprocal Instructions
333  bool HasERI = false;
334 
335  /// Processor has AVX-512 Conflict Detection Instructions
336  bool HasCDI = false;
337 
338  /// Processor has AVX-512 population count Instructions
339  bool HasVPOPCNTDQ = false;
340 
341  /// Processor has AVX-512 Doubleword and Quadword instructions
342  bool HasDQI = false;
343 
344  /// Processor has AVX-512 Byte and Word instructions
345  bool HasBWI = false;
346 
347  /// Processor has AVX-512 Vector Length eXtenstions
348  bool HasVLX = false;
349 
350  /// Processor has PKU extenstions
351  bool HasPKU = false;
352 
353  /// Processor has AVX-512 Vector Neural Network Instructions
354  bool HasVNNI = false;
355 
356  /// Processor has AVX-512 bfloat16 floating-point extensions
357  bool HasBF16 = false;
358 
359  /// Processor supports ENQCMD instructions
360  bool HasENQCMD = false;
361 
362  /// Processor has AVX-512 Bit Algorithms instructions
363  bool HasBITALG = false;
364 
365  /// Processor has AVX-512 vp2intersect instructions
366  bool HasVP2INTERSECT = false;
367 
368  /// Deprecated flag for MPX instructions.
369  bool DeprecatedHasMPX = false;
370 
371  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
372  /// using Shadow Stack
373  bool HasSHSTK = false;
374 
375  /// Processor supports Invalidate Process-Context Identifier
376  bool HasINVPCID = false;
377 
378  /// Processor has Software Guard Extensions
379  bool HasSGX = false;
380 
381  /// Processor supports Flush Cache Line instruction
382  bool HasCLFLUSHOPT = false;
383 
384  /// Processor supports Cache Line Write Back instruction
385  bool HasCLWB = false;
386 
387  /// Processor supports Write Back No Invalidate instruction
388  bool HasWBNOINVD = false;
389 
390  /// Processor support RDPID instruction
391  bool HasRDPID = false;
392 
393  /// Processor supports WaitPKG instructions
394  bool HasWAITPKG = false;
395 
396  /// Processor supports PCONFIG instruction
397  bool HasPCONFIG = false;
398 
399  /// Processor has a single uop BEXTR implementation.
400  bool HasFastBEXTR = false;
401 
402  /// Try harder to combine to horizontal vector ops if they are fast.
403  bool HasFastHorizontalOps = false;
404 
405  /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
406  bool HasFastScalarShiftMasks = false;
407 
408  /// Prefer a left/right vector logical shifts pair over a shift+and pair.
409  bool HasFastVectorShiftMasks = false;
410 
411  /// Use a retpoline thunk rather than indirect calls to block speculative
412  /// execution.
413  bool UseRetpolineIndirectCalls = false;
414 
415  /// Use a retpoline thunk or remove any indirect branch to block speculative
416  /// execution.
417  bool UseRetpolineIndirectBranches = false;
418 
419  /// Deprecated flag, query `UseRetpolineIndirectCalls` and
420  /// `UseRetpolineIndirectBranches` instead.
421  bool DeprecatedUseRetpoline = false;
422 
423  /// When using a retpoline thunk, call an externally provided thunk rather
424  /// than emitting one inside the compiler.
425  bool UseRetpolineExternalThunk = false;
426 
427  /// Use software floating point for code generation.
428  bool UseSoftFloat = false;
429 
430  /// Use alias analysis during code generation.
431  bool UseAA = false;
432 
433  /// The minimum alignment known to hold of the stack frame on
434  /// entry to the function and which must be maintained by every function.
435  unsigned stackAlignment = 4;
436 
437  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
438  ///
439  // FIXME: this is a known good value for Yonah. How about others?
440  unsigned MaxInlineSizeThreshold = 128;
441 
442  /// Indicates target prefers 128 bit instructions.
443  bool Prefer128Bit = false;
444 
445  /// Indicates target prefers 256 bit instructions.
446  bool Prefer256Bit = false;
447 
448  /// Threeway branch is profitable in this subtarget.
449  bool ThreewayBranchProfitable = false;
450 
451  /// What processor and OS we're targeting.
453 
454  /// GlobalISel related APIs.
455  std::unique_ptr<CallLowering> CallLoweringInfo;
456  std::unique_ptr<LegalizerInfo> Legalizer;
457  std::unique_ptr<RegisterBankInfo> RegBankInfo;
458  std::unique_ptr<InstructionSelector> InstSelector;
459 
460 private:
461  /// Override the stack alignment.
462  unsigned StackAlignOverride;
463 
464  /// Preferred vector width from function attribute.
465  unsigned PreferVectorWidthOverride;
466 
467  /// Resolved preferred vector width from function attribute and subtarget
468  /// features.
469  unsigned PreferVectorWidth = UINT32_MAX;
470 
471  /// Required vector width from function attribute.
472  unsigned RequiredVectorWidth;
473 
474  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
475  bool In64BitMode;
476 
477  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
478  bool In32BitMode;
479 
480  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
481  bool In16BitMode;
482 
483  /// Contains the Overhead of gather\scatter instructions
484  int GatherOverhead = 1024;
485  int ScatterOverhead = 1024;
486 
487  X86SelectionDAGInfo TSInfo;
488  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
489  // X86TargetLowering needs.
490  X86InstrInfo InstrInfo;
491  X86TargetLowering TLInfo;
492  X86FrameLowering FrameLowering;
493 
494 public:
495  /// This constructor initializes the data members to match that
496  /// of the specified triple.
497  ///
498  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
499  const X86TargetMachine &TM, unsigned StackAlignOverride,
500  unsigned PreferVectorWidthOverride,
501  unsigned RequiredVectorWidth);
502 
503  const X86TargetLowering *getTargetLowering() const override {
504  return &TLInfo;
505  }
506 
507  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
508 
509  const X86FrameLowering *getFrameLowering() const override {
510  return &FrameLowering;
511  }
512 
513  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
514  return &TSInfo;
515  }
516 
517  const X86RegisterInfo *getRegisterInfo() const override {
518  return &getInstrInfo()->getRegisterInfo();
519  }
520 
521  /// Returns the minimum alignment known to hold of the
522  /// stack frame on entry to the function and which must be maintained by every
523  /// function for this subtarget.
524  unsigned getStackAlignment() const { return stackAlignment; }
525 
526  /// Returns the maximum memset / memcpy size
527  /// that still makes it profitable to inline the call.
528  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
529 
530  /// ParseSubtargetFeatures - Parses features string setting specified
531  /// subtarget options. Definition of function is auto generated by tblgen.
532  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
533 
534  /// Methods used by Global ISel
535  const CallLowering *getCallLowering() const override;
536  InstructionSelector *getInstructionSelector() const override;
537  const LegalizerInfo *getLegalizerInfo() const override;
538  const RegisterBankInfo *getRegBankInfo() const override;
539 
540 private:
541  /// Initialize the full set of dependencies so we can use an initializer
542  /// list for X86Subtarget.
543  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
544  void initSubtargetFeatures(StringRef CPU, StringRef FS);
545 
546 public:
547  /// Is this x86_64? (disregarding specific ABI / programming model)
548  bool is64Bit() const {
549  return In64BitMode;
550  }
551 
552  bool is32Bit() const {
553  return In32BitMode;
554  }
555 
556  bool is16Bit() const {
557  return In16BitMode;
558  }
559 
560  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
561  bool isTarget64BitILP32() const {
562  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
563  TargetTriple.isOSNaCl());
564  }
565 
566  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
567  bool isTarget64BitLP64() const {
568  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
569  !TargetTriple.isOSNaCl());
570  }
571 
572  PICStyles::Style getPICStyle() const { return PICStyle; }
573  void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
574 
575  bool hasX87() const { return HasX87; }
576  bool hasCmpxchg8b() const { return HasCmpxchg8b; }
577  bool hasNOPL() const { return HasNOPL; }
578  // SSE codegen depends on cmovs, and all SSE1+ processors support them.
579  // All 64-bit processors support cmov.
580  bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
581  bool hasSSE1() const { return X86SSELevel >= SSE1; }
582  bool hasSSE2() const { return X86SSELevel >= SSE2; }
583  bool hasSSE3() const { return X86SSELevel >= SSE3; }
584  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
585  bool hasSSE41() const { return X86SSELevel >= SSE41; }
586  bool hasSSE42() const { return X86SSELevel >= SSE42; }
587  bool hasAVX() const { return X86SSELevel >= AVX; }
588  bool hasAVX2() const { return X86SSELevel >= AVX2; }
589  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
590  bool hasInt256() const { return hasAVX2(); }
591  bool hasSSE4A() const { return HasSSE4A; }
592  bool hasMMX() const { return X863DNowLevel >= MMX; }
593  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
594  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
595  bool hasPOPCNT() const { return HasPOPCNT; }
596  bool hasAES() const { return HasAES; }
597  bool hasVAES() const { return HasVAES; }
598  bool hasFXSR() const { return HasFXSR; }
599  bool hasXSAVE() const { return HasXSAVE; }
600  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
601  bool hasXSAVEC() const { return HasXSAVEC; }
602  bool hasXSAVES() const { return HasXSAVES; }
603  bool hasPCLMUL() const { return HasPCLMUL; }
604  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
605  bool hasGFNI() const { return HasGFNI; }
606  // Prefer FMA4 to FMA - its better for commutation/memory folding and
607  // has equal or better performance on all supported targets.
608  bool hasFMA() const { return HasFMA; }
609  bool hasFMA4() const { return HasFMA4; }
610  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
611  bool hasXOP() const { return HasXOP; }
612  bool hasTBM() const { return HasTBM; }
613  bool hasLWP() const { return HasLWP; }
614  bool hasMOVBE() const { return HasMOVBE; }
615  bool hasRDRAND() const { return HasRDRAND; }
616  bool hasF16C() const { return HasF16C; }
617  bool hasFSGSBase() const { return HasFSGSBase; }
618  bool hasLZCNT() const { return HasLZCNT; }
619  bool hasBMI() const { return HasBMI; }
620  bool hasBMI2() const { return HasBMI2; }
621  bool hasVBMI() const { return HasVBMI; }
622  bool hasVBMI2() const { return HasVBMI2; }
623  bool hasIFMA() const { return HasIFMA; }
624  bool hasRTM() const { return HasRTM; }
625  bool hasADX() const { return HasADX; }
626  bool hasSHA() const { return HasSHA; }
627  bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
628  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
629  bool hasSSEPrefetch() const {
630  // We implicitly enable these when we have a write prefix supporting cache
631  // level OR if we have prfchw, but don't already have a read prefetch from
632  // 3dnow.
633  return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
634  }
635  bool hasRDSEED() const { return HasRDSEED; }
636  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
637  bool hasMWAITX() const { return HasMWAITX; }
638  bool hasCLZERO() const { return HasCLZERO; }
639  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
640  bool hasMOVDIRI() const { return HasMOVDIRI; }
641  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
642  bool hasPTWRITE() const { return HasPTWRITE; }
643  bool isSHLDSlow() const { return IsSHLDSlow; }
644  bool isPMULLDSlow() const { return IsPMULLDSlow; }
645  bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
646  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
647  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
648  int getGatherOverhead() const { return GatherOverhead; }
649  int getScatterOverhead() const { return ScatterOverhead; }
650  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
651  bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
652  bool useLeaForSP() const { return UseLeaForSP; }
653  bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
654  bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
655  bool hasFastVariableShuffle() const {
656  return HasFastVariableShuffle;
657  }
659  return HasFastPartialYMMorZMMWrite;
660  }
661  bool hasFastGather() const { return HasFastGather; }
662  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
663  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
664  bool hasFastLZCNT() const { return HasFastLZCNT; }
665  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
666  bool hasFastBEXTR() const { return HasFastBEXTR; }
667  bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
668  bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
669  bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
670  bool hasMacroFusion() const { return HasMacroFusion; }
671  bool hasBranchFusion() const { return HasBranchFusion; }
672  bool hasERMSB() const { return HasERMSB; }
673  bool hasSlowDivide32() const { return HasSlowDivide32; }
674  bool hasSlowDivide64() const { return HasSlowDivide64; }
675  bool padShortFunctions() const { return PadShortFunctions; }
676  bool slowTwoMemOps() const { return SlowTwoMemOps; }
677  bool LEAusesAG() const { return LEAUsesAG; }
678  bool slowLEA() const { return SlowLEA; }
679  bool slow3OpsLEA() const { return Slow3OpsLEA; }
680  bool slowIncDec() const { return SlowIncDec; }
681  bool hasCDI() const { return HasCDI; }
682  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
683  bool hasPFI() const { return HasPFI; }
684  bool hasERI() const { return HasERI; }
685  bool hasDQI() const { return HasDQI; }
686  bool hasBWI() const { return HasBWI; }
687  bool hasVLX() const { return HasVLX; }
688  bool hasPKU() const { return HasPKU; }
689  bool hasVNNI() const { return HasVNNI; }
690  bool hasBF16() const { return HasBF16; }
691  bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
692  bool hasBITALG() const { return HasBITALG; }
693  bool hasSHSTK() const { return HasSHSTK; }
694  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
695  bool hasCLWB() const { return HasCLWB; }
696  bool hasWBNOINVD() const { return HasWBNOINVD; }
697  bool hasRDPID() const { return HasRDPID; }
698  bool hasWAITPKG() const { return HasWAITPKG; }
699  bool hasPCONFIG() const { return HasPCONFIG; }
700  bool hasSGX() const { return HasSGX; }
701  bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
702  bool hasINVPCID() const { return HasINVPCID; }
703  bool hasENQCMD() const { return HasENQCMD; }
704  bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
706  return UseRetpolineIndirectBranches;
707  }
708  bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
709 
710  unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
711  unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
712 
713  // Helper functions to determine when we should allow widening to 512-bit
714  // during codegen.
715  // TODO: Currently we're always allowing widening on CPUs without VLX,
716  // because for many cases we don't have a better option.
717  bool canExtendTo512DQ() const {
718  return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
719  }
720  bool canExtendTo512BW() const {
721  return hasBWI() && canExtendTo512DQ();
722  }
723 
724  // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
725  // disable them in the legalizer.
726  bool useAVX512Regs() const {
727  return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
728  }
729 
730  bool useBWIRegs() const {
731  return hasBWI() && useAVX512Regs();
732  }
733 
734  bool isXRaySupported() const override { return is64Bit(); }
735 
736  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
737 
738  /// TODO: to be removed later and replaced with suitable properties
739  bool isAtom() const { return X86ProcFamily == IntelAtom; }
740  bool isSLM() const { return X86ProcFamily == IntelSLM; }
741  bool isGLM() const {
742  return X86ProcFamily == IntelGLM ||
743  X86ProcFamily == IntelGLP ||
744  X86ProcFamily == IntelTRM;
745  }
746  bool useSoftFloat() const { return UseSoftFloat; }
747  bool useAA() const override { return UseAA; }
748 
749  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
750  /// no-sse2). There isn't any reason to disable it if the target processor
751  /// supports it.
752  bool hasMFence() const { return hasSSE2() || is64Bit(); }
753 
754  const Triple &getTargetTriple() const { return TargetTriple; }
755 
756  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
757  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
758  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
759  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
760  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
761 
762  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
763  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
764  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
765 
766  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
767  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
768  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
769  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
770  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
771  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
772  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
773  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
774  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
775 
776  bool isTargetWindowsMSVC() const {
777  return TargetTriple.isWindowsMSVCEnvironment();
778  }
779 
780  bool isTargetWindowsCoreCLR() const {
781  return TargetTriple.isWindowsCoreCLREnvironment();
782  }
783 
784  bool isTargetWindowsCygwin() const {
785  return TargetTriple.isWindowsCygwinEnvironment();
786  }
787 
788  bool isTargetWindowsGNU() const {
789  return TargetTriple.isWindowsGNUEnvironment();
790  }
791 
792  bool isTargetWindowsItanium() const {
793  return TargetTriple.isWindowsItaniumEnvironment();
794  }
795 
796  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
797 
798  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
799 
800  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
801 
802  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
803 
804  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
805  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
806 
807  bool isPICStyleStubPIC() const {
808  return PICStyle == PICStyles::StubPIC;
809  }
810 
811  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
812 
814  switch (CC) {
815  // On Win64, all these conventions just use the default convention.
816  case CallingConv::C:
817  case CallingConv::Fast:
818  case CallingConv::Swift:
824  return isTargetWin64();
825  // This convention allows using the Win64 convention on other targets.
826  case CallingConv::Win64:
827  return true;
828  // This convention allows using the SysV convention on Windows targets.
830  return false;
831  // Otherwise, who knows what this is.
832  default:
833  return false;
834  }
835  }
836 
837  /// Classify a global variable reference for the current subtarget according
838  /// to how we should reference it in a non-pcrel context.
839  unsigned char classifyLocalReference(const GlobalValue *GV) const;
840 
841  unsigned char classifyGlobalReference(const GlobalValue *GV,
842  const Module &M) const;
843  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
844 
845  /// Classify a global function reference for the current subtarget.
846  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
847  const Module &M) const;
848  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
849 
850  /// Classify a blockaddress reference for the current subtarget according to
851  /// how we should reference it in a non-pcrel context.
852  unsigned char classifyBlockAddressReference() const;
853 
854  /// Return true if the subtarget allows calls to immediate address.
855  bool isLegalToCallImmediateAddr() const;
856 
857  /// If we are using retpolines, we need to expand indirectbr to avoid it
858  /// lowering to an actual indirect jump.
859  bool enableIndirectBrExpand() const override {
860  return useRetpolineIndirectBranches();
861  }
862 
863  /// Enable the MachineScheduler pass for all X86 subtargets.
864  bool enableMachineScheduler() const override { return true; }
865 
866  bool enableEarlyIfConversion() const override;
867 
868  void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
869  &Mutations) const override;
870 
871  AntiDepBreakMode getAntiDepBreakMode() const override {
872  return TargetSubtargetInfo::ANTIDEP_CRITICAL;
873  }
874 
875  bool enableAdvancedRASplitCost() const override { return true; }
876 };
877 
878 } // end namespace llvm
879 
880 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
bool hasBF16() const
Definition: X86Subtarget.h:690
bool hasAVX() const
Definition: X86Subtarget.h:587
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
bool isTargetPS4() const
Definition: X86Subtarget.h:760
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:548
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:91
bool hasSHA() const
Definition: X86Subtarget.h:626
bool hasENQCMD() const
Definition: X86Subtarget.h:703
bool hasSSE41() const
Definition: X86Subtarget.h:585
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:629
bool isOSWindows() const
Definition: X86Subtarget.h:798
bool hasPOPCNT() const
Definition: X86Subtarget.h:595
bool hasAVX2() const
Definition: X86Subtarget.h:588
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasFMA() const
Definition: X86Subtarget.h:608
bool hasWBNOINVD() const
Definition: X86Subtarget.h:696
bool hasSlowDivide64() const
Definition: X86Subtarget.h:674
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
bool hasRDPID() const
Definition: X86Subtarget.h:697
bool hasSGX() const
Definition: X86Subtarget.h:700
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:507
bool hasCLWB() const
Definition: X86Subtarget.h:695
bool slowLEA() const
Definition: X86Subtarget.h:678
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:139
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:509
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:573
bool hasFastVectorShiftMasks() const
Definition: X86Subtarget.h:669
const TargetMachine & TM
Definition: X86Subtarget.h:80
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:864
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:581
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:157
bool hasFastBEXTR() const
Definition: X86Subtarget.h:666
bool hasVBMI2() const
Definition: X86Subtarget.h:622
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructio...
Definition: X86BaseInfo.h:508
bool isPMADDWDSlow() const
Definition: X86Subtarget.h:645
bool hasCLZERO() const
Definition: X86Subtarget.h:638
bool has3DNowA() const
Definition: X86Subtarget.h:594
bool useAVX512Regs() const
Definition: X86Subtarget.h:726
bool isOSFuchsia() const
Definition: Triple.h:505
bool isTargetNaCl64() const
Definition: X86Subtarget.h:772
bool hasVP2INTERSECT() const
Definition: X86Subtarget.h:691
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:561
bool slowTwoMemOps() const
Definition: X86Subtarget.h:676
bool hasPCONFIG() const
Definition: X86Subtarget.h:699
bool hasSHSTK() const
Definition: X86Subtarget.h:693
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:776
bool isTargetMachO() const
Definition: X86Subtarget.h:764
int getGatherOverhead() const
Definition: X86Subtarget.h:648
bool hasXSAVE() const
Definition: X86Subtarget.h:599
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:647
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:807
bool hasVPOPCNTDQ() const
Definition: X86Subtarget.h:682
bool hasPREFETCHWT1() const
Definition: X86Subtarget.h:628
Holds all the information related to register banks.
bool hasLWP() const
Definition: X86Subtarget.h:613
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:805
bool hasFMA4() const
Definition: X86Subtarget.h:609
bool padShortFunctions() const
Definition: X86Subtarget.h:675
bool isTargetSolaris() const
Definition: X86Subtarget.h:759
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:86
bool hasAES() const
Definition: X86Subtarget.h:596
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:567
bool hasPKU() const
Definition: X86Subtarget.h:688
bool is32Bit() const
Definition: X86Subtarget.h:552
bool canExtendTo512DQ() const
Definition: X86Subtarget.h:717
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:143
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:651
bool hasFastLZCNT() const
Definition: X86Subtarget.h:664
bool useRetpolineExternalThunk() const
Definition: X86Subtarget.h:708
bool isOSSolaris() const
Definition: Triple.h:511
bool hasVLX() const
Definition: X86Subtarget.h:687
bool slow3OpsLEA() const
Definition: X86Subtarget.h:679
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:455
bool hasFastSHLDRotate() const
Definition: X86Subtarget.h:665
bool isTargetNaCl() const
Definition: X86Subtarget.h:770
bool hasNOPL() const
Definition: X86Subtarget.h:577
bool isTargetCygMing() const
Definition: X86Subtarget.h:796
bool hasMOVDIRI() const
Definition: X86Subtarget.h:640
bool hasINVPCID() const
Definition: X86Subtarget.h:702
bool hasFastHorizontalOps() const
Definition: X86Subtarget.h:667
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:557
bool isWindowsGNUEnvironment() const
Definition: Triple.h:565
bool hasFSGSBase() const
Definition: X86Subtarget.h:617
bool hasFastVariableShuffle() const
Definition: X86Subtarget.h:655
bool hasDQI() const
Definition: X86Subtarget.h:685
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:553
bool isOSDragonFly() const
Definition: Triple.h:509
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:503
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool hasADX() const
Definition: X86Subtarget.h:625
bool isSLM() const
Definition: X86Subtarget.h:740
bool hasSSSE3() const
Definition: X86Subtarget.h:584
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:767
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:524
bool hasCLDEMOTE() const
Definition: X86Subtarget.h:639
bool hasGFNI() const
Definition: X86Subtarget.h:605
bool isTargetNaCl32() const
Definition: X86Subtarget.h:771
static bool is64Bit(const char *name)
bool isXRaySupported() const override
Definition: X86Subtarget.h:734
bool hasERMSB() const
Definition: X86Subtarget.h:672
bool hasMWAITX() const
Definition: X86Subtarget.h:637
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:650
bool hasF16C() const
Definition: X86Subtarget.h:616
bool hasERI() const
Definition: X86Subtarget.h:684
bool hasPCLMUL() const
Definition: X86Subtarget.h:603
bool useLeaForSP() const
Definition: X86Subtarget.h:652
bool hasMMX() const
Definition: X86Subtarget.h:592
bool hasFXSR() const
Definition: X86Subtarget.h:598
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:788
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:648
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:757
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:78
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:591
bool isPositionIndependent() const
Definition: X86Subtarget.h:811
bool hasCMov() const
Definition: X86Subtarget.h:580
bool isTargetGlibc() const
Definition: X86Subtarget.h:768
X86ProcFamilyEnum getProcFamily() const
Definition: X86Subtarget.h:736
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:754
bool hasVNNI() const
Definition: X86Subtarget.h:689
bool hasXOP() const
Definition: X86Subtarget.h:611
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
bool isTargetDarwin() const
Definition: X86Subtarget.h:756
bool hasSSE42() const
Definition: X86Subtarget.h:586
bool hasX87() const
Definition: X86Subtarget.h:575
bool isTargetMCU() const
Definition: X86Subtarget.h:773
bool isPMULLDSlow() const
Definition: X86Subtarget.h:644
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:704
bool hasPRFCHW() const
Definition: X86Subtarget.h:627
bool isTargetWin64() const
Definition: X86Subtarget.h:800
bool hasSSE3() const
Definition: X86Subtarget.h:583
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool slowIncDec() const
Definition: X86Subtarget.h:680
bool hasBMI2() const
Definition: X86Subtarget.h:620
bool hasVPCLMULQDQ() const
Definition: X86Subtarget.h:604
bool isTargetELF() const
Definition: X86Subtarget.h:762
bool isOSIAMCU() const
Definition: Triple.h:515
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:517
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:458
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:646
bool isAtom() const
TODO: to be removed later and replaced with suitable properties.
Definition: X86Subtarget.h:739
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:528
bool isPICStyleGOT() const
Definition: X86Subtarget.h:804
bool hasMOVDIR64B() const
Definition: X86Subtarget.h:641
bool threewayBranchProfitable() const
Definition: X86Subtarget.h:701
bool hasFastPartialYMMorZMMWrite() const
Definition: X86Subtarget.h:658
bool LEAusesAG() const
Definition: X86Subtarget.h:677
bool has3DNow() const
Definition: X86Subtarget.h:593
bool hasRDSEED() const
Definition: X86Subtarget.h:635
unsigned getPreferVectorWidth() const
Definition: X86Subtarget.h:710
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
bool hasVBMI() const
Definition: X86Subtarget.h:621
bool hasBITALG() const
Definition: X86Subtarget.h:692
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
bool isTargetWin32() const
Definition: X86Subtarget.h:802
bool hasXSAVEC() const
Definition: X86Subtarget.h:601
bool isTargetAndroid() const
Definition: X86Subtarget.h:769
bool isOSFreeBSD() const
Definition: Triple.h:501
bool canExtendTo512BW() const
Definition: X86Subtarget.h:720
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:561
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:662
bool hasCLFLUSHOPT() const
Definition: X86Subtarget.h:694
bool hasPOPCNTFalseDeps() const
Definition: X86Subtarget.h:653
bool hasIFMA() const
Definition: X86Subtarget.h:623
int getScatterOverhead() const
Definition: X86Subtarget.h:649
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:570
bool enableAdvancedRASplitCost() const override
Definition: X86Subtarget.h:875
bool hasAnyFMA() const
Definition: X86Subtarget.h:610
bool useSoftFloat() const
Definition: X86Subtarget.h:746
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:457
bool useRetpolineIndirectBranches() const
Definition: X86Subtarget.h:705
std::unique_ptr< LegalizerInfo > Legalizer
Definition: X86Subtarget.h:456
bool enableIndirectBrExpand() const override
If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect j...
Definition: X86Subtarget.h:859
bool hasRDRAND() const
Definition: X86Subtarget.h:615
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:636
Provides the logic to select generic machine instructions.
bool is16Bit() const
Definition: X86Subtarget.h:556
bool hasVAES() const
Definition: X86Subtarget.h:597
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:611
unsigned getRequiredVectorWidth() const
Definition: X86Subtarget.h:711
bool hasPTWRITE() const
Definition: X86Subtarget.h:642
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:110
bool useBWIRegs() const
Definition: X86Subtarget.h:730
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:153
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:513
bool isTargetDragonFly() const
Definition: X86Subtarget.h:758
bool isPositionIndependent() const
bool isGLM() const
Definition: X86Subtarget.h:741
bool hasInt256() const
Definition: X86Subtarget.h:590
bool isTargetCOFF() const
Definition: X86Subtarget.h:763
bool isTargetFuchsia() const
Definition: X86Subtarget.h:774
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:792
bool hasSlowDivide32() const
Definition: X86Subtarget.h:673
bool hasCDI() const
Definition: X86Subtarget.h:681
bool hasBranchFusion() const
Definition: X86Subtarget.h:671
bool hasPFI() const
Definition: X86Subtarget.h:683
bool useAA() const override
Definition: X86Subtarget.h:747
bool hasMOVBE() const
Definition: X86Subtarget.h:614
bool hasBMI() const
Definition: X86Subtarget.h:619
bool hasXSAVES() const
Definition: X86Subtarget.h:602
bool hasSSE1() const
Definition: X86Subtarget.h:581
bool isTargetLinux() const
Definition: X86Subtarget.h:766
This file describes how to lower LLVM calls to machine code calls.
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:813
bool isSHLDSlow() const
Definition: X86Subtarget.h:643
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:572
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
bool hasCmpxchg8b() const
Definition: X86Subtarget.h:576
bool hasMacroFusion() const
Definition: X86Subtarget.h:670
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:784
bool hasAVX512() const
Definition: X86Subtarget.h:589
bool hasSSE4A() const
Definition: X86Subtarget.h:591
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool hasBWI() const
Definition: X86Subtarget.h:686
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:871
bool hasFastGather() const
Definition: X86Subtarget.h:661
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:548
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:452
bool hasTBM() const
Definition: X86Subtarget.h:612
bool hasWAITPKG() const
Definition: X86Subtarget.h:698
bool hasLZCNT() const
Definition: X86Subtarget.h:618
bool hasMFence() const
Use mfence if we have SSE2 or we&#39;re on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:752
bool hasFastScalarShiftMasks() const
Definition: X86Subtarget.h:668
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:600
bool hasSSE2() const
Definition: X86Subtarget.h:582
bool hasLZCNTFalseDeps() const
Definition: X86Subtarget.h:654
bool hasRTM() const
Definition: X86Subtarget.h:624
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:663
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:780