LLVM 19.0.0git
X86Subtarget.h
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1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the X86 specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15
16#include "X86FrameLowering.h"
17#include "X86ISelLowering.h"
18#include "X86InstrInfo.h"
19#include "X86SelectionDAGInfo.h"
22#include "llvm/IR/CallingConv.h"
24#include <climits>
25#include <memory>
26
27#define GET_SUBTARGETINFO_HEADER
28#include "X86GenSubtargetInfo.inc"
29
30namespace llvm {
31
32class CallLowering;
33class GlobalValue;
34class InstructionSelector;
35class LegalizerInfo;
36class RegisterBankInfo;
37class StringRef;
38class TargetMachine;
39
40/// The X86 backend supports a number of different styles of PIC.
41///
42namespace PICStyles {
43
44enum class Style {
45 StubPIC, // Used on i386-darwin in pic mode.
46 GOT, // Used on 32 bit elf on when in pic mode.
47 RIPRel, // Used on X86-64 when in pic mode.
48 None // Set when not in pic mode.
49};
50
51} // end namespace PICStyles
52
53class X86Subtarget final : public X86GenSubtargetInfo {
54 enum X86SSEEnum {
55 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
56 };
57
58 enum X863DNowEnum {
59 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
60 };
61
62 /// Which PIC style to use
63 PICStyles::Style PICStyle;
64
65 const TargetMachine &TM;
66
67 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
68 X86SSEEnum X86SSELevel = NoSSE;
69
70 /// MMX, 3DNow, 3DNow Athlon, or none supported.
71 X863DNowEnum X863DNowLevel = NoThreeDNow;
72
73#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
74 bool ATTRIBUTE = DEFAULT;
75#include "X86GenSubtargetInfo.inc"
76 /// The minimum alignment known to hold of the stack frame on
77 /// entry to the function and which must be maintained by every function.
78 Align stackAlignment = Align(4);
79
80 Align TileConfigAlignment = Align(4);
81
82 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
83 ///
84 // FIXME: this is a known good value for Yonah. How about others?
85 unsigned MaxInlineSizeThreshold = 128;
86
87 /// What processor and OS we're targeting.
88 Triple TargetTriple;
89
90 /// GlobalISel related APIs.
91 std::unique_ptr<CallLowering> CallLoweringInfo;
92 std::unique_ptr<LegalizerInfo> Legalizer;
93 std::unique_ptr<RegisterBankInfo> RegBankInfo;
94 std::unique_ptr<InstructionSelector> InstSelector;
95
96 /// Override the stack alignment.
97 MaybeAlign StackAlignOverride;
98
99 /// Preferred vector width from function attribute.
100 unsigned PreferVectorWidthOverride;
101
102 /// Resolved preferred vector width from function attribute and subtarget
103 /// features.
104 unsigned PreferVectorWidth = UINT32_MAX;
105
106 /// Required vector width from function attribute.
107 unsigned RequiredVectorWidth;
108
109 X86SelectionDAGInfo TSInfo;
110 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
111 // X86TargetLowering needs.
112 X86InstrInfo InstrInfo;
113 X86TargetLowering TLInfo;
114 X86FrameLowering FrameLowering;
115
116public:
117 /// This constructor initializes the data members to match that
118 /// of the specified triple.
119 ///
120 X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
121 const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
122 unsigned PreferVectorWidthOverride,
123 unsigned RequiredVectorWidth);
124
125 const X86TargetLowering *getTargetLowering() const override {
126 return &TLInfo;
127 }
128
129 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
130
131 const X86FrameLowering *getFrameLowering() const override {
132 return &FrameLowering;
133 }
134
135 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
136 return &TSInfo;
137 }
138
139 const X86RegisterInfo *getRegisterInfo() const override {
140 return &getInstrInfo()->getRegisterInfo();
141 }
142
143 unsigned getTileConfigSize() const { return 64; }
144 Align getTileConfigAlignment() const { return TileConfigAlignment; }
145
146 /// Returns the minimum alignment known to hold of the
147 /// stack frame on entry to the function and which must be maintained by every
148 /// function for this subtarget.
149 Align getStackAlignment() const { return stackAlignment; }
150
151 /// Returns the maximum memset / memcpy size
152 /// that still makes it profitable to inline the call.
153 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
154
155 /// ParseSubtargetFeatures - Parses features string setting specified
156 /// subtarget options. Definition of function is auto generated by tblgen.
158
159 /// Methods used by Global ISel
160 const CallLowering *getCallLowering() const override;
162 const LegalizerInfo *getLegalizerInfo() const override;
163 const RegisterBankInfo *getRegBankInfo() const override;
164
165private:
166 /// Initialize the full set of dependencies so we can use an initializer
167 /// list for X86Subtarget.
168 X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
169 StringRef TuneCPU,
170 StringRef FS);
171 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
172
173public:
174
175#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
176 bool GETTER() const { return ATTRIBUTE; }
177#include "X86GenSubtargetInfo.inc"
178
179 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
180 bool isTarget64BitILP32() const {
181 return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
182 }
183
184 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
185 bool isTarget64BitLP64() const {
186 return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
187 }
188
189 PICStyles::Style getPICStyle() const { return PICStyle; }
190 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
191
192 bool canUseCMPXCHG8B() const { return hasCX8(); }
193 bool canUseCMPXCHG16B() const {
194 // CX16 is just the CPUID bit, instruction requires 64-bit mode too.
195 return hasCX16() && is64Bit();
196 }
197 // SSE codegen depends on cmovs, and all SSE1+ processors support them.
198 // All 64-bit processors support cmov.
199 bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); }
200 bool hasSSE1() const { return X86SSELevel >= SSE1; }
201 bool hasSSE2() const { return X86SSELevel >= SSE2; }
202 bool hasSSE3() const { return X86SSELevel >= SSE3; }
203 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
204 bool hasSSE41() const { return X86SSELevel >= SSE41; }
205 bool hasSSE42() const { return X86SSELevel >= SSE42; }
206 bool hasAVX() const { return X86SSELevel >= AVX; }
207 bool hasAVX2() const { return X86SSELevel >= AVX2; }
208 bool hasAVX512() const { return X86SSELevel >= AVX512; }
209 bool hasInt256() const { return hasAVX2(); }
210 bool hasMMX() const { return X863DNowLevel >= MMX; }
211 bool hasThreeDNow() const { return X863DNowLevel >= ThreeDNow; }
212 bool hasThreeDNowA() const { return X863DNowLevel >= ThreeDNowA; }
213 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
214 bool hasPrefetchW() const {
215 // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
216 // its own CPUID bit as part of deprecating 3DNow. Intel eventually added
217 // it and KNL has another that prefetches to L2 cache. We assume the
218 // L1 version exists if the L2 version does.
219 return hasThreeDNow() || hasPRFCHW() || hasPREFETCHWT1();
220 }
221 bool hasSSEPrefetch() const {
222 // We implicitly enable these when we have a write prefix supporting cache
223 // level OR if we have prfchw, but don't already have a read prefetch from
224 // 3dnow.
225 return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1() ||
226 hasPREFETCHI();
227 }
228 bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); }
229 // These are generic getters that OR together all of the thunk types
230 // supported by the subtarget. Therefore useIndirectThunk*() will return true
231 // if any respective thunk feature is enabled.
233 return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
234 }
236 return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
237 }
238
239 unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
240 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
241
242 // Helper functions to determine when we should allow widening to 512-bit
243 // during codegen.
244 // TODO: Currently we're always allowing widening on CPUs without VLX,
245 // because for many cases we don't have a better option.
246 bool canExtendTo512DQ() const {
247 return hasAVX512() && hasEVEX512() &&
248 (!hasVLX() || getPreferVectorWidth() >= 512);
249 }
250 bool canExtendTo512BW() const {
251 return hasBWI() && canExtendTo512DQ();
252 }
253
254 bool hasNoDomainDelay() const { return NoDomainDelay; }
255 bool hasNoDomainDelayMov() const {
256 return hasNoDomainDelay() || NoDomainDelayMov;
257 }
259 return hasNoDomainDelay() || NoDomainDelayBlend;
260 }
262 return hasNoDomainDelay() || NoDomainDelayShuffle;
263 }
264
265 // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
266 // disable them in the legalizer.
267 bool useAVX512Regs() const {
268 return hasAVX512() && hasEVEX512() &&
269 (canExtendTo512DQ() || RequiredVectorWidth > 256);
270 }
271
273 return getPreferVectorWidth() >= 256 || AllowLight256Bit;
274 }
275
276 bool useBWIRegs() const {
277 return hasBWI() && useAVX512Regs();
278 }
279
280 bool isXRaySupported() const override { return is64Bit(); }
281
282 /// Use clflush if we have SSE2 or we're on x86-64 (even if we asked for
283 /// no-sse2). There isn't any reason to disable it if the target processor
284 /// supports it.
285 bool hasCLFLUSH() const { return hasSSE2() || is64Bit(); }
286
287 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
288 /// no-sse2). There isn't any reason to disable it if the target processor
289 /// supports it.
290 bool hasMFence() const { return hasSSE2() || is64Bit(); }
291
292 const Triple &getTargetTriple() const { return TargetTriple; }
293
294 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
295 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
296 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
297 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
298 bool isTargetPS() const { return TargetTriple.isPS(); }
299
300 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
301 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
302 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
303
304 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
305 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
306 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
307 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
308 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
309 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
310 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
311 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
312 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
313
314 bool isTargetWindowsMSVC() const {
315 return TargetTriple.isWindowsMSVCEnvironment();
316 }
317
319 return TargetTriple.isWindowsCoreCLREnvironment();
320 }
321
323 return TargetTriple.isWindowsCygwinEnvironment();
324 }
325
326 bool isTargetWindowsGNU() const {
327 return TargetTriple.isWindowsGNUEnvironment();
328 }
329
331 return TargetTriple.isWindowsItaniumEnvironment();
332 }
333
334 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
335
336 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
337
338 bool isTargetWin64() const { return Is64Bit && isOSWindows(); }
339
340 bool isTargetWin32() const { return !Is64Bit && isOSWindows(); }
341
342 bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
343 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
344
345 bool isPICStyleStubPIC() const {
346 return PICStyle == PICStyles::Style::StubPIC;
347 }
348
349 bool isPositionIndependent() const;
350
352 switch (CC) {
353 // On Win64, all these conventions just use the default convention.
354 case CallingConv::C:
364 return isTargetWin64();
365 // This convention allows using the Win64 convention on other targets.
367 return true;
368 // This convention allows using the SysV convention on Windows targets.
370 return false;
371 // Otherwise, who knows what this is.
372 default:
373 return false;
374 }
375 }
376
377 /// Classify a global variable reference for the current subtarget according
378 /// to how we should reference it in a non-pcrel context.
379 unsigned char classifyLocalReference(const GlobalValue *GV) const;
380
381 unsigned char classifyGlobalReference(const GlobalValue *GV,
382 const Module &M) const;
383 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
384
385 /// Classify a global function reference for the current subtarget.
386 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
387 const Module &M) const;
388 unsigned char
389 classifyGlobalFunctionReference(const GlobalValue *GV) const override;
390
391 /// Classify a blockaddress reference for the current subtarget according to
392 /// how we should reference it in a non-pcrel context.
393 unsigned char classifyBlockAddressReference() const;
394
395 /// Return true if the subtarget allows calls to immediate address.
396 bool isLegalToCallImmediateAddr() const;
397
398 /// Return whether FrameLowering should always set the "extended frame
399 /// present" bit in FP, or set it based on a symbol in the runtime.
401 // Older OS versions (particularly system unwinders) are confused by the
402 // Swift extended frame, so when building code that might be run on them we
403 // must dynamically query the concurrency library to determine whether
404 // extended frames should be flagged as present.
405 const Triple &TT = getTargetTriple();
406
407 unsigned Major = TT.getOSVersion().getMajor();
408 switch(TT.getOS()) {
409 default:
410 return false;
411 case Triple::IOS:
412 case Triple::TvOS:
413 return Major < 15;
414 case Triple::WatchOS:
415 return Major < 8;
416 case Triple::MacOSX:
417 case Triple::Darwin:
418 return Major < 12;
419 }
420 }
421
422 /// If we are using indirect thunks, we need to expand indirectbr to avoid it
423 /// lowering to an actual indirect jump.
424 bool enableIndirectBrExpand() const override {
426 }
427
428 /// Enable the MachineScheduler pass for all X86 subtargets.
429 bool enableMachineScheduler() const override { return true; }
430
431 bool enableEarlyIfConversion() const override;
432
433 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
434 &Mutations) const override;
435
436 AntiDepBreakMode getAntiDepBreakMode() const override {
437 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
438 }
439};
440
441} // end namespace llvm
442
443#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
static bool is64Bit(const char *name)
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDragonFly() const
Definition: Triple.h:592
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:673
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:662
bool isX32() const
Tests whether the target is X32.
Definition: Triple.h:1037
bool isWindowsGNUEnvironment() const
Definition: Triple.h:657
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:769
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:732
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:645
bool isOSSolaris() const
Definition: Triple.h:594
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:683
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:724
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:624
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:678
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:653
bool isOSFreeBSD() const
Definition: Triple.h:584
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:558
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:703
bool isPS() const
Tests whether the target is the PS4 or PS5 platform.
Definition: Triple.h:766
bool isOSIAMCU() const
Definition: Triple.h:598
bool isOSFuchsia() const
Definition: Triple.h:588
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:634
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:649
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:202
bool canExtendTo512BW() const
Definition: X86Subtarget.h:250
bool hasAnyFMA() const
Definition: X86Subtarget.h:213
bool enableEarlyIfConversion() const override
bool isOSWindows() const
Definition: X86Subtarget.h:336
bool isTargetMachO() const
Definition: X86Subtarget.h:302
unsigned getTileConfigSize() const
Definition: X86Subtarget.h:143
bool canUseLAHFSAHF() const
Definition: X86Subtarget.h:228
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:305
bool isXRaySupported() const override
Definition: X86Subtarget.h:280
unsigned getRequiredVectorWidth() const
Definition: X86Subtarget.h:240
bool useIndirectThunkBranches() const
Definition: X86Subtarget.h:235
bool hasSSE1() const
Definition: X86Subtarget.h:200
bool useLight256BitInstructions() const
Definition: X86Subtarget.h:272
bool isTargetSolaris() const
Definition: X86Subtarget.h:297
bool hasThreeDNow() const
Definition: X86Subtarget.h:211
bool isPICStyleGOT() const
Definition: X86Subtarget.h:342
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:322
bool hasSSE42() const
Definition: X86Subtarget.h:205
InstructionSelector * getInstructionSelector() const override
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:125
bool hasMFence() const
Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:290
bool hasNoDomainDelayBlend() const
Definition: X86Subtarget.h:258
Align getTileConfigAlignment() const
Definition: X86Subtarget.h:144
bool isTargetMCU() const
Definition: X86Subtarget.h:311
bool isTargetDragonFly() const
Definition: X86Subtarget.h:296
bool canUseCMOV() const
Definition: X86Subtarget.h:199
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:345
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:429
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:314
bool canUseCMPXCHG8B() const
Definition: X86Subtarget.h:192
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:180
bool hasNoDomainDelayShuffle() const
Definition: X86Subtarget.h:261
bool isTargetDarwin() const
Definition: X86Subtarget.h:294
bool isTargetWin64() const
Definition: X86Subtarget.h:338
bool hasPrefetchW() const
Definition: X86Subtarget.h:214
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:185
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: X86Subtarget.h:400
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:292
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:436
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:318
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:129
const RegisterBankInfo * getRegBankInfo() const override
bool useAVX512Regs() const
Definition: X86Subtarget.h:267
bool isTargetCOFF() const
Definition: X86Subtarget.h:301
bool hasSSE3() const
Definition: X86Subtarget.h:202
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:351
bool isTargetNaCl() const
Definition: X86Subtarget.h:308
bool hasAVX512() const
Definition: X86Subtarget.h:208
bool canExtendTo512DQ() const
Definition: X86Subtarget.h:246
bool hasSSE41() const
Definition: X86Subtarget.h:204
bool hasMMX() const
Definition: X86Subtarget.h:210
Align getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:149
bool isTargetELF() const
Definition: X86Subtarget.h:300
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:221
bool canUseCMPXCHG16B() const
Definition: X86Subtarget.h:193
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
const LegalizerInfo * getLegalizerInfo() const override
bool isPositionIndependent() const
bool hasSSE2() const
Definition: X86Subtarget.h:201
bool hasThreeDNowA() const
Definition: X86Subtarget.h:212
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:295
bool isTargetGlibc() const
Definition: X86Subtarget.h:306
bool isTargetFuchsia() const
Definition: X86Subtarget.h:312
bool hasSSSE3() const
Definition: X86Subtarget.h:203
bool hasInt256() const
Definition: X86Subtarget.h:209
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:343
bool isTargetCygMing() const
Definition: X86Subtarget.h:334
bool hasNoDomainDelay() const
Definition: X86Subtarget.h:254
bool isTargetNaCl32() const
Definition: X86Subtarget.h:309
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:189
bool enableIndirectBrExpand() const override
If we are using indirect thunks, we need to expand indirectbr to avoid it lowering to an actual indir...
Definition: X86Subtarget.h:424
bool hasNoDomainDelayMov() const
Definition: X86Subtarget.h:255
bool isTargetPS() const
Definition: X86Subtarget.h:298
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:139
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:190
bool hasAVX() const
Definition: X86Subtarget.h:206
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:326
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition: X86Subtarget.h:153
unsigned getPreferVectorWidth() const
Definition: X86Subtarget.h:239
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:330
bool isTargetAndroid() const
Definition: X86Subtarget.h:307
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
bool isTargetNaCl64() const
Definition: X86Subtarget.h:310
bool hasCLFLUSH() const
Use clflush if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:285
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:131
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
bool useBWIRegs() const
Definition: X86Subtarget.h:276
bool isTargetWin32() const
Definition: X86Subtarget.h:340
bool useIndirectThunkCalls() const
Definition: X86Subtarget.h:232
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
bool hasAVX2() const
Definition: X86Subtarget.h:207
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:135
bool isTargetLinux() const
Definition: X86Subtarget.h:304
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:151
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ X86_ThisCall
Similar to X86_StdCall.
Definition: CallingConv.h:122
@ X86_StdCall
stdcall is mostly used by the Win32 API.
Definition: CallingConv.h:99
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ X86_VectorCall
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:163
@ Intel_OCL_BI
Used for Intel OpenCL built-ins.
Definition: CallingConv.h:147
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:159
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ X86_FastCall
'fast' analog of X86_StdCall.
Definition: CallingConv.h:103
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117