LLVM  9.0.0svn
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 
16 #include "X86FrameLowering.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86SelectionDAGInfo.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/CallingConv.h"
29 #include <climits>
30 #include <memory>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "X86GenSubtargetInfo.inc"
34 
35 namespace llvm {
36 
37 class GlobalValue;
38 
39 /// The X86 backend supports a number of different styles of PIC.
40 ///
41 namespace PICStyles {
42 
43 enum Style {
44  StubPIC, // Used on i386-darwin in pic mode.
45  GOT, // Used on 32 bit elf on when in pic mode.
46  RIPRel, // Used on X86-64 when in pic mode.
47  None // Set when not in pic mode.
48 };
49 
50 } // end namespace PICStyles
51 
52 class X86Subtarget final : public X86GenSubtargetInfo {
53 public:
54  // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
55  // are not a good idea. We should be migrating away from these.
62  IntelTRM
63  };
64 
65 protected:
66  enum X86SSEEnum {
67  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
68  };
69 
70  enum X863DNowEnum {
71  NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
72  };
73 
74  /// X86 processor family: Intel Atom, and others
75  X86ProcFamilyEnum X86ProcFamily = Others;
76 
77  /// Which PIC style to use
79 
80  const TargetMachine &TM;
81 
82  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
83  X86SSEEnum X86SSELevel = NoSSE;
84 
85  /// MMX, 3DNow, 3DNow Athlon, or none supported.
86  X863DNowEnum X863DNowLevel = NoThreeDNow;
87 
88  /// True if the processor supports X87 instructions.
89  bool HasX87 = false;
90 
91  /// True if the processor supports CMPXCHG8B.
92  bool HasCmpxchg8b = false;
93 
94  /// True if this processor has NOPL instruction
95  /// (generally pentium pro+).
96  bool HasNOPL = false;
97 
98  /// True if this processor has conditional move instructions
99  /// (generally pentium pro+).
100  bool HasCMov = false;
101 
102  /// True if the processor supports X86-64 instructions.
103  bool HasX86_64 = false;
104 
105  /// True if the processor supports POPCNT.
106  bool HasPOPCNT = false;
107 
108  /// True if the processor supports SSE4A instructions.
109  bool HasSSE4A = false;
110 
111  /// Target has AES instructions
112  bool HasAES = false;
113  bool HasVAES = false;
114 
115  /// Target has FXSAVE/FXRESTOR instructions
116  bool HasFXSR = false;
117 
118  /// Target has XSAVE instructions
119  bool HasXSAVE = false;
120 
121  /// Target has XSAVEOPT instructions
122  bool HasXSAVEOPT = false;
123 
124  /// Target has XSAVEC instructions
125  bool HasXSAVEC = false;
126 
127  /// Target has XSAVES instructions
128  bool HasXSAVES = false;
129 
130  /// Target has carry-less multiplication
131  bool HasPCLMUL = false;
132  bool HasVPCLMULQDQ = false;
133 
134  /// Target has Galois Field Arithmetic instructions
135  bool HasGFNI = false;
136 
137  /// Target has 3-operand fused multiply-add
138  bool HasFMA = false;
139 
140  /// Target has 4-operand fused multiply-add
141  bool HasFMA4 = false;
142 
143  /// Target has XOP instructions
144  bool HasXOP = false;
145 
146  /// Target has TBM instructions.
147  bool HasTBM = false;
148 
149  /// Target has LWP instructions
150  bool HasLWP = false;
151 
152  /// True if the processor has the MOVBE instruction.
153  bool HasMOVBE = false;
154 
155  /// True if the processor has the RDRAND instruction.
156  bool HasRDRAND = false;
157 
158  /// Processor has 16-bit floating point conversion instructions.
159  bool HasF16C = false;
160 
161  /// Processor has FS/GS base insturctions.
162  bool HasFSGSBase = false;
163 
164  /// Processor has LZCNT instruction.
165  bool HasLZCNT = false;
166 
167  /// Processor has BMI1 instructions.
168  bool HasBMI = false;
169 
170  /// Processor has BMI2 instructions.
171  bool HasBMI2 = false;
172 
173  /// Processor has VBMI instructions.
174  bool HasVBMI = false;
175 
176  /// Processor has VBMI2 instructions.
177  bool HasVBMI2 = false;
178 
179  /// Processor has Integer Fused Multiply Add
180  bool HasIFMA = false;
181 
182  /// Processor has RTM instructions.
183  bool HasRTM = false;
184 
185  /// Processor has ADX instructions.
186  bool HasADX = false;
187 
188  /// Processor has SHA instructions.
189  bool HasSHA = false;
190 
191  /// Processor has PRFCHW instructions.
192  bool HasPRFCHW = false;
193 
194  /// Processor has RDSEED instructions.
195  bool HasRDSEED = false;
196 
197  /// Processor has LAHF/SAHF instructions.
198  bool HasLAHFSAHF = false;
199 
200  /// Processor has MONITORX/MWAITX instructions.
201  bool HasMWAITX = false;
202 
203  /// Processor has Cache Line Zero instruction
204  bool HasCLZERO = false;
205 
206  /// Processor has Cache Line Demote instruction
207  bool HasCLDEMOTE = false;
208 
209  /// Processor has MOVDIRI instruction (direct store integer).
210  bool HasMOVDIRI = false;
211 
212  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
213  bool HasMOVDIR64B = false;
214 
215  /// Processor has ptwrite instruction.
216  bool HasPTWRITE = false;
217 
218  /// Processor has Prefetch with intent to Write instruction
219  bool HasPREFETCHWT1 = false;
220 
221  /// True if SHLD instructions are slow.
222  bool IsSHLDSlow = false;
223 
224  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
225  // PMULUDQ.
226  bool IsPMULLDSlow = false;
227 
228  /// True if the PMADDWD instruction is slow compared to PMULLD.
229  bool IsPMADDWDSlow = false;
230 
231  /// True if unaligned memory accesses of 16-bytes are slow.
232  bool IsUAMem16Slow = false;
233 
234  /// True if unaligned memory accesses of 32-bytes are slow.
235  bool IsUAMem32Slow = false;
236 
237  /// True if SSE operations can have unaligned memory operands.
238  /// This may require setting a configuration bit in the processor.
239  bool HasSSEUnalignedMem = false;
240 
241  /// True if this processor has the CMPXCHG16B instruction;
242  /// this is true for most x86-64 chips, but not the first AMD chips.
243  bool HasCmpxchg16b = false;
244 
245  /// True if the LEA instruction should be used for adjusting
246  /// the stack pointer. This is an optimization for Intel Atom processors.
247  bool UseLeaForSP = false;
248 
249  /// True if POPCNT instruction has a false dependency on the destination register.
250  bool HasPOPCNTFalseDeps = false;
251 
252  /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
253  bool HasLZCNTFalseDeps = false;
254 
255  /// True if its preferable to combine to a single shuffle using a variable
256  /// mask over multiple fixed shuffles.
257  bool HasFastVariableShuffle = false;
258 
259  /// True if there is no performance penalty to writing only the lower parts
260  /// of a YMM or ZMM register without clearing the upper part.
261  bool HasFastPartialYMMorZMMWrite = false;
262 
263  /// True if there is no performance penalty for writing NOPs with up to
264  /// 11 bytes.
265  bool HasFast11ByteNOP = false;
266 
267  /// True if there is no performance penalty for writing NOPs with up to
268  /// 15 bytes.
269  bool HasFast15ByteNOP = false;
270 
271  /// True if gather is reasonably fast. This is true for Skylake client and
272  /// all AVX-512 CPUs.
273  bool HasFastGather = false;
274 
275  /// True if hardware SQRTSS instruction is at least as fast (latency) as
276  /// RSQRTSS followed by a Newton-Raphson iteration.
277  bool HasFastScalarFSQRT = false;
278 
279  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
280  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
281  bool HasFastVectorFSQRT = false;
282 
283  /// True if 8-bit divisions are significantly faster than
284  /// 32-bit divisions and should be used when possible.
285  bool HasSlowDivide32 = false;
286 
287  /// True if 32-bit divides are significantly faster than
288  /// 64-bit divisions and should be used when possible.
289  bool HasSlowDivide64 = false;
290 
291  /// True if LZCNT instruction is fast.
292  bool HasFastLZCNT = false;
293 
294  /// True if SHLD based rotate is fast.
295  bool HasFastSHLDRotate = false;
296 
297  /// True if the processor supports macrofusion.
298  bool HasMacroFusion = false;
299 
300  /// True if the processor supports branch fusion.
301  bool HasBranchFusion = false;
302 
303  /// True if the processor has enhanced REP MOVSB/STOSB.
304  bool HasERMSB = false;
305 
306  /// True if the short functions should be padded to prevent
307  /// a stall when returning too early.
308  bool PadShortFunctions = false;
309 
310  /// True if two memory operand instructions should use a temporary register
311  /// instead.
312  bool SlowTwoMemOps = false;
313 
314  /// True if the LEA instruction inputs have to be ready at address generation
315  /// (AG) time.
316  bool LEAUsesAG = false;
317 
318  /// True if the LEA instruction with certain arguments is slow
319  bool SlowLEA = false;
320 
321  /// True if the LEA instruction has all three source operands: base, index,
322  /// and offset or if the LEA instruction uses base and index registers where
323  /// the base is EBP, RBP,or R13
324  bool Slow3OpsLEA = false;
325 
326  /// True if INC and DEC instructions are slow when writing to flags
327  bool SlowIncDec = false;
328 
329  /// Processor has AVX-512 PreFetch Instructions
330  bool HasPFI = false;
331 
332  /// Processor has AVX-512 Exponential and Reciprocal Instructions
333  bool HasERI = false;
334 
335  /// Processor has AVX-512 Conflict Detection Instructions
336  bool HasCDI = false;
337 
338  /// Processor has AVX-512 population count Instructions
339  bool HasVPOPCNTDQ = false;
340 
341  /// Processor has AVX-512 Doubleword and Quadword instructions
342  bool HasDQI = false;
343 
344  /// Processor has AVX-512 Byte and Word instructions
345  bool HasBWI = false;
346 
347  /// Processor has AVX-512 Vector Length eXtenstions
348  bool HasVLX = false;
349 
350  /// Processor has PKU extenstions
351  bool HasPKU = false;
352 
353  /// Processor has AVX-512 Vector Neural Network Instructions
354  bool HasVNNI = false;
355 
356  /// Processor has AVX-512 bfloat16 floating-point extensions
357  bool HasBF16 = false;
358 
359  /// Processor has AVX-512 Bit Algorithms instructions
360  bool HasBITALG = false;
361 
362  /// Processor supports MPX - Memory Protection Extensions
363  bool HasMPX = false;
364 
365  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
366  /// using Shadow Stack
367  bool HasSHSTK = false;
368 
369  /// Processor supports Invalidate Process-Context Identifier
370  bool HasINVPCID = false;
371 
372  /// Processor has Software Guard Extensions
373  bool HasSGX = false;
374 
375  /// Processor supports Flush Cache Line instruction
376  bool HasCLFLUSHOPT = false;
377 
378  /// Processor supports Cache Line Write Back instruction
379  bool HasCLWB = false;
380 
381  /// Processor supports Write Back No Invalidate instruction
382  bool HasWBNOINVD = false;
383 
384  /// Processor support RDPID instruction
385  bool HasRDPID = false;
386 
387  /// Processor supports WaitPKG instructions
388  bool HasWAITPKG = false;
389 
390  /// Processor supports PCONFIG instruction
391  bool HasPCONFIG = false;
392 
393  /// Processor has a single uop BEXTR implementation.
394  bool HasFastBEXTR = false;
395 
396  /// Try harder to combine to horizontal vector ops if they are fast.
397  bool HasFastHorizontalOps = false;
398 
399  /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
400  bool HasFastScalarShiftMasks = false;
401 
402  /// Prefer a left/right vector logical shifts pair over a shift+and pair.
403  bool HasFastVectorShiftMasks = false;
404 
405  /// Use a retpoline thunk rather than indirect calls to block speculative
406  /// execution.
407  bool UseRetpolineIndirectCalls = false;
408 
409  /// Use a retpoline thunk or remove any indirect branch to block speculative
410  /// execution.
411  bool UseRetpolineIndirectBranches = false;
412 
413  /// Deprecated flag, query `UseRetpolineIndirectCalls` and
414  /// `UseRetpolineIndirectBranches` instead.
415  bool DeprecatedUseRetpoline = false;
416 
417  /// When using a retpoline thunk, call an externally provided thunk rather
418  /// than emitting one inside the compiler.
419  bool UseRetpolineExternalThunk = false;
420 
421  /// Use software floating point for code generation.
422  bool UseSoftFloat = false;
423 
424  /// The minimum alignment known to hold of the stack frame on
425  /// entry to the function and which must be maintained by every function.
426  unsigned stackAlignment = 4;
427 
428  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
429  ///
430  // FIXME: this is a known good value for Yonah. How about others?
431  unsigned MaxInlineSizeThreshold = 128;
432 
433  /// Indicates target prefers 256 bit instructions.
434  bool Prefer256Bit = false;
435 
436  /// Threeway branch is profitable in this subtarget.
437  bool ThreewayBranchProfitable = false;
438 
439  /// What processor and OS we're targeting.
441 
442  /// GlobalISel related APIs.
443  std::unique_ptr<CallLowering> CallLoweringInfo;
444  std::unique_ptr<LegalizerInfo> Legalizer;
445  std::unique_ptr<RegisterBankInfo> RegBankInfo;
446  std::unique_ptr<InstructionSelector> InstSelector;
447 
448 private:
449  /// Override the stack alignment.
450  unsigned StackAlignOverride;
451 
452  /// Preferred vector width from function attribute.
453  unsigned PreferVectorWidthOverride;
454 
455  /// Resolved preferred vector width from function attribute and subtarget
456  /// features.
457  unsigned PreferVectorWidth = UINT32_MAX;
458 
459  /// Required vector width from function attribute.
460  unsigned RequiredVectorWidth;
461 
462  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
463  bool In64BitMode;
464 
465  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
466  bool In32BitMode;
467 
468  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
469  bool In16BitMode;
470 
471  /// Contains the Overhead of gather\scatter instructions
472  int GatherOverhead = 1024;
473  int ScatterOverhead = 1024;
474 
475  X86SelectionDAGInfo TSInfo;
476  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
477  // X86TargetLowering needs.
478  X86InstrInfo InstrInfo;
479  X86TargetLowering TLInfo;
480  X86FrameLowering FrameLowering;
481 
482 public:
483  /// This constructor initializes the data members to match that
484  /// of the specified triple.
485  ///
486  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
487  const X86TargetMachine &TM, unsigned StackAlignOverride,
488  unsigned PreferVectorWidthOverride,
489  unsigned RequiredVectorWidth);
490 
491  const X86TargetLowering *getTargetLowering() const override {
492  return &TLInfo;
493  }
494 
495  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
496 
497  const X86FrameLowering *getFrameLowering() const override {
498  return &FrameLowering;
499  }
500 
501  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
502  return &TSInfo;
503  }
504 
505  const X86RegisterInfo *getRegisterInfo() const override {
506  return &getInstrInfo()->getRegisterInfo();
507  }
508 
509  /// Returns the minimum alignment known to hold of the
510  /// stack frame on entry to the function and which must be maintained by every
511  /// function for this subtarget.
512  unsigned getStackAlignment() const { return stackAlignment; }
513 
514  /// Returns the maximum memset / memcpy size
515  /// that still makes it profitable to inline the call.
516  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
517 
518  /// ParseSubtargetFeatures - Parses features string setting specified
519  /// subtarget options. Definition of function is auto generated by tblgen.
520  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
521 
522  /// Methods used by Global ISel
523  const CallLowering *getCallLowering() const override;
524  const InstructionSelector *getInstructionSelector() const override;
525  const LegalizerInfo *getLegalizerInfo() const override;
526  const RegisterBankInfo *getRegBankInfo() const override;
527 
528 private:
529  /// Initialize the full set of dependencies so we can use an initializer
530  /// list for X86Subtarget.
531  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
532  void initSubtargetFeatures(StringRef CPU, StringRef FS);
533 
534 public:
535  /// Is this x86_64? (disregarding specific ABI / programming model)
536  bool is64Bit() const {
537  return In64BitMode;
538  }
539 
540  bool is32Bit() const {
541  return In32BitMode;
542  }
543 
544  bool is16Bit() const {
545  return In16BitMode;
546  }
547 
548  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
549  bool isTarget64BitILP32() const {
550  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
551  TargetTriple.isOSNaCl());
552  }
553 
554  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
555  bool isTarget64BitLP64() const {
556  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
557  !TargetTriple.isOSNaCl());
558  }
559 
560  PICStyles::Style getPICStyle() const { return PICStyle; }
561  void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
562 
563  bool hasX87() const { return HasX87; }
564  bool hasCmpxchg8b() const { return HasCmpxchg8b; }
565  bool hasNOPL() const { return HasNOPL; }
566  // SSE codegen depends on cmovs, and all SSE1+ processors support them.
567  // All 64-bit processors support cmov.
568  bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
569  bool hasSSE1() const { return X86SSELevel >= SSE1; }
570  bool hasSSE2() const { return X86SSELevel >= SSE2; }
571  bool hasSSE3() const { return X86SSELevel >= SSE3; }
572  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
573  bool hasSSE41() const { return X86SSELevel >= SSE41; }
574  bool hasSSE42() const { return X86SSELevel >= SSE42; }
575  bool hasAVX() const { return X86SSELevel >= AVX; }
576  bool hasAVX2() const { return X86SSELevel >= AVX2; }
577  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
578  bool hasInt256() const { return hasAVX2(); }
579  bool hasSSE4A() const { return HasSSE4A; }
580  bool hasMMX() const { return X863DNowLevel >= MMX; }
581  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
582  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
583  bool hasPOPCNT() const { return HasPOPCNT; }
584  bool hasAES() const { return HasAES; }
585  bool hasVAES() const { return HasVAES; }
586  bool hasFXSR() const { return HasFXSR; }
587  bool hasXSAVE() const { return HasXSAVE; }
588  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
589  bool hasXSAVEC() const { return HasXSAVEC; }
590  bool hasXSAVES() const { return HasXSAVES; }
591  bool hasPCLMUL() const { return HasPCLMUL; }
592  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
593  bool hasGFNI() const { return HasGFNI; }
594  // Prefer FMA4 to FMA - its better for commutation/memory folding and
595  // has equal or better performance on all supported targets.
596  bool hasFMA() const { return HasFMA; }
597  bool hasFMA4() const { return HasFMA4; }
598  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
599  bool hasXOP() const { return HasXOP; }
600  bool hasTBM() const { return HasTBM; }
601  bool hasLWP() const { return HasLWP; }
602  bool hasMOVBE() const { return HasMOVBE; }
603  bool hasRDRAND() const { return HasRDRAND; }
604  bool hasF16C() const { return HasF16C; }
605  bool hasFSGSBase() const { return HasFSGSBase; }
606  bool hasLZCNT() const { return HasLZCNT; }
607  bool hasBMI() const { return HasBMI; }
608  bool hasBMI2() const { return HasBMI2; }
609  bool hasVBMI() const { return HasVBMI; }
610  bool hasVBMI2() const { return HasVBMI2; }
611  bool hasIFMA() const { return HasIFMA; }
612  bool hasRTM() const { return HasRTM; }
613  bool hasADX() const { return HasADX; }
614  bool hasSHA() const { return HasSHA; }
615  bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
616  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
617  bool hasSSEPrefetch() const {
618  // We implicitly enable these when we have a write prefix supporting cache
619  // level OR if we have prfchw, but don't already have a read prefetch from
620  // 3dnow.
621  return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
622  }
623  bool hasRDSEED() const { return HasRDSEED; }
624  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
625  bool hasMWAITX() const { return HasMWAITX; }
626  bool hasCLZERO() const { return HasCLZERO; }
627  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
628  bool hasMOVDIRI() const { return HasMOVDIRI; }
629  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
630  bool hasPTWRITE() const { return HasPTWRITE; }
631  bool isSHLDSlow() const { return IsSHLDSlow; }
632  bool isPMULLDSlow() const { return IsPMULLDSlow; }
633  bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
634  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
635  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
636  int getGatherOverhead() const { return GatherOverhead; }
637  int getScatterOverhead() const { return ScatterOverhead; }
638  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
639  bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
640  bool useLeaForSP() const { return UseLeaForSP; }
641  bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
642  bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
643  bool hasFastVariableShuffle() const {
644  return HasFastVariableShuffle;
645  }
647  return HasFastPartialYMMorZMMWrite;
648  }
649  bool hasFastGather() const { return HasFastGather; }
650  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
651  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
652  bool hasFastLZCNT() const { return HasFastLZCNT; }
653  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
654  bool hasFastBEXTR() const { return HasFastBEXTR; }
655  bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
656  bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
657  bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
658  bool hasMacroFusion() const { return HasMacroFusion; }
659  bool hasBranchFusion() const { return HasBranchFusion; }
660  bool hasERMSB() const { return HasERMSB; }
661  bool hasSlowDivide32() const { return HasSlowDivide32; }
662  bool hasSlowDivide64() const { return HasSlowDivide64; }
663  bool padShortFunctions() const { return PadShortFunctions; }
664  bool slowTwoMemOps() const { return SlowTwoMemOps; }
665  bool LEAusesAG() const { return LEAUsesAG; }
666  bool slowLEA() const { return SlowLEA; }
667  bool slow3OpsLEA() const { return Slow3OpsLEA; }
668  bool slowIncDec() const { return SlowIncDec; }
669  bool hasCDI() const { return HasCDI; }
670  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
671  bool hasPFI() const { return HasPFI; }
672  bool hasERI() const { return HasERI; }
673  bool hasDQI() const { return HasDQI; }
674  bool hasBWI() const { return HasBWI; }
675  bool hasVLX() const { return HasVLX; }
676  bool hasPKU() const { return HasPKU; }
677  bool hasVNNI() const { return HasVNNI; }
678  bool hasBF16() const { return HasBF16; }
679  bool hasBITALG() const { return HasBITALG; }
680  bool hasMPX() const { return HasMPX; }
681  bool hasSHSTK() const { return HasSHSTK; }
682  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
683  bool hasCLWB() const { return HasCLWB; }
684  bool hasWBNOINVD() const { return HasWBNOINVD; }
685  bool hasRDPID() const { return HasRDPID; }
686  bool hasWAITPKG() const { return HasWAITPKG; }
687  bool hasPCONFIG() const { return HasPCONFIG; }
688  bool hasSGX() const { return HasSGX; }
689  bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
690  bool hasINVPCID() const { return HasINVPCID; }
691  bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
693  return UseRetpolineIndirectBranches;
694  }
695  bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
696 
697  unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
698  unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
699 
700  // Helper functions to determine when we should allow widening to 512-bit
701  // during codegen.
702  // TODO: Currently we're always allowing widening on CPUs without VLX,
703  // because for many cases we don't have a better option.
704  bool canExtendTo512DQ() const {
705  return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
706  }
707  bool canExtendTo512BW() const {
708  return hasBWI() && canExtendTo512DQ();
709  }
710 
711  // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
712  // disable them in the legalizer.
713  bool useAVX512Regs() const {
714  return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
715  }
716 
717  bool useBWIRegs() const {
718  return hasBWI() && useAVX512Regs();
719  }
720 
721  bool isXRaySupported() const override { return is64Bit(); }
722 
723  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
724 
725  /// TODO: to be removed later and replaced with suitable properties
726  bool isAtom() const { return X86ProcFamily == IntelAtom; }
727  bool isSLM() const { return X86ProcFamily == IntelSLM; }
728  bool isGLM() const {
729  return X86ProcFamily == IntelGLM ||
730  X86ProcFamily == IntelGLP ||
731  X86ProcFamily == IntelTRM;
732  }
733  bool useSoftFloat() const { return UseSoftFloat; }
734 
735  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
736  /// no-sse2). There isn't any reason to disable it if the target processor
737  /// supports it.
738  bool hasMFence() const { return hasSSE2() || is64Bit(); }
739 
740  const Triple &getTargetTriple() const { return TargetTriple; }
741 
742  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
743  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
744  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
745  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
746  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
747 
748  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
749  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
750  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
751 
752  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
753  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
754  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
755  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
756  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
757  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
758  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
759  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
760  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
761 
762  bool isTargetWindowsMSVC() const {
763  return TargetTriple.isWindowsMSVCEnvironment();
764  }
765 
767  return TargetTriple.isKnownWindowsMSVCEnvironment();
768  }
769 
770  bool isTargetWindowsCoreCLR() const {
771  return TargetTriple.isWindowsCoreCLREnvironment();
772  }
773 
774  bool isTargetWindowsCygwin() const {
775  return TargetTriple.isWindowsCygwinEnvironment();
776  }
777 
778  bool isTargetWindowsGNU() const {
779  return TargetTriple.isWindowsGNUEnvironment();
780  }
781 
782  bool isTargetWindowsItanium() const {
783  return TargetTriple.isWindowsItaniumEnvironment();
784  }
785 
786  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
787 
788  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
789 
790  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
791 
792  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
793 
794  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
795  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
796 
797  bool isPICStyleStubPIC() const {
798  return PICStyle == PICStyles::StubPIC;
799  }
800 
801  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
802 
804  switch (CC) {
805  // On Win64, all these conventions just use the default convention.
806  case CallingConv::C:
807  case CallingConv::Fast:
808  case CallingConv::Swift:
814  return isTargetWin64();
815  // This convention allows using the Win64 convention on other targets.
816  case CallingConv::Win64:
817  return true;
818  // This convention allows using the SysV convention on Windows targets.
820  return false;
821  // Otherwise, who knows what this is.
822  default:
823  return false;
824  }
825  }
826 
827  /// Classify a global variable reference for the current subtarget according
828  /// to how we should reference it in a non-pcrel context.
829  unsigned char classifyLocalReference(const GlobalValue *GV) const;
830 
831  unsigned char classifyGlobalReference(const GlobalValue *GV,
832  const Module &M) const;
833  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
834 
835  /// Classify a global function reference for the current subtarget.
836  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
837  const Module &M) const;
838  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
839 
840  /// Classify a blockaddress reference for the current subtarget according to
841  /// how we should reference it in a non-pcrel context.
842  unsigned char classifyBlockAddressReference() const;
843 
844  /// Return true if the subtarget allows calls to immediate address.
845  bool isLegalToCallImmediateAddr() const;
846 
847  /// If we are using retpolines, we need to expand indirectbr to avoid it
848  /// lowering to an actual indirect jump.
849  bool enableIndirectBrExpand() const override {
850  return useRetpolineIndirectBranches();
851  }
852 
853  /// Enable the MachineScheduler pass for all X86 subtargets.
854  bool enableMachineScheduler() const override { return true; }
855 
856  bool enableEarlyIfConversion() const override;
857 
858  void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
859  &Mutations) const override;
860 
861  AntiDepBreakMode getAntiDepBreakMode() const override {
862  return TargetSubtargetInfo::ANTIDEP_CRITICAL;
863  }
864 
865  bool enableAdvancedRASplitCost() const override { return true; }
866 };
867 
868 } // end namespace llvm
869 
870 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
bool hasBF16() const
Definition: X86Subtarget.h:678
bool hasAVX() const
Definition: X86Subtarget.h:575
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:479
bool isTargetPS4() const
Definition: X86Subtarget.h:746
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:536
bool hasSHA() const
Definition: X86Subtarget.h:614
bool hasSSE41() const
Definition: X86Subtarget.h:573
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:617
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool isOSWindows() const
Definition: X86Subtarget.h:788
bool hasPOPCNT() const
Definition: X86Subtarget.h:583
bool hasAVX2() const
Definition: X86Subtarget.h:576
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasFMA() const
Definition: X86Subtarget.h:596
bool hasWBNOINVD() const
Definition: X86Subtarget.h:684
bool hasSlowDivide64() const
Definition: X86Subtarget.h:662
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:617
bool hasRDPID() const
Definition: X86Subtarget.h:685
bool hasSGX() const
Definition: X86Subtarget.h:688
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:495
bool hasCLWB() const
Definition: X86Subtarget.h:683
bool slowLEA() const
Definition: X86Subtarget.h:666
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:497
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:561
bool hasFastVectorShiftMasks() const
Definition: X86Subtarget.h:657
const TargetMachine & TM
Definition: X86Subtarget.h:80
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:854
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:575
bool hasFastBEXTR() const
Definition: X86Subtarget.h:654
bool hasVBMI2() const
Definition: X86Subtarget.h:610
bool isPMADDWDSlow() const
Definition: X86Subtarget.h:633
bool hasCLZERO() const
Definition: X86Subtarget.h:626
bool has3DNowA() const
Definition: X86Subtarget.h:582
bool useAVX512Regs() const
Definition: X86Subtarget.h:713
bool isOSFuchsia() const
Definition: Triple.h:499
bool isTargetNaCl64() const
Definition: X86Subtarget.h:758
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:555
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:766
bool slowTwoMemOps() const
Definition: X86Subtarget.h:664
bool hasPCONFIG() const
Definition: X86Subtarget.h:687
bool hasSHSTK() const
Definition: X86Subtarget.h:681
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:762
bool isTargetMachO() const
Definition: X86Subtarget.h:750
int getGatherOverhead() const
Definition: X86Subtarget.h:636
bool hasXSAVE() const
Definition: X86Subtarget.h:587
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:635
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:797
bool hasVPOPCNTDQ() const
Definition: X86Subtarget.h:670
bool hasPREFETCHWT1() const
Definition: X86Subtarget.h:616
Holds all the information related to register banks.
bool hasLWP() const
Definition: X86Subtarget.h:601
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:795
bool hasFMA4() const
Definition: X86Subtarget.h:597
bool padShortFunctions() const
Definition: X86Subtarget.h:663
bool isTargetSolaris() const
Definition: X86Subtarget.h:745
bool hasAES() const
Definition: X86Subtarget.h:584
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:555
bool isKnownWindowsMSVCEnvironment() const
Checks if the environment is MSVC.
Definition: Triple.h:537
bool hasPKU() const
Definition: X86Subtarget.h:676
bool is32Bit() const
Definition: X86Subtarget.h:540
bool canExtendTo512DQ() const
Definition: X86Subtarget.h:704
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:639
bool hasFastLZCNT() const
Definition: X86Subtarget.h:652
bool useRetpolineExternalThunk() const
Definition: X86Subtarget.h:695
bool isOSSolaris() const
Definition: Triple.h:505
bool hasVLX() const
Definition: X86Subtarget.h:675
bool slow3OpsLEA() const
Definition: X86Subtarget.h:667
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:443
bool hasFastSHLDRotate() const
Definition: X86Subtarget.h:653
bool isTargetNaCl() const
Definition: X86Subtarget.h:756
bool hasNOPL() const
Definition: X86Subtarget.h:565
bool isTargetCygMing() const
Definition: X86Subtarget.h:786
bool hasMOVDIRI() const
Definition: X86Subtarget.h:628
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool hasMPX() const
Definition: X86Subtarget.h:680
bool hasINVPCID() const
Definition: X86Subtarget.h:690
bool hasFastHorizontalOps() const
Definition: X86Subtarget.h:655
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:551
bool isWindowsGNUEnvironment() const
Definition: Triple.h:559
bool hasFSGSBase() const
Definition: X86Subtarget.h:605
bool hasFastVariableShuffle() const
Definition: X86Subtarget.h:643
bool hasDQI() const
Definition: X86Subtarget.h:673
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:547
bool isOSDragonFly() const
Definition: Triple.h:503
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:532
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:491
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:110
bool hasADX() const
Definition: X86Subtarget.h:613
bool isSLM() const
Definition: X86Subtarget.h:727
bool hasSSSE3() const
Definition: X86Subtarget.h:572
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:753
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:622
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:512
bool hasCLDEMOTE() const
Definition: X86Subtarget.h:627
bool hasGFNI() const
Definition: X86Subtarget.h:593
bool isTargetNaCl32() const
Definition: X86Subtarget.h:757
static bool is64Bit(const char *name)
bool isXRaySupported() const override
Definition: X86Subtarget.h:721
bool hasERMSB() const
Definition: X86Subtarget.h:660
bool hasMWAITX() const
Definition: X86Subtarget.h:625
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:638
bool hasF16C() const
Definition: X86Subtarget.h:604
bool hasERI() const
Definition: X86Subtarget.h:672
bool hasPCLMUL() const
Definition: X86Subtarget.h:591
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:157
bool useLeaForSP() const
Definition: X86Subtarget.h:640
bool hasMMX() const
Definition: X86Subtarget.h:580
bool hasFXSR() const
Definition: X86Subtarget.h:586
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:778
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:642
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:743
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:78
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:585
bool isPositionIndependent() const
Definition: X86Subtarget.h:801
bool hasCMov() const
Definition: X86Subtarget.h:568
bool isTargetGlibc() const
Definition: X86Subtarget.h:754
X86ProcFamilyEnum getProcFamily() const
Definition: X86Subtarget.h:723
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:740
bool hasVNNI() const
Definition: X86Subtarget.h:677
bool hasXOP() const
Definition: X86Subtarget.h:599
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:627
bool isTargetDarwin() const
Definition: X86Subtarget.h:742
bool hasSSE42() const
Definition: X86Subtarget.h:574
bool hasX87() const
Definition: X86Subtarget.h:563
bool isTargetMCU() const
Definition: X86Subtarget.h:759
bool isPMULLDSlow() const
Definition: X86Subtarget.h:632
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:691
bool hasPRFCHW() const
Definition: X86Subtarget.h:615
bool isTargetWin64() const
Definition: X86Subtarget.h:790
bool hasSSE3() const
Definition: X86Subtarget.h:571
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool slowIncDec() const
Definition: X86Subtarget.h:668
bool hasBMI2() const
Definition: X86Subtarget.h:608
bool hasVPCLMULQDQ() const
Definition: X86Subtarget.h:592
bool isTargetELF() const
Definition: X86Subtarget.h:748
bool isOSIAMCU() const
Definition: Triple.h:509
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:505
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:446
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:634
bool isAtom() const
TODO: to be removed later and replaced with suitable properties.
Definition: X86Subtarget.h:726
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:516
bool isPICStyleGOT() const
Definition: X86Subtarget.h:794
bool hasMOVDIR64B() const
Definition: X86Subtarget.h:629
bool threewayBranchProfitable() const
Definition: X86Subtarget.h:689
bool hasFastPartialYMMorZMMWrite() const
Definition: X86Subtarget.h:646
bool LEAusesAG() const
Definition: X86Subtarget.h:665
bool has3DNow() const
Definition: X86Subtarget.h:581
bool hasRDSEED() const
Definition: X86Subtarget.h:623
unsigned getPreferVectorWidth() const
Definition: X86Subtarget.h:697
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:580
bool hasVBMI() const
Definition: X86Subtarget.h:609
bool hasBITALG() const
Definition: X86Subtarget.h:679
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:312
bool isTargetWin32() const
Definition: X86Subtarget.h:792
bool hasXSAVEC() const
Definition: X86Subtarget.h:589
bool isTargetAndroid() const
Definition: X86Subtarget.h:755
bool isOSFreeBSD() const
Definition: Triple.h:495
bool canExtendTo512BW() const
Definition: X86Subtarget.h:707
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:549
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:650
bool hasCLFLUSHOPT() const
Definition: X86Subtarget.h:682
bool hasPOPCNTFalseDeps() const
Definition: X86Subtarget.h:641
bool hasIFMA() const
Definition: X86Subtarget.h:611
int getScatterOverhead() const
Definition: X86Subtarget.h:637
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:564
bool enableAdvancedRASplitCost() const override
Definition: X86Subtarget.h:865
bool hasAnyFMA() const
Definition: X86Subtarget.h:598
bool useSoftFloat() const
Definition: X86Subtarget.h:733
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:445
bool useRetpolineIndirectBranches() const
Definition: X86Subtarget.h:692
std::unique_ptr< LegalizerInfo > Legalizer
Definition: X86Subtarget.h:444
bool enableIndirectBrExpand() const override
If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect j...
Definition: X86Subtarget.h:849
bool hasRDRAND() const
Definition: X86Subtarget.h:603
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:624
Provides the logic to select generic machine instructions.
bool is16Bit() const
Definition: X86Subtarget.h:544
bool hasVAES() const
Definition: X86Subtarget.h:585
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:605
unsigned getRequiredVectorWidth() const
Definition: X86Subtarget.h:698
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:139
bool hasPTWRITE() const
Definition: X86Subtarget.h:630
bool useBWIRegs() const
Definition: X86Subtarget.h:717
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:501
bool isTargetDragonFly() const
Definition: X86Subtarget.h:744
bool isPositionIndependent() const
bool isGLM() const
Definition: X86Subtarget.h:728
bool hasInt256() const
Definition: X86Subtarget.h:578
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:143
bool isTargetCOFF() const
Definition: X86Subtarget.h:749
bool isTargetFuchsia() const
Definition: X86Subtarget.h:760
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:782
bool hasSlowDivide32() const
Definition: X86Subtarget.h:661
bool hasCDI() const
Definition: X86Subtarget.h:669
bool hasBranchFusion() const
Definition: X86Subtarget.h:659
bool hasPFI() const
Definition: X86Subtarget.h:671
bool hasMOVBE() const
Definition: X86Subtarget.h:602
bool hasBMI() const
Definition: X86Subtarget.h:607
bool hasXSAVES() const
Definition: X86Subtarget.h:590
bool hasSSE1() const
Definition: X86Subtarget.h:569
bool isTargetLinux() const
Definition: X86Subtarget.h:752
This file describes how to lower LLVM calls to machine code calls.
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:803
bool isSHLDSlow() const
Definition: X86Subtarget.h:631
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:560
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:655
bool hasCmpxchg8b() const
Definition: X86Subtarget.h:564
bool hasMacroFusion() const
Definition: X86Subtarget.h:658
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:153
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:774
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:91
bool hasAVX512() const
Definition: X86Subtarget.h:577
bool hasSSE4A() const
Definition: X86Subtarget.h:579
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool hasBWI() const
Definition: X86Subtarget.h:674
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:861
bool hasFastGather() const
Definition: X86Subtarget.h:649
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:86
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:542
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:440
bool hasTBM() const
Definition: X86Subtarget.h:600
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructio...
Definition: X86BaseInfo.h:508
bool hasWAITPKG() const
Definition: X86Subtarget.h:686
bool hasLZCNT() const
Definition: X86Subtarget.h:606
bool hasMFence() const
Use mfence if we have SSE2 or we&#39;re on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:738
bool hasFastScalarShiftMasks() const
Definition: X86Subtarget.h:656
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:588
bool hasSSE2() const
Definition: X86Subtarget.h:570
bool hasLZCNTFalseDeps() const
Definition: X86Subtarget.h:642
bool hasRTM() const
Definition: X86Subtarget.h:612
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:651
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:770