LLVM 17.0.0git
X86Subtarget.h
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1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the X86 specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15
16#include "X86FrameLowering.h"
17#include "X86ISelLowering.h"
18#include "X86InstrInfo.h"
19#include "X86SelectionDAGInfo.h"
21#include "llvm/IR/CallingConv.h"
23#include <climits>
24#include <memory>
25
26#define GET_SUBTARGETINFO_HEADER
27#include "X86GenSubtargetInfo.inc"
28
29namespace llvm {
30
31class CallLowering;
32class GlobalValue;
33class InstructionSelector;
34class LegalizerInfo;
35class RegisterBankInfo;
36class StringRef;
37class TargetMachine;
38
39/// The X86 backend supports a number of different styles of PIC.
40///
41namespace PICStyles {
42
43enum class Style {
44 StubPIC, // Used on i386-darwin in pic mode.
45 GOT, // Used on 32 bit elf on when in pic mode.
46 RIPRel, // Used on X86-64 when in pic mode.
47 None // Set when not in pic mode.
48};
49
50} // end namespace PICStyles
51
52class X86Subtarget final : public X86GenSubtargetInfo {
53 enum X86SSEEnum {
54 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
55 };
56
57 enum X863DNowEnum {
58 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
59 };
60
61 /// Which PIC style to use
62 PICStyles::Style PICStyle;
63
64 const TargetMachine &TM;
65
66 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
67 X86SSEEnum X86SSELevel = NoSSE;
68
69 /// MMX, 3DNow, 3DNow Athlon, or none supported.
70 X863DNowEnum X863DNowLevel = NoThreeDNow;
71
72#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
73 bool ATTRIBUTE = DEFAULT;
74#include "X86GenSubtargetInfo.inc"
75 /// The minimum alignment known to hold of the stack frame on
76 /// entry to the function and which must be maintained by every function.
77 Align stackAlignment = Align(4);
78
79 Align TileConfigAlignment = Align(4);
80
81 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
82 ///
83 // FIXME: this is a known good value for Yonah. How about others?
84 unsigned MaxInlineSizeThreshold = 128;
85
86 /// What processor and OS we're targeting.
87 Triple TargetTriple;
88
89 /// GlobalISel related APIs.
90 std::unique_ptr<CallLowering> CallLoweringInfo;
91 std::unique_ptr<LegalizerInfo> Legalizer;
92 std::unique_ptr<RegisterBankInfo> RegBankInfo;
93 std::unique_ptr<InstructionSelector> InstSelector;
94
95 /// Override the stack alignment.
96 MaybeAlign StackAlignOverride;
97
98 /// Preferred vector width from function attribute.
99 unsigned PreferVectorWidthOverride;
100
101 /// Resolved preferred vector width from function attribute and subtarget
102 /// features.
103 unsigned PreferVectorWidth = UINT32_MAX;
104
105 /// Required vector width from function attribute.
106 unsigned RequiredVectorWidth;
107
108 X86SelectionDAGInfo TSInfo;
109 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
110 // X86TargetLowering needs.
111 X86InstrInfo InstrInfo;
112 X86TargetLowering TLInfo;
113 X86FrameLowering FrameLowering;
114
115public:
116 /// This constructor initializes the data members to match that
117 /// of the specified triple.
118 ///
119 X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
120 const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
121 unsigned PreferVectorWidthOverride,
122 unsigned RequiredVectorWidth);
123
124 const X86TargetLowering *getTargetLowering() const override {
125 return &TLInfo;
126 }
127
128 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
129
130 const X86FrameLowering *getFrameLowering() const override {
131 return &FrameLowering;
132 }
133
134 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
135 return &TSInfo;
136 }
137
138 const X86RegisterInfo *getRegisterInfo() const override {
139 return &getInstrInfo()->getRegisterInfo();
140 }
141
142 unsigned getTileConfigSize() const { return 64; }
143 Align getTileConfigAlignment() const { return TileConfigAlignment; }
144
145 /// Returns the minimum alignment known to hold of the
146 /// stack frame on entry to the function and which must be maintained by every
147 /// function for this subtarget.
148 Align getStackAlignment() const { return stackAlignment; }
149
150 /// Returns the maximum memset / memcpy size
151 /// that still makes it profitable to inline the call.
152 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
153
154 /// ParseSubtargetFeatures - Parses features string setting specified
155 /// subtarget options. Definition of function is auto generated by tblgen.
157
158 /// Methods used by Global ISel
159 const CallLowering *getCallLowering() const override;
161 const LegalizerInfo *getLegalizerInfo() const override;
162 const RegisterBankInfo *getRegBankInfo() const override;
163
164private:
165 /// Initialize the full set of dependencies so we can use an initializer
166 /// list for X86Subtarget.
167 X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
168 StringRef TuneCPU,
169 StringRef FS);
170 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
171
172public:
173
174#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
175 bool GETTER() const { return ATTRIBUTE; }
176#include "X86GenSubtargetInfo.inc"
177
178 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
179 bool isTarget64BitILP32() const {
180 return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
181 }
182
183 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
184 bool isTarget64BitLP64() const {
185 return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
186 }
187
188 PICStyles::Style getPICStyle() const { return PICStyle; }
189 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
190
191 bool canUseCMPXCHG8B() const { return hasCX8(); }
192 bool canUseCMPXCHG16B() const {
193 // CX16 is just the CPUID bit, instruction requires 64-bit mode too.
194 return hasCX16() && is64Bit();
195 }
196 // SSE codegen depends on cmovs, and all SSE1+ processors support them.
197 // All 64-bit processors support cmov.
198 bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); }
199 bool hasSSE1() const { return X86SSELevel >= SSE1; }
200 bool hasSSE2() const { return X86SSELevel >= SSE2; }
201 bool hasSSE3() const { return X86SSELevel >= SSE3; }
202 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
203 bool hasSSE41() const { return X86SSELevel >= SSE41; }
204 bool hasSSE42() const { return X86SSELevel >= SSE42; }
205 bool hasAVX() const { return X86SSELevel >= AVX; }
206 bool hasAVX2() const { return X86SSELevel >= AVX2; }
207 bool hasAVX512() const { return X86SSELevel >= AVX512; }
208 bool hasInt256() const { return hasAVX2(); }
209 bool hasMMX() const { return X863DNowLevel >= MMX; }
210 bool hasThreeDNow() const { return X863DNowLevel >= ThreeDNow; }
211 bool hasThreeDNowA() const { return X863DNowLevel >= ThreeDNowA; }
212 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
213 bool hasPrefetchW() const {
214 // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
215 // its own CPUID bit as part of deprecating 3DNow. Intel eventually added
216 // it and KNL has another that prefetches to L2 cache. We assume the
217 // L1 version exists if the L2 version does.
218 return hasThreeDNow() || hasPRFCHW() || hasPREFETCHWT1();
219 }
220 bool hasSSEPrefetch() const {
221 // We implicitly enable these when we have a write prefix supporting cache
222 // level OR if we have prfchw, but don't already have a read prefetch from
223 // 3dnow.
224 return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1() ||
225 hasPREFETCHI();
226 }
227 bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); }
228 // These are generic getters that OR together all of the thunk types
229 // supported by the subtarget. Therefore useIndirectThunk*() will return true
230 // if any respective thunk feature is enabled.
232 return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
233 }
235 return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
236 }
237
238 unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
239 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
240
241 // Helper functions to determine when we should allow widening to 512-bit
242 // during codegen.
243 // TODO: Currently we're always allowing widening on CPUs without VLX,
244 // because for many cases we don't have a better option.
245 bool canExtendTo512DQ() const {
246 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
247 }
248 bool canExtendTo512BW() const {
249 return hasBWI() && canExtendTo512DQ();
250 }
251
252 bool hasNoDomainDelay() const { return NoDomainDelay; }
253 bool hasNoDomainDelayMov() const {
254 return hasNoDomainDelay() || NoDomainDelayMov;
255 }
257 return hasNoDomainDelay() || NoDomainDelayBlend;
258 }
260 return hasNoDomainDelay() || NoDomainDelayShuffle;
261 }
262
263 // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
264 // disable them in the legalizer.
265 bool useAVX512Regs() const {
266 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
267 }
268
270 return getPreferVectorWidth() >= 256 || AllowLight256Bit;
271 }
272
273 bool useBWIRegs() const {
274 return hasBWI() && useAVX512Regs();
275 }
276
277 bool isXRaySupported() const override { return is64Bit(); }
278
279 /// Use clflush if we have SSE2 or we're on x86-64 (even if we asked for
280 /// no-sse2). There isn't any reason to disable it if the target processor
281 /// supports it.
282 bool hasCLFLUSH() const { return hasSSE2() || is64Bit(); }
283
284 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
285 /// no-sse2). There isn't any reason to disable it if the target processor
286 /// supports it.
287 bool hasMFence() const { return hasSSE2() || is64Bit(); }
288
289 const Triple &getTargetTriple() const { return TargetTriple; }
290
291 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
292 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
293 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
294 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
295 bool isTargetPS() const { return TargetTriple.isPS(); }
296
297 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
298 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
299 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
300
301 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
302 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
303 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
304 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
305 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
306 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
307 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
308 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
309 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
310
311 bool isTargetWindowsMSVC() const {
312 return TargetTriple.isWindowsMSVCEnvironment();
313 }
314
316 return TargetTriple.isWindowsCoreCLREnvironment();
317 }
318
320 return TargetTriple.isWindowsCygwinEnvironment();
321 }
322
323 bool isTargetWindowsGNU() const {
324 return TargetTriple.isWindowsGNUEnvironment();
325 }
326
328 return TargetTriple.isWindowsItaniumEnvironment();
329 }
330
331 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
332
333 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
334
335 bool isTargetWin64() const { return Is64Bit && isOSWindows(); }
336
337 bool isTargetWin32() const { return !Is64Bit && isOSWindows(); }
338
339 bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
340 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
341
342 bool isPICStyleStubPIC() const {
343 return PICStyle == PICStyles::Style::StubPIC;
344 }
345
346 bool isPositionIndependent() const;
347
349 switch (CC) {
350 // On Win64, all these conventions just use the default convention.
351 case CallingConv::C:
361 return isTargetWin64();
362 // This convention allows using the Win64 convention on other targets.
364 return true;
365 // This convention allows using the SysV convention on Windows targets.
367 return false;
368 // Otherwise, who knows what this is.
369 default:
370 return false;
371 }
372 }
373
374 /// Classify a global variable reference for the current subtarget according
375 /// to how we should reference it in a non-pcrel context.
376 unsigned char classifyLocalReference(const GlobalValue *GV) const;
377
378 unsigned char classifyGlobalReference(const GlobalValue *GV,
379 const Module &M) const;
380 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
381
382 /// Classify a global function reference for the current subtarget.
383 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
384 const Module &M) const;
385 unsigned char
386 classifyGlobalFunctionReference(const GlobalValue *GV) const override;
387
388 /// Classify a blockaddress reference for the current subtarget according to
389 /// how we should reference it in a non-pcrel context.
390 unsigned char classifyBlockAddressReference() const;
391
392 /// Return true if the subtarget allows calls to immediate address.
393 bool isLegalToCallImmediateAddr() const;
394
395 /// Return whether FrameLowering should always set the "extended frame
396 /// present" bit in FP, or set it based on a symbol in the runtime.
398 // Older OS versions (particularly system unwinders) are confused by the
399 // Swift extended frame, so when building code that might be run on them we
400 // must dynamically query the concurrency library to determine whether
401 // extended frames should be flagged as present.
402 const Triple &TT = getTargetTriple();
403
404 unsigned Major = TT.getOSVersion().getMajor();
405 switch(TT.getOS()) {
406 default:
407 return false;
408 case Triple::IOS:
409 case Triple::TvOS:
410 return Major < 15;
411 case Triple::WatchOS:
412 return Major < 8;
413 case Triple::MacOSX:
414 case Triple::Darwin:
415 return Major < 12;
416 }
417 }
418
419 /// If we are using indirect thunks, we need to expand indirectbr to avoid it
420 /// lowering to an actual indirect jump.
421 bool enableIndirectBrExpand() const override {
423 }
424
425 /// Enable the MachineScheduler pass for all X86 subtargets.
426 bool enableMachineScheduler() const override { return true; }
427
428 bool enableEarlyIfConversion() const override;
429
430 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
431 &Mutations) const override;
432
433 AntiDepBreakMode getAntiDepBreakMode() const override {
434 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
435 }
436};
437
438} // end namespace llvm
439
440#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
const char LLVMTargetMachineRef TM
return InstrInfo
static bool is64Bit(const char *name)
Provides the logic to select generic machine instructions.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDragonFly() const
Definition: Triple.h:553
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:633
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:622
bool isX32() const
Tests whether the target is X32.
Definition: Triple.h:965
bool isWindowsGNUEnvironment() const
Definition: Triple.h:617
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:725
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:688
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:605
bool isOSSolaris() const
Definition: Triple.h:555
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:643
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:680
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:584
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:638
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:613
bool isOSFreeBSD() const
Definition: Triple.h:545
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:519
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:663
bool isPS() const
Tests whether the target is the PS4 or PS5 platform.
Definition: Triple.h:722
bool isOSIAMCU() const
Definition: Triple.h:559
bool isOSFuchsia() const
Definition: Triple.h:549
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:594
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:609
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:157
bool canExtendTo512BW() const
Definition: X86Subtarget.h:248
bool hasAnyFMA() const
Definition: X86Subtarget.h:212
bool enableEarlyIfConversion() const override
bool isOSWindows() const
Definition: X86Subtarget.h:333
bool isTargetMachO() const
Definition: X86Subtarget.h:299
unsigned getTileConfigSize() const
Definition: X86Subtarget.h:142
bool canUseLAHFSAHF() const
Definition: X86Subtarget.h:227
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:302
bool isXRaySupported() const override
Definition: X86Subtarget.h:277
unsigned getRequiredVectorWidth() const
Definition: X86Subtarget.h:239
bool useIndirectThunkBranches() const
Definition: X86Subtarget.h:234
bool hasSSE1() const
Definition: X86Subtarget.h:199
bool useLight256BitInstructions() const
Definition: X86Subtarget.h:269
bool isTargetSolaris() const
Definition: X86Subtarget.h:294
bool hasThreeDNow() const
Definition: X86Subtarget.h:210
bool isPICStyleGOT() const
Definition: X86Subtarget.h:339
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:319
bool hasSSE42() const
Definition: X86Subtarget.h:204
InstructionSelector * getInstructionSelector() const override
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:124
bool hasMFence() const
Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:287
bool hasNoDomainDelayBlend() const
Definition: X86Subtarget.h:256
Align getTileConfigAlignment() const
Definition: X86Subtarget.h:143
bool isTargetMCU() const
Definition: X86Subtarget.h:308
bool isTargetDragonFly() const
Definition: X86Subtarget.h:293
bool canUseCMOV() const
Definition: X86Subtarget.h:198
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:342
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:426
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:311
bool canUseCMPXCHG8B() const
Definition: X86Subtarget.h:191
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:179
bool hasNoDomainDelayShuffle() const
Definition: X86Subtarget.h:259
bool isTargetDarwin() const
Definition: X86Subtarget.h:291
bool isTargetWin64() const
Definition: X86Subtarget.h:335
bool hasPrefetchW() const
Definition: X86Subtarget.h:213
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:184
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: X86Subtarget.h:397
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:289
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:433
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:315
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:128
const RegisterBankInfo * getRegBankInfo() const override
bool useAVX512Regs() const
Definition: X86Subtarget.h:265
bool isTargetCOFF() const
Definition: X86Subtarget.h:298
bool hasSSE3() const
Definition: X86Subtarget.h:201
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:348
bool isTargetNaCl() const
Definition: X86Subtarget.h:305
bool hasAVX512() const
Definition: X86Subtarget.h:207
bool canExtendTo512DQ() const
Definition: X86Subtarget.h:245
bool hasSSE41() const
Definition: X86Subtarget.h:203
bool hasMMX() const
Definition: X86Subtarget.h:209
Align getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:148
bool isTargetELF() const
Definition: X86Subtarget.h:297
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:220
bool canUseCMPXCHG16B() const
Definition: X86Subtarget.h:192
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
const LegalizerInfo * getLegalizerInfo() const override
bool isPositionIndependent() const
bool hasSSE2() const
Definition: X86Subtarget.h:200
bool hasThreeDNowA() const
Definition: X86Subtarget.h:211
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:292
bool isTargetGlibc() const
Definition: X86Subtarget.h:303
bool isTargetFuchsia() const
Definition: X86Subtarget.h:309
bool hasSSSE3() const
Definition: X86Subtarget.h:202
bool hasInt256() const
Definition: X86Subtarget.h:208
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:340
bool isTargetCygMing() const
Definition: X86Subtarget.h:331
bool hasNoDomainDelay() const
Definition: X86Subtarget.h:252
bool isTargetNaCl32() const
Definition: X86Subtarget.h:306
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:188
bool enableIndirectBrExpand() const override
If we are using indirect thunks, we need to expand indirectbr to avoid it lowering to an actual indir...
Definition: X86Subtarget.h:421
bool hasNoDomainDelayMov() const
Definition: X86Subtarget.h:253
bool isTargetPS() const
Definition: X86Subtarget.h:295
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:138
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:189
bool hasAVX() const
Definition: X86Subtarget.h:205
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:323
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition: X86Subtarget.h:152
unsigned getPreferVectorWidth() const
Definition: X86Subtarget.h:238
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:327
bool isTargetAndroid() const
Definition: X86Subtarget.h:304
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
bool isTargetNaCl64() const
Definition: X86Subtarget.h:307
bool hasCLFLUSH() const
Use clflush if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:282
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:130
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
bool useBWIRegs() const
Definition: X86Subtarget.h:273
bool isTargetWin32() const
Definition: X86Subtarget.h:337
bool useIndirectThunkCalls() const
Definition: X86Subtarget.h:231
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
bool hasAVX2() const
Definition: X86Subtarget.h:206
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:134
bool isTargetLinux() const
Definition: X86Subtarget.h:301
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:148
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ X86_ThisCall
Similar to X86_StdCall.
Definition: CallingConv.h:119
@ X86_StdCall
stdcall is mostly used by the Win32 API.
Definition: CallingConv.h:96
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ X86_VectorCall
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:160
@ Intel_OCL_BI
Used for Intel OpenCL built-ins.
Definition: CallingConv.h:144
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:156
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ X86_FastCall
'fast' analog of X86_StdCall.
Definition: CallingConv.h:100
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117