LLVM  14.0.0git
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 
16 #include "X86FrameLowering.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86SelectionDAGInfo.h"
20 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include <climits>
24 #include <memory>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
28 
29 namespace llvm {
30 
31 class CallLowering;
32 class GlobalValue;
33 class InstructionSelector;
34 class LegalizerInfo;
35 class RegisterBankInfo;
36 class StringRef;
37 class TargetMachine;
38 
39 /// The X86 backend supports a number of different styles of PIC.
40 ///
41 namespace PICStyles {
42 
43 enum class Style {
44  StubPIC, // Used on i386-darwin in pic mode.
45  GOT, // Used on 32 bit elf on when in pic mode.
46  RIPRel, // Used on X86-64 when in pic mode.
47  None // Set when not in pic mode.
48 };
49 
50 } // end namespace PICStyles
51 
52 class X86Subtarget final : public X86GenSubtargetInfo {
53  // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
54  // are not a good idea. We should be migrating away from these.
55  enum X86ProcFamilyEnum {
56  Others,
57  IntelAtom,
58  IntelSLM
59  };
60 
61  enum X86SSEEnum {
62  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
63  };
64 
65  enum X863DNowEnum {
66  NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
67  };
68 
69  /// X86 processor family: Intel Atom, and others
70  X86ProcFamilyEnum X86ProcFamily = Others;
71 
72  /// Which PIC style to use
73  PICStyles::Style PICStyle;
74 
75  const TargetMachine &TM;
76 
77  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
78  X86SSEEnum X86SSELevel = NoSSE;
79 
80  /// MMX, 3DNow, 3DNow Athlon, or none supported.
81  X863DNowEnum X863DNowLevel = NoThreeDNow;
82 
83  /// True if the processor supports X87 instructions.
84  bool HasX87 = false;
85 
86  /// True if the processor supports CMPXCHG8B.
87  bool HasCmpxchg8b = false;
88 
89  /// True if this processor has NOPL instruction
90  /// (generally pentium pro+).
91  bool HasNOPL = false;
92 
93  /// True if this processor has conditional move instructions
94  /// (generally pentium pro+).
95  bool HasCMov = false;
96 
97  /// True if the processor supports X86-64 instructions.
98  bool HasX86_64 = false;
99 
100  /// True if the processor supports POPCNT.
101  bool HasPOPCNT = false;
102 
103  /// True if the processor supports SSE4A instructions.
104  bool HasSSE4A = false;
105 
106  /// Target has AES instructions
107  bool HasAES = false;
108  bool HasVAES = false;
109 
110  /// Target has FXSAVE/FXRESTOR instructions
111  bool HasFXSR = false;
112 
113  /// Target has XSAVE instructions
114  bool HasXSAVE = false;
115 
116  /// Target has XSAVEOPT instructions
117  bool HasXSAVEOPT = false;
118 
119  /// Target has XSAVEC instructions
120  bool HasXSAVEC = false;
121 
122  /// Target has XSAVES instructions
123  bool HasXSAVES = false;
124 
125  /// Target has carry-less multiplication
126  bool HasPCLMUL = false;
127  bool HasVPCLMULQDQ = false;
128 
129  /// Target has Galois Field Arithmetic instructions
130  bool HasGFNI = false;
131 
132  /// Target has 3-operand fused multiply-add
133  bool HasFMA = false;
134 
135  /// Target has 4-operand fused multiply-add
136  bool HasFMA4 = false;
137 
138  /// Target has XOP instructions
139  bool HasXOP = false;
140 
141  /// Target has TBM instructions.
142  bool HasTBM = false;
143 
144  /// Target has LWP instructions
145  bool HasLWP = false;
146 
147  /// True if the processor has the MOVBE instruction.
148  bool HasMOVBE = false;
149 
150  /// True if the processor has the RDRAND instruction.
151  bool HasRDRAND = false;
152 
153  /// Processor has 16-bit floating point conversion instructions.
154  bool HasF16C = false;
155 
156  /// Processor has FS/GS base insturctions.
157  bool HasFSGSBase = false;
158 
159  /// Processor has LZCNT instruction.
160  bool HasLZCNT = false;
161 
162  /// Processor has BMI1 instructions.
163  bool HasBMI = false;
164 
165  /// Processor has BMI2 instructions.
166  bool HasBMI2 = false;
167 
168  /// Processor has VBMI instructions.
169  bool HasVBMI = false;
170 
171  /// Processor has VBMI2 instructions.
172  bool HasVBMI2 = false;
173 
174  /// Processor has Integer Fused Multiply Add
175  bool HasIFMA = false;
176 
177  /// Processor has RTM instructions.
178  bool HasRTM = false;
179 
180  /// Processor has ADX instructions.
181  bool HasADX = false;
182 
183  /// Processor has SHA instructions.
184  bool HasSHA = false;
185 
186  /// Processor has PRFCHW instructions.
187  bool HasPRFCHW = false;
188 
189  /// Processor has RDSEED instructions.
190  bool HasRDSEED = false;
191 
192  /// Processor has LAHF/SAHF instructions in 64-bit mode.
193  bool HasLAHFSAHF64 = false;
194 
195  /// Processor has MONITORX/MWAITX instructions.
196  bool HasMWAITX = false;
197 
198  /// Processor has Cache Line Zero instruction
199  bool HasCLZERO = false;
200 
201  /// Processor has Cache Line Demote instruction
202  bool HasCLDEMOTE = false;
203 
204  /// Processor has MOVDIRI instruction (direct store integer).
205  bool HasMOVDIRI = false;
206 
207  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
208  bool HasMOVDIR64B = false;
209 
210  /// Processor has ptwrite instruction.
211  bool HasPTWRITE = false;
212 
213  /// Processor has Prefetch with intent to Write instruction
214  bool HasPREFETCHWT1 = false;
215 
216  /// True if SHLD instructions are slow.
217  bool IsSHLDSlow = false;
218 
219  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
220  // PMULUDQ.
221  bool IsPMULLDSlow = false;
222 
223  /// True if the PMADDWD instruction is slow compared to PMULLD.
224  bool IsPMADDWDSlow = false;
225 
226  /// True if unaligned memory accesses of 16-bytes are slow.
227  bool IsUAMem16Slow = false;
228 
229  /// True if unaligned memory accesses of 32-bytes are slow.
230  bool IsUAMem32Slow = false;
231 
232  /// True if SSE operations can have unaligned memory operands.
233  /// This may require setting a configuration bit in the processor.
234  bool HasSSEUnalignedMem = false;
235 
236  /// True if this processor has the CMPXCHG16B instruction;
237  /// this is true for most x86-64 chips, but not the first AMD chips.
238  bool HasCmpxchg16b = false;
239 
240  /// True if the LEA instruction should be used for adjusting
241  /// the stack pointer. This is an optimization for Intel Atom processors.
242  bool UseLeaForSP = false;
243 
244  /// True if POPCNT instruction has a false dependency on the destination register.
245  bool HasPOPCNTFalseDeps = false;
246 
247  /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
248  bool HasLZCNTFalseDeps = false;
249 
250  /// True if its preferable to combine to a single cross-lane shuffle
251  /// using a variable mask over multiple fixed shuffles.
252  bool HasFastVariableCrossLaneShuffle = false;
253 
254  /// True if its preferable to combine to a single per-lane shuffle
255  /// using a variable mask over multiple fixed shuffles.
256  bool HasFastVariablePerLaneShuffle = false;
257 
258  /// True if vzeroupper instructions should be inserted after code that uses
259  /// ymm or zmm registers.
260  bool InsertVZEROUPPER = false;
261 
262  /// True if there is no performance penalty for writing NOPs with up to
263  /// 7 bytes.
264  bool HasFast7ByteNOP = false;
265 
266  /// True if there is no performance penalty for writing NOPs with up to
267  /// 11 bytes.
268  bool HasFast11ByteNOP = false;
269 
270  /// True if there is no performance penalty for writing NOPs with up to
271  /// 15 bytes.
272  bool HasFast15ByteNOP = false;
273 
274  /// True if gather is reasonably fast. This is true for Skylake client and
275  /// all AVX-512 CPUs.
276  bool HasFastGather = false;
277 
278  /// True if hardware SQRTSS instruction is at least as fast (latency) as
279  /// RSQRTSS followed by a Newton-Raphson iteration.
280  bool HasFastScalarFSQRT = false;
281 
282  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
283  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
284  bool HasFastVectorFSQRT = false;
285 
286  /// True if 8-bit divisions are significantly faster than
287  /// 32-bit divisions and should be used when possible.
288  bool HasSlowDivide32 = false;
289 
290  /// True if 32-bit divides are significantly faster than
291  /// 64-bit divisions and should be used when possible.
292  bool HasSlowDivide64 = false;
293 
294  /// True if LZCNT instruction is fast.
295  bool HasFastLZCNT = false;
296 
297  /// True if SHLD based rotate is fast.
298  bool HasFastSHLDRotate = false;
299 
300  /// True if the processor supports macrofusion.
301  bool HasMacroFusion = false;
302 
303  /// True if the processor supports branch fusion.
304  bool HasBranchFusion = false;
305 
306  /// True if the processor has enhanced REP MOVSB/STOSB.
307  bool HasERMSB = false;
308 
309  /// True if the processor has fast short REP MOV.
310  bool HasFSRM = false;
311 
312  /// True if the short functions should be padded to prevent
313  /// a stall when returning too early.
314  bool PadShortFunctions = false;
315 
316  /// True if two memory operand instructions should use a temporary register
317  /// instead.
318  bool SlowTwoMemOps = false;
319 
320  /// True if the LEA instruction inputs have to be ready at address generation
321  /// (AG) time.
322  bool LEAUsesAG = false;
323 
324  /// True if the LEA instruction with certain arguments is slow
325  bool SlowLEA = false;
326 
327  /// True if the LEA instruction has all three source operands: base, index,
328  /// and offset or if the LEA instruction uses base and index registers where
329  /// the base is EBP, RBP,or R13
330  bool Slow3OpsLEA = false;
331 
332  /// True if INC and DEC instructions are slow when writing to flags
333  bool SlowIncDec = false;
334 
335  /// Processor has AVX-512 PreFetch Instructions
336  bool HasPFI = false;
337 
338  /// Processor has AVX-512 Exponential and Reciprocal Instructions
339  bool HasERI = false;
340 
341  /// Processor has AVX-512 Conflict Detection Instructions
342  bool HasCDI = false;
343 
344  /// Processor has AVX-512 population count Instructions
345  bool HasVPOPCNTDQ = false;
346 
347  /// Processor has AVX-512 Doubleword and Quadword instructions
348  bool HasDQI = false;
349 
350  /// Processor has AVX-512 Byte and Word instructions
351  bool HasBWI = false;
352 
353  /// Processor has AVX-512 Vector Length eXtenstions
354  bool HasVLX = false;
355 
356  /// Processor has AVX-512 16 bit floating-point extenstions
357  bool HasFP16 = false;
358 
359  /// Processor has PKU extenstions
360  bool HasPKU = false;
361 
362  /// Processor has AVX-512 Vector Neural Network Instructions
363  bool HasVNNI = false;
364 
365  /// Processor has AVX Vector Neural Network Instructions
366  bool HasAVXVNNI = false;
367 
368  /// Processor has AVX-512 bfloat16 floating-point extensions
369  bool HasBF16 = false;
370 
371  /// Processor supports ENQCMD instructions
372  bool HasENQCMD = false;
373 
374  /// Processor has AVX-512 Bit Algorithms instructions
375  bool HasBITALG = false;
376 
377  /// Processor has AVX-512 vp2intersect instructions
378  bool HasVP2INTERSECT = false;
379 
380  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
381  /// using Shadow Stack
382  bool HasSHSTK = false;
383 
384  /// Processor supports Invalidate Process-Context Identifier
385  bool HasINVPCID = false;
386 
387  /// Processor has Software Guard Extensions
388  bool HasSGX = false;
389 
390  /// Processor supports Flush Cache Line instruction
391  bool HasCLFLUSHOPT = false;
392 
393  /// Processor supports Cache Line Write Back instruction
394  bool HasCLWB = false;
395 
396  /// Processor supports Write Back No Invalidate instruction
397  bool HasWBNOINVD = false;
398 
399  /// Processor support RDPID instruction
400  bool HasRDPID = false;
401 
402  /// Processor supports WaitPKG instructions
403  bool HasWAITPKG = false;
404 
405  /// Processor supports PCONFIG instruction
406  bool HasPCONFIG = false;
407 
408  /// Processor support key locker instructions
409  bool HasKL = false;
410 
411  /// Processor support key locker wide instructions
412  bool HasWIDEKL = false;
413 
414  /// Processor supports HRESET instruction
415  bool HasHRESET = false;
416 
417  /// Processor supports SERIALIZE instruction
418  bool HasSERIALIZE = false;
419 
420  /// Processor supports TSXLDTRK instruction
421  bool HasTSXLDTRK = false;
422 
423  /// Processor has AMX support
424  bool HasAMXTILE = false;
425  bool HasAMXBF16 = false;
426  bool HasAMXINT8 = false;
427 
428  /// Processor supports User Level Interrupt instructions
429  bool HasUINTR = false;
430 
431  /// Enable SSE4.2 CRC32 instruction (Used when SSE4.2 is supported but
432  /// function is GPR only)
433  bool HasCRC32 = false;
434 
435  /// Processor has a single uop BEXTR implementation.
436  bool HasFastBEXTR = false;
437 
438  /// Try harder to combine to horizontal vector ops if they are fast.
439  bool HasFastHorizontalOps = false;
440 
441  /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
442  bool HasFastScalarShiftMasks = false;
443 
444  /// Prefer a left/right vector logical shifts pair over a shift+and pair.
445  bool HasFastVectorShiftMasks = false;
446 
447  /// Prefer a movbe over a single-use load + bswap / single-use bswap + store.
448  bool HasFastMOVBE = false;
449 
450  /// Use a retpoline thunk rather than indirect calls to block speculative
451  /// execution.
452  bool UseRetpolineIndirectCalls = false;
453 
454  /// Use a retpoline thunk or remove any indirect branch to block speculative
455  /// execution.
456  bool UseRetpolineIndirectBranches = false;
457 
458  /// Deprecated flag, query `UseRetpolineIndirectCalls` and
459  /// `UseRetpolineIndirectBranches` instead.
460  bool DeprecatedUseRetpoline = false;
461 
462  /// When using a retpoline thunk, call an externally provided thunk rather
463  /// than emitting one inside the compiler.
464  bool UseRetpolineExternalThunk = false;
465 
466  /// Prevent generation of indirect call/branch instructions from memory,
467  /// and force all indirect call/branch instructions from a register to be
468  /// preceded by an LFENCE. Also decompose RET instructions into a
469  /// POP+LFENCE+JMP sequence.
470  bool UseLVIControlFlowIntegrity = false;
471 
472  /// Enable Speculative Execution Side Effect Suppression
473  bool UseSpeculativeExecutionSideEffectSuppression = false;
474 
475  /// Insert LFENCE instructions to prevent data speculatively injected into
476  /// loads from being used maliciously.
477  bool UseLVILoadHardening = false;
478 
479  /// Use software floating point for code generation.
480  bool UseSoftFloat = false;
481 
482  /// Use alias analysis during code generation.
483  bool UseAA = false;
484 
485  /// The minimum alignment known to hold of the stack frame on
486  /// entry to the function and which must be maintained by every function.
487  Align stackAlignment = Align(4);
488 
489  Align TileConfigAlignment = Align(4);
490 
491  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
492  ///
493  // FIXME: this is a known good value for Yonah. How about others?
494  unsigned MaxInlineSizeThreshold = 128;
495 
496  /// Indicates target prefers 128 bit instructions.
497  bool Prefer128Bit = false;
498 
499  /// Indicates target prefers 256 bit instructions.
500  bool Prefer256Bit = false;
501 
502  /// Indicates target prefers AVX512 mask registers.
503  bool PreferMaskRegisters = false;
504 
505  /// Use Goldmont specific floating point div/sqrt costs.
506  bool UseGLMDivSqrtCosts = false;
507 
508  /// What processor and OS we're targeting.
509  Triple TargetTriple;
510 
511  /// GlobalISel related APIs.
512  std::unique_ptr<CallLowering> CallLoweringInfo;
513  std::unique_ptr<LegalizerInfo> Legalizer;
514  std::unique_ptr<RegisterBankInfo> RegBankInfo;
515  std::unique_ptr<InstructionSelector> InstSelector;
516 
517 private:
518  /// Override the stack alignment.
519  MaybeAlign StackAlignOverride;
520 
521  /// Preferred vector width from function attribute.
522  unsigned PreferVectorWidthOverride;
523 
524  /// Resolved preferred vector width from function attribute and subtarget
525  /// features.
526  unsigned PreferVectorWidth = UINT32_MAX;
527 
528  /// Required vector width from function attribute.
529  unsigned RequiredVectorWidth;
530 
531  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
532  bool In64BitMode = false;
533 
534  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
535  bool In32BitMode = false;
536 
537  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
538  bool In16BitMode = false;
539 
540  X86SelectionDAGInfo TSInfo;
541  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
542  // X86TargetLowering needs.
543  X86InstrInfo InstrInfo;
544  X86TargetLowering TLInfo;
545  X86FrameLowering FrameLowering;
546 
547 public:
548  /// This constructor initializes the data members to match that
549  /// of the specified triple.
550  ///
551  X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
552  const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
553  unsigned PreferVectorWidthOverride,
554  unsigned RequiredVectorWidth);
555 
556  const X86TargetLowering *getTargetLowering() const override {
557  return &TLInfo;
558  }
559 
560  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
561 
562  const X86FrameLowering *getFrameLowering() const override {
563  return &FrameLowering;
564  }
565 
566  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
567  return &TSInfo;
568  }
569 
570  const X86RegisterInfo *getRegisterInfo() const override {
571  return &getInstrInfo()->getRegisterInfo();
572  }
573 
574  unsigned getTileConfigSize() const { return 64; }
575  Align getTileConfigAlignment() const { return TileConfigAlignment; }
576 
577  /// Returns the minimum alignment known to hold of the
578  /// stack frame on entry to the function and which must be maintained by every
579  /// function for this subtarget.
580  Align getStackAlignment() const { return stackAlignment; }
581 
582  /// Returns the maximum memset / memcpy size
583  /// that still makes it profitable to inline the call.
584  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
585 
586  /// ParseSubtargetFeatures - Parses features string setting specified
587  /// subtarget options. Definition of function is auto generated by tblgen.
589 
590  /// Methods used by Global ISel
591  const CallLowering *getCallLowering() const override;
593  const LegalizerInfo *getLegalizerInfo() const override;
594  const RegisterBankInfo *getRegBankInfo() const override;
595 
596 private:
597  /// Initialize the full set of dependencies so we can use an initializer
598  /// list for X86Subtarget.
599  X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
600  StringRef TuneCPU,
601  StringRef FS);
602  void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
603 
604 public:
605  /// Is this x86_64? (disregarding specific ABI / programming model)
606  bool is64Bit() const {
607  return In64BitMode;
608  }
609 
610  bool is32Bit() const {
611  return In32BitMode;
612  }
613 
614  bool is16Bit() const {
615  return In16BitMode;
616  }
617 
618  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
619  bool isTarget64BitILP32() const {
620  return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
621  }
622 
623  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
624  bool isTarget64BitLP64() const {
625  return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
626  }
627 
628  PICStyles::Style getPICStyle() const { return PICStyle; }
629  void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
630 
631  bool hasX87() const { return HasX87; }
632  bool hasCmpxchg8b() const { return HasCmpxchg8b; }
633  bool hasNOPL() const { return HasNOPL; }
634  // SSE codegen depends on cmovs, and all SSE1+ processors support them.
635  // All 64-bit processors support cmov.
636  bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
637  bool hasSSE1() const { return X86SSELevel >= SSE1; }
638  bool hasSSE2() const { return X86SSELevel >= SSE2; }
639  bool hasSSE3() const { return X86SSELevel >= SSE3; }
640  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
641  bool hasSSE41() const { return X86SSELevel >= SSE41; }
642  bool hasSSE42() const { return X86SSELevel >= SSE42; }
643  bool hasAVX() const { return X86SSELevel >= AVX; }
644  bool hasAVX2() const { return X86SSELevel >= AVX2; }
645  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
646  bool hasInt256() const { return hasAVX2(); }
647  bool hasSSE4A() const { return HasSSE4A; }
648  bool hasMMX() const { return X863DNowLevel >= MMX; }
649  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
650  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
651  bool hasPOPCNT() const { return HasPOPCNT; }
652  bool hasAES() const { return HasAES; }
653  bool hasVAES() const { return HasVAES; }
654  bool hasFXSR() const { return HasFXSR; }
655  bool hasXSAVE() const { return HasXSAVE; }
656  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
657  bool hasXSAVEC() const { return HasXSAVEC; }
658  bool hasXSAVES() const { return HasXSAVES; }
659  bool hasPCLMUL() const { return HasPCLMUL; }
660  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
661  bool hasGFNI() const { return HasGFNI; }
662  // Prefer FMA4 to FMA - its better for commutation/memory folding and
663  // has equal or better performance on all supported targets.
664  bool hasFMA() const { return HasFMA; }
665  bool hasFMA4() const { return HasFMA4; }
666  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
667  bool hasXOP() const { return HasXOP; }
668  bool hasTBM() const { return HasTBM; }
669  bool hasLWP() const { return HasLWP; }
670  bool hasMOVBE() const { return HasMOVBE; }
671  bool hasRDRAND() const { return HasRDRAND; }
672  bool hasF16C() const { return HasF16C; }
673  bool hasFSGSBase() const { return HasFSGSBase; }
674  bool hasLZCNT() const { return HasLZCNT; }
675  bool hasBMI() const { return HasBMI; }
676  bool hasBMI2() const { return HasBMI2; }
677  bool hasVBMI() const { return HasVBMI; }
678  bool hasVBMI2() const { return HasVBMI2; }
679  bool hasIFMA() const { return HasIFMA; }
680  bool hasRTM() const { return HasRTM; }
681  bool hasADX() const { return HasADX; }
682  bool hasSHA() const { return HasSHA; }
683  bool hasPRFCHW() const { return HasPRFCHW; }
684  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
685  bool hasPrefetchW() const {
686  // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
687  // its own CPUID bit as part of deprecating 3DNow. Intel eventually added
688  // it and KNL has another that prefetches to L2 cache. We assume the
689  // L1 version exists if the L2 version does.
690  return has3DNow() || hasPRFCHW() || hasPREFETCHWT1();
691  }
692  bool hasSSEPrefetch() const {
693  // We implicitly enable these when we have a write prefix supporting cache
694  // level OR if we have prfchw, but don't already have a read prefetch from
695  // 3dnow.
696  return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
697  }
698  bool hasRDSEED() const { return HasRDSEED; }
699  bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); }
700  bool hasMWAITX() const { return HasMWAITX; }
701  bool hasCLZERO() const { return HasCLZERO; }
702  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
703  bool hasMOVDIRI() const { return HasMOVDIRI; }
704  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
705  bool hasPTWRITE() const { return HasPTWRITE; }
706  bool isSHLDSlow() const { return IsSHLDSlow; }
707  bool isPMULLDSlow() const { return IsPMULLDSlow; }
708  bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
709  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
710  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
711  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
712  bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
713  bool useLeaForSP() const { return UseLeaForSP; }
714  bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
715  bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
717  return HasFastVariableCrossLaneShuffle;
718  }
720  return HasFastVariablePerLaneShuffle;
721  }
722  bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
723  bool hasFastGather() const { return HasFastGather; }
724  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
725  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
726  bool hasFastLZCNT() const { return HasFastLZCNT; }
727  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
728  bool hasFastBEXTR() const { return HasFastBEXTR; }
729  bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
730  bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
731  bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
732  bool hasFastMOVBE() const { return HasFastMOVBE; }
733  bool hasMacroFusion() const { return HasMacroFusion; }
734  bool hasBranchFusion() const { return HasBranchFusion; }
735  bool hasERMSB() const { return HasERMSB; }
736  bool hasFSRM() const { return HasFSRM; }
737  bool hasSlowDivide32() const { return HasSlowDivide32; }
738  bool hasSlowDivide64() const { return HasSlowDivide64; }
739  bool padShortFunctions() const { return PadShortFunctions; }
740  bool slowTwoMemOps() const { return SlowTwoMemOps; }
741  bool LEAusesAG() const { return LEAUsesAG; }
742  bool slowLEA() const { return SlowLEA; }
743  bool slow3OpsLEA() const { return Slow3OpsLEA; }
744  bool slowIncDec() const { return SlowIncDec; }
745  bool hasCDI() const { return HasCDI; }
746  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
747  bool hasPFI() const { return HasPFI; }
748  bool hasERI() const { return HasERI; }
749  bool hasDQI() const { return HasDQI; }
750  bool hasBWI() const { return HasBWI; }
751  bool hasVLX() const { return HasVLX; }
752  bool hasFP16() const { return HasFP16; }
753  bool hasPKU() const { return HasPKU; }
754  bool hasVNNI() const { return HasVNNI; }
755  bool hasBF16() const { return HasBF16; }
756  bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
757  bool hasBITALG() const { return HasBITALG; }
758  bool hasSHSTK() const { return HasSHSTK; }
759  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
760  bool hasCLWB() const { return HasCLWB; }
761  bool hasWBNOINVD() const { return HasWBNOINVD; }
762  bool hasRDPID() const { return HasRDPID; }
763  bool hasWAITPKG() const { return HasWAITPKG; }
764  bool hasPCONFIG() const { return HasPCONFIG; }
765  bool hasSGX() const { return HasSGX; }
766  bool hasINVPCID() const { return HasINVPCID; }
767  bool hasENQCMD() const { return HasENQCMD; }
768  bool hasKL() const { return HasKL; }
769  bool hasWIDEKL() const { return HasWIDEKL; }
770  bool hasHRESET() const { return HasHRESET; }
771  bool hasSERIALIZE() const { return HasSERIALIZE; }
772  bool hasTSXLDTRK() const { return HasTSXLDTRK; }
773  bool hasUINTR() const { return HasUINTR; }
774  bool hasCRC32() const { return HasCRC32; }
775  bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
777  return UseRetpolineIndirectBranches;
778  }
779  bool hasAVXVNNI() const { return HasAVXVNNI; }
780  bool hasAMXTILE() const { return HasAMXTILE; }
781  bool hasAMXBF16() const { return HasAMXBF16; }
782  bool hasAMXINT8() const { return HasAMXINT8; }
783  bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
784 
785  // These are generic getters that OR together all of the thunk types
786  // supported by the subtarget. Therefore useIndirectThunk*() will return true
787  // if any respective thunk feature is enabled.
788  bool useIndirectThunkCalls() const {
790  }
793  }
794 
795  bool preferMaskRegisters() const { return PreferMaskRegisters; }
796  bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; }
797  bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; }
798  bool useLVILoadHardening() const { return UseLVILoadHardening; }
800  return UseSpeculativeExecutionSideEffectSuppression;
801  }
802 
803  unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
804  unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
805 
806  // Helper functions to determine when we should allow widening to 512-bit
807  // during codegen.
808  // TODO: Currently we're always allowing widening on CPUs without VLX,
809  // because for many cases we don't have a better option.
810  bool canExtendTo512DQ() const {
811  return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
812  }
813  bool canExtendTo512BW() const {
814  return hasBWI() && canExtendTo512DQ();
815  }
816 
817  // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
818  // disable them in the legalizer.
819  bool useAVX512Regs() const {
820  return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
821  }
822 
823  bool useBWIRegs() const {
824  return hasBWI() && useAVX512Regs();
825  }
826 
827  bool isXRaySupported() const override { return is64Bit(); }
828 
829  /// TODO: to be removed later and replaced with suitable properties
830  bool isAtom() const { return X86ProcFamily == IntelAtom; }
831  bool isSLM() const { return X86ProcFamily == IntelSLM; }
832  bool useSoftFloat() const { return UseSoftFloat; }
833  bool useAA() const override { return UseAA; }
834 
835  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
836  /// no-sse2). There isn't any reason to disable it if the target processor
837  /// supports it.
838  bool hasMFence() const { return hasSSE2() || is64Bit(); }
839 
840  const Triple &getTargetTriple() const { return TargetTriple; }
841 
842  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
843  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
844  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
845  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
846  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
847 
848  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
849  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
850  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
851 
852  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
853  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
854  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
855  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
856  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
857  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
858  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
859  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
860  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
861 
862  bool isTargetWindowsMSVC() const {
863  return TargetTriple.isWindowsMSVCEnvironment();
864  }
865 
866  bool isTargetWindowsCoreCLR() const {
867  return TargetTriple.isWindowsCoreCLREnvironment();
868  }
869 
870  bool isTargetWindowsCygwin() const {
871  return TargetTriple.isWindowsCygwinEnvironment();
872  }
873 
874  bool isTargetWindowsGNU() const {
875  return TargetTriple.isWindowsGNUEnvironment();
876  }
877 
878  bool isTargetWindowsItanium() const {
879  return TargetTriple.isWindowsItaniumEnvironment();
880  }
881 
882  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
883 
884  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
885 
886  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
887 
888  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
889 
890  bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
891  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
892 
893  bool isPICStyleStubPIC() const {
894  return PICStyle == PICStyles::Style::StubPIC;
895  }
896 
897  bool isPositionIndependent() const;
898 
900  switch (CC) {
901  // On Win64, all these conventions just use the default convention.
902  case CallingConv::C:
903  case CallingConv::Fast:
904  case CallingConv::Tail:
905  case CallingConv::Swift:
912  return isTargetWin64();
913  // This convention allows using the Win64 convention on other targets.
914  case CallingConv::Win64:
915  return true;
916  // This convention allows using the SysV convention on Windows targets.
918  return false;
919  // Otherwise, who knows what this is.
920  default:
921  return false;
922  }
923  }
924 
925  /// Classify a global variable reference for the current subtarget according
926  /// to how we should reference it in a non-pcrel context.
927  unsigned char classifyLocalReference(const GlobalValue *GV) const;
928 
929  unsigned char classifyGlobalReference(const GlobalValue *GV,
930  const Module &M) const;
931  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
932 
933  /// Classify a global function reference for the current subtarget.
934  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
935  const Module &M) const;
936  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
937 
938  /// Classify a blockaddress reference for the current subtarget according to
939  /// how we should reference it in a non-pcrel context.
940  unsigned char classifyBlockAddressReference() const;
941 
942  /// Return true if the subtarget allows calls to immediate address.
943  bool isLegalToCallImmediateAddr() const;
944 
945  /// Return whether FrameLowering should always set the "extended frame
946  /// present" bit in FP, or set it based on a symbol in the runtime.
948  // Older OS versions (particularly system unwinders) are confused by the
949  // Swift extended frame, so when building code that might be run on them we
950  // must dynamically query the concurrency library to determine whether
951  // extended frames should be flagged as present.
952  const Triple &TT = getTargetTriple();
953 
954  unsigned Major, Minor, Micro;
955  TT.getOSVersion(Major, Minor, Micro);
956  switch(TT.getOS()) {
957  default:
958  return false;
959  case Triple::IOS:
960  case Triple::TvOS:
961  return Major < 15;
962  case Triple::WatchOS:
963  return Major < 8;
964  case Triple::MacOSX:
965  case Triple::Darwin:
966  return Major < 12;
967  }
968  }
969 
970  /// If we are using indirect thunks, we need to expand indirectbr to avoid it
971  /// lowering to an actual indirect jump.
972  bool enableIndirectBrExpand() const override {
973  return useIndirectThunkBranches();
974  }
975 
976  /// Enable the MachineScheduler pass for all X86 subtargets.
977  bool enableMachineScheduler() const override { return true; }
978 
979  bool enableEarlyIfConversion() const override;
980 
981  void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
982  &Mutations) const override;
983 
984  AntiDepBreakMode getAntiDepBreakMode() const override {
985  return TargetSubtargetInfo::ANTIDEP_CRITICAL;
986  }
987 
988  bool enableAdvancedRASplitCost() const override { return false; }
989 };
990 
991 } // end namespace llvm
992 
993 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::X86Subtarget::hasBWI
bool hasBWI() const
Definition: X86Subtarget.h:750
llvm::X86Subtarget::getRequiredVectorWidth
unsigned getRequiredVectorWidth() const
Definition: X86Subtarget.h:804
llvm::X86Subtarget::hasSSEPrefetch
bool hasSSEPrefetch() const
Definition: X86Subtarget.h:692
llvm::X86Subtarget::getFrameLowering
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:562
llvm::X86Subtarget::hasMOVBE
bool hasMOVBE() const
Definition: X86Subtarget.h:670
llvm::X86Subtarget::useLVIControlFlowIntegrity
bool useLVIControlFlowIntegrity() const
Definition: X86Subtarget.h:797
llvm::CallingConv::SwiftTail
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
Definition: CallingConv.h:92
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::X86Subtarget::hasERMSB
bool hasERMSB() const
Definition: X86Subtarget.h:735
llvm::X86Subtarget::hasFastVectorShiftMasks
bool hasFastVectorShiftMasks() const
Definition: X86Subtarget.h:731
llvm::X86Subtarget::hasLWP
bool hasLWP() const
Definition: X86Subtarget.h:669
llvm::X86Subtarget::getTileConfigSize
unsigned getTileConfigSize() const
Definition: X86Subtarget.h:574
llvm::X86Subtarget::hasTBM
bool hasTBM() const
Definition: X86Subtarget.h:668
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:638
llvm::X86Subtarget::hasPTWRITE
bool hasPTWRITE() const
Definition: X86Subtarget.h:705
llvm::X86Subtarget::hasIFMA
bool hasIFMA() const
Definition: X86Subtarget.h:679
llvm::X86Subtarget::hasAVX2
bool hasAVX2() const
Definition: X86Subtarget.h:644
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:637
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:852
llvm::Triple::Darwin
@ Darwin
Definition: Triple.h:169
llvm::X86Subtarget::getInstrInfo
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:560
llvm::X86Subtarget::hasFastScalarFSQRT
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:724
X86SelectionDAGInfo.h
llvm::X86Subtarget::hasBITALG
bool hasBITALG() const
Definition: X86Subtarget.h:757
llvm::X86Subtarget::isSHLDSlow
bool isSHLDSlow() const
Definition: X86Subtarget.h:706
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::PICStyles::Style::StubPIC
@ StubPIC
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:619
llvm::Triple::IOS
@ IOS
Definition: Triple.h:173
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::X86Subtarget::isLegalToCallImmediateAddr
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
Definition: X86Subtarget.cpp:234
llvm::CallingConv::X86_StdCall
@ X86_StdCall
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:102
llvm::X86Subtarget::isTargetMCU
bool isTargetMCU() const
Definition: X86Subtarget.h:859
llvm::X86Subtarget::hasHRESET
bool hasHRESET() const
Definition: X86Subtarget.h:770
llvm::X86Subtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: X86Subtarget.h:856
llvm::X86Subtarget::isXRaySupported
bool isXRaySupported() const override
Definition: X86Subtarget.h:827
llvm::Triple::isWindowsItaniumEnvironment
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:566
llvm::X86Subtarget::getPreferVectorWidth
unsigned getPreferVectorWidth() const
Definition: X86Subtarget.h:803
llvm::X86Subtarget::hasMMX
bool hasMMX() const
Definition: X86Subtarget.h:648
llvm::X86Subtarget::hasSlowDivide32
bool hasSlowDivide32() const
Definition: X86Subtarget.h:737
llvm::X86Subtarget::hasCMov
bool hasCMov() const
Definition: X86Subtarget.h:636
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:891
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:595
llvm::X86Subtarget::hasRDPID
bool hasRDPID() const
Definition: X86Subtarget.h:762
llvm::X86Subtarget::slow3OpsLEA
bool slow3OpsLEA() const
Definition: X86Subtarget.h:743
llvm::X86Subtarget::isSLM
bool isSLM() const
Definition: X86Subtarget.h:831
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:886
llvm::Triple::isPS4CPU
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:660
llvm::X86Subtarget::isUnalignedMem16Slow
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:709
llvm::Triple::WatchOS
@ WatchOS
Definition: Triple.h:194
llvm::X86Subtarget::hasPCONFIG
bool hasPCONFIG() const
Definition: X86Subtarget.h:764
llvm::X86Subtarget::X86Subtarget
X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const X86TargetMachine &TM, MaybeAlign StackAlignOverride, unsigned PreferVectorWidthOverride, unsigned RequiredVectorWidth)
This constructor initializes the data members to match that of the specified triple.
Definition: X86Subtarget.cpp:299
llvm::X86Subtarget::is32Bit
bool is32Bit() const
Definition: X86Subtarget.h:610
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:557
llvm::X86Subtarget::hasGFNI
bool hasGFNI() const
Definition: X86Subtarget.h:661
llvm::X86Subtarget::isTargetSolaris
bool isTargetSolaris() const
Definition: X86Subtarget.h:845
X86FrameLowering.h
llvm::X86Subtarget::getStackAlignment
Align getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:580
llvm::X86Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:169
llvm::X86Subtarget::isPMADDWDSlow
bool isPMADDWDSlow() const
Definition: X86Subtarget.h:708
llvm::X86Subtarget::isPICStyleStubPIC
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:893
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:673
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:632
llvm::X86Subtarget::hasSHA
bool hasSHA() const
Definition: X86Subtarget.h:682
llvm::X86Subtarget::isTargetKFreeBSD
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:853
llvm::X86Subtarget::hasBMI2
bool hasBMI2() const
Definition: X86Subtarget.h:676
llvm::X86Subtarget::isTargetGlibc
bool isTargetGlibc() const
Definition: X86Subtarget.h:854
llvm::X86Subtarget::hasFastVectorFSQRT
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:725
llvm::Triple::TvOS
@ TvOS
Definition: Triple.h:193
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:484
llvm::X86Subtarget::canExtendTo512DQ
bool canExtendTo512DQ() const
Definition: X86Subtarget.h:810
llvm::X86Subtarget::isTargetWin32
bool isTargetWin32() const
Definition: X86Subtarget.h:888
llvm::Legalizer
Definition: Legalizer.h:31
llvm::X86Subtarget::hasSlowDivide64
bool hasSlowDivide64() const
Definition: X86Subtarget.h:738
llvm::X86Subtarget::hasCLFLUSHOPT
bool hasCLFLUSHOPT() const
Definition: X86Subtarget.h:759
llvm::X86Subtarget::getRegisterInfo
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:570
llvm::X86Subtarget::hasAnyFMA
bool hasAnyFMA() const
Definition: X86Subtarget.h:666
llvm::X86Subtarget::isAtom
bool isAtom() const
TODO: to be removed later and replaced with suitable properties.
Definition: X86Subtarget.h:830
llvm::X86Subtarget::isTargetWindowsCoreCLR
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:866
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:637
llvm::X86Subtarget::hasXSAVE
bool hasXSAVE() const
Definition: X86Subtarget.h:655
llvm::X86Subtarget::slowIncDec
bool slowIncDec() const
Definition: X86Subtarget.h:744
llvm::X86Subtarget::hasXOP
bool hasXOP() const
Definition: X86Subtarget.h:667
llvm::X86Subtarget::hasCRC32
bool hasCRC32() const
Definition: X86Subtarget.h:774
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:645
llvm::X86Subtarget::hasBMI
bool hasBMI() const
Definition: X86Subtarget.h:675
llvm::X86Subtarget::hasSERIALIZE
bool hasSERIALIZE() const
Definition: X86Subtarget.h:771
llvm::X86Subtarget::hasAVXVNNI
bool hasAVXVNNI() const
Definition: X86Subtarget.h:779
llvm::X86Subtarget::hasPKU
bool hasPKU() const
Definition: X86Subtarget.h:753
llvm::X86Subtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: X86Subtarget.cpp:351
llvm::Triple::isOSIAMCU
bool isOSIAMCU() const
Definition: Triple.h:524
llvm::X86Subtarget::getTileConfigAlignment
Align getTileConfigAlignment() const
Definition: X86Subtarget.h:575
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:641
llvm::X86Subtarget::useGLMDivSqrtCosts
bool useGLMDivSqrtCosts() const
Definition: X86Subtarget.h:796
llvm::X86Subtarget::classifyGlobalReference
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
Definition: X86Subtarget.cpp:123
llvm::X86Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: X86Subtarget.h:850
llvm::X86TargetLowering
Definition: X86ISelLowering.h:918
llvm::X86Subtarget::hasFastGather
bool hasFastGather() const
Definition: X86Subtarget.h:723
llvm::X86Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: X86Subtarget.cpp:339
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::X86Subtarget::hasADX
bool hasADX() const
Definition: X86Subtarget.h:681
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86Subtarget::isOSWindows
bool isOSWindows() const
Definition: X86Subtarget.h:884
llvm::PICStyles::Style::RIPRel
@ RIPRel
llvm::X86Subtarget::isTargetELF
bool isTargetELF() const
Definition: X86Subtarget.h:848
llvm::Triple::isOSNaCl
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:590
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::X86Subtarget::isUnalignedMem32Slow
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:710
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:624
llvm::X86Subtarget::classifyLocalReference
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
Definition: X86Subtarget.cpp:69
llvm::X86Subtarget::hasBF16
bool hasBF16() const
Definition: X86Subtarget.h:755
llvm::X86Subtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:977
llvm::X86Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: X86Subtarget.cpp:343
llvm::X86Subtarget::isTargetCygMing
bool isTargetCygMing() const
Definition: X86Subtarget.h:882
X86GenSubtargetInfo
llvm::X86Subtarget::hasPrefetchW
bool hasPrefetchW() const
Definition: X86Subtarget.h:685
llvm::Triple::isOSFuchsia
bool isOSFuchsia() const
Definition: Triple.h:514
llvm::CallingConv::Intel_OCL_BI
@ Intel_OCL_BI
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:155
llvm::X86Subtarget::hasPOPCNT
bool hasPOPCNT() const
Definition: X86Subtarget.h:651
llvm::X86Subtarget::hasERI
bool hasERI() const
Definition: X86Subtarget.h:748
llvm::X86Subtarget::getSelectionDAGInfo
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:566
llvm::X86Subtarget::hasFastMOVBE
bool hasFastMOVBE() const
Definition: X86Subtarget.h:732
llvm::X86Subtarget::hasSHSTK
bool hasSHSTK() const
Definition: X86Subtarget.h:758
llvm::Triple::MacOSX
@ MacOSX
Definition: Triple.h:177
llvm::Triple::isOSSolaris
bool isOSSolaris() const
Definition: Triple.h:520
llvm::X86Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: X86Subtarget.cpp:347
llvm::CallingConv::X86_ThisCall
@ X86_ThisCall
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:126
llvm::Triple::isOSDragonFly
bool isOSDragonFly() const
Definition: Triple.h:518
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::X86Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: X86Subtarget.cpp:335
llvm::X86Subtarget::hasFastBEXTR
bool hasFastBEXTR() const
Definition: X86Subtarget.h:728
llvm::X86Subtarget::hasXSAVEC
bool hasXSAVEC() const
Definition: X86Subtarget.h:657
llvm::Triple::isOSCygMing
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:579
llvm::X86Subtarget::preferMaskRegisters
bool preferMaskRegisters() const
Definition: X86Subtarget.h:795
llvm::X86Subtarget::hasWIDEKL
bool hasWIDEKL() const
Definition: X86Subtarget.h:769
llvm::X86Subtarget::insertVZEROUPPER
bool insertVZEROUPPER() const
Definition: X86Subtarget.h:722
llvm::X86FrameLowering
Definition: X86FrameLowering.h:27
llvm::Triple::isOSFreeBSD
bool isOSFreeBSD() const
Definition: Triple.h:510
llvm::X86Subtarget::hasFSGSBase
bool hasFSGSBase() const
Definition: X86Subtarget.h:673
llvm::X86Subtarget::hasXSAVEOPT
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:656
llvm::X86Subtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: X86Subtarget.h:849
llvm::Triple::isOSGlibc
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:620
llvm::X86Subtarget::hasFSRM
bool hasFSRM() const
Definition: X86Subtarget.h:736
llvm::X86Subtarget::hasUINTR
bool hasUINTR() const
Definition: X86Subtarget.h:773
llvm::X86Subtarget::hasAMXINT8
bool hasAMXINT8() const
Definition: X86Subtarget.h:782
llvm::X86Subtarget::hasBranchFusion
bool hasBranchFusion() const
Definition: X86Subtarget.h:734
llvm::X86Subtarget::hasFMA
bool hasFMA() const
Definition: X86Subtarget.h:664
llvm::X86Subtarget::hasFMA4
bool hasFMA4() const
Definition: X86Subtarget.h:665
llvm::CallingConv::X86_64_SysV
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:159
llvm::X86Subtarget::has3DNowA
bool has3DNowA() const
Definition: X86Subtarget.h:650
llvm::Triple::isWindowsCoreCLREnvironment
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:562
llvm::X86Subtarget::has3DNow
bool has3DNow() const
Definition: X86Subtarget.h:649
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::X86Subtarget::hasX87
bool hasX87() const
Definition: X86Subtarget.h:631
llvm::X86Subtarget::is16Bit
bool is16Bit() const
Definition: X86Subtarget.h:614
llvm::X86Subtarget::hasMacroFusion
bool hasMacroFusion() const
Definition: X86Subtarget.h:733
llvm::X86Subtarget::getTargetLowering
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:556
llvm::X86Subtarget::useIndirectThunkBranches
bool useIndirectThunkBranches() const
Definition: X86Subtarget.h:791
llvm::X86Subtarget::hasAES
bool hasAES() const
Definition: X86Subtarget.h:652
llvm::X86Subtarget::isTargetPS4
bool isTargetPS4() const
Definition: X86Subtarget.h:846
llvm::X86Subtarget::hasCLWB
bool hasCLWB() const
Definition: X86Subtarget.h:760
llvm::X86Subtarget::hasENQCMD
bool hasENQCMD() const
Definition: X86Subtarget.h:767
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
llvm::X86Subtarget::hasRDRAND
bool hasRDRAND() const
Definition: X86Subtarget.h:671
llvm::X86Subtarget::hasMOVDIR64B
bool hasMOVDIR64B() const
Definition: X86Subtarget.h:704
llvm::X86Subtarget::hasCmpxchg16b
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:712
llvm::X86Subtarget::isTargetDragonFly
bool isTargetDragonFly() const
Definition: X86Subtarget.h:844
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::X86Subtarget::hasCLZERO
bool hasCLZERO() const
Definition: X86Subtarget.h:701
llvm::X86Subtarget::classifyBlockAddressReference
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
Definition: X86Subtarget.cpp:57
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:646
llvm::X86Subtarget::useRetpolineIndirectBranches
bool useRetpolineIndirectBranches() const
Definition: X86Subtarget.h:776
llvm::X86Subtarget::hasVPCLMULQDQ
bool hasVPCLMULQDQ() const
Definition: X86Subtarget.h:660
llvm::X86Subtarget::hasRDSEED
bool hasRDSEED() const
Definition: X86Subtarget.h:698
llvm::X86Subtarget::hasF16C
bool hasF16C() const
Definition: X86Subtarget.h:672
Triple.h
llvm::X86Subtarget::LEAusesAG
bool LEAusesAG() const
Definition: X86Subtarget.h:741
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::X86Subtarget::hasFastVariableCrossLaneShuffle
bool hasFastVariableCrossLaneShuffle() const
Definition: X86Subtarget.h:716
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:842
llvm::X86Subtarget::isTargetFuchsia
bool isTargetFuchsia() const
Definition: X86Subtarget.h:860
llvm::X86Subtarget::padShortFunctions
bool padShortFunctions() const
Definition: X86Subtarget.h:739
llvm::X86Subtarget::hasVNNI
bool hasVNNI() const
Definition: X86Subtarget.h:754
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::X86Subtarget::hasPOPCNTFalseDeps
bool hasPOPCNTFalseDeps() const
Definition: X86Subtarget.h:714
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::X86Subtarget::hasFastLZCNT
bool hasFastLZCNT() const
Definition: X86Subtarget.h:726
TargetSubtargetInfo.h
llvm::X86Subtarget::hasFXSR
bool hasFXSR() const
Definition: X86Subtarget.h:654
llvm::X86Subtarget::setPICStyle
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:629
llvm::CallingConv::X86_VectorCall
@ X86_VectorCall
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:173
llvm::X86InstrInfo::getRegisterInfo
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:149
llvm::X86Subtarget::useSpeculativeExecutionSideEffectSuppression
bool useSpeculativeExecutionSideEffectSuppression() const
Definition: X86Subtarget.h:799
llvm::X86Subtarget::hasFastScalarShiftMasks
bool hasFastScalarShiftMasks() const
Definition: X86Subtarget.h:730
llvm::X86Subtarget::hasPRFCHW
bool hasPRFCHW() const
Definition: X86Subtarget.h:683
llvm::X86Subtarget::useBWIRegs
bool useBWIRegs() const
Definition: X86Subtarget.h:823
llvm::X86Subtarget::isTargetWindowsGNU
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:874
llvm::X86Subtarget::hasPREFETCHWT1
bool hasPREFETCHWT1() const
Definition: X86Subtarget.h:684
llvm::X86Subtarget::hasINVPCID
bool hasINVPCID() const
Definition: X86Subtarget.h:766
llvm::X86Subtarget::hasSSE3
bool hasSSE3() const
Definition: X86Subtarget.h:639
llvm::X86Subtarget::hasFastSHLDRotate
bool hasFastSHLDRotate() const
Definition: X86Subtarget.h:727
llvm::X86Subtarget::hasAMXTILE
bool hasAMXTILE() const
Definition: X86Subtarget.h:780
llvm::X86Subtarget::slowTwoMemOps
bool slowTwoMemOps() const
Definition: X86Subtarget.h:740
llvm::X86Subtarget::hasMWAITX
bool hasMWAITX() const
Definition: X86Subtarget.h:700
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:547
llvm::X86Subtarget::hasWBNOINVD
bool hasWBNOINVD() const
Definition: X86Subtarget.h:761
llvm::X86Subtarget::hasLZCNTFalseDeps
bool hasLZCNTFalseDeps() const
Definition: X86Subtarget.h:715
CallingConv.h
llvm::X86Subtarget::isPMULLDSlow
bool isPMULLDSlow() const
Definition: X86Subtarget.h:707
llvm::X86Subtarget::useAA
bool useAA() const override
Definition: X86Subtarget.h:833
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:645
llvm::X86Subtarget::isTargetFreeBSD
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:843
llvm::X86Subtarget::hasMFence
bool hasMFence() const
Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:838
llvm::X86Subtarget::hasWAITPKG
bool hasWAITPKG() const
Definition: X86Subtarget.h:763
llvm::X86Subtarget::isTargetWindowsMSVC
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:862
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:899
llvm::X86Subtarget::hasTSXLDTRK
bool hasTSXLDTRK() const
Definition: X86Subtarget.h:772
llvm::X86Subtarget::hasPCLMUL
bool hasPCLMUL() const
Definition: X86Subtarget.h:659
llvm::X86Subtarget::hasVLX
bool hasVLX() const
Definition: X86Subtarget.h:751
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::X86Subtarget::hasCDI
bool hasCDI() const
Definition: X86Subtarget.h:745
llvm::X86Subtarget::hasPFI
bool hasPFI() const
Definition: X86Subtarget.h:747
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:574
llvm::X86Subtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: X86Subtarget.h:855
llvm::X86Subtarget::classifyGlobalFunctionReference
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
Definition: X86Subtarget.cpp:185
llvm::X86Subtarget::hasRTM
bool hasRTM() const
Definition: X86Subtarget.h:680
llvm::PICStyles::Style::None
@ None
llvm::X86Subtarget::hasSGX
bool hasSGX() const
Definition: X86Subtarget.h:765
llvm::X86Subtarget::hasXSAVES
bool hasXSAVES() const
Definition: X86Subtarget.h:658
llvm::X86Subtarget::canExtendTo512BW
bool canExtendTo512BW() const
Definition: X86Subtarget.h:813
X86ISelLowering.h
llvm::X86Subtarget::hasAVX
bool hasAVX() const
Definition: X86Subtarget.h:643
llvm::X86Subtarget::hasCmpxchg8b
bool hasCmpxchg8b() const
Definition: X86Subtarget.h:632
llvm::X86Subtarget::useSoftFloat
bool useSoftFloat() const
Definition: X86Subtarget.h:832
llvm::X86Subtarget::hasNOPL
bool hasNOPL() const
Definition: X86Subtarget.h:633
llvm::X86Subtarget::isTargetWindowsItanium
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:878
llvm::X86Subtarget::hasMOVDIRI
bool hasMOVDIRI() const
Definition: X86Subtarget.h:703
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::X86Subtarget::useRetpolineExternalThunk
bool useRetpolineExternalThunk() const
Definition: X86Subtarget.h:783
llvm::X86Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:840
llvm::CallingConv::X86_FastCall
@ X86_FastCall
X86_FastCall - 'fast' analog of X86_StdCall.
Definition: CallingConv.h:107
llvm::X86Subtarget::getAntiDepBreakMode
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:984
llvm::X86Subtarget::isTargetNaCl32
bool isTargetNaCl32() const
Definition: X86Subtarget.h:857
llvm::X86Subtarget::hasDQI
bool hasDQI() const
Definition: X86Subtarget.h:749
llvm::PICStyles::Style
Style
Definition: X86Subtarget.h:43
llvm::X86Subtarget::hasSSSE3
bool hasSSSE3() const
Definition: X86Subtarget.h:640
llvm::X86Subtarget::hasVBMI
bool hasVBMI() const
Definition: X86Subtarget.h:677
llvm::X86Subtarget::hasCLDEMOTE
bool hasCLDEMOTE() const
Definition: X86Subtarget.h:702
llvm::Triple::isX32
bool isX32() const
Tests whether the target is X32.
Definition: Triple.h:809
llvm::X86Subtarget::getPICStyle
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:628
llvm::X86SelectionDAGInfo
Definition: X86SelectionDAGInfo.h:20
llvm::X86Subtarget::hasSSEUnalignedMem
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:711
llvm::X86Subtarget::hasSSE4A
bool hasSSE4A() const
Definition: X86Subtarget.h:647
llvm::X86Subtarget::useLVILoadHardening
bool useLVILoadHardening() const
Definition: X86Subtarget.h:798
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::PICStyles::Style::GOT
@ GOT
llvm::X86Subtarget::hasSSE42
bool hasSSE42() const
Definition: X86Subtarget.h:642
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:606
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1110
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86Subtarget::useAVX512Regs
bool useAVX512Regs() const
Definition: X86Subtarget.h:819
llvm::X86Subtarget::hasLZCNT
bool hasLZCNT() const
Definition: X86Subtarget.h:674
llvm::X86Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
Definition: X86Subtarget.cpp:331
llvm::X86Subtarget::enableIndirectBrExpand
bool enableIndirectBrExpand() const override
If we are using indirect thunks, we need to expand indirectbr to avoid it lowering to an actual indir...
Definition: X86Subtarget.h:972
llvm::X86Subtarget::enableAdvancedRASplitCost
bool enableAdvancedRASplitCost() const override
Definition: X86Subtarget.h:988
llvm::X86Subtarget::slowLEA
bool slowLEA() const
Definition: X86Subtarget.h:742
llvm::X86Subtarget::isTargetWindowsCygwin
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:870
llvm::X86Subtarget::getMaxInlineSizeThreshold
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition: X86Subtarget.h:584
llvm::X86Subtarget::hasFastHorizontalOps
bool hasFastHorizontalOps() const
Definition: X86Subtarget.h:729
llvm::X86Subtarget::isPositionIndependent
bool isPositionIndependent() const
Definition: X86Subtarget.cpp:356
X86InstrInfo.h
llvm::X86Subtarget::hasKL
bool hasKL() const
Definition: X86Subtarget.h:768
llvm::X86Subtarget::useLeaForSP
bool useLeaForSP() const
Definition: X86Subtarget.h:713
llvm::CallLowering
Definition: CallLowering.h:43
llvm::X86Subtarget::hasLAHFSAHF
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:699
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:890
llvm::X86Subtarget::useIndirectThunkCalls
bool useIndirectThunkCalls() const
Definition: X86Subtarget.h:788
llvm::Triple::isOSKFreeBSD
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:600
llvm::X86Subtarget::hasVPOPCNTDQ
bool hasVPOPCNTDQ() const
Definition: X86Subtarget.h:746
llvm::X86Subtarget::swiftAsyncContextIsDynamicallySet
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: X86Subtarget.h:947
llvm::X86Subtarget::isTargetNaCl64
bool isTargetNaCl64() const
Definition: X86Subtarget.h:858
llvm::X86Subtarget::hasFP16
bool hasFP16() const
Definition: X86Subtarget.h:752
llvm::Triple::isWindowsCygwinEnvironment
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:570
llvm::X86Subtarget::hasFastVariablePerLaneShuffle
bool hasFastVariablePerLaneShuffle() const
Definition: X86Subtarget.h:719
llvm::X86Subtarget::hasVP2INTERSECT
bool hasVP2INTERSECT() const
Definition: X86Subtarget.h:756
llvm::X86Subtarget::hasAMXBF16
bool hasAMXBF16() const
Definition: X86Subtarget.h:781
llvm::X86Subtarget::useRetpolineIndirectCalls
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:775
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::X86Subtarget::hasVBMI2
bool hasVBMI2() const
Definition: X86Subtarget.h:678
llvm::X86Subtarget::hasVAES
bool hasVAES() const
Definition: X86Subtarget.h:653