14#ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15#define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
22 class X86TargetMachine;
937 bool hasSymbolicDisplacement);
942 bool is64Bit,
bool IsVarArg,
bool GuaranteeTCO);
949 bool AllowPartialUndefs =
true);
954 bool AssumeSingleUse =
false);
959 const X86Subtarget &Subtarget,
960 bool AssumeSingleUse =
false);
998 unsigned JTI,
MCContext &Ctx)
const override;
1024 unsigned *
Fast)
const override;
1034 unsigned *
Fast =
nullptr)
const override;
1038 unsigned *
Fast)
const {
1058 EVT ExtVT)
const override;
1061 EVT VT)
const override;
1080 const SDNode *SETCC1)
const override;
1086 bool LegalOperations,
bool ForCodeSize,
1088 unsigned Depth)
const override;
1138 unsigned OldShiftOpcode,
unsigned NewShiftOpcode,
1142 EVT VT,
unsigned ShiftOpc,
bool MayTransformRotate,
1143 const APInt &ShiftOrRotateAmt,
1144 const std::optional<APInt> &AndMask)
const override;
1155 unsigned KeptBits)
const override {
1160 auto VTIsOk = [](
EVT VT) ->
bool {
1161 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
1168 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
1173 unsigned ExpansionFactor)
const override;
1192 EVT VT)
const override;
1195 const APInt &DemandedElts,
1196 TargetLoweringOpt &TLO)
const override;
1202 const APInt &DemandedElts,
1204 unsigned Depth = 0)
const override;
1208 const APInt &DemandedElts,
1210 unsigned Depth)
const override;
1213 const APInt &DemandedElts,
1216 TargetLoweringOpt &TLO,
1217 unsigned Depth)
const override;
1220 const APInt &DemandedElts,
1222 TargetLoweringOpt &TLO,
1223 unsigned Depth)
const;
1227 const APInt &DemandedElts,
1229 TargetLoweringOpt &TLO,
1230 unsigned Depth)
const override;
1238 bool PoisonOnly,
unsigned Depth)
const override;
1242 bool PoisonOnly,
bool ConsiderFlags,
unsigned Depth)
const override;
1246 unsigned Depth)
const override;
1254 Op.getOperand(0).isUndef()))
1275 const char *Constraint)
const override;
1283 std::vector<SDValue> &Ops,
1288 if (ConstraintCode ==
"v")
1296 const AsmOperandInfo &Constraint,
1303 std::pair<unsigned, const TargetRegisterClass *>
1310 Type *Ty,
unsigned AS,
1369 EVT VT)
const override;
1377 EVT VT)
const override;
1385 unsigned Intrinsic)
const override;
1391 bool ForCodeSize)
const override;
1408 EVT ConditionVT)
const override;
1418 EVT NewVT)
const override;
1427 Type *Ty)
const override;
1439 unsigned Index)
const override;
1449 return (EltVT == MVT::f32 || EltVT == MVT::f64) &&
Index == 0;
1456 bool MathUsed)
const override;
1459 unsigned AddrSpace)
const override {
1462 return IsZero || NumElem > 2;
1504 const SDLoc &
DL)
const override;
1524 EVT VT)
const override;
1528 EVT VT)
const override;
1532 unsigned &NumIntermediates,
MVT &RegisterVT)
const override;
1555 unsigned OpNo)
const override;
1562 unsigned Factor)
const override;
1567 unsigned Factor)
const override;
1581 std::pair<const TargetRegisterClass *, uint8_t>
1583 MVT VT)
const override;
1591 std::vector<APFloat> LegalFPImmediates;
1595 void addLegalFPImmediate(
const APFloat& Imm) {
1596 LegalFPImmediates.push_back(Imm);
1599 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
1601 const SmallVectorImpl<ISD::InputArg> &Ins,
1602 const SDLoc &dl, SelectionDAG &DAG,
1603 SmallVectorImpl<SDValue> &InVals,
1606 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1607 const SDLoc &dl, SelectionDAG &DAG,
1608 const CCValAssign &VA, MachineFrameInfo &MFI,
1610 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1611 const SDLoc &dl, SelectionDAG &DAG,
1612 const CCValAssign &VA,
1613 ISD::ArgFlagsTy Flags,
bool isByval)
const;
1619 bool IsEligibleForTailCallOptimization(
1620 SDValue Callee,
CallingConv::ID CalleeCC,
bool IsCalleeStackStructRet,
1621 bool isVarArg, Type *
RetTy,
const SmallVectorImpl<ISD::OutputArg> &Outs,
1622 const SmallVectorImpl<SDValue> &OutVals,
1623 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG)
const;
1624 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1625 SDValue Chain,
bool IsTailCall,
1626 bool Is64Bit,
int FPDiff,
1627 const SDLoc &dl)
const;
1629 unsigned GetAlignedArgumentStackSize(
unsigned StackSize,
1630 SelectionDAG &DAG)
const;
1632 unsigned getAddressSpace()
const;
1634 SDValue FP_TO_INTHelper(SDValue
Op, SelectionDAG &DAG,
bool IsSigned,
1635 SDValue &Chain)
const;
1636 SDValue LRINT_LLRINTHelper(SDNode *
N, SelectionDAG &DAG)
const;
1638 SDValue LowerBUILD_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1639 SDValue LowerVSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1640 SDValue LowerEXTRACT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1641 SDValue LowerINSERT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1643 unsigned getGlobalWrapperKind(
const GlobalValue *GV,
1644 const unsigned char OpFlags)
const;
1645 SDValue LowerConstantPool(SDValue
Op, SelectionDAG &DAG)
const;
1646 SDValue LowerBlockAddress(SDValue
Op, SelectionDAG &DAG)
const;
1647 SDValue LowerGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
1648 SDValue LowerGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1649 SDValue LowerExternalSymbol(SDValue
Op, SelectionDAG &DAG)
const;
1653 SDValue LowerGlobalOrExternal(SDValue
Op, SelectionDAG &DAG,
1654 bool ForCall)
const;
1656 SDValue LowerSINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1657 SDValue LowerUINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1658 SDValue LowerTRUNCATE(SDValue
Op, SelectionDAG &DAG)
const;
1659 SDValue LowerFP_TO_INT(SDValue
Op, SelectionDAG &DAG)
const;
1660 SDValue LowerFP_TO_INT_SAT(SDValue
Op, SelectionDAG &DAG)
const;
1661 SDValue LowerLRINT_LLRINT(SDValue
Op, SelectionDAG &DAG)
const;
1662 SDValue LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const;
1663 SDValue LowerSETCCCARRY(SDValue
Op, SelectionDAG &DAG)
const;
1664 SDValue LowerSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1665 SDValue LowerBRCOND(SDValue
Op, SelectionDAG &DAG)
const;
1666 SDValue LowerJumpTable(SDValue
Op, SelectionDAG &DAG)
const;
1667 SDValue LowerDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1668 SDValue LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const;
1669 SDValue LowerVAARG(SDValue
Op, SelectionDAG &DAG)
const;
1670 SDValue LowerRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1671 SDValue LowerADDROFRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1672 SDValue LowerFRAMEADDR(SDValue
Op, SelectionDAG &DAG)
const;
1673 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue
Op, SelectionDAG &DAG)
const;
1674 SDValue LowerEH_RETURN(SDValue
Op, SelectionDAG &DAG)
const;
1675 SDValue lowerEH_SJLJ_SETJMP(SDValue
Op, SelectionDAG &DAG)
const;
1676 SDValue lowerEH_SJLJ_LONGJMP(SDValue
Op, SelectionDAG &DAG)
const;
1677 SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue
Op, SelectionDAG &DAG)
const;
1678 SDValue LowerINIT_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1679 SDValue LowerGET_ROUNDING(SDValue
Op, SelectionDAG &DAG)
const;
1680 SDValue LowerSET_ROUNDING(SDValue
Op, SelectionDAG &DAG)
const;
1681 SDValue LowerGET_FPENV_MEM(SDValue
Op, SelectionDAG &DAG)
const;
1682 SDValue LowerSET_FPENV_MEM(SDValue
Op, SelectionDAG &DAG)
const;
1683 SDValue LowerRESET_FPENV(SDValue
Op, SelectionDAG &DAG)
const;
1684 SDValue LowerWin64_i128OP(SDValue
Op, SelectionDAG &DAG)
const;
1685 SDValue LowerWin64_FP_TO_INT128(SDValue
Op, SelectionDAG &DAG,
1686 SDValue &Chain)
const;
1687 SDValue LowerWin64_INT128_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1688 SDValue LowerGC_TRANSITION(SDValue
Op, SelectionDAG &DAG)
const;
1689 SDValue LowerINTRINSIC_WO_CHAIN(SDValue
Op, SelectionDAG &DAG)
const;
1690 SDValue lowerFaddFsub(SDValue
Op, SelectionDAG &DAG)
const;
1691 SDValue LowerFP_EXTEND(SDValue
Op, SelectionDAG &DAG)
const;
1692 SDValue LowerFP_ROUND(SDValue
Op, SelectionDAG &DAG)
const;
1693 SDValue LowerFP_TO_BF16(SDValue
Op, SelectionDAG &DAG)
const;
1696 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1697 const SmallVectorImpl<ISD::InputArg> &Ins,
1698 const SDLoc &dl, SelectionDAG &DAG,
1699 SmallVectorImpl<SDValue> &InVals)
const override;
1700 SDValue LowerCall(CallLoweringInfo &CLI,
1701 SmallVectorImpl<SDValue> &InVals)
const override;
1703 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1704 const SmallVectorImpl<ISD::OutputArg> &Outs,
1705 const SmallVectorImpl<SDValue> &OutVals,
1706 const SDLoc &dl, SelectionDAG &DAG)
const override;
1708 bool supportSplitCSR(MachineFunction *MF)
const override {
1710 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1712 void initializeSplitCSR(MachineBasicBlock *Entry)
const override;
1713 void insertCopiesSplitCSR(
1714 MachineBasicBlock *Entry,
1715 const SmallVectorImpl<MachineBasicBlock *> &Exits)
const override;
1717 bool splitValueIntoRegisterParts(
1718 SelectionDAG & DAG,
const SDLoc &
DL, SDValue Val, SDValue *Parts,
1719 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID>
CC)
1722 SDValue joinRegisterPartsIntoValue(
1723 SelectionDAG & DAG,
const SDLoc &
DL,
const SDValue *Parts,
1724 unsigned NumParts, MVT PartVT, EVT ValueVT,
1725 std::optional<CallingConv::ID>
CC)
const override;
1727 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
1729 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
1731 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1736 const SmallVectorImpl<ISD::OutputArg> &Outs,
1737 LLVMContext &Context)
const override;
1740 ArrayRef<MCPhysReg> getRoundingControlRegisters()
const override;
1743 shouldExpandAtomicLoadInIR(LoadInst *LI)
const override;
1745 shouldExpandAtomicStoreInIR(StoreInst *SI)
const override;
1747 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI)
const override;
1749 shouldExpandLogicAtomicRMWInIR(AtomicRMWInst *AI)
const;
1750 void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI)
const override;
1751 void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI)
const override;
1754 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI)
const override;
1756 bool needsCmpXchgNb(Type *MemType)
const;
1758 void SetupEntryBlockForSjLj(MachineInstr &
MI, MachineBasicBlock *
MBB,
1759 MachineBasicBlock *DispatchBB,
int FI)
const;
1763 EmitVAARGWithCustomInserter(MachineInstr &
MI, MachineBasicBlock *
MBB)
const;
1766 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1768 MachineBasicBlock *BB)
const;
1770 MachineBasicBlock *EmitLoweredSelect(MachineInstr &
I,
1771 MachineBasicBlock *BB)
const;
1773 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &
MI,
1774 MachineBasicBlock *BB)
const;
1776 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &
MI,
1777 MachineBasicBlock *BB)
const;
1779 MachineBasicBlock *EmitLoweredProbedAlloca(MachineInstr &
MI,
1780 MachineBasicBlock *BB)
const;
1782 MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &
MI,
1783 MachineBasicBlock *BB)
const;
1785 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &
MI,
1786 MachineBasicBlock *BB)
const;
1788 MachineBasicBlock *EmitLoweredIndirectThunk(MachineInstr &
MI,
1789 MachineBasicBlock *BB)
const;
1791 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &
MI,
1792 MachineBasicBlock *
MBB)
const;
1794 void emitSetJmpShadowStackFix(MachineInstr &
MI,
1795 MachineBasicBlock *
MBB)
const;
1797 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &
MI,
1798 MachineBasicBlock *
MBB)
const;
1800 MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &
MI,
1801 MachineBasicBlock *
MBB)
const;
1803 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &
MI,
1804 MachineBasicBlock *
MBB)
const;
1809 const SDLoc &dl, SelectionDAG &DAG,
1810 SDValue &X86CC)
const;
1812 bool optimizeFMulOrFDivAsShiftAddBitcast(SDNode *
N, SDValue FPConst,
1813 SDValue IntPow2)
const override;
1816 bool isFsqrtCheap(SDValue
Op, SelectionDAG &DAG)
const override;
1819 SDValue getSqrtEstimate(SDValue
Op, SelectionDAG &DAG,
int Enabled,
1820 int &RefinementSteps,
bool &UseOneConstNR,
1821 bool Reciprocal)
const override;
1824 SDValue getRecipEstimate(SDValue
Op, SelectionDAG &DAG,
int Enabled,
1825 int &RefinementSteps)
const override;
1828 unsigned combineRepeatedFPDivisors()
const override;
1830 SDValue BuildSDIVPow2(SDNode *
N,
const APInt &Divisor, SelectionDAG &DAG,
1831 SmallVectorImpl<SDNode *> &Created)
const override;
1833 SDValue getMOVL(SelectionDAG &DAG,
const SDLoc &dl, MVT VT, SDValue V1,
1839 const TargetLibraryInfo *libInfo);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
BlockVerifier::State From
Analysis containing CSE Info
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
This file describes how to lower LLVM code to machine code.
static bool is64Bit(const char *name)
static constexpr uint32_t RegMask
static constexpr uint32_t Opcode
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Common base class shared among various IRBuilders.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Representation of each machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
const SDValue & getOperand(unsigned Num) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
AndOrSETCCFoldKind
Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ....
NegatibleCost
Enum that specifies when a float negation is beneficial.
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
virtual bool isTargetCanonicalConstantNode(SDValue Op) const
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
const SDValue & getPassThru() const
static bool classof(const SDNode *N)
const SDValue & getBasePtr() const
X86MaskedGatherScatterSDNode()=delete
const SDValue & getScale() const
static bool classof(const SDNode *N)
~X86MaskedGatherScatterSDNode()=delete
const SDValue & getMask() const
const SDValue & getIndex() const
const SDValue & getValue() const
static bool classof(const SDNode *N)
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating exp...
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
bool preferABDSToABSWithNSW(EVT VT) const override
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
std::pair< SDValue, SDValue > BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) const
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
bool isMemoryAccessFast(EVT VT, Align Alignment) const
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Handle Lowering flag assembly outputs.
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const override
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth) const override
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool useSoftFloat() const override
bool isVectorShiftByScalarCheap(Type *Ty) const override
This is used to enable splatted operand transforms for vector shifts and vector funnel shifts.
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool isLegalStoreImmediate(int64_t Imm) const override
Return true if the specified immediate is legal for the value input of a store instruction.
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override
Return true if it's profitable to narrow operations of type SrcVT to DestVT.
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldSplatInsEltVarIndex(EVT VT) const override
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Return true if sinking I's operands to the same basic block as I is profitable, e....
bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const override
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
MVT hasFastEqualityCompare(unsigned NumBits) const override
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
bool SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) const
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const override
bool isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode Cond, EVT VT) const override
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast) const
bool preferScalarizeSplat(SDNode *N) const override
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const override
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
StringRef getStackProbeSymbolName(const MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
bool useStackGuardXorFP() const override
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
bool shouldScalarizeBinop(SDValue) const override
Scalar ops always have equal or better analysis/performance/power than the vector equivalent,...
void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool areJTsAllowed(const Function *Fn) const override
Returns true if lowering to a jump table is allowed.
bool isCommutativeBinOp(unsigned Opcode) const override
Returns true if the opcode is a commutative binary operation.
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const override
Returns preferred type for switch condition.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower interleaved store(s) into target specific instructions/intrinsics.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
bool isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Customize the preferred legalization strategy for certain types.
bool shouldConvertPhiType(Type *From, Type *To) const override
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
bool hasStackProbeSymbol(const MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
This function returns true if the memory access is aligned or if the target allows this specific unal...
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool softPromoteHalfType() const override
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
TargetLowering::AndOrSETCCFoldKind isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const override
Return prefered fold type, Abs if this is a vector, AddAnd if its an integer, None otherwise.
bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expansion.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool isBinOp(unsigned Opcode) const override
Add x86-specific opcodes to the default list.
bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const override
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDValue unwrapAddress(SDValue N) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const override
For types supported by the target, this is an identity function.
bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override
Return true if Op can create undef or poison from non-undef & non-poison operands.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool needsFixedCatchObjects() const override
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ CXX_FAST_TLS
Used for access functions.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ X86
Windows x64, Windows Itanium (IA-64)
@ FST
This instruction implements a truncating store from FP stack slots.
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
@ CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
@ FMAX
Floating point max and min.
@ BT
X86 bit-test instructions.
@ HADD
Integer horizontal add/sub.
@ MOVQ2DQ
Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero fi...
@ BLENDI
Blend where the selector is an immediate.
@ CMP
X86 compare and logical compare instructions.
@ BLENDV
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
@ ADDSUB
Combined add and sub on an FP vector.
@ RET_GLUE
Return with a glue operand.
@ STRICT_FCMP
X86 strict FP compare instructions.
@ STRICT_CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
@ FHADD
Floating point horizontal add/sub.
@ FMAXS
Scalar intrinsic floating point max and min.
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
@ NT_BRIND
BRIND node with NoTrack prefix.
@ FSETCCM
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.
@ PEXTRB
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
@ FXOR
Bitwise logical XOR of floating point values.
@ BRCOND
X86 conditional branches.
@ FSETCC
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
@ PINSRB
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
@ INSERTPS
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
@ PSHUFB
Shuffle 16 8-bit values within a vector.
@ PEXTRW
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
@ CALL
These operations represent an abstract X86 call instruction, which includes a bunch of information.
@ AADD
RAO arithmetic instructions.
@ FANDN
Bitwise logical ANDNOT of floating point values.
@ GlobalBaseReg
On Darwin, this node represents the result of the popl at function entry, used for PIC code.
@ FMAXC
Commutative FMIN and FMAX.
@ EXTRQI
SSE4A Extraction and Insertion.
@ FLD
This instruction implements an extending load to FP stack slots.
@ TC_RETURN
Tail call return.
@ PSADBW
Compute Sum of Absolute Differences.
@ FOR
Bitwise logical OR of floating point values.
@ LCMPXCHG16_SAVE_RBX_DAG
@ FIST
This instruction implements a fp->int store from FP stack slots.
@ FP_TO_INT_IN_MEM
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.
@ LADD
LOCK-prefixed arithmetic read-modify-write instructions.
@ DBPSADBW
Compute Double Block Packed Sum-Absolute-Differences.
@ MMX_MOVW2D
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.
@ Wrapper
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress,...
@ PINSRW
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
@ CMPCCXADD
Compare and Add if Condition is Met.
@ NT_CALL
Same as call except it adds the NoTrack prefix.
@ MMX_MOVD2W
Copies a 32-bit value from the low word of a MMX vector to a GPR.
@ FILD
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.
@ MOVDQ2Q
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
@ ANDNP
Bitwise Logical AND NOT of Packed FP values.
@ VAARG_64
These instructions grab the address of the next argument from a va_list.
@ FAND
Bitwise logical AND of floating point values.
@ CMOV
X86 conditional moves.
@ WrapperRIP
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
@ FSHL
X86 funnel/double shift i16 instructions.
@ FRSQRT
Floating point reciprocal-sqrt and reciprocal approximation.
RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
bool mayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into a vector splat instruction as a memory oper...
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
bool mayFoldIntoZeroExtend(SDValue Op)
Check if Op is an operation that could be folded into a zero extend x86 instruction.
bool mayFoldIntoStore(SDValue Op)
Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory...
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
bool mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into some other x86 instruction as a memory oper...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
Returns true of the given offset can be fit into displacement field of the instruction.
bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs)
If Op is a constant whose elements are all the same constant or undefined, return true and return the...
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void createUnpackShuffleMask(EVT VT, SmallVectorImpl< int > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
void createSplat2ShuffleMask(MVT VT, SmallVectorImpl< int > &Mask, bool Lo)
Similar to unpacklo/unpackhi, but without the 128-bit lane limitation imposed by AVX and specific to ...
DWARFExpression::Operation Op
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class contains a discriminated union of information about pointers in memory operands,...