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X86ISelLowering.h
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1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that X86 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15#define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16
19
20namespace llvm {
21 class X86Subtarget;
22 class X86TargetMachine;
23
24 namespace X86ISD {
25 // X86 Specific DAG Nodes
26 enum NodeType : unsigned {
27 // Start the numbering where the builtin ops leave off.
29
30 /// Bit scan forward.
32 /// Bit scan reverse.
34
35 /// X86 funnel/double shift i16 instructions. These correspond to
36 /// X86::SHLDW and X86::SHRDW instructions which have different amt
37 /// modulo rules to generic funnel shifts.
38 /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.
41
42 /// Bitwise logical AND of floating point values. This corresponds
43 /// to X86::ANDPS or X86::ANDPD.
45
46 /// Bitwise logical OR of floating point values. This corresponds
47 /// to X86::ORPS or X86::ORPD.
49
50 /// Bitwise logical XOR of floating point values. This corresponds
51 /// to X86::XORPS or X86::XORPD.
53
54 /// Bitwise logical ANDNOT of floating point values. This
55 /// corresponds to X86::ANDNPS or X86::ANDNPD.
57
58 /// These operations represent an abstract X86 call
59 /// instruction, which includes a bunch of information. In particular the
60 /// operands of these node are:
61 ///
62 /// #0 - The incoming token chain
63 /// #1 - The callee
64 /// #2 - The number of arg bytes the caller pushes on the stack.
65 /// #3 - The number of arg bytes the callee pops off the stack.
66 /// #4 - The value to pass in AL/AX/EAX (optional)
67 /// #5 - The value to pass in DL/DX/EDX (optional)
68 ///
69 /// The result values of these nodes are:
70 ///
71 /// #0 - The outgoing token chain
72 /// #1 - The first register result value (optional)
73 /// #2 - The second register result value (optional)
74 ///
76
77 /// Same as call except it adds the NoTrack prefix.
79
80 // Pseudo for a OBJC call that gets emitted together with a special
81 // marker instruction.
83
84 /// The same as ISD::CopyFromReg except that this node makes it explicit
85 /// that it may lower to an x87 FPU stack pop. Optimizations should be more
86 /// cautious when handling this node than a normal CopyFromReg to avoid
87 /// removing a required FPU stack pop. A key requirement is optimizations
88 /// should not optimize any users of a chain that contains a
89 /// POP_FROM_X87_REG to use a chain from a point earlier than the
90 /// POP_FROM_X87_REG (which may remove a required FPU stack pop).
92
93 // Pseudo for a call to an imported function to ensure the correct machine
94 // instruction is emitted for Import Call Optimization.
96
97 /// X86 compare and logical compare instructions.
102
103 // X86 compare with Intrinsics similar to COMI.
106
107 /// X86 bit-test instructions.
109
110 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
111 /// operand, usually produced by a CMP instruction.
113
114 /// X86 Select
116
117 // Same as SETCC except it's materialized with a sbb and the value is all
118 // one's or all zero's.
119 SETCC_CARRY, // R = carry_bit ? ~0 : 0
120
121 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
122 /// Operands are two FP values to compare; result is a mask of
123 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
125
126 /// X86 FP SETCC, similar to above, but with output as an i1 mask and
127 /// and a version with SAE.
130
131 /// X86 conditional moves. Operand 0 and operand 1 are the two values
132 /// to select from. Operand 2 is the condition code, and operand 3 is the
133 /// flag operand produced by a CMP or TEST instruction.
135
136 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
137 /// is the block to branch if condition is true, operand 2 is the
138 /// condition code, and operand 3 is the flag operand produced by a CMP
139 /// or TEST instruction.
141
142 /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
143 /// operand 1 is the target address.
145
146 /// Return with a glue operand. Operand 0 is the chain operand, operand
147 /// 1 is the number of bytes of stack to pop.
149
150 /// Return from interrupt. Operand 0 is the number of bytes to pop.
152
153 /// Repeat fill, corresponds to X86::REP_STOSx.
155
156 /// Repeat move, corresponds to X86::REP_MOVSx.
158
159 /// On Darwin, this node represents the result of the popl
160 /// at function entry, used for PIC code.
162
163 /// A wrapper node for TargetConstantPool, TargetJumpTable,
164 /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
165 /// MCSymbol and TargetBlockAddress.
167
168 /// Special wrapper used under X86-64 PIC mode for RIP
169 /// relative displacements.
171
172 /// Copies a 64-bit value from an MMX vector to the low word
173 /// of an XMM vector, with the high word zero filled.
175
176 /// Copies a 64-bit value from the low word of an XMM vector
177 /// to an MMX vector.
179
180 /// Copies a 32-bit value from the low word of a MMX
181 /// vector to a GPR.
183
184 /// Copies a GPR into the low 32-bit word of a MMX vector
185 /// and zero out the high word.
187
188 /// Extract an 8-bit value from a vector and zero extend it to
189 /// i32, corresponds to X86::PEXTRB.
191
192 /// Extract a 16-bit value from a vector and zero extend it to
193 /// i32, corresponds to X86::PEXTRW.
195
196 /// Insert any element of a 4 x float vector into any element
197 /// of a destination 4 x floatvector.
199
200 /// Insert the lower 8-bits of a 32-bit value to a vector,
201 /// corresponds to X86::PINSRB.
203
204 /// Insert the lower 16-bits of a 32-bit value to a vector,
205 /// corresponds to X86::PINSRW.
207
208 /// Shuffle 16 8-bit values within a vector.
210
211 /// Compute Sum of Absolute Differences.
213 /// Compute Double Block Packed Sum-Absolute-Differences
215
216 /// Bitwise Logical AND NOT of Packed FP values.
218
219 /// Blend where the selector is an immediate.
221
222 /// Dynamic (non-constant condition) vector blend where only the sign bits
223 /// of the condition elements are used. This is used to enforce that the
224 /// condition mask is not valid for generic VSELECT optimizations. This
225 /// is also used to implement the intrinsics.
226 /// Operands are in VSELECT order: MASK, TRUE, FALSE
228
229 /// Combined add and sub on an FP vector.
231
232 // FP vector ops with rounding mode.
252
253 // FP vector get exponent.
258 // Extract Normalized Mantissas.
263 // FP Scale.
268
269 /// Integer horizontal add/sub.
272
273 /// Floating point horizontal add/sub.
276
277 // Detect Conflicts Within a Vector
279
280 /// Floating point max and min.
283
284 /// Commutative FMIN and FMAX.
287
288 /// Scalar intrinsic floating point max and min.
291
292 /// Floating point reciprocal-sqrt and reciprocal approximation.
293 /// Note that these typically require refinement
294 /// in order to obtain suitable precision.
297
298 // AVX-512 reciprocal approximations with a little more precision.
303
304 // Thread Local Storage.
306
307 // Thread Local Storage. A call to get the start address
308 // of the TLS block for the current module.
310
311 // Thread Local Storage. When calling to an OS provided
312 // thunk at the address from an earlier relocation.
314
315 // Thread Local Storage. A descriptor containing pointer to
316 // code and to argument to get the TLS offset for the symbol.
318
319 // Exception Handling helpers.
321
322 // SjLj exception handling setjmp.
324
325 // SjLj exception handling longjmp.
327
328 // SjLj exception handling dispatch.
330
331 /// Tail call return. See X86TargetLowering::LowerCall for
332 /// the list of operands.
334
335 // Vector move to low scalar and zero higher vector elements.
337
338 // Vector integer truncate.
340 // Vector integer truncate with unsigned/signed saturation.
343
344 // Masked version of the above. Used when less than a 128-bit result is
345 // produced since the mask only applies to the lower elements and can't
346 // be represented by a select.
347 // SRC, PASSTHRU, MASK
351
352 // Vector FP extend.
357
358 // Vector FP round.
360 // Convert TWO packed single data to one packed data
366
367 // Masked version of above. Used for v2f64->v4f32.
368 // SRC, PASSTHRU, MASK
370
371 // 128-bit vector logical left / right shift
374
375 // Vector shift elements
379
380 // Vector variable shift
384
385 // Vector shift elements by immediate
389
390 // Shifts of mask registers.
393
394 // Bit rotate by immediate
397
398 // Vector packed double/float comparison.
400
401 // Vector integer comparisons.
404
405 // v8i16 Horizontal minimum and position.
407
409
410 /// Vector comparison generating mask bits for fp and
411 /// integer signed and unsigned data types.
413 // Vector mask comparison generating mask bits for FP values.
415 // Vector mask comparison with SAE for FP values.
417
418 // Arithmetic operations with FLAGS results.
428
429 // Bit field extract.
432
433 // Zero High Bits Starting with Specified Bit Position.
435
436 // Parallel extract and deposit.
439
440 // X86-specific multiply by immediate.
442
443 // Vector sign bit extraction.
445
446 // Vector bitwise comparisons.
448
449 // Vector packed fp sign bitwise comparisons.
451
452 // OR/AND test for masks.
455
456 // ADD for masks.
458
459 // Several flavors of instructions with vector shuffle behaviors.
460 // Saturated signed/unnsigned packing.
463 // Intra-lane alignr.
465 // AVX512 inter-lane alignr.
471 // VBMI2 Concat & Shift.
474
475 // Shuffle Packed Values at 128-bit granularity.
491
492 // Variable Permute (VPERM).
493 // Res = VPERMV MaskV, V0
495
496 // 3-op Variable Permute (VPERMT2).
497 // Res = VPERMV3 V0, MaskV, V1
499
500 // Bitwise ternary logic.
502 // Fix Up Special Packed Float32/64 values.
507 // Range Restriction Calculation For Packed Pairs of Float32/64 values.
512 // Reduce - Perform Reduction Transformation on scalar\packed FP.
517 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
518 // Also used by the legacy (V)ROUND intrinsics where we mask out the
519 // scaling part of the immediate.
524 // Tests Types Of a FP Values for packed types.
526 // Tests Types Of a FP Values for scalar types.
528
529 // Broadcast (splat) scalar or element 0 of a vector. If the operand is
530 // a vector, this node may change the vector length as part of the splat.
532 // Broadcast mask to vector.
534
535 /// SSE4A Extraction and Insertion.
538
539 // XOP arithmetic/logical shifts.
542 // XOP signed/unsigned integer comparisons.
545 // XOP packed permute bytes.
547 // XOP two source permutation.
549
550 // Vector multiply packed unsigned doubleword integers.
552 // Vector multiply packed signed doubleword integers.
554 // Vector Multiply Packed UnsignedIntegers with Round and Scale.
556
557 // Multiply and Add Packed Integers.
560
561 // AVX512IFMA multiply and add.
562 // NOTE: These are different than the instruction and perform
563 // op0 x op1 + op2.
566
567 // VNNI
572
573 // FMA nodes.
574 // We use the target independent ISD::FMA for the non-inverted case.
580
581 // FMA with rounding mode.
588
589 // AVX512-FP16 complex addition and multiplication.
594
599
604
609
616
623
628
637
639
661
662 // Compress and expand.
665
666 // Bits shuffle
668
669 // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
676
677 // Vector float/double to signed/unsigned integer.
682 // Scalar float/double to signed/unsigned integer.
687
688 // Vector float/double to signed/unsigned integer with truncation.
693
694 // Saturation enabled Vector float/double to signed/unsigned
695 // integer with truncation.
700 // Masked versions of above. Used for v2f64 to v4i32.
701 // SRC, PASSTHRU, MASK
704
705 // Scalar float/double to signed/unsigned integer with truncation.
710
711 // Vector signed/unsigned integer to float/double.
714
715 // Scalar float/double to signed/unsigned integer with saturation.
720
721 // Masked versions of above. Used for v2f64->v4f32.
722 // SRC, PASSTHRU, MASK
729
730 // Custom handling for FP_TO_xINT_SAT
733
734 // Vector float to bfloat16.
735 // Convert packed single data to packed BF16 data
737 // Masked version of above.
738 // SRC, PASSTHRU, MASK
740
741 // Dot product of BF16/FP16 pairs to accumulated into
742 // packed single precision.
745
746 // A stack checking function call. On Windows it's _chkstk call.
748
749 // For allocating variable amounts of stack space when using
750 // segmented stacks. Check if the current stacklet has enough space, and
751 // falls back to heap allocation if not.
753
754 // For allocating stack space when using stack clash protector.
755 // Allocation is performed by block, and each block is probed.
757
758 // Memory barriers.
760
761 // Get a random integer and indicate whether it is valid in CF.
763
764 // Get a NIST SP800-90B & C compliant random integer and
765 // indicate whether it is valid in CF.
767
768 // Protection keys
769 // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
770 // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
771 // value for ECX.
774
775 // SSE42 string comparisons.
776 // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
777 // will emit one or two instructions based on which results are used. If
778 // flags and index/mask this allows us to use a single instruction since
779 // we won't have to pick and opcode for flags. Instead we can rely on the
780 // DAG to CSE everything and decide at isel.
783
784 // Test if in transactional execution.
786
787 // Conversions between float and half-float.
792
793 // Masked version of above.
794 // SRC, RND, PASSTHRU, MASK
797
798 // Galois Field Arithmetic Instructions
802
803 // LWP insert record.
805
806 // User level wait
809
810 // Enqueue Stores Instructions
813
814 // For avx512-vp2intersect
816
817 // User level interrupts - testui
819
820 // Perform an FP80 add after changing precision control in FPCW.
822
823 // Conditional compare instructions
826
827 /// X86 strict FP compare instructions.
831
832 // Vector packed double/float comparison.
834
835 /// Vector comparison generating mask bits for fp and
836 /// integer signed and unsigned data types.
838
839 // Vector float/double to signed/unsigned integer with truncation.
842
843 // Vector FP extend.
845
846 // Vector FP round.
848
849 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
850 // Also used by the legacy (V)ROUND intrinsics where we mask out the
851 // scaling part of the immediate.
853
854 // Vector signed/unsigned integer to float/double.
857
858 // Strict FMA nodes.
862
863 // Conversions between float and half-float.
866
867 // Perform an FP80 add after changing precision control in FPCW.
869
870 /// Floating point max and min.
874
875 // Compare and swap.
881
882 /// LOCK-prefixed arithmetic read-modify-write instructions.
883 /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
895
896 /// RAO arithmetic instructions.
897 /// OUTCHAIN = AADD(INCHAIN, PTR, RHS)
902
903 // Load, scalar_to_vector, and zero extend.
905
906 // extract_vector_elt, store.
908
909 // scalar broadcast from memory.
911
912 // subvector broadcast from memory.
914
915 // Store FP control word into i16 memory.
917
918 // Load FP control word from i16 memory.
920
921 // Store x87 FPU environment into memory.
923
924 // Load x87 FPU environment from memory.
926
927 /// This instruction implements FP_TO_SINT with the
928 /// integer destination in memory and a FP reg source. This corresponds
929 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
930 /// has two inputs (token chain and address) and two outputs (int value
931 /// and token chain). Memory VT specifies the type to store to.
933
934 /// This instruction implements SINT_TO_FP with the
935 /// integer source in memory and FP reg result. This corresponds to the
936 /// X86::FILD*m instructions. It has two inputs (token chain and address)
937 /// and two outputs (FP value and token chain). The integer source type is
938 /// specified by the memory VT.
940
941 /// This instruction implements a fp->int store from FP stack
942 /// slots. This corresponds to the fist instruction. It takes a
943 /// chain operand, value to store, address, and glue. The memory VT
944 /// specifies the type to store as.
946
947 /// This instruction implements an extending load to FP stack slots.
948 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
949 /// operand, and ptr to load from. The memory VT specifies the type to
950 /// load from.
952
953 /// This instruction implements a truncating store from FP stack
954 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
955 /// chain operand, value to store, address, and glue. The memory VT
956 /// specifies the type to store as.
958
959 /// These instructions grab the address of the next argument
960 /// from a va_list. (reads and modifies the va_list in memory)
963
964 // Vector truncating store with unsigned/signed saturation
967 // Vector truncating masked store with unsigned/signed saturation
970
971 // X86 specific gather and scatter
974
975 // Key locker nodes that produce flags.
984
985 /// Compare and Add if Condition is Met. Compare value in operand 2 with
986 /// value in memory of operand 1. If condition of operand 4 is met, add
987 /// value operand 3 to m32 and write new value in operand 1. Operand 2 is
988 /// always updated with the original value from operand 1.
990
991 // Save xmm argument registers to the stack, according to %al. An operator
992 // is needed so that this can be expanded with control flow.
994
995 // Conditional load/store instructions
999 };
1000 } // end namespace X86ISD
1001
1002 namespace X86 {
1003 /// Current rounding mode is represented in bits 11:10 of FPSR. These
1004 /// values are same as corresponding constants for rounding mode used
1005 /// in glibc.
1007 rmInvalid = -1, // For handle Invalid rounding mode
1008 rmToNearest = 0, // FE_TONEAREST
1009 rmDownward = 1 << 10, // FE_DOWNWARD
1010 rmUpward = 2 << 10, // FE_UPWARD
1011 rmTowardZero = 3 << 10, // FE_TOWARDZERO
1012 rmMask = 3 << 10 // Bit mask selecting rounding mode
1013 };
1014 }
1015
1016 /// Define some predicates that are used for node matching.
1017 namespace X86 {
1018 /// Returns true if Elt is a constant zero or floating point constant +0.0.
1019 bool isZeroNode(SDValue Elt);
1020
1021 /// Returns true of the given offset can be
1022 /// fit into displacement field of the instruction.
1024 bool hasSymbolicDisplacement);
1025
1026 /// Determines whether the callee is required to pop its
1027 /// own arguments. Callee pop is necessary to support tail calls.
1028 bool isCalleePop(CallingConv::ID CallingConv,
1029 bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
1030
1031 /// If Op is a constant whose elements are all the same constant or
1032 /// undefined, return true and return the constant value in \p SplatVal.
1033 /// If we have undef bits that don't cover an entire element, we treat these
1034 /// as zero if AllowPartialUndefs is set, else we fail and return false.
1035 bool isConstantSplat(SDValue Op, APInt &SplatVal,
1036 bool AllowPartialUndefs = true);
1037
1038 /// Check if Op is a load operation that could be folded into some other x86
1039 /// instruction as a memory operand. Example: vpaddd (%rdi), %xmm0, %xmm0.
1040 bool mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget,
1041 bool AssumeSingleUse = false);
1042
1043 /// Check if Op is a load operation that could be folded into a vector splat
1044 /// instruction as a memory operand. Example: vbroadcastss 16(%rdi), %xmm2.
1046 const X86Subtarget &Subtarget,
1047 bool AssumeSingleUse = false);
1048
1049 /// Check if Op is a value that could be used to fold a store into some
1050 /// other x86 instruction as a memory operand. Ex: pextrb $0, %xmm0, (%rdi).
1052
1053 /// Check if Op is an operation that could be folded into a zero extend x86
1054 /// instruction.
1056
1057 /// True if the target supports the extended frame for async Swift
1058 /// functions.
1059 bool isExtendedSwiftAsyncFrameSupported(const X86Subtarget &Subtarget,
1060 const MachineFunction &MF);
1061
1062 /// Convert LLVM rounding mode to X86 rounding mode.
1063 int getRoundingModeX86(unsigned RM);
1064
1065 } // end namespace X86
1066
1067 //===--------------------------------------------------------------------===//
1068 // X86 Implementation of the TargetLowering interface
1069 class X86TargetLowering final : public TargetLowering {
1070 public:
1071 explicit X86TargetLowering(const X86TargetMachine &TM,
1072 const X86Subtarget &STI);
1073
1074 unsigned getJumpTableEncoding() const override;
1075 bool useSoftFloat() const override;
1076
1077 void markLibCallAttributes(MachineFunction *MF, unsigned CC,
1078 ArgListTy &Args) const override;
1079
1080 MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
1081 return MVT::i8;
1082 }
1083
1084 const MCExpr *
1086 const MachineBasicBlock *MBB, unsigned uid,
1087 MCContext &Ctx) const override;
1088
1089 /// Returns relocation base for the given PIC jumptable.
1091 SelectionDAG &DAG) const override;
1092 const MCExpr *
1094 unsigned JTI, MCContext &Ctx) const override;
1095
1096 /// Return the desired alignment for ByVal aggregate
1097 /// function arguments in the caller parameter area. For X86, aggregates
1098 /// that contains are placed at 16-byte boundaries while the rest are at
1099 /// 4-byte boundaries.
1100 Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override;
1101
1102 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
1103 const AttributeList &FuncAttributes) const override;
1104
1105 /// Returns true if it's safe to use load / store of the
1106 /// specified type to expand memcpy / memset inline. This is mostly true
1107 /// for all types except for some special cases. For example, on X86
1108 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
1109 /// also does type conversion. Note the specified type doesn't have to be
1110 /// legal as the hook is used before type legalization.
1111 bool isSafeMemOpType(MVT VT) const override;
1112
1113 bool isMemoryAccessFast(EVT VT, Align Alignment) const;
1114
1115 /// Returns true if the target allows unaligned memory accesses of the
1116 /// specified type. Returns whether it is "fast" in the last argument.
1117 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
1119 unsigned *Fast) const override;
1120
1121 /// This function returns true if the memory access is aligned or if the
1122 /// target allows this specific unaligned memory access. If the access is
1123 /// allowed, the optional final parameter returns a relative speed of the
1124 /// access (as defined by the target).
1125 bool allowsMemoryAccess(
1126 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1127 Align Alignment,
1129 unsigned *Fast = nullptr) const override;
1130
1132 const MachineMemOperand &MMO,
1133 unsigned *Fast) const {
1134 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1135 MMO.getAlign(), MMO.getFlags(), Fast);
1136 }
1137
1138 /// Provide custom lowering hooks for some operations.
1139 ///
1140 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
1141
1142 /// Replace the results of node with an illegal result
1143 /// type with new values built out of custom code.
1144 ///
1146 SelectionDAG &DAG) const override;
1147
1148 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
1149
1150 bool preferABDSToABSWithNSW(EVT VT) const override;
1151
1152 bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT,
1153 EVT ExtVT) const override;
1154
1156 EVT VT) const override;
1157
1158 /// Return true if the target has native support for
1159 /// the specified value type and it is 'desirable' to use the type for the
1160 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1161 /// instruction encodings are longer and some i16 instructions are slow.
1162 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
1163
1164 /// Return true if the target has native support for the
1165 /// specified value type and it is 'desirable' to use the type. e.g. On x86
1166 /// i16 is legal, but undesirable since i16 instruction encodings are longer
1167 /// and some i16 instructions are slow.
1168 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
1169
1170 /// Return prefered fold type, Abs if this is a vector, AddAnd if its an
1171 /// integer, None otherwise.
1174 const SDNode *SETCC0,
1175 const SDNode *SETCC1) const override;
1176
1177 /// Return the newly negated expression if the cost is not expensive and
1178 /// set the cost in \p Cost to indicate that if it is cheaper or neutral to
1179 /// do the negation.
1181 bool LegalOperations, bool ForCodeSize,
1183 unsigned Depth) const override;
1184
1187 MachineBasicBlock *MBB) const override;
1188
1189 /// This method returns the name of a target specific DAG node.
1190 const char *getTargetNodeName(unsigned Opcode) const override;
1191
1192 /// Do not merge vector stores after legalization because that may conflict
1193 /// with x86-specific store splitting optimizations.
1194 bool mergeStoresAfterLegalization(EVT MemVT) const override {
1195 return !MemVT.isVector();
1196 }
1197
1198 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
1199 const MachineFunction &MF) const override;
1200
1201 bool isCheapToSpeculateCttz(Type *Ty) const override;
1202
1203 bool isCheapToSpeculateCtlz(Type *Ty) const override;
1204
1205 bool isCtlzFast() const override;
1206
1207 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
1208 // If the pair to store is a mixture of float and int values, we will
1209 // save two bitwise instructions and one float-to-int instruction and
1210 // increase one store instruction. There is potentially a more
1211 // significant benefit because it avoids the float->int domain switch
1212 // for input value. So It is more likely a win.
1213 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
1214 (LTy.isInteger() && HTy.isFloatingPoint()))
1215 return true;
1216 // If the pair only contains int values, we will save two bitwise
1217 // instructions and increase one store instruction (costing one more
1218 // store buffer). Since the benefit is more blurred so we leave
1219 // such pair out until we get testcase to prove it is a win.
1220 return false;
1221 }
1222
1223 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1224
1225 bool hasAndNotCompare(SDValue Y) const override;
1226
1227 bool hasAndNot(SDValue Y) const override;
1228
1229 bool hasBitTest(SDValue X, SDValue Y) const override;
1230
1233 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
1234 SelectionDAG &DAG) const override;
1235
1237 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
1238 const APInt &ShiftOrRotateAmt,
1239 const std::optional<APInt> &AndMask) const override;
1240
1241 bool preferScalarizeSplat(SDNode *N) const override;
1242
1243 CondMergingParams
1245 const Value *Rhs) const override;
1246
1248 CombineLevel Level) const override;
1249
1250 bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
1251
1252 bool
1254 unsigned KeptBits) const override {
1255 // For vectors, we don't have a preference..
1256 if (XVT.isVector())
1257 return false;
1258
1259 auto VTIsOk = [](EVT VT) -> bool {
1260 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
1261 VT == MVT::i64;
1262 };
1263
1264 // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
1265 // XVT will be larger than KeptBitsVT.
1266 MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
1267 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
1268 }
1269
1272 unsigned ExpansionFactor) const override;
1273
1274 bool shouldSplatInsEltVarIndex(EVT VT) const override;
1275
1276 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override {
1277 // Converting to sat variants holds little benefit on X86 as we will just
1278 // need to saturate the value back using fp arithmatic.
1280 }
1281
1282 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
1283 return VT.isScalarInteger();
1284 }
1285
1286 /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
1287 MVT hasFastEqualityCompare(unsigned NumBits) const override;
1288
1289 /// Return the value type to use for ISD::SETCC.
1291 EVT VT) const override;
1292
1294 const APInt &DemandedElts,
1295 TargetLoweringOpt &TLO) const override;
1296
1297 /// Determine which of the bits specified in Mask are known to be either
1298 /// zero or one and return them in the KnownZero/KnownOne bitsets.
1300 KnownBits &Known,
1301 const APInt &DemandedElts,
1302 const SelectionDAG &DAG,
1303 unsigned Depth = 0) const override;
1304
1305 /// Determine the number of bits in the operation that are sign bits.
1307 const APInt &DemandedElts,
1308 const SelectionDAG &DAG,
1309 unsigned Depth) const override;
1310
1312 const APInt &DemandedElts,
1313 APInt &KnownUndef,
1314 APInt &KnownZero,
1315 TargetLoweringOpt &TLO,
1316 unsigned Depth) const override;
1317
1319 const APInt &DemandedElts,
1320 unsigned MaskIndex,
1321 TargetLoweringOpt &TLO,
1322 unsigned Depth) const;
1323
1325 const APInt &DemandedBits,
1326 const APInt &DemandedElts,
1327 KnownBits &Known,
1328 TargetLoweringOpt &TLO,
1329 unsigned Depth) const override;
1330
1332 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1333 SelectionDAG &DAG, unsigned Depth) const override;
1334
1336 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
1337 bool PoisonOnly, unsigned Depth) const override;
1338
1340 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
1341 bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override;
1342
1343 bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
1344 APInt &UndefElts, const SelectionDAG &DAG,
1345 unsigned Depth) const override;
1346
1348 // Peek through bitcasts/extracts/inserts to see if we have a vector
1349 // load/broadcast from memory.
1350 while (Op.getOpcode() == ISD::BITCAST ||
1351 Op.getOpcode() == ISD::EXTRACT_SUBVECTOR ||
1352 (Op.getOpcode() == ISD::INSERT_SUBVECTOR &&
1353 Op.getOperand(0).isUndef()))
1354 Op = Op.getOperand(Op.getOpcode() == ISD::INSERT_SUBVECTOR ? 1 : 0);
1355
1356 return Op.getOpcode() == X86ISD::VBROADCAST_LOAD ||
1357 Op.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD ||
1358 (Op.getOpcode() == ISD::LOAD &&
1361 }
1362
1363 bool isTargetCanonicalSelect(SDNode *N) const override;
1364
1365 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
1366
1367 SDValue unwrapAddress(SDValue N) const override;
1368
1370
1371 ConstraintType getConstraintType(StringRef Constraint) const override;
1372
1373 /// Examine constraint string and operand type and determine a weight value.
1374 /// The operand object must already have been set up with the operand type.
1376 getSingleConstraintMatchWeight(AsmOperandInfo &Info,
1377 const char *Constraint) const override;
1378
1379 const char *LowerXConstraint(EVT ConstraintVT) const override;
1380
1381 /// Lower the specified operand into the Ops vector. If it is invalid, don't
1382 /// add anything to Ops. If hasMemory is true it means one of the asm
1383 /// constraint of the inline asm instruction being processed is 'm'.
1385 std::vector<SDValue> &Ops,
1386 SelectionDAG &DAG) const override;
1387
1389 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1390 if (ConstraintCode == "v")
1392 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1393 }
1394
1395 /// Handle Lowering flag assembly outputs.
1397 const SDLoc &DL,
1398 const AsmOperandInfo &Constraint,
1399 SelectionDAG &DAG) const override;
1400
1401 /// Given a physical register constraint
1402 /// (e.g. {edx}), return the register number and the register class for the
1403 /// register. This should only be used for C_Register constraints. On
1404 /// error, this returns a register number of 0.
1405 std::pair<unsigned, const TargetRegisterClass *>
1407 StringRef Constraint, MVT VT) const override;
1408
1409 /// Return true if the addressing mode represented
1410 /// by AM is legal for this target, for a load/store of the specified type.
1411 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1412 Type *Ty, unsigned AS,
1413 Instruction *I = nullptr) const override;
1414
1415 bool addressingModeSupportsTLS(const GlobalValue &GV) const override;
1416
1417 /// Return true if the specified immediate is legal
1418 /// icmp immediate, that is the target has icmp instructions which can
1419 /// compare a register against the immediate without having to materialize
1420 /// the immediate into a register.
1421 bool isLegalICmpImmediate(int64_t Imm) const override;
1422
1423 /// Return true if the specified immediate is legal
1424 /// add immediate, that is the target has add instructions which can
1425 /// add a register and the immediate without having to materialize
1426 /// the immediate into a register.
1427 bool isLegalAddImmediate(int64_t Imm) const override;
1428
1429 bool isLegalStoreImmediate(int64_t Imm) const override;
1430
1431 /// Add x86-specific opcodes to the default list.
1432 bool isBinOp(unsigned Opcode) const override;
1433
1434 /// Returns true if the opcode is a commutative binary operation.
1435 bool isCommutativeBinOp(unsigned Opcode) const override;
1436
1437 /// Return true if it's free to truncate a value of
1438 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1439 /// register EAX to i16 by referencing its sub-register AX.
1440 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1441 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1442
1443 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
1444
1445 /// Return true if any actual instruction that defines a
1446 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1447 /// register. This does not necessarily include registers defined in
1448 /// unknown ways, such as incoming arguments, or copies from unknown
1449 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1450 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1451 /// all instructions that define 32-bit values implicit zero-extend the
1452 /// result out to 64 bits.
1453 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
1454 bool isZExtFree(EVT VT1, EVT VT2) const override;
1455 bool isZExtFree(SDValue Val, EVT VT2) const override;
1456
1457 bool shouldConvertPhiType(Type *From, Type *To) const override;
1458
1459 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1460 /// extend node) is profitable.
1461 bool isVectorLoadExtDesirable(SDValue) const override;
1462
1463 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1464 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
1465 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
1467 EVT VT) const override;
1468
1469 /// Return true if it's profitable to narrow operations of type SrcVT to
1470 /// DestVT. e.g. on x86, it's profitable to narrow from i32 to i8 but not
1471 /// from i32 to i16.
1472 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
1473
1474 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
1475 unsigned SelectOpcode, SDValue X,
1476 SDValue Y) const override;
1477
1478 /// Given an intrinsic, checks if on the target the intrinsic will need to map
1479 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1480 /// true and stores the intrinsic information into the IntrinsicInfo that was
1481 /// passed to the function.
1482 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1483 MachineFunction &MF,
1484 unsigned Intrinsic) const override;
1485
1486 /// Returns true if the target can instruction select the
1487 /// specified FP immediate natively. If false, the legalizer will
1488 /// materialize the FP immediate as a load from a constant pool.
1489 bool isFPImmLegal(const APFloat &Imm, EVT VT,
1490 bool ForCodeSize) const override;
1491
1492 /// Targets can use this to indicate that they only support *some*
1493 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1494 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1495 /// be legal.
1496 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1497
1498 /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1499 /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1500 /// constant pool entry.
1501 bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1502
1503 /// Returns true if lowering to a jump table is allowed.
1504 bool areJTsAllowed(const Function *Fn) const override;
1505
1507 EVT ConditionVT) const override;
1508
1509 /// If true, then instruction selection should
1510 /// seek to shrink the FP constant of the specified type to a smaller type
1511 /// in order to save space and / or reduce runtime.
1512 bool ShouldShrinkFPConstant(EVT VT) const override;
1513
1514 /// Return true if we believe it is correct and profitable to reduce the
1515 /// load node to a smaller type.
1516 bool
1518 std::optional<unsigned> ByteOffset) const override;
1519
1520 /// Return true if the specified scalar FP type is computed in an SSE
1521 /// register, not on the X87 floating point stack.
1522 bool isScalarFPTypeInSSEReg(EVT VT) const;
1523
1524 /// Returns true if it is beneficial to convert a load of a constant
1525 /// to just the constant itself.
1527 Type *Ty) const override;
1528
1529 bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override;
1530
1531 bool convertSelectOfConstantsToMath(EVT VT) const override;
1532
1533 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
1534 SDValue C) const override;
1535
1536 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1537 /// with this index.
1538 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1539 unsigned Index) const override;
1540
1541 /// Scalar ops always have equal or better analysis/performance/power than
1542 /// the vector equivalent, so this always makes sense if the scalar op is
1543 /// supported.
1544 bool shouldScalarizeBinop(SDValue) const override;
1545
1546 /// Extract of a scalar FP value from index 0 of a vector is free.
1547 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1548 EVT EltVT = VT.getScalarType();
1549 return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
1550 }
1551
1552 /// Overflow nodes should get combined/lowered to optimal instructions
1553 /// (they should allow eliminating explicit compares by getting flags from
1554 /// math ops).
1555 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
1556 bool MathUsed) const override;
1557
1558 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
1559 unsigned AddrSpace) const override {
1560 // If we can replace more than 2 scalar stores, there will be a reduction
1561 // in instructions even after we add a vector constant load.
1562 return IsZero || NumElem > 2;
1563 }
1564
1565 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
1566 const SelectionDAG &DAG,
1567 const MachineMemOperand &MMO) const override;
1568
1569 Register getRegisterByName(const char* RegName, LLT VT,
1570 const MachineFunction &MF) const override;
1571
1572 /// If a physical register, this returns the register that receives the
1573 /// exception address on entry to an EH pad.
1574 Register
1575 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1576
1577 /// If a physical register, this returns the register that receives the
1578 /// exception typeid on entry to a landing pad.
1579 Register
1580 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1581
1582 bool needsFixedCatchObjects() const override;
1583
1584 /// This method returns a target specific FastISel object,
1585 /// or null if the target does not support "fast" ISel.
1587 const TargetLibraryInfo *libInfo) const override;
1588
1589 /// If the target has a standard location for the stack protector cookie,
1590 /// returns the address of that location. Otherwise, returns nullptr.
1591 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
1592
1593 bool useLoadStackGuardNode(const Module &M) const override;
1594 bool useStackGuardXorFP() const override;
1595 void insertSSPDeclarations(Module &M) const override;
1596 Function *getSSPStackGuardCheck(const Module &M) const override;
1598 const SDLoc &DL) const override;
1599
1600
1601 /// Return true if the target stores SafeStack pointer at a fixed offset in
1602 /// some non-standard address space, and populates the address space and
1603 /// offset as appropriate.
1604 Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
1605
1606 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
1607 SDValue Chain, SDValue Pointer,
1608 MachinePointerInfo PtrInfo,
1609 Align Alignment,
1610 SelectionDAG &DAG) const;
1611
1612 /// Customize the preferred legalization strategy for certain types.
1613 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1614
1615 bool softPromoteHalfType() const override { return true; }
1616
1618 EVT VT) const override;
1619
1621 CallingConv::ID CC,
1622 EVT VT) const override;
1623
1625 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
1626 unsigned &NumIntermediates, MVT &RegisterVT) const override;
1627
1629 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
1630 const DataLayout &DL) const override;
1631
1632 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1633
1634 bool supportSwiftError() const override;
1635
1636 bool supportKCFIBundles() const override { return true; }
1637
1640 const TargetInstrInfo *TII) const override;
1641
1642 bool hasStackProbeSymbol(const MachineFunction &MF) const override;
1643 bool hasInlineStackProbe(const MachineFunction &MF) const override;
1644 StringRef getStackProbeSymbolName(const MachineFunction &MF) const override;
1645
1646 unsigned getStackProbeSize(const MachineFunction &MF) const;
1647
1648 bool hasVectorBlend() const override { return true; }
1649
1650 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1651
1653 unsigned OpNo) const override;
1654
1655 SDValue visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
1656 MachineMemOperand *MMO, SDValue &NewLoad,
1657 SDValue Ptr, SDValue PassThru,
1658 SDValue Mask) const override;
1661 SDValue Mask) const override;
1662
1663 /// Lower interleaved load(s) into target specific
1664 /// instructions/intrinsics.
1665 bool lowerInterleavedLoad(Instruction *Load, Value *Mask,
1667 ArrayRef<unsigned> Indices, unsigned Factor,
1668 const APInt &GapMask) const override;
1669
1670 /// Lower interleaved store(s) into target specific
1671 /// instructions/intrinsics.
1672 bool lowerInterleavedStore(Instruction *Store, Value *Mask,
1673 ShuffleVectorInst *SVI, unsigned Factor,
1674 const APInt &GapMask) const override;
1675
1677 int JTI, SelectionDAG &DAG) const override;
1678
1679 Align getPrefLoopAlignment(MachineLoop *ML) const override;
1680
1681 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const override {
1682 if (VT == MVT::f80)
1683 return EVT::getIntegerVT(Context, 96);
1684 return TargetLoweringBase::getTypeToTransformTo(Context, VT);
1685 }
1686
1687 protected:
1688 std::pair<const TargetRegisterClass *, uint8_t>
1690 MVT VT) const override;
1691
1692 private:
1693 /// Keep a reference to the X86Subtarget around so that we can
1694 /// make the right decision when generating code for different targets.
1695 const X86Subtarget &Subtarget;
1696
1697 /// A list of legal FP immediates.
1698 std::vector<APFloat> LegalFPImmediates;
1699
1700 /// Indicate that this x86 target can instruction
1701 /// select the specified FP immediate natively.
1702 void addLegalFPImmediate(const APFloat& Imm) {
1703 LegalFPImmediates.push_back(Imm);
1704 }
1705
1706 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
1707 CallingConv::ID CallConv, bool isVarArg,
1708 const SmallVectorImpl<ISD::InputArg> &Ins,
1709 const SDLoc &dl, SelectionDAG &DAG,
1710 SmallVectorImpl<SDValue> &InVals,
1711 uint32_t *RegMask) const;
1712 SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1713 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1714 const SDLoc &dl, SelectionDAG &DAG,
1715 const CCValAssign &VA, MachineFrameInfo &MFI,
1716 unsigned i) const;
1717 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1718 const SDLoc &dl, SelectionDAG &DAG,
1719 const CCValAssign &VA,
1720 ISD::ArgFlagsTy Flags, bool isByval) const;
1721
1722 // Call lowering helpers.
1723
1724 /// Check whether the call is eligible for tail call optimization. Targets
1725 /// that want to do tail call optimization should implement this function.
1726 bool IsEligibleForTailCallOptimization(
1727 TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo,
1728 SmallVectorImpl<CCValAssign> &ArgLocs, bool IsCalleePopSRet) const;
1729 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1730 SDValue Chain, bool IsTailCall,
1731 bool Is64Bit, int FPDiff,
1732 const SDLoc &dl) const;
1733
1734 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1735 SelectionDAG &DAG) const;
1736
1737 unsigned getAddressSpace() const;
1738
1739 SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned,
1740 SDValue &Chain) const;
1741 SDValue LRINT_LLRINTHelper(SDNode *N, SelectionDAG &DAG) const;
1742
1743 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1744 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1745 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1746 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1747
1748 unsigned getGlobalWrapperKind(const GlobalValue *GV,
1749 const unsigned char OpFlags) const;
1750 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1751 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1752 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1753 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1754 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1755
1756 /// Creates target global address or external symbol nodes for calls or
1757 /// other uses.
1758 SDValue LowerGlobalOrExternal(SDValue Op, SelectionDAG &DAG, bool ForCall,
1759 bool *IsImpCall) const;
1760
1761 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1762 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1763 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1764 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1765 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1766 SDValue LowerLRINT_LLRINT(SDValue Op, SelectionDAG &DAG) const;
1767 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1768 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1769 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1770 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1771 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1772 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1773 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1774 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1775 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1776 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1777 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1778 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1779 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1780 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1781 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1782 SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1783 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1784 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1785 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1786 SDValue LowerGET_FPENV_MEM(SDValue Op, SelectionDAG &DAG) const;
1787 SDValue LowerSET_FPENV_MEM(SDValue Op, SelectionDAG &DAG) const;
1788 SDValue LowerRESET_FPENV(SDValue Op, SelectionDAG &DAG) const;
1789 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1790 SDValue LowerWin64_FP_TO_INT128(SDValue Op, SelectionDAG &DAG,
1791 SDValue &Chain) const;
1792 SDValue LowerWin64_INT128_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1793 SDValue LowerGC_TRANSITION(SDValue Op, SelectionDAG &DAG) const;
1794 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1795 SDValue lowerFaddFsub(SDValue Op, SelectionDAG &DAG) const;
1796 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1797 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1798 SDValue LowerFP_TO_BF16(SDValue Op, SelectionDAG &DAG) const;
1799
1800 SDValue
1801 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1802 const SmallVectorImpl<ISD::InputArg> &Ins,
1803 const SDLoc &dl, SelectionDAG &DAG,
1804 SmallVectorImpl<SDValue> &InVals) const override;
1805 SDValue LowerCall(CallLoweringInfo &CLI,
1806 SmallVectorImpl<SDValue> &InVals) const override;
1807
1808 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1809 const SmallVectorImpl<ISD::OutputArg> &Outs,
1810 const SmallVectorImpl<SDValue> &OutVals,
1811 const SDLoc &dl, SelectionDAG &DAG) const override;
1812
1813 bool supportSplitCSR(MachineFunction *MF) const override {
1814 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
1815 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1816 }
1817 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1818 void insertCopiesSplitCSR(
1819 MachineBasicBlock *Entry,
1820 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1821
1822 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1823
1824 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1825
1826 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1827 ISD::NodeType ExtendKind) const override;
1828
1829 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1830 bool isVarArg,
1831 const SmallVectorImpl<ISD::OutputArg> &Outs,
1832 LLVMContext &Context,
1833 const Type *RetTy) const override;
1834
1835 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1837
1839 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
1841 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1843 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1845 shouldExpandLogicAtomicRMWInIR(AtomicRMWInst *AI) const;
1846 void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const override;
1847 void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const override;
1848
1849 LoadInst *
1850 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1851
1852 bool needsCmpXchgNb(Type *MemType) const;
1853
1854 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1855 MachineBasicBlock *DispatchBB, int FI) const;
1856
1857 // Utility function to emit the low-level va_arg code for X86-64.
1858 MachineBasicBlock *
1859 EmitVAARGWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
1860
1861 /// Utility function to emit the xmm reg save portion of va_start.
1862 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1863 MachineInstr &MI2,
1864 MachineBasicBlock *BB) const;
1865
1866 MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1867 MachineBasicBlock *BB) const;
1868
1869 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1870 MachineBasicBlock *BB) const;
1871
1872 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1873 MachineBasicBlock *BB) const;
1874
1875 MachineBasicBlock *EmitLoweredProbedAlloca(MachineInstr &MI,
1876 MachineBasicBlock *BB) const;
1877
1878 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1879 MachineBasicBlock *BB) const;
1880
1881 MachineBasicBlock *EmitLoweredIndirectThunk(MachineInstr &MI,
1882 MachineBasicBlock *BB) const;
1883
1884 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1885 MachineBasicBlock *MBB) const;
1886
1887 void emitSetJmpShadowStackFix(MachineInstr &MI,
1888 MachineBasicBlock *MBB) const;
1889
1890 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1891 MachineBasicBlock *MBB) const;
1892
1893 MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1894 MachineBasicBlock *MBB) const;
1895
1896 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1897 MachineBasicBlock *MBB) const;
1898
1899 MachineBasicBlock *emitPatchableEventCall(MachineInstr &MI,
1900 MachineBasicBlock *MBB) const;
1901
1902 /// Emit flags for the given setcc condition and operands. Also returns the
1903 /// corresponding X86 condition code constant in X86CC.
1904 SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC,
1905 const SDLoc &dl, SelectionDAG &DAG,
1906 SDValue &X86CC) const;
1907
1908 bool optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst,
1909 SDValue IntPow2) const override;
1910
1911 /// Check if replacement of SQRT with RSQRT should be disabled.
1912 bool isFsqrtCheap(SDValue Op, SelectionDAG &DAG) const override;
1913
1914 /// Use rsqrt* to speed up sqrt calculations.
1915 SDValue getSqrtEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1916 int &RefinementSteps, bool &UseOneConstNR,
1917 bool Reciprocal) const override;
1918
1919 /// Use rcp* to speed up fdiv calculations.
1920 SDValue getRecipEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1921 int &RefinementSteps) const override;
1922
1923 /// Reassociate floating point divisions into multiply by reciprocal.
1924 unsigned combineRepeatedFPDivisors() const override;
1925
1926 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1927 SmallVectorImpl<SDNode *> &Created) const override;
1928
1929 SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
1930 SDValue V2) const;
1931 };
1932
1933 namespace X86 {
1934 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1935 const TargetLibraryInfo *libInfo);
1936 } // end namespace X86
1937
1938 // X86 specific Gather/Scatter nodes.
1939 // The class has the same order of operands as MaskedGatherScatterSDNode for
1940 // convenience.
1942 public:
1943 // This is a intended as a utility and should never be directly created.
1946
1947 const SDValue &getBasePtr() const { return getOperand(3); }
1948 const SDValue &getIndex() const { return getOperand(4); }
1949 const SDValue &getMask() const { return getOperand(2); }
1950 const SDValue &getScale() const { return getOperand(5); }
1951
1952 static bool classof(const SDNode *N) {
1953 return N->getOpcode() == X86ISD::MGATHER ||
1954 N->getOpcode() == X86ISD::MSCATTER;
1955 }
1956 };
1957
1959 public:
1960 const SDValue &getPassThru() const { return getOperand(1); }
1961
1962 static bool classof(const SDNode *N) {
1963 return N->getOpcode() == X86ISD::MGATHER;
1964 }
1965 };
1966
1968 public:
1969 const SDValue &getValue() const { return getOperand(1); }
1970
1971 static bool classof(const SDNode *N) {
1972 return N->getOpcode() == X86ISD::MSCATTER;
1973 }
1974 };
1975
1976 /// Generate unpacklo/unpackhi shuffle mask.
1977 void createUnpackShuffleMask(EVT VT, SmallVectorImpl<int> &Mask, bool Lo,
1978 bool Unary);
1979
1980 /// Similar to unpacklo/unpackhi, but without the 128-bit lane limitation
1981 /// imposed by AVX and specific to the unary pattern. Example:
1982 /// v8iX Lo --> <0, 0, 1, 1, 2, 2, 3, 3>
1983 /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7>
1984 void createSplat2ShuffleMask(MVT VT, SmallVectorImpl<int> &Mask, bool Lo);
1985
1986} // end namespace llvm
1987
1988#endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
static SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG)
return SDValue()
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Analysis containing CSE Info
Definition CSEInfo.cpp:27
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define RegName(no)
#define I(x, y, z)
Definition MD5.cpp:58
Register const TargetRegisterInfo * TRI
static unsigned getAddressSpace(const Value *V, unsigned MaxLookup)
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.
const SmallVectorImpl< MachineOperand > & Cond
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
This file describes how to lower LLVM code to machine code.
static bool is64Bit(const char *name)
static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
Class for arbitrary precision integers.
Definition APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition Constant.h:43
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:63
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Common base class shared among various IRBuilders.
Definition IRBuilder.h:114
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Definition MCContext.h:83
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
Machine Value Type.
static MVT getIntegerVT(unsigned BitWidth)
Instructions::iterator instr_iterator
Representation of each machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
Flags getFlags() const
Return the raw flags of the source value,.
LLVM_ABI Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
A Module instance is used to store all the information related to an LLVM module.
Definition Module.h:67
Wrapper class representing virtual and physical registers.
Definition Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
const SDValue & getOperand(unsigned Num) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
AndOrSETCCFoldKind
Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ....
NegatibleCost
Enum that specifies when a float negation is beneficial.
std::vector< ArgListEntry > ArgListTy
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
virtual bool isTargetCanonicalConstantNode(SDValue Op) const
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
TargetLowering(const TargetLowering &)=delete
virtual ArrayRef< MCPhysReg > getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
LLVM Value Representation.
Definition Value.h:75
const SDValue & getPassThru() const
static bool classof(const SDNode *N)
static bool classof(const SDNode *N)
const SDValue & getValue() const
static bool classof(const SDNode *N)
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating exp...
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
bool preferABDSToABSWithNSW(EVT VT) const override
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
std::pair< SDValue, SDValue > BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) const
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
bool isMemoryAccessFast(EVT VT, Align Alignment) const
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Handle Lowering flag assembly outputs.
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const override
More limited version of SimplifyDemandedBits that can be used to "lookthrough" ops that don't contrib...
bool useLoadStackGuardNode(const Module &M) const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth) const override
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool useSoftFloat() const override
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool isLegalStoreImmediate(int64_t Imm) const override
Return true if the specified immediate is legal for the value input of a store instruction.
SDValue visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const override
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldSplatInsEltVarIndex(EVT VT) const override
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const override
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
MVT hasFastEqualityCompare(unsigned NumBits) const override
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
bool SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) const
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const override
bool isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode Cond, EVT VT) const override
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional< unsigned > ByteOffset) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast) const
bool preferScalarizeSplat(SDNode *N) const override
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool lowerInterleavedStore(Instruction *Store, Value *Mask, ShuffleVectorInst *SVI, unsigned Factor, const APInt &GapMask) const override
Lower interleaved store(s) into target specific instructions/intrinsics.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override
Return true if it's profitable to narrow operations of type SrcVT to DestVT.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const override
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool lowerInterleavedLoad(Instruction *Load, Value *Mask, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor, const APInt &GapMask) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) !...
bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
StringRef getStackProbeSymbolName(const MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
bool useStackGuardXorFP() const override
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
bool shouldScalarizeBinop(SDValue) const override
Scalar ops always have equal or better analysis/performance/power than the vector equivalent,...
void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool areJTsAllowed(const Function *Fn) const override
Returns true if lowering to a jump table is allowed.
bool isCommutativeBinOp(unsigned Opcode) const override
Returns true if the opcode is a commutative binary operation.
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const override
Returns preferred type for switch condition.
SDValue visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const override
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
bool isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Customize the preferred legalization strategy for certain types.
bool shouldConvertPhiType(Type *From, Type *To) const override
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
bool hasStackProbeSymbol(const MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
This function returns true if the memory access is aligned or if the target allows this specific unal...
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool softPromoteHalfType() const override
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
TargetLowering::AndOrSETCCFoldKind isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const override
Return prefered fold type, Abs if this is a vector, AddAnd if its an integer, None otherwise.
bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT, unsigned SelectOpcode, SDValue X, SDValue Y) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool addressingModeSupportsTLS(const GlobalValue &GV) const override
Returns true if the targets addressing mode can target thread local storage (TLS).
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expansion.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool isBinOp(unsigned Opcode) const override
Add x86-specific opcodes to the default list.
bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const override
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDValue unwrapAddress(SDValue N) const override
CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
bool isTargetCanonicalSelect(SDNode *N) const override
Return true if the given select/vselect should be considered canonical and not be transformed.
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const override
For types supported by the target, this is an identity function.
bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override
Return true if Op can create undef or poison from non-undef & non-poison operands.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool needsFixedCatchObjects() const override
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
@ CXX_FAST_TLS
Used for access functions.
Definition CallingConv.h:72
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition ISDOpcodes.h:41
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
Definition ISDOpcodes.h:587
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition ISDOpcodes.h:601
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.
@ FST
This instruction implements a truncating store from FP stack slots.
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
@ CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
@ FMAX
Floating point max and min.
@ BT
X86 bit-test instructions.
@ HADD
Integer horizontal add/sub.
@ MOVQ2DQ
Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero fi...
@ BLENDI
Blend where the selector is an immediate.
@ CMP
X86 compare and logical compare instructions.
@ BLENDV
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
@ ADDSUB
Combined add and sub on an FP vector.
@ RET_GLUE
Return with a glue operand.
@ STRICT_FMAX
Floating point max and min.
@ STRICT_CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
@ FHADD
Floating point horizontal add/sub.
@ FMAXS
Scalar intrinsic floating point max and min.
@ BSR
Bit scan reverse.
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
@ SETCC
X86 SetCC.
@ NT_BRIND
BRIND node with NoTrack prefix.
@ SELECTS
X86 Select.
@ FSETCCM
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.
@ PEXTRB
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
@ FXOR
Bitwise logical XOR of floating point values.
@ BRCOND
X86 conditional branches.
@ FSETCC
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
@ PINSRB
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
@ INSERTPS
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
@ PSHUFB
Shuffle 16 8-bit values within a vector.
@ PEXTRW
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
@ CALL
These operations represent an abstract X86 call instruction, which includes a bunch of information.
@ AADD
RAO arithmetic instructions.
@ FANDN
Bitwise logical ANDNOT of floating point values.
@ GlobalBaseReg
On Darwin, this node represents the result of the popl at function entry, used for PIC code.
@ FMAXC
Commutative FMIN and FMAX.
@ EXTRQI
SSE4A Extraction and Insertion.
@ FLD
This instruction implements an extending load to FP stack slots.
@ TC_RETURN
Tail call return.
@ PSADBW
Compute Sum of Absolute Differences.
@ FOR
Bitwise logical OR of floating point values.
@ FIST
This instruction implements a fp->int store from FP stack slots.
@ FP_TO_INT_IN_MEM
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.
@ LADD
LOCK-prefixed arithmetic read-modify-write instructions.
@ DBPSADBW
Compute Double Block Packed Sum-Absolute-Differences.
@ MMX_MOVW2D
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.
@ Wrapper
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress,...
@ PINSRW
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
@ CMPCCXADD
Compare and Add if Condition is Met.
@ NT_CALL
Same as call except it adds the NoTrack prefix.
@ MMX_MOVD2W
Copies a 32-bit value from the low word of a MMX vector to a GPR.
@ FILD
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.
@ MOVDQ2Q
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
@ ANDNP
Bitwise Logical AND NOT of Packed FP values.
@ BSF
Bit scan forward.
@ POP_FROM_X87_REG
The same as ISD::CopyFromReg except that this node makes it explicit that it may lower to an x87 FPU ...
@ VAARG_64
These instructions grab the address of the next argument from a va_list.
@ FAND
Bitwise logical AND of floating point values.
@ CMOV
X86 conditional moves.
@ WrapperRIP
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
@ FIRST_STRICTFP_OPCODE
X86 strict FP compare instructions.
@ FSHL
X86 funnel/double shift i16 instructions.
@ FRSQRT
Floating point reciprocal-sqrt and reciprocal approximation.
Define some predicates that are used for node matching.
RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
bool mayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into a vector splat instruction as a memory oper...
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
bool mayFoldIntoZeroExtend(SDValue Op)
Check if Op is an operation that could be folded into a zero extend x86 instruction.
bool mayFoldIntoStore(SDValue Op)
Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory...
bool isExtendedSwiftAsyncFrameSupported(const X86Subtarget &Subtarget, const MachineFunction &MF)
True if the target supports the extended frame for async Swift functions.
int getRoundingModeX86(unsigned RM)
Convert LLVM rounding mode to X86 rounding mode.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
bool mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into some other x86 instruction as a memory oper...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
Returns true of the given offset can be fit into displacement field of the instruction.
bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs)
If Op is a constant whose elements are all the same constant or undefined, return true and return the...
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
InstructionCost Cost
void createUnpackShuffleMask(EVT VT, SmallVectorImpl< int > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
void createSplat2ShuffleMask(MVT VT, SmallVectorImpl< int > &Mask, bool Lo)
Similar to unpacklo/unpackhi, but without the 128-bit lane limitation imposed by AVX and specific to ...
CombineLevel
Definition DAGCombine.h:15
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:565
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
Extended Value Type.
Definition ValueTypes.h:35
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition ValueTypes.h:147
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition ValueTypes.h:65
bool isVector() const
Return true if this is a vector value type.
Definition ValueTypes.h:168
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition ValueTypes.h:323
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition ValueTypes.h:157
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition ValueTypes.h:152
This class contains a discriminated union of information about pointers in memory operands,...