LLVM 19.0.0git
Classes | Public Member Functions | Static Public Member Functions | List of all members
llvm::EVT Struct Reference

Extended Value Type. More...

#include "llvm/CodeGen/ValueTypes.h"

Classes

struct  compareRawBits
 A meaningless but well-behaved order, useful for constructing containers. More...
 

Public Member Functions

constexpr EVT ()=default
 
constexpr EVT (MVT::SimpleValueType SVT)
 
constexpr EVT (MVT S)
 
bool operator== (EVT VT) const
 
bool operator!= (EVT VT) const
 
EVT changeVectorElementTypeToInteger () const
 Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
 
EVT changeVectorElementType (EVT EltVT) const
 Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
 
EVT changeElementType (EVT EltVT) const
 Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
 
EVT changeTypeToInteger () const
 Return the type converted to an equivalently sized integer or vector with integer element type.
 
bool isZeroSized () const
 Test if the given EVT has zero size, this will fail if called on a scalable type.
 
bool isSimple () const
 Test if the given EVT is simple (as opposed to being extended).
 
bool isExtended () const
 Test if the given EVT is extended (as opposed to being simple).
 
bool isFloatingPoint () const
 Return true if this is a FP or a vector FP type.
 
bool isInteger () const
 Return true if this is an integer or a vector integer type.
 
bool isScalarInteger () const
 Return true if this is an integer, but not a vector.
 
bool isScalableTargetExtVT () const
 Return true if this is a vector type where the runtime length is machine dependent.
 
bool isVector () const
 Return true if this is a vector value type.
 
bool isScalableVector () const
 Return true if this is a vector type where the runtime length is machine dependent.
 
bool isFixedLengthVector () const
 
bool isScalableVT () const
 Return true if the type is a scalable type.
 
bool is16BitVector () const
 Return true if this is a 16-bit vector type.
 
bool is32BitVector () const
 Return true if this is a 32-bit vector type.
 
bool is64BitVector () const
 Return true if this is a 64-bit vector type.
 
bool is128BitVector () const
 Return true if this is a 128-bit vector type.
 
bool is256BitVector () const
 Return true if this is a 256-bit vector type.
 
bool is512BitVector () const
 Return true if this is a 512-bit vector type.
 
bool is1024BitVector () const
 Return true if this is a 1024-bit vector type.
 
bool is2048BitVector () const
 Return true if this is a 2048-bit vector type.
 
bool isOverloaded () const
 Return true if this is an overloaded type for TableGen.
 
bool isByteSized () const
 Return true if the bit size is a multiple of 8.
 
bool isRound () const
 Return true if the size is a power-of-two number of bytes.
 
bool bitsEq (EVT VT) const
 Return true if this has the same number of bits as VT.
 
bool knownBitsGT (EVT VT) const
 Return true if we know at compile time this has more bits than VT.
 
bool knownBitsGE (EVT VT) const
 Return true if we know at compile time this has more than or the same bits as VT.
 
bool knownBitsLT (EVT VT) const
 Return true if we know at compile time this has fewer bits than VT.
 
bool knownBitsLE (EVT VT) const
 Return true if we know at compile time this has fewer than or the same bits as VT.
 
bool bitsGT (EVT VT) const
 Return true if this has more bits than VT.
 
bool bitsGE (EVT VT) const
 Return true if this has no less bits than VT.
 
bool bitsLT (EVT VT) const
 Return true if this has less bits than VT.
 
bool bitsLE (EVT VT) const
 Return true if this has no more bits than VT.
 
MVT getSimpleVT () const
 Return the SimpleValueType held in the specified simple EVT.
 
EVT getScalarType () const
 If this is a vector type, return the element type, otherwise return this.
 
EVT getVectorElementType () const
 Given a vector type, return the type of each element.
 
unsigned getVectorNumElements () const
 Given a vector type, return the number of elements it contains.
 
ElementCount getVectorElementCount () const
 
unsigned getVectorMinNumElements () const
 Given a vector type, return the minimum number of elements it contains.
 
TypeSize getSizeInBits () const
 Return the size of the specified value type in bits.
 
uint64_t getFixedSizeInBits () const
 Return the size of the specified fixed width value type in bits.
 
uint64_t getScalarSizeInBits () const
 
TypeSize getStoreSize () const
 Return the number of bytes overwritten by a store of the specified value type.
 
uint64_t getScalarStoreSize () const
 
TypeSize getStoreSizeInBits () const
 Return the number of bits overwritten by a store of the specified value type.
 
EVT getRoundIntegerType (LLVMContext &Context) const
 Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight), and returns the integer EVT with that number of bits.
 
EVT getHalfSizedIntegerVT (LLVMContext &Context) const
 Finds the smallest simple value type that is greater than or equal to half the width of this EVT.
 
EVT widenIntegerVectorElementType (LLVMContext &Context) const
 Return a VT for an integer vector type with the size of the elements doubled.
 
EVT getHalfNumVectorElementsVT (LLVMContext &Context) const
 
EVT getDoubleNumVectorElementsVT (LLVMContext &Context) const
 
bool isPow2VectorType () const
 Returns true if the given vector is a power of 2.
 
EVT getPow2VectorType (LLVMContext &Context) const
 Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
 
std::string getEVTString () const
 This function returns value type as a string, e.g. "i32".
 
void dump () const
 Support for debugging, callable in GDB: VT.dump()
 
void print (raw_ostream &OS) const
 Implement operator<<.
 
TypegetTypeForEVT (LLVMContext &Context) const
 This method returns an LLVM type corresponding to the specified EVT.
 
intptr_t getRawBits () const
 

Static Public Member Functions

static EVT getFloatingPointVT (unsigned BitWidth)
 Returns the EVT that represents a floating-point type with the given number of bits.
 
static EVT getIntegerVT (LLVMContext &Context, unsigned BitWidth)
 Returns the EVT that represents an integer with the given number of bits.
 
static EVT getVectorVT (LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
 Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
 
static EVT getVectorVT (LLVMContext &Context, EVT VT, ElementCount EC)
 Returns the EVT that represents a vector EC.Min elements in length, where each element is of type VT.
 
static EVT getEVT (Type *Ty, bool HandleUnknown=false)
 Return the value type corresponding to the specified type.
 

Detailed Description

Extended Value Type.

Capable of holding value types which are not native for any processor (such as the i12345 type), as well as the types an MVT can represent.

Definition at line 34 of file ValueTypes.h.

Constructor & Destructor Documentation

◆ EVT() [1/3]

constexpr llvm::EVT::EVT ( )
constexprdefault

◆ EVT() [2/3]

constexpr llvm::EVT::EVT ( MVT::SimpleValueType  SVT)
inlineconstexpr

Definition at line 41 of file ValueTypes.h.

◆ EVT() [3/3]

constexpr llvm::EVT::EVT ( MVT  S)
inlineconstexpr

Definition at line 42 of file ValueTypes.h.

Member Function Documentation

◆ bitsEq()

bool llvm::EVT::bitsEq ( EVT  VT) const
inline

Return true if this has the same number of bits as VT.

Definition at line 246 of file ValueTypes.h.

References getSizeInBits().

Referenced by llvm::SelectionDAG::getStrictFPExtendOrRound(), lowerFCMPIntrinsic(), lowerICMPIntrinsic(), and AMDGPUDAGToDAGISel::Select().

◆ bitsGE()

bool llvm::EVT::bitsGE ( EVT  VT) const
inline

◆ bitsGT()

bool llvm::EVT::bitsGT ( EVT  VT) const
inline

◆ bitsLE()

bool llvm::EVT::bitsLE ( EVT  VT) const
inline

◆ bitsLT()

bool llvm::EVT::bitsLT ( EVT  VT) const
inline

◆ changeElementType()

EVT llvm::EVT::changeElementType ( EVT  EltVT) const
inline

Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller.

Definition at line 112 of file ValueTypes.h.

References changeVectorElementType(), getScalarType(), and isVector().

◆ changeTypeToInteger()

EVT llvm::EVT::changeTypeToInteger ( ) const
inline

◆ changeVectorElementType()

EVT llvm::EVT::changeVectorElementType ( EVT  EltVT) const
inline

◆ changeVectorElementTypeToInteger()

EVT llvm::EVT::changeVectorElementTypeToInteger ( ) const
inline

◆ dump()

void EVT::dump ( ) const

Support for debugging, callable in GDB: VT.dump()

Definition at line 193 of file ValueTypes.cpp.

References llvm::dbgs(), and print().

◆ getDoubleNumVectorElementsVT()

EVT llvm::EVT::getDoubleNumVectorElementsVT ( LLVMContext Context) const
inline

◆ getEVT()

EVT EVT::getEVT ( Type Ty,
bool  HandleUnknown = false 
)
static

Return the value type corresponding to the specified type.

getEVT - Return the value type corresponding to the specified type.

This returns all pointers as iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.

This returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.

Definition at line 628 of file ValueTypes.cpp.

References llvm::Type::FixedVectorTyID, llvm::Type::getContext(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getEVT(), getIntegerVT(), llvm::Type::getTypeID(), getVectorVT(), llvm::MVT::getVT(), llvm::Type::IntegerTyID, llvm::Type::ScalableVectorTyID, and llvm::Type::TokenTyID.

Referenced by llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::CallLowering::determineAssignments(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), getEVT(), llvm::TargetLoweringBase::getMemValueType(), llvm::FastISel::getRegForGEPIndex(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getValueType(), llvm::CallLowering::handleAssignments(), llvm::TargetLoweringBase::isExtFree(), isNoopBitcast(), llvm::HexagonTargetLowering::isTruncateFree(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), memVTFromLoadIntrData(), llvm::FastISel::selectBinaryOp(), and splitMergedValStore().

◆ getEVTString()

std::string EVT::getEVTString ( ) const

This function returns value type as a string, e.g. "i32".

getEVTString - This function returns value type as a string, e.g. "i32".

Definition at line 161 of file ValueTypes.cpp.

References getEVTString(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), isFloatingPoint(), isInteger(), isScalableVector(), isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by getEVTString(), print(), llvm::MVT::print(), and llvm::SDNode::print_types().

◆ getFixedSizeInBits()

uint64_t llvm::EVT::getFixedSizeInBits ( ) const
inline

Return the size of the specified fixed width value type in bits.

The function will assert if the type is scalable.

Definition at line 366 of file ValueTypes.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), and getSizeInBits().

Referenced by clampDynamicVectorIndex(), combineBROADCAST_LOAD(), combineLoad(), combineScalarToVector(), detectAVGPattern(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVectorSplice(), findMemType(), llvm::TargetLowering::forceExpandWideMUL(), getCopyFromPartsVector(), getCopyToPartsVector(), getFauxShuffleMask(), getReducedGprRegisterClass(), llvm::SDValue::getScalarValueSizeInBits(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLowering::IncrementMemoryAddress(), IsMulWideOperandDemotable(), llvm::AArch64TargetLowering::isTruncateFree(), llvm::MSP430TargetLowering::isTruncateFree(), llvm::SystemZTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), lookThroughSignExtension(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerVAARG(), performFPExtendCombine(), performSETCCCombine(), performSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PromoteScalarIntegerPTX(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), truncateScalarIntegerArg(), tryWidenMaskForShuffle(), llvm::AArch64Subtarget::useSVEForFixedLengthVectors(), and llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().

◆ getFloatingPointVT()

static EVT llvm::EVT::getFloatingPointVT ( unsigned  BitWidth)
inlinestatic

Returns the EVT that represents a floating-point type with the given number of bits.

There are two floating-point types with 128 bits - this returns f128 rather than ppcf128.

Definition at line 58 of file ValueTypes.h.

References llvm::BitWidth, and llvm::MVT::getFloatingPointVT().

Referenced by combineConcatVectorOfScalars(), EltsFromConsecutiveLoads(), lowerFP_TO_SINT_STORE(), LowerVECTOR_SHUFFLE(), and llvm::LoongArchTargetLowering::ReplaceNodeResults().

◆ getHalfNumVectorElementsVT()

EVT llvm::EVT::getHalfNumVectorElementsVT ( LLVMContext Context) const
inline

◆ getHalfSizedIntegerVT()

EVT llvm::EVT::getHalfSizedIntegerVT ( LLVMContext Context) const
inline

Finds the smallest simple value type that is greater than or equal to half the width of this EVT.

If no simple value type can be found, an extended integer value type of half the size (rounded up) is returned.

Definition at line 415 of file ValueTypes.h.

References assert(), Context, EVT(), getIntegerVT(), getSizeInBits(), isInteger(), and isVector().

Referenced by llvm::TargetLowering::expandUnalignedStore(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), performSUBCombine(), and performVectorAddSubExtCombine().

◆ getIntegerVT()

static EVT llvm::EVT::getIntegerVT ( LLVMContext Context,
unsigned  BitWidth 
)
inlinestatic

Returns the EVT that represents an integer with the given number of bits.

Definition at line 64 of file ValueTypes.h.

References llvm::BitWidth, Context, llvm::MVT::getIntegerVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced by llvm::BasicTTIImplBase< T >::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), combineAnd(), combineBitcastvxi1(), combineBoolVectorAndTruncateStore(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineExtractWithShuffle(), combineLoad(), combineOr(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineShiftToAVG(), combineShuffleToZeroExtendVectorInReg(), combineStore(), combinevXi1ConstantToInteger(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), expandDivFix(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::forceExpandWideMUL(), llvm::getApproximateEVTForLLT(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), getEVT(), getHalfSizedIntegerVT(), getMemsetValue(), getPackedVectorTypeFromPredicateType(), getRoundIntegerType(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), llvm::AMDGPUTargetLowering::getTypeForExtReturn(), llvm::X86TargetLowering::getTypeToTransformTo(), getVectorBitwiseReduce(), llvm::TargetLowering::IncrementMemoryAddress(), lowerBitreverseShuffle(), llvm::SystemZTargetLowering::LowerCall(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerFCMPIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), lowerICMPIntrinsic(), LowerPredicateLoad(), LowerPredicateStore(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), LowerStore(), LowerVectorAllEqual(), narrowIndex(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), PerformExtractFpToIntStores(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), PerformUMinFpToSatCombine(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::FastISel::selectFNeg(), llvm::TargetLowering::ShrinkDemandedOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), and widenIntegerVectorElementType().

◆ getPow2VectorType()

EVT llvm::EVT::getPow2VectorType ( LLVMContext Context) const
inline

◆ getRawBits()

intptr_t llvm::EVT::getRawBits ( ) const
inline

◆ getRoundIntegerType()

EVT llvm::EVT::getRoundIntegerType ( LLVMContext Context) const
inline

Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight), and returns the integer EVT with that number of bits.

Definition at line 404 of file ValueTypes.h.

References assert(), llvm::bit_ceil(), llvm::BitWidth, Context, EVT(), getIntegerVT(), getSizeInBits(), isInteger(), and isVector().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLoweringBase::getTypeConversion(), and narrowIndex().

◆ getScalarSizeInBits()

uint64_t llvm::EVT::getScalarSizeInBits ( ) const
inline

Definition at line 370 of file ValueTypes.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getSizeInBits().

Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), areLoadedOffsetButOtherwiseSame(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canExpandVectorCTPOP(), canLowerSRLToRoundingShiftForVT(), canonicalizeShuffleWithOp(), canReduceVMulWidth(), combineAnd(), combineAndMaskToShift(), combineArithReduction(), combineBinOpOfExtractToReduceTree(), combineBitcast(), combineBitOpWithMOVMSK(), combineBVOfVecSExt(), combineCMP(), combineConcatVectorOps(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineHorizOpWithShuffle(), combineI8TruncStore(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineMul(), combineOr(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCC(), combineShiftAnd1ToBitTest(), combineShiftRightArithmetic(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineTargetShuffle(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorInsert(), combineVectorPack(), combineVectorShiftImm(), combineVSelectWithAllOnesOrZeros(), combineVTRUNC(), combineZext(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::AArch64TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), createBSWAPShuffleMask(), createShuffleMaskFromVSELECT(), llvm::createUnpackShuffleMask(), createVariablePermute(), llvm::X86TargetLowering::decomposeMulByConstant(), detectSSatPattern(), detectUSatPattern(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), EmitVectorComparison(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), expandVPFunnelShift(), extractShiftForRotate(), findMoreOptimalIndexType(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndToUsubsat(), foldBoolSelectToLogic(), llvm::SelectionDAG::FoldConstantArithmetic(), FoldIntToFPToInt(), foldVSelectToSignBitSplatMask(), GeneratePerfectShuffle(), llvm::SelectionDAG::getAllOnesConstant(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::BuildVectorSDNode::getConstantRawBits(), getEXTEND_VECTOR_INREG(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemsetValue(), llvm::GCNTTIImpl::getMinMaxReductionCost(), llvm::ARMTTIImpl::getMinMaxReductionCost(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SelectionDAG::getStepVector(), getTargetConstantBitsFromNode(), getTruncatedUSUBSAT(), getVectorShuffleOpcode(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported(), llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported(), llvm::BuildVectorSDNode::isConstantSequence(), llvm::BuildVectorSDNode::isConstantSplat(), isExtendedBUILD_VECTOR(), isFNEG(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), isLegalBitRotate(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isREVMask(), llvm::ARMTargetLowering::isShuffleMaskLegal(), llvm::SelectionDAG::isSplatValue(), isValidEGW(), isVectorElementSwap(), isVMOVModifiedImm(), llvm::isVREVMask(), isVShiftLImm(), isVShiftRImm(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), isWideDUPMask(), lower1BitShuffle(), lowerBALLOTIntrinsic(), lowerBitreverseShuffle(), LowerCONCAT_VECTORS(), LowerCTPOP(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), LowerFP_TO_INT_SAT(), LowerINSERT_VECTOR_ELT_i1(), lowerMSABitClearImm(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), matchTruncateWithPACK(), MatchVectorAllEqualTest(), narrowIndex(), PerformBITCASTCombine(), performBuildShuffleExtendCombine(), performCONCAT_VECTORSStridedLoadCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), performFP_TO_INTCombine(), performFpToIntCombine(), performGatherLoadCombine(), performLOADCombine(), performMulVectorCmpZeroCombine(), PerformMVEVMULLCombine(), performPostLD1Combine(), performScatterStoreCombine(), performSETCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToWideningLoad(), performSUBCombine(), performSVESpliceCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVZextCombine(), PerformVDUPLANECombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), PerformVQDMULHCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), llvm::X86TargetLowering::ReplaceNodeResults(), SaturateWidenedDIVFIX(), AMDGPUDAGToDAGISel::Select(), selectUmullSmull(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::SelectionDAG::SplitEVL(), stripModuloOnShift(), supportedVectorShiftWithImm(), supportedVectorVarShift(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), TryCombineBaseUpdate(), tryCombineToBSL(), tryLowerToSLI(), tryToFoldExtendOfConstant(), and tryToWidenSetCCOperands().

◆ getScalarStoreSize()

uint64_t llvm::EVT::getScalarStoreSize ( ) const
inline

◆ getScalarType()

EVT llvm::EVT::getScalarType ( ) const
inline

If this is a vector type, return the element type, otherwise return this.

Definition at line 313 of file ValueTypes.h.

References getVectorElementType(), and isVector().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), BuildExactSDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), changeElementType(), combineAnd(), combineArithReduction(), combineBitcast(), combineBitcastvxi1(), combineBITREVERSE(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFMA(), combineFneg(), combineLoad(), combineMinMaxReduction(), combineScalarToVector(), combineSelect(), combineShuffleOfScalars(), combineSIntToFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineTruncatedArithmetic(), combineUIntToFP(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), concatSubVectors(), llvm::createUnpackShuffleMask(), llvm::SITargetLowering::denormalsEnabledForType(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandUINT_TO_FP(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldSetCC(), foldShuffleOfConcatUndefs(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), getCopyFromPartsVector(), getCopyToPartsVector(), getEstimateRefinementSteps(), getFauxShuffleMask(), llvm::SelectionDAG::getLoad(), getMemsetStores(), getMemsetValue(), llvm::X86TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), llvm::SITargetLowering::getNumRegistersForCallingConv(), getReciprocalOpName(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), getScalarSizeInBits(), getScalarStoreSize(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::X86TTIImpl::getVectorInstrCost(), getVectorShuffle(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported(), llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported(), llvm::X86TargetLowering::isExtractVecEltCheap(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::SITargetLowering::isFPExtFoldable(), llvm::AMDGPUTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), isSaturatingMinMax(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::SITargetLowering::lowerFP_EXTEND(), LowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerTruncate(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVectorExtend(), lowerVectorSplatImm(), llvm::SelectionDAG::matchBinOpReduction(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), padEltsToUndef(), performBitcastCombine(), performBuildShuffleExtendCombine(), performExtBinopLoadFold(), performLOADCombine(), PerformMinMaxFpToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), performVectorAddSubExtCombine(), PerformVQDMULHCombine(), performVSelectCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), ReplaceAddWithADDP(), scalarizeExtEltFP(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), setInfoSVEStN(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), llvm::X86TargetLowering::shouldScalarizeBinop(), llvm::AMDGPUTargetLowering::ShouldShrinkFPConstant(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), takeInexpensiveLog2(), tryToFoldExtendOfConstant(), and widenSubVector().

◆ getSimpleVT()

MVT llvm::EVT::getSimpleVT ( ) const
inline

Return the SimpleValueType held in the specified simple EVT.

Definition at line 306 of file ValueTypes.h.

References assert(), and isSimple().

Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::HexagonTargetLowering::allowsMemoryAccess(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(), llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), analyzeCallOperands(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), changeTypeToInteger(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineAndMaskToShift(), combineArithReduction(), combineBitcastvxi1(), combineCONCAT_VECTORS(), combineConcatVectorOps(), combineExtractWithShuffle(), combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineTargetShuffle(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), ComputePTXValueVTs(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), EltsFromConsecutiveLoads(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::SelectionDAG::FoldSetCC(), foldVectorXorShiftIntoCmp(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), getContainerForFixedLengthVector(), getExtensionTo64Bits(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getLdStRegType(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), getPackedSVEVectorVT(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getPredicateForFixedLengthVector(), llvm::FastISel::getRegForGEPIndex(), llvm::FastISel::getRegForValue(), llvm::TargetLoweringBase::getRegisterType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), llvm::SDValue::getSimpleValueType(), llvm::TargetLoweringBase::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::AArch64TTIImpl::getSpliceCost(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(), llvm::SelectionDAG::getValueType(), getVectorTyFromPredicateVector(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::ISD::InputArg::InputArg(), is32Bit(), isAddSubOrSubAdd(), isConstantSplatVectorMaskForType(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), llvm::HexagonTargetLowering::isTruncateFree(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::TargetLoweringBase::isTypeLegal(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), LowerADDSUBSAT(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerFMINIMUM_FMAXIMUM(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::HexagonTargetLowering::LowerLoad(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerStore(), llvm::VETargetLowering::lowerToVVP(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), NarrowVector(), llvm::TargetLowering::ParseConstraints(), performCONCAT_VECTORSStridedLoadCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performFP_TO_INTCombine(), performLOADCombine(), performScatterStoreCombine(), performUADDVZextCombine(), performUzpCombine(), performVSelectCombine(), llvm::SITargetLowering::PostISelFolding(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::FastISel::selectFreeze(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), unpackFromRegLoc(), usePartialVectorLoads(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), llvm::SelectionDAGBuilder::visitBitTestHeader(), WidenVector(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().

◆ getSizeInBits()

TypeSize llvm::EVT::getSizeInBits ( ) const
inline

Return the size of the specified value type in bits.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 358 of file ValueTypes.h.

References isSimple().

Referenced by addRequiredExtensionForVectorMULL(), AddRequiredExtensionForVMULL(), llvm::X86TargetLowering::allowsMemoryAccess(), llvm::SITargetLowering::allowsMisalignedMemoryAccesses(), allUsesTruncate(), llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), bitsEq(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), llvm::AArch64TargetLowering::canMergeStoresTo(), llvm::ARMTargetLowering::canMergeStoresTo(), llvm::X86TargetLowering::canMergeStoresTo(), llvm::R600TargetLowering::canMergeStoresTo(), llvm::SITargetLowering::canMergeStoresTo(), canonicalizeShuffleMaskWithHorizOp(), checkZExtBool(), clampDynamicVectorIndex(), collectConcatOps(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAnd(), combineArithReduction(), combineBasicSADPattern(), combineBEXTR(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBROADCAST_LOAD(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineI8TruncStore(), combineLoad(), combineMinMaxReduction(), combineMulToPMADDWD(), combinePMULH(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSetCC(), combineShiftRightArithmetic(), combineShiftToPMULH(), combineSignExtendInReg(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorSizedSetCCEquality(), combineVEXTRACT_STORE(), combineVPDPBUSDPattern(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), concatSubVectors(), ConstantBuildVector(), constructDup(), constructRetValue(), convertIntLogicToFPLogic(), createPSADBW(), llvm::createUnpackShuffleMask(), llvm::LoongArchTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::decomposeMulByConstant(), detectAVGPattern(), EltsFromConsecutiveLoads(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EmitVectorComparison(), Expand64BitShift(), expandDivFix(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), extractSubVector(), llvm::SwitchCG::SwitchLowering::findBitTestClusters(), findMemType(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendedSignBitTest(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GenerateTBL(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), llvm::SelectionDAG::getElementCount(), getEVTString(), getEXTEND_VECTOR_INREG(), llvm::ARMTTIImpl::getExtendedReductionCost(), getExtensionTo64Bits(), getExtFactor(), getFauxShuffleMask(), getFixedSizeInBits(), getHalfSizedIntegerVT(), getHorizDemandedElts(), getLeftShift(), getLoadStackGuard(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), llvm::ARMTTIImpl::getMulAccReductionCost(), llvm::SelectionDAG::getNeutralElement(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), getOnesVector(), getPackDemandedElts(), getPredicateForFixedLengthVector(), llvm::X86TargetLowering::getPreferredSwitchConditionType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(), getRoundIntegerType(), getScalarSizeInBits(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), getStoreSize(), getTargetConstantBitsFromNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::AMDGPUTargetLowering::getTypeForExtReturn(), llvm::MipsTargetLowering::getTypeForExtReturn(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueSizeInBits(), getVectorBitwiseReduce(), llvm::X86TTIImpl::getVectorInstrCost(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getVScale(), llvm::AArch64TargetLowering::hasAndNot(), llvm::X86TargetLowering::hasAndNot(), llvm::AArch64TargetLowering::hasPairedLoad(), llvm::TargetLowering::IncrementMemoryAddress(), insertSubVector(), isBitfieldDstMask(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), isBitfieldPositioningOpFromAnd(), isByteSized(), isConcatMask(), isConsecutiveLSLoc(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), isExtendedFrom16Bits(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::AArch64TargetLowering::isFPImmLegal(), llvm::HexagonSubtarget::isHVXVectorType(), isI24(), isLegalT2AddressImmediate(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::X86TargetLowering::isMemoryAccessFast(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::AMDGPUTargetLowering::isNarrowingProfitable(), isPackedVectorType(), isPerfectIncrement(), isRound(), isSaturatingMinMax(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::AMDGPUTargetLowering::isTruncateFree(), llvm::ARMTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::PPCTargetLowering::isTruncateFree(), llvm::X86TargetLowering::isTruncateFree(), llvm::AArch64CallLowering::isTypeIsValidForThisReturn(), isUnpackedVectorVT(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidEGW(), isVectorElementSwap(), isWideDUPMask(), isWorthFoldingIntoOrrWithShift(), isZeroSized(), llvm::AArch64TargetLowering::isZExtFree(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), lowerAddSubToHorizontalOp(), llvm::NVPTXTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::MipsTargetLowering::lowerLOAD(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MipsTargetLowering::lowerSTORE(), LowerSVEIntrinsicEXT(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVectorAllEqual(), lowerVectorSplatImm(), lowerX86CmpEqZeroToCtlzSrl(), llvm::ARMTargetLowering::LowerXConstraint(), MatchingStackOffset(), matchPMADDWD_2(), matchTruncateWithPACK(), MatchVectorAllEqualTest(), llvm::ARMTTIImpl::maybeLoweredToCall(), narrowExtractedVectorBinOp(), NormalizeBuildVector(), performANDCombine(), PerformARMBUILD_VECTORCombine(), performBITREVERSECombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractFpToIntStores(), llvm::AMDGPUTargetLowering::performFNegCombine(), performGatherLoadCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performIntToFpCombine(), performLD1Combine(), performLOADCombine(), performMSTORECombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performORCombine(), performScatterStoreCombine(), performSelectCombine(), performSHLCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSRACombine(), performSVEAndCombine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performVectorAddSubExtCombine(), performVectorCompareAndMaskUnaryOpCombine(), PerformVQDMULHCombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), resolveBuildVector(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::FastISel::selectFNeg(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::LoongArchDAGToDAGISel::selectVSplatImm(), llvm::LoongArchDAGToDAGISel::selectVSplatUimmInvPow2(), llvm::LoongArchDAGToDAGISel::selectVSplatUimmPow2(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), shouldTransformMulToShiftsAddsSubs(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SplitOpsAndApply(), splitStores(), splitStoreSplat(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), splitVector(), takeInexpensiveLog2(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), TryCombineBaseUpdate(), tryDemorganOfBooleanCondition(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), UnpackFromArgumentSlot(), unpackFromMemLoc(), unrollVectorShift(), vectorToScalarBitmask(), VerifySDNode(), llvm::SelectionDAGBuilder::visitBitTestHeader(), widenIntegerVectorElementType(), and widenVec().

◆ getStoreSize()

TypeSize llvm::EVT::getStoreSize ( ) const
inline

Return the number of bytes overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 380 of file ValueTypes.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().

Referenced by llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(), llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::X86TargetLowering::BuildFILD(), calculateSrcByte(), CalculateStackSlotAlignment(), CalculateStackSlotSize(), CanMergeParamLoadStoresStartingAt(), combineStore(), ComputePTXValueVTs(), llvm::SelectionDAG::CreateStackTemporary(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVectorSplice(), findConsecutiveLoad(), getBROADCAST_LOAD(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMemIntrinsicNode(), getParamsForOneTrueMaskedElt(), getScalarStoreSize(), llvm::SelectionDAG::getStore(), getStoreSizeInBits(), llvm::PPCTargetLowering::getTgtMemIntrinsic(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), getVPermMask(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), isOnlyUsedByStores(), llvm::AMDGPUTargetLowering::loadStackInputValue(), llvm::SystemZTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::MemSDNode::MemSDNode(), narrowExtractedVectorLoad(), llvm::SITargetLowering::passSpecialInputs(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), ShrinkLoadReplaceStoreWithStore(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), and unpackFromMemLoc().

◆ getStoreSizeInBits()

TypeSize llvm::EVT::getStoreSizeInBits ( ) const
inline

Return the number of bits overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 397 of file ValueTypes.h.

References getStoreSize().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineBoolVectorAndTruncateStore(), EltsFromConsecutiveLoads(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::AMDGPUTargetLowering::shouldReduceLoadWidth(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().

◆ getTypeForEVT()

Type * EVT::getTypeForEVT ( LLVMContext Context) const

This method returns an LLVM type corresponding to the specified EVT.

getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.

For integer types, this returns an unsigned type. Note that this will abort for types that cannot be represented.

Definition at line 202 of file ValueTypes.cpp.

References assert(), Context, llvm::IntegerType::get(), llvm::TargetExtType::get(), llvm::ScalableVectorType::get(), llvm::FixedVectorType::get(), llvm::Type::getBFloatTy(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::Type::getFP128Ty(), llvm::Type::getHalfTy(), llvm::Type::getInt128Ty(), llvm::Type::getInt16Ty(), llvm::Type::getInt1Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), llvm::Type::getInt8Ty(), llvm::Type::getIntNTy(), llvm::Type::getMetadataTy(), llvm::Type::getPPC_FP128Ty(), llvm::Type::getVoidTy(), llvm::Type::getWasm_ExternrefTy(), llvm::Type::getWasm_FuncrefTy(), llvm::Type::getX86_AMXTy(), llvm::Type::getX86_FP80Ty(), llvm::Type::getX86_MMXTy(), isExtended(), and llvm::MVT::SimpleTy.

Referenced by llvm::TargetLoweringBase::allowsMemoryAccessForAlignment(), llvm::analyzeArguments(), canFoldInAddressingMode(), combineTargetShuffle(), llvm::SelectionDAG::CreateStackTemporary(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::SelectionDAG::expandVAArg(), llvm::AArch64TTIImpl::getArithmeticReductionCostSVE(), llvm::AArch64TTIImpl::getCastInstrCost(), getConstantVector(), getDivRemArgList(), llvm::SelectionDAG::getEVTAlign(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemsetStores(), getMemsetStringVal(), llvm::AArch64TTIImpl::getMinMaxReductionCost(), getPrefTypeAlign(), llvm::SelectionDAG::getReducedAlign(), llvm::CallLowering::getReturnInfo(), llvm::AArch64TTIImpl::getSpliceCost(), llvm::PPCTargetLowering::isFMAFasterThanFMulAndFAdd(), isSaturatingMinMax(), llvm::NVPTXTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerFSINCOS(), llvm::AArch64CallLowering::lowerReturn(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), llvm::PPCTargetLowering::PerformDAGCombine(), and llvm::SITargetLowering::ReplaceNodeResults().

◆ getVectorElementCount()

ElementCount llvm::EVT::getVectorElementCount ( ) const
inline

Definition at line 340 of file ValueTypes.h.

References assert(), isSimple(), and isVector().

Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineConcatVectorOfCasts(), combineShiftToAVG(), earlyExpandDIVFIX(), expandDivFix(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandVectorSplice(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendVectorInregToExtendOfSubvector(), getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SelectionDAG::GetDependentSplitDestVTs(), getDoubleNumVectorElementsVT(), getEVTString(), getHalfNumVectorElementsVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::AArch64TargetLowering::getNumRegistersForCallingConv(), getPackedVectorTypeFromPredicateType(), getPow2VectorType(), llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::TargetLoweringBase::getTypeConversion(), getVectorMinNumElements(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::RISCVTargetLowering::PerformDAGCombine(), performIntrinsicCombine(), performLastTrueTestVectorCombine(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), performSUBCombine(), performSVESpliceCombine(), PerformUMinFpToSatCombine(), performVectorAddSubExtCombine(), performVSelectCombine(), setInfoSVEStN(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::SelectionDAG::SplitEVL(), widenIntegerVectorElementType(), and widenVectorToPartType().

◆ getVectorElementType()

EVT llvm::EVT::getVectorElementType ( ) const
inline

Given a vector type, return the type of each element.

Definition at line 318 of file ValueTypes.h.

References assert(), isSimple(), and isVector().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(), CollectOpsToWiden(), combineAdd(), combineBinOpOfExtractToReduceTree(), combineBitcast(), combineBitcastvxi1(), combineBoolVectorAndTruncateStore(), combineCastedMaskArithmetic(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFP_EXTEND(), combineFP_ROUND(), combineMulToPMADDWD(), combineMulToPMULDQ(), combinePMULH(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCC(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfConcatUndef(), combineSIntToFP(), combineStore(), combineTruncateWithSat(), combineUIntToFP(), combineVSelectToBLENDV(), combinevXi1ConstantToInteger(), combineX86ShufflesRecursively(), combineXor(), CompactSwizzlableVector(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), ComputePTXValueVTs(), constructRetValue(), detectAVGPattern(), detectPMADDUBSW(), detectZextAbsDiff(), EmitVectorComparison(), expandDivFix(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVectorSplice(), extractSubVector(), llvm::SelectionDAG::ExtractVectorElements(), findMemType(), findMoreOptimalIndexType(), foldIndexIntoBase(), foldVectorXorShiftIntoCmp(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), llvm::ARMTTIImpl::getArithmeticReductionCost(), getContainerForFixedLengthVector(), getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SelectionDAG::GetDependentSplitDestVTs(), getDoubleNumVectorElementsVT(), getEVTString(), getHalfNumVectorElementsVT(), getInvertedVectorForFMA(), getKnownUndefForVectorBinop(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemsetStringVal(), llvm::ARMTTIImpl::getMinMaxReductionCost(), llvm::SelectionDAG::getNode(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), getOneTrueElt(), getPackedVectorTypeFromPredicateType(), getParamsForOneTrueMaskedElt(), getPow2VectorType(), getPredicateForFixedLengthVector(), getPredicateRegisterClass(), getPromotedVTForPredicate(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), getScalarType(), getShuffleScalarElt(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getSplatVector(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::SelectionDAG::getStepVector(), getSVEPredicateBitCast(), llvm::TargetLoweringBase::getTypeConversion(), getVectorBitwiseReduce(), llvm::TargetLowering::getVectorElementPointer(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), getVPermMask(), insertSubVector(), isConstantSplatVectorMaskForType(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), isFNEG(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), llvm::isMaskType(), llvm::X86TargetLowering::isTypeDesirableForOp(), llvm::HexagonSubtarget::isTypeForHVX(), isValidSplatLoad(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeScatterGatherIndexType(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCTTZ(), llvm::R600TargetLowering::LowerFormalArguments(), lowerMSACopyIntr(), LowerMULO(), llvm::AArch64TargetLowering::LowerOperation(), lowerScalarInsert(), LowerStore(), LowerSVEIntrinsicEXT(), LowerVecReduce(), LowerVecReduceMinMax(), lowerVECTOR_SHUFFLE_VSHF(), LowerVectorINT_TO_FP(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), matchPMADDWD(), matchPMADDWD_2(), matchTruncateWithPACK(), narrowIndex(), NarrowVector(), NormalizeBuildVector(), llvm::MipsCCState::originalEVTTypeIsVectorFloat(), performAddUADDVCombine(), PerformARMBUILD_VECTORCombine(), performBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performDupLane128Combine(), PerformEXTRACTCombine(), performExtractSubvectorCombine(), performFirstTrueTestVectorCombine(), performFPExtendCombine(), performGLD1Combine(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), performIntrinsicCombine(), performLastTrueTestVectorCombine(), PerformLOADCombine(), performLOADCombine(), performMSTORECombine(), performPostLD1Combine(), performScatterStoreCombine(), performSETCCCombine(), performSignExtendInRegCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSTORECombine(), performSUBCombine(), performSVEAndCombine(), performSVESpliceCombine(), performTruncateCombine(), performUnpackCombine(), PerformVDUPLANECombine(), performVecReduceAddCombine(), performVecReduceBitwiseCombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), ReorganizeVector(), replaceBoolVectorBitcast(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceVPICKVE2GRResults(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), AMDGPUDAGToDAGISel::Select(), llvm::LoongArchDAGToDAGISel::Select(), AMDGPUDAGToDAGISel::SelectBuildVector(), SelectOpcodeFromVT(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), truncateAVX512SetCCNoBWI(), TryCombineBaseUpdate(), tryFormConcatFromShuffle(), tryGetOriginalBoolVectorType(), tryWidenMaskForShuffle(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), vectorToScalarBitmask(), widenIntegerVectorElementType(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), llvm::SelectionDAG::WidenVector(), WidenVector(), and widenVectorToPartType().

◆ getVectorMinNumElements()

unsigned llvm::EVT::getVectorMinNumElements ( ) const
inline

◆ getVectorNumElements()

unsigned llvm::EVT::getVectorNumElements ( ) const
inline

Given a vector type, return the number of elements it contains.

Definition at line 326 of file ValueTypes.h.

References assert(), isScalableVector(), isSimple(), isVector(), and llvm::reportInvalidSizeRequest().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), buildScalarToVector(), canCombineShuffleToExtendVectorInreg(), llvm::SelectionDAG::canCreateUndefOrPoison(), canonicalizeShuffleMaskWithHorizOp(), collectConcatOps(), CollectOpsToWiden(), combineAddOfPMADDWD(), combineAnd(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBitcast(), combineBitcastvxi1(), combineBITREVERSE(), combineCMP(), combineConcatVectorOfExtracts(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTEND_VECTOR_INREG(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFP_EXTEND(), combineFP_ROUND(), combineKSHIFT(), combineLoad(), combineMaskedLoadConstantMask(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCCMOVMSK(), combineShuffle(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToConsecutiveLoads(), combineToExtendBoolVectorInReg(), combineTruncateWithSat(), combineTruncationShuffle(), combineUIntToFP(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVPMADD(), combinevXi1ConstantToInteger(), combineX86INT_TO_FP(), combineX86ShufflesRecursively(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), ComputePTXValueVTs(), llvm::SelectionDAG::computeVectorKnownZeroElements(), concatSubVectors(), constructDup(), constructRetValue(), ConvertSelectToConcatVector(), createBSWAPShuffleMask(), createShuffleMaskFromVSELECT(), llvm::createUnpackShuffleMask(), createVariablePermute(), detectAVGPattern(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), ExtractBitFromMaskVector(), extractSubVector(), llvm::SelectionDAG::ExtractVectorElements(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), GenerateFixedLengthSVETBL(), getBuildVectorSplat(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getConstantLaneNumOfExtractHalfOperand(), getCopyFromPartsVector(), getDemandedSrcElements(), getEXTEND_VECTOR_INREG(), getFauxShuffleMask(), getKnownUndefForVectorBinop(), llvm::ShuffleVectorSDNode::getMask(), llvm::VECustomDAG::getMaskBroadcast(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemsetStringVal(), llvm::SelectionDAG::getNode(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), getOneTrueElt(), getPredicateForFixedLengthVector(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::HexagonTargetLowering::getSetCCResultType(), llvm::SITargetLowering::getSetCCResultType(), llvm::NVPTXTargetLowering::getSetCCResultType(), getShuffleScalarElt(), llvm::SelectionDAG::getSplatBuildVector(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getSplatSourceVector(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::SelectionDAG::getStepVector(), getSToVPermuted(), getTargetConstantBitsFromNode(), getTargetShuffleAndZeroables(), getVectorBitwiseReduce(), llvm::SelectionDAG::getVectorShuffle(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), getVPermMask(), isAllConstantBuildVector(), isConcatMask(), isEXTMask(), llvm::ARMTargetLowering::isExtractSubvectorCheap(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), isHorizontalBinOpPart(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalBitRotate(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::isPackedVectorType(), isReverseMask(), isREVMask(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::ARMTargetLowering::isShuffleMaskLegal(), isSingletonEXTMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplatMask(), llvm::SelectionDAG::isSplatValue(), isTargetShuffleEquivalent(), isTRN_v_undef_Mask(), isTRNMask(), isTruncMask(), llvm::HexagonSubtarget::isTypeForHVX(), isUZP_v_undef_Mask(), isUZPMask(), isVectorElementSwap(), isVEXTMask(), isVMOVNMask(), isVMOVNTruncMask(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), isWideDUPMask(), isWideTypeMask(), isZIP_v_undef_Mask(), isZIPMask(), lowerAddSubToHorizontalOp(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerCONCAT_VECTORS_i1(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), lowerMSASplatZExt(), LowerPredicateStore(), LowerReverse_VECTOR_SHUFFLE(), LowerStore(), llvm::VETargetLowering::lowerToVVP(), LowerVecReduce(), LowerVecReduceMinMax(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), matchBinaryShuffle(), matchIndexAsShuffle(), matchIndexAsWiderOp(), matchPMADDWD(), matchPMADDWD_2(), matchScalarReduction(), matchTruncateWithPACK(), mergeEltWithShuffle(), narrowExtractedVectorBinOp(), NarrowVector(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), performBitcastCombine(), performBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performCONCAT_VECTORSStridedLoadCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performINTRINSIC_WO_CHAINCombine(), performIntrinsicCombine(), PerformLOADCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), performSelectCombine(), performSETCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVAddCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), PerformVQDMULHCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), reduceVMULWidth(), ReplaceAddWithADDP(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), AMDGPUDAGToDAGISel::Select(), AMDGPUDAGToDAGISel::SelectBuildVector(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), SplitOpsAndApply(), splitStores(), llvm::AMDGPUTargetLowering::splitVector(), splitVector(), splitVectorIntUnary(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryBuildVectorShuffle(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryCombineToBSL(), tryToFoldExtendOfConstant(), tryWidenMaskForShuffle(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), vectorToScalarBitmask(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), llvm::SelectionDAG::WidenVector(), and WidenVector().

◆ getVectorVT() [1/2]

static EVT llvm::EVT::getVectorVT ( LLVMContext Context,
EVT  VT,
ElementCount  EC 
)
inlinestatic

Returns the EVT that represents a vector EC.Min elements in length, where each element is of type VT.

Definition at line 83 of file ValueTypes.h.

References Context, llvm::MVT::getVectorVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

◆ getVectorVT() [2/2]

static EVT llvm::EVT::getVectorVT ( LLVMContext Context,
EVT  VT,
unsigned  NumElements,
bool  IsScalable = false 
)
inlinestatic

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

Definition at line 73 of file ValueTypes.h.

References Context, llvm::MVT::getVectorVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced by AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), canCombineShuffleToExtendVectorInreg(), CollectOpsToWiden(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBitcastToBoolVector(), combineConcatVectorOfCasts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractWithShuffle(), combineFP_EXTEND(), combineFP_ROUND(), combineI8TruncStore(), combineLoad(), combinePMULH(), combineShiftToAVG(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineUIntToFP(), combineV3I8LoadExt(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), concatSubVectors(), constructRetValue(), convertIntLogicToFPLogic(), detectAVGPattern(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), expandDivFix(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandVectorSplice(), extractSubVector(), foldExtendVectorInregToExtendOfSubvector(), foldShuffleOfConcatUndefs(), GenerateFixedLengthSVETBL(), llvm::getApproximateEVTForLLT(), llvm::SelectionDAG::getConstant(), getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SelectionDAG::GetDependentSplitDestVTs(), getDoubleNumVectorElementsVT(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), getEVT(), getHalfNumVectorElementsVT(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemsetStores(), getMemsetStringVal(), llvm::TargetLoweringBase::getMemValueType(), getPackedVectorTypeFromPredicateType(), getPow2VectorType(), llvm::HexagonTargetLowering::getSetCCResultType(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::SITargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::NVPTXTargetLowering::getSetCCResultType(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUniformBase(), llvm::TargetLoweringBase::getValueType(), llvm::TargetLowering::getVectorElementPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::VECustomDAG::getVectorVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), LowerAsSplatVectorLoad(), lowerBitreverseShuffle(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SITargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerOperation(), LowerSVEIntrinsicEXT(), LowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVSETCC(), llvm::SelectionDAG::matchBinOpReduction(), matchPMADDWD(), matchPMADDWD_2(), memVTFromLoadIntrData(), narrowExtractedVectorBinOp(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformInsertEltCombine(), performIntrinsicCombine(), performLOADCombine(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), performSelectCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), PerformSTORECombine(), performSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), performVecReduceAddCombine(), performVectorAddSubExtCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), setInfoSVEStN(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), widenIntegerVectorElementType(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), and llvm::SelectionDAG::WidenVector().

◆ is1024BitVector()

bool llvm::EVT::is1024BitVector ( ) const
inline

Return true if this is a 1024-bit vector type.

Definition at line 218 of file ValueTypes.h.

References isSimple().

◆ is128BitVector()

bool llvm::EVT::is128BitVector ( ) const
inline

◆ is16BitVector()

bool llvm::EVT::is16BitVector ( ) const
inline

Return true if this is a 16-bit vector type.

Definition at line 188 of file ValueTypes.h.

References isSimple().

◆ is2048BitVector()

bool llvm::EVT::is2048BitVector ( ) const
inline

Return true if this is a 2048-bit vector type.

Definition at line 223 of file ValueTypes.h.

References isSimple().

◆ is256BitVector()

bool llvm::EVT::is256BitVector ( ) const
inline

◆ is32BitVector()

bool llvm::EVT::is32BitVector ( ) const
inline

Return true if this is a 32-bit vector type.

Definition at line 193 of file ValueTypes.h.

References isSimple().

◆ is512BitVector()

bool llvm::EVT::is512BitVector ( ) const
inline

◆ is64BitVector()

bool llvm::EVT::is64BitVector ( ) const
inline

◆ isByteSized()

bool llvm::EVT::isByteSized ( ) const
inline

◆ isExtended()

bool llvm::EVT::isExtended ( ) const
inline

◆ isFixedLengthVector()

bool llvm::EVT::isFixedLengthVector ( ) const
inline

Definition at line 177 of file ValueTypes.h.

References isSimple().

Referenced by clampDynamicVectorIndex(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), convertFromScalableVector(), findMoreOptimalIndexType(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtractSubvectorFromShuffleVector(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), getConstantLaneNumOfExtractHalfOperand(), getContainerForFixedLengthVector(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), llvm::AArch64TargetLowering::getNumRegistersForCallingConv(), getPredicateForFixedLengthVector(), getPredicateForVector(), llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(), getVectorBitwiseReduce(), llvm::isConstOrConstSplat(), llvm::isConstOrConstSplatFP(), llvm::RISCVTargetLowering::isCtpopFast(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), isPackedVectorType(), isPassedInFPR(), llvm::RISCVTargetLowering::LowerOperation(), narrowExtractedVectorBinOp(), performBitcastCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performFP_TO_INTCombine(), performFPExtendCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performIntrinsicCombine(), performSETCCCombine(), performSTORECombine(), performTruncateCombine(), performVecReduceBitwiseCombine(), performVectorAddSubExtCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::SelectionDAG::SplitEVL(), splitStores(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryToFoldExtOfLoad(), llvm::AArch64Subtarget::useSVEForFixedLengthVectors(), and llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().

◆ isFloatingPoint()

bool llvm::EVT::isFloatingPoint ( ) const
inline

Return true if this is a FP or a vector FP type.

Definition at line 146 of file ValueTypes.h.

References isSimple().

Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), combineBitcast(), combineBitcastToBoolVector(), combineBitOpWithMOVMSK(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractWithShuffle(), combineHorizOpWithShuffle(), llvm::VETargetLowering::combineSelect(), combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineVSelectWithAllOnesOrZeros(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), decideComp(), EltsFromConsecutiveLoads(), emitComparison(), EmitVectorComparison(), llvm::AArch64TargetLowering::enableAggressiveFMAFusion(), llvm::PPCTargetLowering::enableAggressiveFMAFusion(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::findOptimalMemOpLowering(), foldAndOrOfSETCC(), llvm::SelectionDAG::FoldSetCC(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getEVTString(), getLdStRegType(), llvm::SelectionDAG::getNode(), getPredicateForSetCC(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::AArch64TargetLowering::hasPairedLoad(), llvm::TargetLoweringBase::isFAbsFree(), llvm::AMDGPUTargetLowering::isFAbsFree(), llvm::TargetLoweringBase::isFNegFree(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::TargetLoweringBase::isFPExtFoldable(), llvm::TargetLoweringBase::isFPExtFree(), llvm::PPCTargetLowering::isFPExtFree(), isLegalT2AddressImmediate(), isLegalToCombineMinNumMaxNum(), isMImm(), llvm::RISCVTargetLowering::isMultiStoresCheaperThanBitsMerge(), llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge(), isPassedInFPR(), isSimm7(), isSupportedType(), llvm::ConstantFPSDNode::isValueValidForType(), llvm::NVPTXTargetLowering::LowerCall(), LowerVectorAllEqual(), LowerVSETCC(), llvm::TargetLowering::LowerXConstraint(), llvm::ARMTargetLowering::LowerXConstraint(), llvm::X86TargetLowering::LowerXConstraint(), llvm::ARMTTIImpl::maybeLoweredToCall(), NormalizeBuildVector(), llvm::MipsCCState::originalEVTTypeIsVectorFloat(), performGatherLoadCombine(), performLD1ReplicateCombine(), performLDNT1Combine(), performScatterStoreCombine(), performSelectCombine(), performST1Combine(), performSTNT1Combine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformVCMPCombine(), performVSelectCombine(), llvm::X86TargetLowering::reduceSelectOfFPConstantLoads(), ReplaceAddWithADDP(), replaceSplatVectorStore(), safeWithoutCompWithNull(), llvm::TargetLowering::SimplifyDemandedBits(), tryWidenMaskForShuffle(), and VerifySDNode().

◆ isInteger()

bool llvm::EVT::isInteger ( ) const
inline

Return true if this is an integer or a vector integer type.

Definition at line 151 of file ValueTypes.h.

References isSimple().

Referenced by AddCombineBUILD_VECTORToVPADDL(), canCombineShuffleToExtendVectorInreg(), combineAddOrSubToADCOrSBB(), combineAndMaskToShift(), combineBinOpOfExtractToReduceTree(), combineBitcast(), combineBITREVERSE(), combineCarryThroughADD(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineExtractWithShuffle(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMul(), combineSelect(), combineSetCC(), combineShiftLeft(), combineShuffleOfScalars(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSubOfBoolean(), combineTruncationShuffle(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), convertValVTToLocVT(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::findOptimalMemOpLowering(), foldAndOrOfSETCC(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldSetCC(), llvm::SelectionDAG::getAssertAlign(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getEVTString(), getHalfSizedIntegerVT(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemsetStringVal(), getMemsetValue(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::TargetLoweringBase::getRegisterType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::GetReturnInfo(), getRoundIntegerType(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::TargetLoweringBase::getTypeConversion(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::AArch64TargetLowering::hasPairedLoad(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), isLegalT2AddressImmediate(), isMImm(), llvm::RISCVTargetLowering::isMultiStoresCheaperThanBitsMerge(), llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge(), isSimm7(), llvm::SelectionDAG::isSplatValue(), isSupportedType(), llvm::ARMTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::AArch64TargetLowering::isTruncateFree(), llvm::MSP430TargetLowering::isTruncateFree(), llvm::PPCTargetLowering::isTruncateFree(), llvm::SystemZTargetLowering::isTruncateFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerMUL(), llvm::TargetLowering::LowerXConstraint(), llvm::ARMTTIImpl::maybeLoweredToCall(), OptimizeNoopCopyExpression(), PerformADDCombineWithOperands(), llvm::ARMTargetLowering::PerformCMOVCombine(), performExtractVectorEltCombine(), performGatherLoadCombine(), performLD1Combine(), performSELECTCombine(), performSignExtendSetCCCombine(), performSVESpliceCombine(), performXORCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::TargetLowering::softenSetCCOperands(), splitIntVSETCC(), takeInexpensiveLog2(), and VerifySDNode().

◆ isOverloaded()

bool llvm::EVT::isOverloaded ( ) const
inline

Return true if this is an overloaded type for TableGen.

Definition at line 228 of file ValueTypes.h.

◆ isPow2VectorType()

bool llvm::EVT::isPow2VectorType ( ) const
inline

◆ isRound()

bool llvm::EVT::isRound ( ) const
inline

◆ isScalableTargetExtVT()

bool llvm::EVT::isScalableTargetExtVT ( ) const
inline

Return true if this is a vector type where the runtime length is machine dependent.

Definition at line 162 of file ValueTypes.h.

References isSimple().

Referenced by isScalableVT().

◆ isScalableVector()

bool llvm::EVT::isScalableVector ( ) const
inline

Return true if this is a vector type where the runtime length is machine dependent.

Definition at line 173 of file ValueTypes.h.

References isSimple().

Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), llvm::SelectionDAG::canCreateUndefOrPoison(), clampDynamicVectorIndex(), combineBinOpOfExtractToReduceTree(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOfShuffleAndItsOperands(), combineShuffleToZeroExtendVectorInReg(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::computeVectorKnownZeroElements(), convertToScalableVector(), convertValVTToLocVT(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), findMemType(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), llvm::AArch64TargetLowering::generateFMAsInMachineCombiner(), llvm::SelectionDAG::getConstant(), getCopyToPartsVector(), getEVTString(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), getPackedVectorTypeFromPredicateType(), getPredicateForScalableVector(), getPredicateRegisterClass(), getPromotedVTForPredicate(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatSourceVector(), llvm::SelectionDAG::getStepVector(), getSVEPredicateBitCast(), getVectorNumElements(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::RISCVTargetLowering::isCtpopFast(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), llvm::HexagonSubtarget::isHVXVectorType(), isPassedInFPR(), isRound(), isScalableVT(), llvm::SelectionDAG::isSplatValue(), isUnpackedVectorVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerOperation(), LowerSVEIntrinsicEXT(), performANDCombine(), performBSPExpandForSVE(), performBUILD_VECTORCombine(), performCONCAT_VECTORSStridedLoadCombine(), performConcatVectorsCombine(), performExtractSubvectorCombine(), performFirstTrueTestVectorCombine(), performGatherLoadCombine(), performINSERT_VECTOR_ELTCombine(), performLastTrueTestVectorCombine(), performLOADCombine(), performScatterStoreCombine(), performSVEMulAddSubCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), replaceZeroVectorStore(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), SelectOpcodeFromVT(), llvm::AArch64TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SelectionDAG::SplitVector(), takeInexpensiveLog2(), trySimplifySrlAddToRshrnb(), and unpackFromMemLoc().

◆ isScalableVT()

bool llvm::EVT::isScalableVT ( ) const
inline

Return true if the type is a scalable type.

Definition at line 183 of file ValueTypes.h.

References isScalableTargetExtVT(), and isScalableVector().

Referenced by canLowerSRLToRoundingShiftForVT(), performSelectCombine(), and performVecReduceAddCombine().

◆ isScalarInteger()

bool llvm::EVT::isScalarInteger ( ) const
inline

◆ isSimple()

bool llvm::EVT::isSimple ( ) const
inline

Test if the given EVT is simple (as opposed to being extended).

Definition at line 136 of file ValueTypes.h.

References llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::R600TargetLowering::allowsMisalignedMemoryAccesses(), analyzeCallOperands(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), changeTypeToInteger(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineAndMaskToShift(), combineBitcastvxi1(), combineConcatVectorOps(), combineMul(), combineStore(), combineVectorInsert(), combineX86ShufflesRecursively(), llvm::createUnpackShuffleMask(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::SelectionDAG::FoldSetCC(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), getExtensionTo64Bits(), getFauxShuffleMask(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::ARMTTIImpl::getMulAccReductionCost(), llvm::TargetLoweringBase::getNumRegisters(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getRawBits(), llvm::FastISel::getRegForValue(), llvm::TargetLoweringBase::getRegisterType(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getSimpleVT(), getSizeInBits(), getSVEContainerType(), getTargetShuffleInputs(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(), llvm::SelectionDAG::getValueType(), getVectorElementCount(), getVectorElementType(), getVectorNumElements(), llvm::AArch64TargetLowering::hasPairedLoad(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), isConstantSplatVectorMaskForType(), isExtended(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), isSaturatingMinMax(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), llvm::HexagonTargetLowering::isTruncateFree(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::TargetLoweringBase::isTypeLegal(), isVector(), isVectorElementSwap(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), LowerADDSUBSAT(), llvm::VETargetLowering::lowerToVVP(), llvm::TargetLowering::ParseConstraints(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performTruncateCombine(), performUzpCombine(), performVSelectCombine(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::TargetLoweringBase::shouldFormOverflowOp(), llvm::X86TargetLowering::shouldFormOverflowOp(), llvm::TargetLowering::SimplifyDemandedBits(), supportedVectorShiftWithImm(), supportedVectorVarShift(), tryGetOriginalBoolVectorType(), usePartialVectorLoads(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), and vectorToScalarBitmask().

◆ isVector()

bool llvm::EVT::isVector ( ) const
inline

Return true if this is a vector value type.

Definition at line 167 of file ValueTypes.h.

References isSimple().

Referenced by adjustLoadValueTypeImpl(), llvm::X86TargetLowering::allowsMemoryAccess(), llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(), llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::SelectionDAG::canCreateUndefOrPoison(), canExpandVectorCTPOP(), changeElementType(), changeTypeToInteger(), CollectOpsToWiden(), combineAdd(), combineAnd(), combineBitcast(), combineBitcastToBoolVector(), combineBITREVERSE(), combineBoolVectorAndTruncateStore(), combineCastedMaskArithmetic(), combineConcatVectorOfCasts(), combineExtSetcc(), combineFMinNumFMaxNum(), combineFP_EXTEND(), combineFP_ROUND(), combineLoad(), combineMul(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combinePMULH(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), llvm::VETargetLowering::combineSelect(), combineSelect(), combineSelectAndUse(), llvm::VETargetLowering::combineSelectCC(), combineSetCC(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfBitcast(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineX86ShufflesRecursively(), combineXor(), combineZext(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), ComputePTXValueVTs(), llvm::SelectionDAG::computeVectorKnownZeroElements(), constructRetValue(), llvm::X86TargetLowering::convertSelectOfConstantsToMath(), detectAVGPattern(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::SelectionDAG::FoldConstantArithmetic(), foldIndexIntoBase(), foldVectorXorShiftIntoCmp(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), llvm::VECustomDAG::getBroadcast(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getDemandedSrcElements(), getEVTString(), getEXTEND_VECTOR_INREG(), getFauxShuffleMask(), getHalfSizedIntegerVT(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), getReciprocalOpName(), llvm::SelectionDAG::getReducedAlign(), llvm::TargetLoweringBase::getRegisterType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), getRoundIntegerType(), getScalarType(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::SelectionDAG::getSetCC(), llvm::HexagonTargetLowering::getSetCCResultType(), llvm::R600TargetLowering::getSetCCResultType(), llvm::SystemZTargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::SITargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::CSKYTargetLowering::getSetCCResultType(), llvm::LoongArchTargetLowering::getSetCCResultType(), llvm::MipsTargetLowering::getSetCCResultType(), llvm::PPCTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::SparcTargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::NVPTXTargetLowering::getSetCCResultType(), llvm::SelectionDAG::getShiftAmountOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::GetSplitDestVTs(), getTargetShuffleInputs(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::TargetLoweringBase::getTypeConversion(), llvm::AMDGPUTargetLowering::getTypeForExtReturn(), llvm::getTypePacking(), llvm::TargetLoweringBase::getTypeToExpandTo(), getVectorElementCount(), getVectorElementType(), getVectorNumElements(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getZeroExtendInReg(), getZeroVector(), llvm::AArch64TargetLowering::hasAndNot(), llvm::VETargetLowering::hasAndNot(), llvm::X86TargetLowering::hasAndNot(), llvm::RISCVTargetLowering::hasAndNotCompare(), llvm::X86TargetLowering::hasAndNotCompare(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), isExtendedFrom16Bits(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), isHorizontalBinOpPart(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::AArch64TargetLowering::isIntDivCheap(), llvm::RISCVTargetLowering::isIntDivCheap(), llvm::X86TargetLowering::isIntDivCheap(), isLegalT2AddressImmediate(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), llvm::isMaskType(), isMImm(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), llvm::isPackedVectorType(), isPackedVectorType(), isSimm7(), llvm::SelectionDAG::isSplatValue(), isSupportedType(), llvm::ARMTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::AArch64TargetLowering::isTruncateFree(), llvm::X86TargetLowering::isTypeDesirableForOp(), isVectorElementSwap(), isVShiftLImm(), isVShiftRImm(), llvm::X86TargetLowering::isXAndYEqZeroPreferableToXAndYEqY(), llvm::AArch64TargetLowering::isZExtFree(), lowerBuildVectorAsBroadcast(), LowerCTTZ(), llvm::AMDGPUTargetLowering::lowerFEXP(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::VETargetLowering::lowerLOAD(), llvm::RISCVTargetLowering::LowerOperation(), LowerShift(), lowerStatepointMetaArgs(), LowerStore(), llvm::VETargetLowering::lowerSTORE(), LowerTruncateVectorStore(), llvm::ARMTargetLowering::LowerXConstraint(), matchPMADDWD(), matchPMADDWD_2(), llvm::X86TargetLowering::mergeStoresAfterLegalization(), llvm::MipsCCState::originalEVTTypeIsVectorFloat(), padEltsToUndef(), PerformADDCombineWithOperands(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INTCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), performMADD_MSUBCombine(), PerformMinMaxFpToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performMULCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), PerformORCombine(), performSelectCombine(), PerformShiftCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), performVectorCompareAndMaskUnaryOpCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), llvm::X86TargetLowering::preferSextInRegOfTruncate(), PromoteMaskArithmetic(), replaceBoolVectorBitcast(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask(), llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::TargetLoweringBase::shouldFormOverflowOp(), llvm::X86TargetLowering::shouldFormOverflowOp(), llvm::TargetLoweringBase::shouldReduceLoadWidth(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::SelectionDAG::SplitScalar(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::AMDGPUTargetLowering::splitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), stripModuloOnShift(), takeInexpensiveLog2(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), truncateAVX512SetCCNoBWI(), truncateVectorWithPACK(), tryCombineToBSL(), tryFoldToZero(), tryGetOriginalBoolVectorType(), tryLowerToSLI(), tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToWidenSetCCOperands(), llvm::SelectionDAG::UnrollVectorOp(), vectorToScalarBitmask(), VerifySDNode(), widenAbs(), widenVec(), and widenVectorToPartType().

◆ isZeroSized()

bool llvm::EVT::isZeroSized ( ) const
inline

Test if the given EVT has zero size, this will fail if called on a scalable type.

Definition at line 131 of file ValueTypes.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isZero().

Referenced by llvm::TargetLoweringBase::allowsMemoryAccessForAlignment(), and isByteSized().

◆ knownBitsGE()

bool llvm::EVT::knownBitsGE ( EVT  VT) const
inline

Return true if we know at compile time this has more than or the same bits as VT.

Definition at line 258 of file ValueTypes.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().

Referenced by bitsGE().

◆ knownBitsGT()

bool llvm::EVT::knownBitsGT ( EVT  VT) const
inline

Return true if we know at compile time this has more bits than VT.

Definition at line 252 of file ValueTypes.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().

Referenced by bitsGT().

◆ knownBitsLE()

bool llvm::EVT::knownBitsLE ( EVT  VT) const
inline

Return true if we know at compile time this has fewer than or the same bits as VT.

Definition at line 269 of file ValueTypes.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().

Referenced by bitsLE().

◆ knownBitsLT()

bool llvm::EVT::knownBitsLT ( EVT  VT) const
inline

Return true if we know at compile time this has fewer bits than VT.

Definition at line 263 of file ValueTypes.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().

Referenced by bitsLT().

◆ operator!=()

bool llvm::EVT::operator!= ( EVT  VT) const
inline

Definition at line 47 of file ValueTypes.h.

References llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, and llvm::MVT::SimpleTy.

◆ operator==()

bool llvm::EVT::operator== ( EVT  VT) const
inline

Definition at line 44 of file ValueTypes.h.

◆ print()

void llvm::EVT::print ( raw_ostream OS) const
inline

Implement operator<<.

Definition at line 481 of file ValueTypes.h.

References getEVTString(), and OS.

Referenced by dump().

◆ widenIntegerVectorElementType()

EVT llvm::EVT::widenIntegerVectorElementType ( LLVMContext Context) const
inline

Return a VT for an integer vector type with the size of the elements doubled.

The typed returned may be an extended type.

Definition at line 429 of file ValueTypes.h.

References Context, getIntegerVT(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), and getVectorVT().

Referenced by performMSTORECombine().


The documentation for this struct was generated from the following files: