LLVM 19.0.0git
LanaiISelLowering.cpp
Go to the documentation of this file.
1//===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LanaiTargetLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LanaiISelLowering.h"
14#include "Lanai.h"
15#include "LanaiCondCode.h"
17#include "LanaiSubtarget.h"
20#include "llvm/ADT/APInt.h"
21#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/StringRef.h"
36#include "llvm/IR/CallingConv.h"
38#include "llvm/IR/Function.h"
39#include "llvm/IR/GlobalValue.h"
43#include "llvm/Support/Debug.h"
49#include <cassert>
50#include <cmath>
51#include <cstdint>
52#include <cstdlib>
53#include <utility>
54
55#define DEBUG_TYPE "lanai-lower"
56
57using namespace llvm;
58
59// Limit on number of instructions the lowered multiplication may have before a
60// call to the library function should be generated instead. The threshold is
61// currently set to 14 as this was the smallest threshold that resulted in all
62// constant multiplications being lowered. A threshold of 5 covered all cases
63// except for one multiplication which required 14. mulsi3 requires 16
64// instructions (including the prologue and epilogue but excluding instructions
65// at call site). Until we can inline mulsi3, generating at most 14 instructions
66// will be faster than invoking mulsi3.
68 "lanai-constant-mul-threshold", cl::Hidden,
69 cl::desc("Maximum number of instruction to generate when lowering constant "
70 "multiplication instead of calling library function [default=14]"),
71 cl::init(14));
72
74 const LanaiSubtarget &STI)
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78
79 // Compute derived properties from the register classes
80 TRI = STI.getRegisterInfo();
82
84
91
96
100
105
112
118
124
129
133
134 // Extended load operations for i1 types must be promoted
135 for (MVT VT : MVT::integer_valuetypes()) {
139 }
140
142
143 // Function alignments
146
147 setJumpIsExpensive(true);
148
149 // TODO: Setting the minimum jump table entries needed before a
150 // switch is transformed to a jump table to 100 to avoid creating jump tables
151 // as this was causing bad performance compared to a large group of if
152 // statements. Re-evaluate this on new benchmarks.
154
155 // Use fast calling convention for library functions.
156 for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
158 }
159
160 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
162 MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
164 MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
166
167 // Booleans always contain 0 or 1.
169
171}
172
174 SelectionDAG &DAG) const {
175 switch (Op.getOpcode()) {
176 case ISD::MUL:
177 return LowerMUL(Op, DAG);
178 case ISD::BR_CC:
179 return LowerBR_CC(Op, DAG);
181 return LowerConstantPool(Op, DAG);
183 return LowerGlobalAddress(Op, DAG);
185 return LowerBlockAddress(Op, DAG);
186 case ISD::JumpTable:
187 return LowerJumpTable(Op, DAG);
188 case ISD::SELECT_CC:
189 return LowerSELECT_CC(Op, DAG);
190 case ISD::SETCC:
191 return LowerSETCC(Op, DAG);
192 case ISD::SHL_PARTS:
193 return LowerSHL_PARTS(Op, DAG);
194 case ISD::SRL_PARTS:
195 return LowerSRL_PARTS(Op, DAG);
196 case ISD::VASTART:
197 return LowerVASTART(Op, DAG);
199 return LowerDYNAMIC_STACKALLOC(Op, DAG);
200 case ISD::RETURNADDR:
201 return LowerRETURNADDR(Op, DAG);
202 case ISD::FRAMEADDR:
203 return LowerFRAMEADDR(Op, DAG);
204 default:
205 llvm_unreachable("unimplemented operand");
206 }
207}
208
209//===----------------------------------------------------------------------===//
210// Lanai Inline Assembly Support
211//===----------------------------------------------------------------------===//
212
214 const char *RegName, LLT /*VT*/,
215 const MachineFunction & /*MF*/) const {
216 // Only unallocatable registers should be matched here.
218 .Case("pc", Lanai::PC)
219 .Case("sp", Lanai::SP)
220 .Case("fp", Lanai::FP)
221 .Case("rr1", Lanai::RR1)
222 .Case("r10", Lanai::R10)
223 .Case("rr2", Lanai::RR2)
224 .Case("r11", Lanai::R11)
225 .Case("rca", Lanai::RCA)
226 .Default(0);
227
228 if (Reg)
229 return Reg;
230 report_fatal_error("Invalid register name global variable");
231}
232
233std::pair<unsigned, const TargetRegisterClass *>
235 StringRef Constraint,
236 MVT VT) const {
237 if (Constraint.size() == 1)
238 // GCC Constraint Letters
239 switch (Constraint[0]) {
240 case 'r': // GENERAL_REGS
241 return std::make_pair(0U, &Lanai::GPRRegClass);
242 default:
243 break;
244 }
245
247}
248
249// Examine constraint type and operand type and determine a weight value.
250// This object must already have been set up with the operand type
251// and the current alternative constraint selected.
254 AsmOperandInfo &Info, const char *Constraint) const {
256 Value *CallOperandVal = Info.CallOperandVal;
257 // If we don't have a value, we can't do a match,
258 // but allow it at the lowest weight.
259 if (CallOperandVal == nullptr)
260 return CW_Default;
261 // Look at the constraint type.
262 switch (*Constraint) {
263 case 'I': // signed 16 bit immediate
264 case 'J': // integer zero
265 case 'K': // unsigned 16 bit immediate
266 case 'L': // immediate in the range 0 to 31
267 case 'M': // signed 32 bit immediate where lower 16 bits are 0
268 case 'N': // signed 26 bit immediate
269 case 'O': // integer zero
270 if (isa<ConstantInt>(CallOperandVal))
271 Weight = CW_Constant;
272 break;
273 default:
275 break;
276 }
277 return Weight;
278}
279
280// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
281// vector. If it is invalid, don't add anything to Ops.
283 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
284 SelectionDAG &DAG) const {
285 SDValue Result;
286
287 // Only support length 1 constraints for now.
288 if (Constraint.size() > 1)
289 return;
290
291 char ConstraintLetter = Constraint[0];
292 switch (ConstraintLetter) {
293 case 'I': // Signed 16 bit constant
294 // If this fails, the parent routine will give an error
295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
296 if (isInt<16>(C->getSExtValue())) {
297 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
298 Op.getValueType());
299 break;
300 }
301 }
302 return;
303 case 'J': // integer zero
304 case 'O':
305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
306 if (C->getZExtValue() == 0) {
307 Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
308 break;
309 }
310 }
311 return;
312 case 'K': // unsigned 16 bit immediate
313 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
314 if (isUInt<16>(C->getZExtValue())) {
315 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
316 Op.getValueType());
317 break;
318 }
319 }
320 return;
321 case 'L': // immediate in the range 0 to 31
322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
323 if (C->getZExtValue() <= 31) {
324 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
325 Op.getValueType());
326 break;
327 }
328 }
329 return;
330 case 'M': // signed 32 bit immediate where lower 16 bits are 0
331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
332 int64_t Val = C->getSExtValue();
333 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
334 Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
335 break;
336 }
337 }
338 return;
339 case 'N': // signed 26 bit immediate
340 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
341 int64_t Val = C->getSExtValue();
342 if ((Val >= -33554432) && (Val <= 33554431)) {
343 Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
344 break;
345 }
346 }
347 return;
348 default:
349 break; // This will fall through to the generic implementation
350 }
351
352 if (Result.getNode()) {
353 Ops.push_back(Result);
354 return;
355 }
356
358}
359
360//===----------------------------------------------------------------------===//
361// Calling Convention Implementation
362//===----------------------------------------------------------------------===//
363
364#include "LanaiGenCallingConv.inc"
365
366static unsigned NumFixedArgs;
367static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
368 CCValAssign::LocInfo LocInfo,
369 ISD::ArgFlagsTy ArgFlags, CCState &State) {
370 // Handle fixed arguments with default CC.
371 // Note: Both the default and fast CC handle VarArg the same and hence the
372 // calling convention of the function is not considered here.
373 if (ValNo < NumFixedArgs) {
374 return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
375 }
376
377 // Promote i8/i16 args to i32
378 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
379 LocVT = MVT::i32;
380 if (ArgFlags.isSExt())
381 LocInfo = CCValAssign::SExt;
382 else if (ArgFlags.isZExt())
383 LocInfo = CCValAssign::ZExt;
384 else
385 LocInfo = CCValAssign::AExt;
386 }
387
388 // VarArgs get passed on stack
389 unsigned Offset = State.AllocateStack(4, Align(4));
390 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
391 return false;
392}
393
394SDValue LanaiTargetLowering::LowerFormalArguments(
395 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
396 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
397 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
398 switch (CallConv) {
399 case CallingConv::C:
401 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
402 default:
403 report_fatal_error("Unsupported calling convention");
404 }
405}
406
407SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
408 SmallVectorImpl<SDValue> &InVals) const {
409 SelectionDAG &DAG = CLI.DAG;
410 SDLoc &DL = CLI.DL;
412 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
414 SDValue Chain = CLI.Chain;
415 SDValue Callee = CLI.Callee;
416 bool &IsTailCall = CLI.IsTailCall;
417 CallingConv::ID CallConv = CLI.CallConv;
418 bool IsVarArg = CLI.IsVarArg;
419
420 // Lanai target does not yet support tail call optimization.
421 IsTailCall = false;
422
423 switch (CallConv) {
425 case CallingConv::C:
426 return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
427 OutVals, Ins, DL, DAG, InVals);
428 default:
429 report_fatal_error("Unsupported calling convention");
430 }
431}
432
433// LowerCCCArguments - transform physical registers into virtual registers and
434// generate load operations for arguments places on the stack.
435SDValue LanaiTargetLowering::LowerCCCArguments(
436 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
437 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
438 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
440 MachineFrameInfo &MFI = MF.getFrameInfo();
443
444 // Assign locations to all of the incoming arguments.
446 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
447 *DAG.getContext());
448 if (CallConv == CallingConv::Fast) {
449 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
450 } else {
451 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
452 }
453
454 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
455 CCValAssign &VA = ArgLocs[i];
456 if (VA.isRegLoc()) {
457 // Arguments passed in registers
458 EVT RegVT = VA.getLocVT();
459 switch (RegVT.getSimpleVT().SimpleTy) {
460 case MVT::i32: {
461 Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
462 RegInfo.addLiveIn(VA.getLocReg(), VReg);
463 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
464
465 // If this is an 8/16-bit value, it is really passed promoted to 32
466 // bits. Insert an assert[sz]ext to capture this, then truncate to the
467 // right size.
468 if (VA.getLocInfo() == CCValAssign::SExt)
469 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
470 DAG.getValueType(VA.getValVT()));
471 else if (VA.getLocInfo() == CCValAssign::ZExt)
472 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
473 DAG.getValueType(VA.getValVT()));
474
475 if (VA.getLocInfo() != CCValAssign::Full)
476 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
477
478 InVals.push_back(ArgValue);
479 break;
480 }
481 default:
482 LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
483 << RegVT << "\n");
484 llvm_unreachable("unhandled argument type");
485 }
486 } else {
487 // Only arguments passed on the stack should make it here.
488 assert(VA.isMemLoc());
489 // Load the argument to a virtual register
490 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
491 // Check that the argument fits in stack slot
492 if (ObjSize > 4) {
493 errs() << "LowerFormalArguments Unhandled argument type: "
494 << VA.getLocVT() << "\n";
495 }
496 // Create the frame index object for this incoming parameter...
497 int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
498
499 // Create the SelectionDAG nodes corresponding to a load
500 // from this parameter
501 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
502 InVals.push_back(DAG.getLoad(
503 VA.getLocVT(), DL, Chain, FIN,
505 }
506 }
507
508 // The Lanai ABI for returning structs by value requires that we copy
509 // the sret argument into rv for the return. Save the argument into
510 // a virtual register so that we can access it from the return points.
511 if (MF.getFunction().hasStructRetAttr()) {
512 Register Reg = LanaiMFI->getSRetReturnReg();
513 if (!Reg) {
515 LanaiMFI->setSRetReturnReg(Reg);
516 }
517 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
518 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
519 }
520
521 if (IsVarArg) {
522 // Record the frame index of the first variable argument
523 // which is a value necessary to VASTART.
524 int FI = MFI.CreateFixedObject(4, CCInfo.getStackSize(), true);
525 LanaiMFI->setVarArgsFrameIndex(FI);
526 }
527
528 return Chain;
529}
530
532 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
533 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
535 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
536
537 return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
538}
539
541LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
542 bool IsVarArg,
544 const SmallVectorImpl<SDValue> &OutVals,
545 const SDLoc &DL, SelectionDAG &DAG) const {
546 // CCValAssign - represent the assignment of the return value to a location
548
549 // CCState - Info about the registers and stack slot.
550 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
551 *DAG.getContext());
552
553 // Analize return values.
554 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
555
556 SDValue Glue;
557 SmallVector<SDValue, 4> RetOps(1, Chain);
558
559 // Copy the result values into the output registers.
560 for (unsigned i = 0; i != RVLocs.size(); ++i) {
561 CCValAssign &VA = RVLocs[i];
562 assert(VA.isRegLoc() && "Can only return in registers!");
563
564 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue);
565
566 // Guarantee that all emitted copies are stuck together with flags.
567 Glue = Chain.getValue(1);
568 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
569 }
570
571 // The Lanai ABI for returning structs by value requires that we copy
572 // the sret argument into rv for the return. We saved the argument into
573 // a virtual register in the entry block, so now we copy the value out
574 // and into rv.
578 Register Reg = LanaiMFI->getSRetReturnReg();
579 assert(Reg &&
580 "SRetReturnReg should have been set in LowerFormalArguments().");
581 SDValue Val =
582 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
583
584 Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Glue);
585 Glue = Chain.getValue(1);
586 RetOps.push_back(
587 DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
588 }
589
590 RetOps[0] = Chain; // Update chain
591
592 unsigned Opc = LanaiISD::RET_GLUE;
593 if (Glue.getNode())
594 RetOps.push_back(Glue);
595
596 // Return Void
597 return DAG.getNode(Opc, DL, MVT::Other,
598 ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
599}
600
601// LowerCCCCallTo - functions arguments are copied from virtual regs to
602// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
603SDValue LanaiTargetLowering::LowerCCCCallTo(
604 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
605 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
606 const SmallVectorImpl<SDValue> &OutVals,
607 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
608 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
609 // Analyze operands of the call, assigning locations to each operand.
611 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
612 *DAG.getContext());
613 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
615
616 NumFixedArgs = 0;
617 if (IsVarArg && G) {
618 const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
619 if (CalleeFn)
621 }
622 if (NumFixedArgs)
623 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
624 else {
625 if (CallConv == CallingConv::Fast)
626 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
627 else
628 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
629 }
630
631 // Get a count of how many bytes are to be pushed on the stack.
632 unsigned NumBytes = CCInfo.getStackSize();
633
634 // Create local copies for byval args.
635 SmallVector<SDValue, 8> ByValArgs;
636 for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
637 ISD::ArgFlagsTy Flags = Outs[I].Flags;
638 if (!Flags.isByVal())
639 continue;
640
641 SDValue Arg = OutVals[I];
642 unsigned Size = Flags.getByValSize();
643 Align Alignment = Flags.getNonZeroByValAlign();
644
645 int FI = MFI.CreateStackObject(Size, Alignment, false);
646 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
647 SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
648
649 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
650 /*IsVolatile=*/false,
651 /*AlwaysInline=*/false,
652 /*isTailCall=*/false, MachinePointerInfo(),
654 ByValArgs.push_back(FIPtr);
655 }
656
657 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
658
660 SmallVector<SDValue, 12> MemOpChains;
662
663 // Walk the register/memloc assignments, inserting copies/loads.
664 for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
665 CCValAssign &VA = ArgLocs[I];
666 SDValue Arg = OutVals[I];
667 ISD::ArgFlagsTy Flags = Outs[I].Flags;
668
669 // Promote the value if needed.
670 switch (VA.getLocInfo()) {
672 break;
674 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
675 break;
677 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
678 break;
680 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
681 break;
682 default:
683 llvm_unreachable("Unknown loc info!");
684 }
685
686 // Use local copy if it is a byval arg.
687 if (Flags.isByVal())
688 Arg = ByValArgs[J++];
689
690 // Arguments that can be passed on register must be kept at RegsToPass
691 // vector
692 if (VA.isRegLoc()) {
693 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
694 } else {
695 assert(VA.isMemLoc());
696
697 if (StackPtr.getNode() == nullptr)
698 StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
700
701 SDValue PtrOff =
702 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
704
705 MemOpChains.push_back(
706 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
707 }
708 }
709
710 // Transform all store nodes into one single node because all store nodes are
711 // independent of each other.
712 if (!MemOpChains.empty())
713 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
714 ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
715
716 SDValue InGlue;
717
718 // Build a sequence of copy-to-reg nodes chained together with token chain and
719 // flag operands which copy the outgoing args into registers. The InGlue in
720 // necessary since all emitted instructions must be stuck together.
721 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
722 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
723 RegsToPass[I].second, InGlue);
724 InGlue = Chain.getValue(1);
725 }
726
727 // If the callee is a GlobalAddress node (quite common, every direct call is)
728 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
729 // Likewise ExternalSymbol -> TargetExternalSymbol.
730 uint8_t OpFlag = LanaiII::MO_NO_FLAG;
731 if (G) {
733 G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
734 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
736 E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
737 }
738
739 // Returns a chain & a flag for retval copy to use.
740 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
742 Ops.push_back(Chain);
743 Ops.push_back(Callee);
744
745 // Add a register mask operand representing the call-preserved registers.
746 // TODO: Should return-twice functions be handled?
747 const uint32_t *Mask =
748 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
749 assert(Mask && "Missing call preserved mask for calling convention");
750 Ops.push_back(DAG.getRegisterMask(Mask));
751
752 // Add argument registers to the end of the list so that they are
753 // known live into the call.
754 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
755 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
756 RegsToPass[I].second.getValueType()));
757
758 if (InGlue.getNode())
759 Ops.push_back(InGlue);
760
761 Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
762 ArrayRef<SDValue>(&Ops[0], Ops.size()));
763 InGlue = Chain.getValue(1);
764
765 // Create the CALLSEQ_END node.
766 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InGlue, DL);
767 InGlue = Chain.getValue(1);
768
769 // Handle result values, copying them out of physregs into vregs that we
770 // return.
771 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
772 InVals);
773}
774
775// LowerCallResult - Lower the result values of a call into the
776// appropriate copies out of appropriate physical registers.
777SDValue LanaiTargetLowering::LowerCallResult(
778 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
779 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
780 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
781 // Assign locations to each value returned by this call.
783 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
784 *DAG.getContext());
785
786 CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
787
788 // Copy all of the result registers out of their specified physreg.
789 for (unsigned I = 0; I != RVLocs.size(); ++I) {
790 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
791 RVLocs[I].getValVT(), InGlue)
792 .getValue(1);
793 InGlue = Chain.getValue(2);
794 InVals.push_back(Chain.getValue(0));
795 }
796
797 return Chain;
798}
799
800//===----------------------------------------------------------------------===//
801// Custom Lowerings
802//===----------------------------------------------------------------------===//
803
805 SDValue &RHS, SelectionDAG &DAG) {
806 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
807
808 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
809 // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
810 // and Lanai only supports integer comparisons, so only provide definitions
811 // for them.
812 switch (SetCCOpcode) {
813 case ISD::SETEQ:
814 return LPCC::ICC_EQ;
815 case ISD::SETGT:
816 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
817 if (RHSC->getZExtValue() == 0xFFFFFFFF) {
818 // X > -1 -> X >= 0 -> is_plus(X)
819 RHS = DAG.getConstant(0, DL, RHS.getValueType());
820 return LPCC::ICC_PL;
821 }
822 return LPCC::ICC_GT;
823 case ISD::SETUGT:
824 return LPCC::ICC_UGT;
825 case ISD::SETLT:
826 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
827 if (RHSC->getZExtValue() == 0)
828 // X < 0 -> is_minus(X)
829 return LPCC::ICC_MI;
830 return LPCC::ICC_LT;
831 case ISD::SETULT:
832 return LPCC::ICC_ULT;
833 case ISD::SETLE:
834 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
835 if (RHSC->getZExtValue() == 0xFFFFFFFF) {
836 // X <= -1 -> X < 0 -> is_minus(X)
837 RHS = DAG.getConstant(0, DL, RHS.getValueType());
838 return LPCC::ICC_MI;
839 }
840 return LPCC::ICC_LE;
841 case ISD::SETULE:
842 return LPCC::ICC_ULE;
843 case ISD::SETGE:
844 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
845 if (RHSC->getZExtValue() == 0)
846 // X >= 0 -> is_plus(X)
847 return LPCC::ICC_PL;
848 return LPCC::ICC_GE;
849 case ISD::SETUGE:
850 return LPCC::ICC_UGE;
851 case ISD::SETNE:
852 return LPCC::ICC_NE;
853 case ISD::SETONE:
854 case ISD::SETUNE:
855 case ISD::SETOGE:
856 case ISD::SETOLE:
857 case ISD::SETOLT:
858 case ISD::SETOGT:
859 case ISD::SETOEQ:
860 case ISD::SETUEQ:
861 case ISD::SETO:
862 case ISD::SETUO:
863 llvm_unreachable("Unsupported comparison.");
864 default:
865 llvm_unreachable("Unknown integer condition code!");
866 }
867}
868
870 SDValue Chain = Op.getOperand(0);
871 SDValue Cond = Op.getOperand(1);
872 SDValue LHS = Op.getOperand(2);
873 SDValue RHS = Op.getOperand(3);
874 SDValue Dest = Op.getOperand(4);
875 SDLoc DL(Op);
876
878 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
879 SDValue Glue =
880 DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
881
882 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
883 TargetCC, Glue);
884}
885
887 EVT VT = Op->getValueType(0);
888 if (VT != MVT::i32)
889 return SDValue();
890
891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
892 if (!C)
893 return SDValue();
894
895 int64_t MulAmt = C->getSExtValue();
896 int32_t HighestOne = -1;
897 uint32_t NonzeroEntries = 0;
898 int SignedDigit[32] = {0};
899
900 // Convert to non-adjacent form (NAF) signed-digit representation.
901 // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
902 // minimal Hamming weight representation of a number (on average 1/3 of the
903 // digits will be non-zero vs 1/2 for regular binary representation). And as
904 // the non-zero digits will be the only digits contributing to the instruction
905 // count, this is desirable. The next loop converts it to NAF (following the
906 // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
907 // choosing the non-zero coefficients such that the resulting quotient is
908 // divisible by 2 which will cause the next coefficient to be zero.
909 int64_t E = std::abs(MulAmt);
910 int S = (MulAmt < 0 ? -1 : 1);
911 int I = 0;
912 while (E > 0) {
913 int ZI = 0;
914 if (E % 2 == 1) {
915 ZI = 2 - (E % 4);
916 if (ZI != 0)
917 ++NonzeroEntries;
918 }
919 SignedDigit[I] = S * ZI;
920 if (SignedDigit[I] == 1)
921 HighestOne = I;
922 E = (E - ZI) / 2;
923 ++I;
924 }
925
926 // Compute number of instructions required. Due to differences in lowering
927 // between the different processors this count is not exact.
928 // Start by assuming a shift and a add/sub for every non-zero entry (hence
929 // every non-zero entry requires 1 shift and 1 add/sub except for the first
930 // entry).
931 int32_t InstrRequired = 2 * NonzeroEntries - 1;
932 // Correct possible over-adding due to shift by 0 (which is not emitted).
933 if (std::abs(MulAmt) % 2 == 1)
934 --InstrRequired;
935 // Return if the form generated would exceed the instruction threshold.
936 if (InstrRequired > LanaiLowerConstantMulThreshold)
937 return SDValue();
938
939 SDValue Res;
940 SDLoc DL(Op);
941 SDValue V = Op->getOperand(0);
942
943 // Initialize the running sum. Set the running sum to the maximal shifted
944 // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
945 // term NAF).
946 if (HighestOne == -1)
947 Res = DAG.getConstant(0, DL, MVT::i32);
948 else {
949 Res = DAG.getNode(ISD::SHL, DL, VT, V,
950 DAG.getConstant(HighestOne, DL, MVT::i32));
951 SignedDigit[HighestOne] = 0;
952 }
953
954 // Assemble multiplication from shift, add, sub using NAF form and running
955 // sum.
956 for (unsigned int I = 0; I < std::size(SignedDigit); ++I) {
957 if (SignedDigit[I] == 0)
958 continue;
959
960 // Shifted multiplicand (v<<i).
961 SDValue Op =
962 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
963 if (SignedDigit[I] == 1)
964 Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
965 else if (SignedDigit[I] == -1)
966 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
967 }
968 return Res;
969}
970
972 SDValue LHS = Op.getOperand(0);
973 SDValue RHS = Op.getOperand(1);
974 SDValue Cond = Op.getOperand(2);
975 SDLoc DL(Op);
976
978 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
979 SDValue Glue =
980 DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
981
982 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue);
983}
984
986 SelectionDAG &DAG) const {
987 SDValue LHS = Op.getOperand(0);
988 SDValue RHS = Op.getOperand(1);
989 SDValue TrueV = Op.getOperand(2);
990 SDValue FalseV = Op.getOperand(3);
991 SDValue Cond = Op.getOperand(4);
992 SDLoc DL(Op);
993
995 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
996 SDValue Glue =
997 DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
998
999 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1000 return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1001 Glue);
1002}
1003
1007
1008 SDLoc DL(Op);
1009 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1011
1012 // vastart just stores the address of the VarArgsFrameIndex slot into the
1013 // memory location argument.
1014 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1015 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1016 MachinePointerInfo(SV));
1017}
1018
1020 SelectionDAG &DAG) const {
1021 SDValue Chain = Op.getOperand(0);
1022 SDValue Size = Op.getOperand(1);
1023 SDLoc DL(Op);
1024
1026
1027 // Get a reference to the stack pointer.
1028 SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1029
1030 // Subtract the dynamic size from the actual stack size to
1031 // obtain the new stack size.
1032 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1033
1034 // For Lanai, the outgoing memory arguments area should be on top of the
1035 // alloca area on the stack i.e., the outgoing memory arguments should be
1036 // at a lower address than the alloca area. Move the alloca area down the
1037 // stack by adding back the space reserved for outgoing arguments to SP
1038 // here.
1039 //
1040 // We do not know what the size of the outgoing args is at this point.
1041 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1042 // stack pointer. We replace this instruction with on that has the correct,
1043 // known offset in emitPrologue().
1044 SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1045
1046 // The Sub result contains the new stack start address, so it
1047 // must be placed in the stack pointer register.
1048 SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1049
1050 SDValue Ops[2] = {ArgAdjust, CopyChain};
1051 return DAG.getMergeValues(Ops, DL);
1052}
1053
1055 SelectionDAG &DAG) const {
1057 MachineFrameInfo &MFI = MF.getFrameInfo();
1058 MFI.setReturnAddressIsTaken(true);
1059
1060 EVT VT = Op.getValueType();
1061 SDLoc DL(Op);
1062 unsigned Depth = Op.getConstantOperandVal(0);
1063 if (Depth) {
1064 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1065 const unsigned Offset = -4;
1066 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1068 return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1069 }
1070
1071 // Return the link register, which contains the return address.
1072 // Mark it an implicit live-in.
1073 Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1074 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1075}
1076
1078 SelectionDAG &DAG) const {
1080 MFI.setFrameAddressIsTaken(true);
1081
1082 EVT VT = Op.getValueType();
1083 SDLoc DL(Op);
1084 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1085 unsigned Depth = Op.getConstantOperandVal(0);
1086 while (Depth--) {
1087 const unsigned Offset = -8;
1088 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1090 FrameAddr =
1091 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1092 }
1093 return FrameAddr;
1094}
1095
1096const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1097 switch (Opcode) {
1099 return "LanaiISD::ADJDYNALLOC";
1100 case LanaiISD::RET_GLUE:
1101 return "LanaiISD::RET_GLUE";
1102 case LanaiISD::CALL:
1103 return "LanaiISD::CALL";
1105 return "LanaiISD::SELECT_CC";
1106 case LanaiISD::SETCC:
1107 return "LanaiISD::SETCC";
1108 case LanaiISD::SUBBF:
1109 return "LanaiISD::SUBBF";
1110 case LanaiISD::SET_FLAG:
1111 return "LanaiISD::SET_FLAG";
1112 case LanaiISD::BR_CC:
1113 return "LanaiISD::BR_CC";
1114 case LanaiISD::Wrapper:
1115 return "LanaiISD::Wrapper";
1116 case LanaiISD::HI:
1117 return "LanaiISD::HI";
1118 case LanaiISD::LO:
1119 return "LanaiISD::LO";
1120 case LanaiISD::SMALL:
1121 return "LanaiISD::SMALL";
1122 default:
1123 return nullptr;
1124 }
1125}
1126
1128 SelectionDAG &DAG) const {
1129 SDLoc DL(Op);
1130 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1131 const Constant *C = N->getConstVal();
1132 const LanaiTargetObjectFile *TLOF =
1133 static_cast<const LanaiTargetObjectFile *>(
1135
1136 // If the code model is small or constant will be placed in the small section,
1137 // then assume address will fit in 21-bits.
1140 SDValue Small = DAG.getTargetConstantPool(
1141 C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG);
1142 return DAG.getNode(ISD::OR, DL, MVT::i32,
1143 DAG.getRegister(Lanai::R0, MVT::i32),
1144 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1145 } else {
1146 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1147 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1148
1149 SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1150 N->getOffset(), OpFlagHi);
1151 SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1152 N->getOffset(), OpFlagLo);
1153 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1154 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1155 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1156 return Result;
1157 }
1158}
1159
1161 SelectionDAG &DAG) const {
1162 SDLoc DL(Op);
1163 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1164 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1165
1166 const LanaiTargetObjectFile *TLOF =
1167 static_cast<const LanaiTargetObjectFile *>(
1169
1170 // If the code model is small or global variable will be placed in the small
1171 // section, then assume address will fit in 21-bits.
1172 const GlobalObject *GO = GV->getAliaseeObject();
1173 if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1174 SDValue Small = DAG.getTargetGlobalAddress(
1176 return DAG.getNode(ISD::OR, DL, MVT::i32,
1177 DAG.getRegister(Lanai::R0, MVT::i32),
1178 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1179 } else {
1180 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1181 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1182
1183 // Create the TargetGlobalAddress node, folding in the constant offset.
1185 GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1187 GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1188 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1189 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1190 return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1191 }
1192}
1193
1195 SelectionDAG &DAG) const {
1196 SDLoc DL(Op);
1197 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1198
1199 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1200 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1201
1202 SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1203 SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1204 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1205 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1206 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1207 return Result;
1208}
1209
1211 SelectionDAG &DAG) const {
1212 SDLoc DL(Op);
1213 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1214
1215 // If the code model is small assume address will fit in 21-bits.
1217 SDValue Small = DAG.getTargetJumpTable(
1218 JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1219 return DAG.getNode(ISD::OR, DL, MVT::i32,
1220 DAG.getRegister(Lanai::R0, MVT::i32),
1221 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1222 } else {
1223 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1224 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1225
1227 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1229 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1230 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1231 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1232 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1233 return Result;
1234 }
1235}
1236
1238 SelectionDAG &DAG) const {
1239 EVT VT = Op.getValueType();
1240 unsigned VTBits = VT.getSizeInBits();
1241 SDLoc dl(Op);
1242 assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1243 SDValue ShOpLo = Op.getOperand(0);
1244 SDValue ShOpHi = Op.getOperand(1);
1245 SDValue ShAmt = Op.getOperand(2);
1246
1247 // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1248 // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1249 // HiBitsForHi = ShOpHi << ShAmt
1250 // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1251 // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1252 // return (Hi << 32) | Lo;
1253
1254 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1255 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1256 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1257
1258 // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1259 // wanted 0, so CSEL it directly.
1260 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1261 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1262 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1263
1264 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1265 DAG.getConstant(VTBits, dl, MVT::i32));
1266 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1267 SDValue HiForNormalShift =
1268 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1269
1270 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1271
1272 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1273 SDValue Hi =
1274 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1275
1276 // Lanai shifts of larger than register sizes are wrapped rather than
1277 // clamped, so we can't just emit "lo << b" if b is too big.
1278 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1279 SDValue Lo = DAG.getSelect(
1280 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1281
1282 SDValue Ops[2] = {Lo, Hi};
1283 return DAG.getMergeValues(Ops, dl);
1284}
1285
1287 SelectionDAG &DAG) const {
1288 MVT VT = Op.getSimpleValueType();
1289 unsigned VTBits = VT.getSizeInBits();
1290 SDLoc dl(Op);
1291 SDValue ShOpLo = Op.getOperand(0);
1292 SDValue ShOpHi = Op.getOperand(1);
1293 SDValue ShAmt = Op.getOperand(2);
1294
1295 // Performs the following for a >> b:
1296 // unsigned r_high = a_high >> b;
1297 // r_high = (32 - b <= 0) ? 0 : r_high;
1298 //
1299 // unsigned r_low = a_low >> b;
1300 // r_low = (32 - b <= 0) ? r_high : r_low;
1301 // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1302 // return (unsigned long long)r_high << 32 | r_low;
1303 // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1304 // mask the shift amount.
1305
1306 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1307 SDValue NegatedPlus32 = DAG.getNode(
1308 ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1309 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1310
1311 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1312 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1313
1314 SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1315 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1316 SDValue CarryBits =
1317 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1318 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1319 Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1320 DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1321
1322 SDValue Ops[2] = {Lo, Hi};
1323 return DAG.getMergeValues(Ops, dl);
1324}
1325
1326// Helper function that checks if N is a null or all ones constant.
1327static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1329}
1330
1331// Return true if N is conditionally 0 or all ones.
1332// Detects these expressions where cc is an i1 value:
1333//
1334// (select cc 0, y) [AllOnes=0]
1335// (select cc y, 0) [AllOnes=0]
1336// (zext cc) [AllOnes=0]
1337// (sext cc) [AllOnes=0/1]
1338// (select cc -1, y) [AllOnes=1]
1339// (select cc y, -1) [AllOnes=1]
1340//
1341// * AllOnes determines whether to check for an all zero (AllOnes false) or an
1342// all ones operand (AllOnes true).
1343// * Invert is set when N is the all zero/ones constant when CC is false.
1344// * OtherOp is set to the alternative value of N.
1345//
1346// For example, for (select cc X, Y) and AllOnes = 0 if:
1347// * X = 0, Invert = False and OtherOp = Y
1348// * Y = 0, Invert = True and OtherOp = X
1350 bool &Invert, SDValue &OtherOp,
1351 SelectionDAG &DAG) {
1352 switch (N->getOpcode()) {
1353 default:
1354 return false;
1355 case ISD::SELECT: {
1356 CC = N->getOperand(0);
1357 SDValue N1 = N->getOperand(1);
1358 SDValue N2 = N->getOperand(2);
1359 if (isZeroOrAllOnes(N1, AllOnes)) {
1360 Invert = false;
1361 OtherOp = N2;
1362 return true;
1363 }
1364 if (isZeroOrAllOnes(N2, AllOnes)) {
1365 Invert = true;
1366 OtherOp = N1;
1367 return true;
1368 }
1369 return false;
1370 }
1371 case ISD::ZERO_EXTEND: {
1372 // (zext cc) can never be the all ones value.
1373 if (AllOnes)
1374 return false;
1375 CC = N->getOperand(0);
1376 if (CC.getValueType() != MVT::i1)
1377 return false;
1378 SDLoc dl(N);
1379 EVT VT = N->getValueType(0);
1380 OtherOp = DAG.getConstant(1, dl, VT);
1381 Invert = true;
1382 return true;
1383 }
1384 case ISD::SIGN_EXTEND: {
1385 CC = N->getOperand(0);
1386 if (CC.getValueType() != MVT::i1)
1387 return false;
1388 SDLoc dl(N);
1389 EVT VT = N->getValueType(0);
1390 Invert = !AllOnes;
1391 if (AllOnes)
1392 // When looking for an AllOnes constant, N is an sext, and the 'other'
1393 // value is 0.
1394 OtherOp = DAG.getConstant(0, dl, VT);
1395 else
1396 OtherOp = DAG.getAllOnesConstant(dl, VT);
1397 return true;
1398 }
1399 }
1400}
1401
1402// Combine a constant select operand into its use:
1403//
1404// (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1405// (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1406// (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1407// (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1408// (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1409//
1410// The transform is rejected if the select doesn't have a constant operand that
1411// is null, or all ones when AllOnes is set.
1412//
1413// Also recognize sext/zext from i1:
1414//
1415// (add (zext cc), x) -> (select cc (add x, 1), x)
1416// (add (sext cc), x) -> (select cc (add x, -1), x)
1417//
1418// These transformations eventually create predicated instructions.
1421 bool AllOnes) {
1422 SelectionDAG &DAG = DCI.DAG;
1423 EVT VT = N->getValueType(0);
1424 SDValue NonConstantVal;
1425 SDValue CCOp;
1426 bool SwapSelectOps;
1427 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1428 NonConstantVal, DAG))
1429 return SDValue();
1430
1431 // Slct is now know to be the desired identity constant when CC is true.
1432 SDValue TrueVal = OtherOp;
1433 SDValue FalseVal =
1434 DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1435 // Unless SwapSelectOps says CC should be false.
1436 if (SwapSelectOps)
1437 std::swap(TrueVal, FalseVal);
1438
1439 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1440}
1441
1442// Attempt combineSelectAndUse on each operand of a commutative operator N.
1443static SDValue
1445 bool AllOnes) {
1446 SDValue N0 = N->getOperand(0);
1447 SDValue N1 = N->getOperand(1);
1448 if (N0.getNode()->hasOneUse())
1449 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1450 return Result;
1451 if (N1.getNode()->hasOneUse())
1452 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1453 return Result;
1454 return SDValue();
1455}
1456
1457// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1460 SDValue N0 = N->getOperand(0);
1461 SDValue N1 = N->getOperand(1);
1462
1463 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1464 if (N1.getNode()->hasOneUse())
1465 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1466 return Result;
1467
1468 return SDValue();
1469}
1470
1472 DAGCombinerInfo &DCI) const {
1473 switch (N->getOpcode()) {
1474 default:
1475 break;
1476 case ISD::ADD:
1477 case ISD::OR:
1478 case ISD::XOR:
1479 return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1480 case ISD::AND:
1481 return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1482 case ISD::SUB:
1483 return PerformSUBCombine(N, DCI);
1484 }
1485
1486 return SDValue();
1487}
1488
1490 const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1491 const SelectionDAG &DAG, unsigned Depth) const {
1492 unsigned BitWidth = Known.getBitWidth();
1493 switch (Op.getOpcode()) {
1494 default:
1495 break;
1496 case LanaiISD::SETCC:
1497 Known = KnownBits(BitWidth);
1498 Known.Zero.setBits(1, BitWidth);
1499 break;
1501 KnownBits Known2;
1502 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1503 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1504 Known = Known.intersectWith(Known2);
1505 break;
1506 }
1507}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements a class to represent arbitrary precision integral constant values and operations...
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
static SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
#define RegName(no)
static unsigned NumFixedArgs
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
LLVMContext & Context
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:76
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
Definition: APInt.h:1345
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:889
CCState - This class holds information needed while lowering arguments and return values.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
bool isMemLoc() const
int64_t getLocMemOffset() const
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:142
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:201
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:662
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:375
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
const LanaiRegisterInfo * getRegisterInfo() const override
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
Machine Value Type.
SimpleValueType SimpleTy
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setReturnAddressIsTaken(bool s)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool hasOneUse() const
Return true if there is exactly one use of this node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:721
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:731
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:471
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
Definition: SelectionDAG.h:658
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:772
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:675
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:468
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:798
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
Definition: SelectionDAG.h:484
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:738
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:553
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
virtual TargetLoweringObjectFile * getObjFileLowering() const
CodeModel::Model getCodeModel() const
Returns the code model.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:750
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1126
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1122
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:714
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1155
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:783
@ RETURNADDR
Definition: ISDOpcodes.h:95
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1077
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1056
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:727
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1151
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:651
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:780
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:742
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:1041
@ ConstantPool
Definition: ISDOpcodes.h:82
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:798
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:786
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1146
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1070
@ BlockAddress
Definition: ISDOpcodes.h:84
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:763
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
@ AssertZext
Definition: ISDOpcodes.h:62
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1523
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:306
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
Definition: KnownBits.h:307
unsigned getRARegister() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals