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LanaiISelLowering.cpp
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1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LanaiTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LanaiISelLowering.h"
14 #include "Lanai.h"
15 #include "LanaiCondCode.h"
17 #include "LanaiSubtarget.h"
18 #include "LanaiTargetObjectFile.h"
20 #include "llvm/ADT/APInt.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalValue.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/KnownBits.h"
49 #include <cassert>
50 #include <cmath>
51 #include <cstdint>
52 #include <cstdlib>
53 #include <utility>
54 
55 #define DEBUG_TYPE "lanai-lower"
56 
57 using namespace llvm;
58 
59 // Limit on number of instructions the lowered multiplication may have before a
60 // call to the library function should be generated instead. The threshold is
61 // currently set to 14 as this was the smallest threshold that resulted in all
62 // constant multiplications being lowered. A threshold of 5 covered all cases
63 // except for one multiplication which required 14. mulsi3 requires 16
64 // instructions (including the prologue and epilogue but excluding instructions
65 // at call site). Until we can inline mulsi3, generating at most 14 instructions
66 // will be faster than invoking mulsi3.
68  "lanai-constant-mul-threshold", cl::Hidden,
69  cl::desc("Maximum number of instruction to generate when lowering constant "
70  "multiplication instead of calling library function [default=14]"),
71  cl::init(14));
72 
74  const LanaiSubtarget &STI)
75  : TargetLowering(TM) {
76  // Set up the register classes.
77  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78 
79  // Compute derived properties from the register classes
80  TRI = STI.getRegisterInfo();
82 
84 
91 
96 
100 
105 
112 
118 
124 
129 
133 
134  // Extended load operations for i1 types must be promoted
135  for (MVT VT : MVT::integer_valuetypes()) {
139  }
140 
142 
143  // Function alignments
146 
147  setJumpIsExpensive(true);
148 
149  // TODO: Setting the minimum jump table entries needed before a
150  // switch is transformed to a jump table to 100 to avoid creating jump tables
151  // as this was causing bad performance compared to a large group of if
152  // statements. Re-evaluate this on new benchmarks.
154 
155  // Use fast calling convention for library functions.
156  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
158  }
159 
160  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
162  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
164  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
166 
167  // Booleans always contain 0 or 1.
169 }
170 
172  SelectionDAG &DAG) const {
173  switch (Op.getOpcode()) {
174  case ISD::MUL:
175  return LowerMUL(Op, DAG);
176  case ISD::BR_CC:
177  return LowerBR_CC(Op, DAG);
178  case ISD::ConstantPool:
179  return LowerConstantPool(Op, DAG);
180  case ISD::GlobalAddress:
181  return LowerGlobalAddress(Op, DAG);
182  case ISD::BlockAddress:
183  return LowerBlockAddress(Op, DAG);
184  case ISD::JumpTable:
185  return LowerJumpTable(Op, DAG);
186  case ISD::SELECT_CC:
187  return LowerSELECT_CC(Op, DAG);
188  case ISD::SETCC:
189  return LowerSETCC(Op, DAG);
190  case ISD::SHL_PARTS:
191  return LowerSHL_PARTS(Op, DAG);
192  case ISD::SRL_PARTS:
193  return LowerSRL_PARTS(Op, DAG);
194  case ISD::VASTART:
195  return LowerVASTART(Op, DAG);
197  return LowerDYNAMIC_STACKALLOC(Op, DAG);
198  case ISD::RETURNADDR:
199  return LowerRETURNADDR(Op, DAG);
200  case ISD::FRAMEADDR:
201  return LowerFRAMEADDR(Op, DAG);
202  default:
203  llvm_unreachable("unimplemented operand");
204  }
205 }
206 
207 //===----------------------------------------------------------------------===//
208 // Lanai Inline Assembly Support
209 //===----------------------------------------------------------------------===//
210 
212  const char *RegName, LLT /*VT*/,
213  const MachineFunction & /*MF*/) const {
214  // Only unallocatable registers should be matched here.
216  .Case("pc", Lanai::PC)
217  .Case("sp", Lanai::SP)
218  .Case("fp", Lanai::FP)
219  .Case("rr1", Lanai::RR1)
220  .Case("r10", Lanai::R10)
221  .Case("rr2", Lanai::RR2)
222  .Case("r11", Lanai::R11)
223  .Case("rca", Lanai::RCA)
224  .Default(0);
225 
226  if (Reg)
227  return Reg;
228  report_fatal_error("Invalid register name global variable");
229 }
230 
231 std::pair<unsigned, const TargetRegisterClass *>
233  StringRef Constraint,
234  MVT VT) const {
235  if (Constraint.size() == 1)
236  // GCC Constraint Letters
237  switch (Constraint[0]) {
238  case 'r': // GENERAL_REGS
239  return std::make_pair(0U, &Lanai::GPRRegClass);
240  default:
241  break;
242  }
243 
244  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
245 }
246 
247 // Examine constraint type and operand type and determine a weight value.
248 // This object must already have been set up with the operand type
249 // and the current alternative constraint selected.
252  AsmOperandInfo &Info, const char *Constraint) const {
253  ConstraintWeight Weight = CW_Invalid;
254  Value *CallOperandVal = Info.CallOperandVal;
255  // If we don't have a value, we can't do a match,
256  // but allow it at the lowest weight.
257  if (CallOperandVal == nullptr)
258  return CW_Default;
259  // Look at the constraint type.
260  switch (*Constraint) {
261  case 'I': // signed 16 bit immediate
262  case 'J': // integer zero
263  case 'K': // unsigned 16 bit immediate
264  case 'L': // immediate in the range 0 to 31
265  case 'M': // signed 32 bit immediate where lower 16 bits are 0
266  case 'N': // signed 26 bit immediate
267  case 'O': // integer zero
268  if (isa<ConstantInt>(CallOperandVal))
269  Weight = CW_Constant;
270  break;
271  default:
273  break;
274  }
275  return Weight;
276 }
277 
278 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
279 // vector. If it is invalid, don't add anything to Ops.
281  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
282  SelectionDAG &DAG) const {
283  SDValue Result;
284 
285  // Only support length 1 constraints for now.
286  if (Constraint.length() > 1)
287  return;
288 
289  char ConstraintLetter = Constraint[0];
290  switch (ConstraintLetter) {
291  case 'I': // Signed 16 bit constant
292  // If this fails, the parent routine will give an error
293  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
294  if (isInt<16>(C->getSExtValue())) {
295  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
296  Op.getValueType());
297  break;
298  }
299  }
300  return;
301  case 'J': // integer zero
302  case 'O':
303  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
304  if (C->getZExtValue() == 0) {
305  Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
306  break;
307  }
308  }
309  return;
310  case 'K': // unsigned 16 bit immediate
311  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
312  if (isUInt<16>(C->getZExtValue())) {
313  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
314  Op.getValueType());
315  break;
316  }
317  }
318  return;
319  case 'L': // immediate in the range 0 to 31
320  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
321  if (C->getZExtValue() <= 31) {
322  Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
323  Op.getValueType());
324  break;
325  }
326  }
327  return;
328  case 'M': // signed 32 bit immediate where lower 16 bits are 0
329  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
330  int64_t Val = C->getSExtValue();
331  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
332  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
333  break;
334  }
335  }
336  return;
337  case 'N': // signed 26 bit immediate
338  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
339  int64_t Val = C->getSExtValue();
340  if ((Val >= -33554432) && (Val <= 33554431)) {
341  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
342  break;
343  }
344  }
345  return;
346  default:
347  break; // This will fall through to the generic implementation
348  }
349 
350  if (Result.getNode()) {
351  Ops.push_back(Result);
352  return;
353  }
354 
355  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
356 }
357 
358 //===----------------------------------------------------------------------===//
359 // Calling Convention Implementation
360 //===----------------------------------------------------------------------===//
361 
362 #include "LanaiGenCallingConv.inc"
363 
364 static unsigned NumFixedArgs;
365 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
366  CCValAssign::LocInfo LocInfo,
367  ISD::ArgFlagsTy ArgFlags, CCState &State) {
368  // Handle fixed arguments with default CC.
369  // Note: Both the default and fast CC handle VarArg the same and hence the
370  // calling convention of the function is not considered here.
371  if (ValNo < NumFixedArgs) {
372  return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
373  }
374 
375  // Promote i8/i16 args to i32
376  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
377  LocVT = MVT::i32;
378  if (ArgFlags.isSExt())
379  LocInfo = CCValAssign::SExt;
380  else if (ArgFlags.isZExt())
381  LocInfo = CCValAssign::ZExt;
382  else
383  LocInfo = CCValAssign::AExt;
384  }
385 
386  // VarArgs get passed on stack
387  unsigned Offset = State.AllocateStack(4, Align(4));
388  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
389  return false;
390 }
391 
392 SDValue LanaiTargetLowering::LowerFormalArguments(
393  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
395  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
396  switch (CallConv) {
397  case CallingConv::C:
398  case CallingConv::Fast:
399  return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
400  default:
401  report_fatal_error("Unsupported calling convention");
402  }
403 }
404 
405 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
406  SmallVectorImpl<SDValue> &InVals) const {
407  SelectionDAG &DAG = CLI.DAG;
408  SDLoc &DL = CLI.DL;
410  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
412  SDValue Chain = CLI.Chain;
413  SDValue Callee = CLI.Callee;
414  bool &IsTailCall = CLI.IsTailCall;
415  CallingConv::ID CallConv = CLI.CallConv;
416  bool IsVarArg = CLI.IsVarArg;
417 
418  // Lanai target does not yet support tail call optimization.
419  IsTailCall = false;
420 
421  switch (CallConv) {
422  case CallingConv::Fast:
423  case CallingConv::C:
424  return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
425  OutVals, Ins, DL, DAG, InVals);
426  default:
427  report_fatal_error("Unsupported calling convention");
428  }
429 }
430 
431 // LowerCCCArguments - transform physical registers into virtual registers and
432 // generate load operations for arguments places on the stack.
433 SDValue LanaiTargetLowering::LowerCCCArguments(
434  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
436  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
438  MachineFrameInfo &MFI = MF.getFrameInfo();
439  MachineRegisterInfo &RegInfo = MF.getRegInfo();
441 
442  // Assign locations to all of the incoming arguments.
444  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
445  *DAG.getContext());
446  if (CallConv == CallingConv::Fast) {
447  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
448  } else {
449  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
450  }
451 
452  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
453  CCValAssign &VA = ArgLocs[i];
454  if (VA.isRegLoc()) {
455  // Arguments passed in registers
456  EVT RegVT = VA.getLocVT();
457  switch (RegVT.getSimpleVT().SimpleTy) {
458  case MVT::i32: {
459  Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
460  RegInfo.addLiveIn(VA.getLocReg(), VReg);
461  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
462 
463  // If this is an 8/16-bit value, it is really passed promoted to 32
464  // bits. Insert an assert[sz]ext to capture this, then truncate to the
465  // right size.
466  if (VA.getLocInfo() == CCValAssign::SExt)
467  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
468  DAG.getValueType(VA.getValVT()));
469  else if (VA.getLocInfo() == CCValAssign::ZExt)
470  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
471  DAG.getValueType(VA.getValVT()));
472 
473  if (VA.getLocInfo() != CCValAssign::Full)
474  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
475 
476  InVals.push_back(ArgValue);
477  break;
478  }
479  default:
480  LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
481  << RegVT.getEVTString() << "\n");
482  llvm_unreachable("unhandled argument type");
483  }
484  } else {
485  // Only arguments passed on the stack should make it here.
486  assert(VA.isMemLoc());
487  // Load the argument to a virtual register
488  unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
489  // Check that the argument fits in stack slot
490  if (ObjSize > 4) {
491  errs() << "LowerFormalArguments Unhandled argument type: "
492  << EVT(VA.getLocVT()).getEVTString() << "\n";
493  }
494  // Create the frame index object for this incoming parameter...
495  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
496 
497  // Create the SelectionDAG nodes corresponding to a load
498  // from this parameter
499  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
500  InVals.push_back(DAG.getLoad(
501  VA.getLocVT(), DL, Chain, FIN,
503  }
504  }
505 
506  // The Lanai ABI for returning structs by value requires that we copy
507  // the sret argument into rv for the return. Save the argument into
508  // a virtual register so that we can access it from the return points.
509  if (MF.getFunction().hasStructRetAttr()) {
510  Register Reg = LanaiMFI->getSRetReturnReg();
511  if (!Reg) {
513  LanaiMFI->setSRetReturnReg(Reg);
514  }
515  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
516  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
517  }
518 
519  if (IsVarArg) {
520  // Record the frame index of the first variable argument
521  // which is a value necessary to VASTART.
522  int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
523  LanaiMFI->setVarArgsFrameIndex(FI);
524  }
525 
526  return Chain;
527 }
528 
530  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
533  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
534 
535  return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
536 }
537 
538 SDValue
539 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
540  bool IsVarArg,
542  const SmallVectorImpl<SDValue> &OutVals,
543  const SDLoc &DL, SelectionDAG &DAG) const {
544  // CCValAssign - represent the assignment of the return value to a location
546 
547  // CCState - Info about the registers and stack slot.
548  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
549  *DAG.getContext());
550 
551  // Analize return values.
552  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
553 
554  SDValue Flag;
555  SmallVector<SDValue, 4> RetOps(1, Chain);
556 
557  // Copy the result values into the output registers.
558  for (unsigned i = 0; i != RVLocs.size(); ++i) {
559  CCValAssign &VA = RVLocs[i];
560  assert(VA.isRegLoc() && "Can only return in registers!");
561 
562  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
563 
564  // Guarantee that all emitted copies are stuck together with flags.
565  Flag = Chain.getValue(1);
566  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
567  }
568 
569  // The Lanai ABI for returning structs by value requires that we copy
570  // the sret argument into rv for the return. We saved the argument into
571  // a virtual register in the entry block, so now we copy the value out
572  // and into rv.
576  Register Reg = LanaiMFI->getSRetReturnReg();
577  assert(Reg &&
578  "SRetReturnReg should have been set in LowerFormalArguments().");
579  SDValue Val =
580  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
581 
582  Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
583  Flag = Chain.getValue(1);
584  RetOps.push_back(
585  DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
586  }
587 
588  RetOps[0] = Chain; // Update chain
589 
590  unsigned Opc = LanaiISD::RET_FLAG;
591  if (Flag.getNode())
592  RetOps.push_back(Flag);
593 
594  // Return Void
595  return DAG.getNode(Opc, DL, MVT::Other,
596  ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
597 }
598 
599 // LowerCCCCallTo - functions arguments are copied from virtual regs to
600 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
601 SDValue LanaiTargetLowering::LowerCCCCallTo(
602  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
603  bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
604  const SmallVectorImpl<SDValue> &OutVals,
606  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
607  // Analyze operands of the call, assigning locations to each operand.
609  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
610  *DAG.getContext());
611  GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
613 
614  NumFixedArgs = 0;
615  if (IsVarArg && G) {
616  const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
617  if (CalleeFn)
618  NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
619  }
620  if (NumFixedArgs)
621  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
622  else {
623  if (CallConv == CallingConv::Fast)
624  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
625  else
626  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
627  }
628 
629  // Get a count of how many bytes are to be pushed on the stack.
630  unsigned NumBytes = CCInfo.getNextStackOffset();
631 
632  // Create local copies for byval args.
633  SmallVector<SDValue, 8> ByValArgs;
634  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
635  ISD::ArgFlagsTy Flags = Outs[I].Flags;
636  if (!Flags.isByVal())
637  continue;
638 
639  SDValue Arg = OutVals[I];
640  unsigned Size = Flags.getByValSize();
642 
643  int FI = MFI.CreateStackObject(Size, Alignment, false);
644  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
645  SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
646 
647  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
648  /*IsVolatile=*/false,
649  /*AlwaysInline=*/false,
650  /*isTailCall=*/false, MachinePointerInfo(),
652  ByValArgs.push_back(FIPtr);
653  }
654 
655  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
656 
658  SmallVector<SDValue, 12> MemOpChains;
660 
661  // Walk the register/memloc assignments, inserting copies/loads.
662  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
663  CCValAssign &VA = ArgLocs[I];
664  SDValue Arg = OutVals[I];
665  ISD::ArgFlagsTy Flags = Outs[I].Flags;
666 
667  // Promote the value if needed.
668  switch (VA.getLocInfo()) {
669  case CCValAssign::Full:
670  break;
671  case CCValAssign::SExt:
672  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
673  break;
674  case CCValAssign::ZExt:
675  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
676  break;
677  case CCValAssign::AExt:
678  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
679  break;
680  default:
681  llvm_unreachable("Unknown loc info!");
682  }
683 
684  // Use local copy if it is a byval arg.
685  if (Flags.isByVal())
686  Arg = ByValArgs[J++];
687 
688  // Arguments that can be passed on register must be kept at RegsToPass
689  // vector
690  if (VA.isRegLoc()) {
691  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
692  } else {
693  assert(VA.isMemLoc());
694 
695  if (StackPtr.getNode() == nullptr)
696  StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
697  getPointerTy(DAG.getDataLayout()));
698 
699  SDValue PtrOff =
700  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
702 
703  MemOpChains.push_back(
704  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
705  }
706  }
707 
708  // Transform all store nodes into one single node because all store nodes are
709  // independent of each other.
710  if (!MemOpChains.empty())
711  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
712  ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
713 
714  SDValue InFlag;
715 
716  // Build a sequence of copy-to-reg nodes chained together with token chain and
717  // flag operands which copy the outgoing args into registers. The InFlag in
718  // necessary since all emitted instructions must be stuck together.
719  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
720  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
721  RegsToPass[I].second, InFlag);
722  InFlag = Chain.getValue(1);
723  }
724 
725  // If the callee is a GlobalAddress node (quite common, every direct call is)
726  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
727  // Likewise ExternalSymbol -> TargetExternalSymbol.
728  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
729  if (G) {
731  G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
732  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
734  E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
735  }
736 
737  // Returns a chain & a flag for retval copy to use.
738  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
740  Ops.push_back(Chain);
741  Ops.push_back(Callee);
742 
743  // Add a register mask operand representing the call-preserved registers.
744  // TODO: Should return-twice functions be handled?
745  const uint32_t *Mask =
746  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
747  assert(Mask && "Missing call preserved mask for calling convention");
748  Ops.push_back(DAG.getRegisterMask(Mask));
749 
750  // Add argument registers to the end of the list so that they are
751  // known live into the call.
752  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
753  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
754  RegsToPass[I].second.getValueType()));
755 
756  if (InFlag.getNode())
757  Ops.push_back(InFlag);
758 
759  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
760  ArrayRef<SDValue>(&Ops[0], Ops.size()));
761  InFlag = Chain.getValue(1);
762 
763  // Create the CALLSEQ_END node.
764  Chain = DAG.getCALLSEQ_END(
765  Chain,
766  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
767  DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
768  DL);
769  InFlag = Chain.getValue(1);
770 
771  // Handle result values, copying them out of physregs into vregs that we
772  // return.
773  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
774  InVals);
775 }
776 
777 // LowerCallResult - Lower the result values of a call into the
778 // appropriate copies out of appropriate physical registers.
779 SDValue LanaiTargetLowering::LowerCallResult(
780  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
782  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
783  // Assign locations to each value returned by this call.
785  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
786  *DAG.getContext());
787 
788  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
789 
790  // Copy all of the result registers out of their specified physreg.
791  for (unsigned I = 0; I != RVLocs.size(); ++I) {
792  Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
793  RVLocs[I].getValVT(), InFlag)
794  .getValue(1);
795  InFlag = Chain.getValue(2);
796  InVals.push_back(Chain.getValue(0));
797  }
798 
799  return Chain;
800 }
801 
802 //===----------------------------------------------------------------------===//
803 // Custom Lowerings
804 //===----------------------------------------------------------------------===//
805 
807  SDValue &RHS, SelectionDAG &DAG) {
808  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
809 
810  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
811  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
812  // and Lanai only supports integer comparisons, so only provide definitions
813  // for them.
814  switch (SetCCOpcode) {
815  case ISD::SETEQ:
816  return LPCC::ICC_EQ;
817  case ISD::SETGT:
818  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
819  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
820  // X > -1 -> X >= 0 -> is_plus(X)
821  RHS = DAG.getConstant(0, DL, RHS.getValueType());
822  return LPCC::ICC_PL;
823  }
824  return LPCC::ICC_GT;
825  case ISD::SETUGT:
826  return LPCC::ICC_UGT;
827  case ISD::SETLT:
828  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
829  if (RHSC->getZExtValue() == 0)
830  // X < 0 -> is_minus(X)
831  return LPCC::ICC_MI;
832  return LPCC::ICC_LT;
833  case ISD::SETULT:
834  return LPCC::ICC_ULT;
835  case ISD::SETLE:
836  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
837  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
838  // X <= -1 -> X < 0 -> is_minus(X)
839  RHS = DAG.getConstant(0, DL, RHS.getValueType());
840  return LPCC::ICC_MI;
841  }
842  return LPCC::ICC_LE;
843  case ISD::SETULE:
844  return LPCC::ICC_ULE;
845  case ISD::SETGE:
846  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
847  if (RHSC->getZExtValue() == 0)
848  // X >= 0 -> is_plus(X)
849  return LPCC::ICC_PL;
850  return LPCC::ICC_GE;
851  case ISD::SETUGE:
852  return LPCC::ICC_UGE;
853  case ISD::SETNE:
854  return LPCC::ICC_NE;
855  case ISD::SETONE:
856  case ISD::SETUNE:
857  case ISD::SETOGE:
858  case ISD::SETOLE:
859  case ISD::SETOLT:
860  case ISD::SETOGT:
861  case ISD::SETOEQ:
862  case ISD::SETUEQ:
863  case ISD::SETO:
864  case ISD::SETUO:
865  llvm_unreachable("Unsupported comparison.");
866  default:
867  llvm_unreachable("Unknown integer condition code!");
868  }
869 }
870 
872  SDValue Chain = Op.getOperand(0);
873  SDValue Cond = Op.getOperand(1);
874  SDValue LHS = Op.getOperand(2);
875  SDValue RHS = Op.getOperand(3);
876  SDValue Dest = Op.getOperand(4);
877  SDLoc DL(Op);
878 
880  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
881  SDValue Flag =
882  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
883 
884  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
885  TargetCC, Flag);
886 }
887 
889  EVT VT = Op->getValueType(0);
890  if (VT != MVT::i32)
891  return SDValue();
892 
893  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
894  if (!C)
895  return SDValue();
896 
897  int64_t MulAmt = C->getSExtValue();
898  int32_t HighestOne = -1;
899  uint32_t NonzeroEntries = 0;
900  int SignedDigit[32] = {0};
901 
902  // Convert to non-adjacent form (NAF) signed-digit representation.
903  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
904  // minimal Hamming weight representation of a number (on average 1/3 of the
905  // digits will be non-zero vs 1/2 for regular binary representation). And as
906  // the non-zero digits will be the only digits contributing to the instruction
907  // count, this is desirable. The next loop converts it to NAF (following the
908  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
909  // choosing the non-zero coefficients such that the resulting quotient is
910  // divisible by 2 which will cause the next coefficient to be zero.
911  int64_t E = std::abs(MulAmt);
912  int S = (MulAmt < 0 ? -1 : 1);
913  int I = 0;
914  while (E > 0) {
915  int ZI = 0;
916  if (E % 2 == 1) {
917  ZI = 2 - (E % 4);
918  if (ZI != 0)
919  ++NonzeroEntries;
920  }
921  SignedDigit[I] = S * ZI;
922  if (SignedDigit[I] == 1)
923  HighestOne = I;
924  E = (E - ZI) / 2;
925  ++I;
926  }
927 
928  // Compute number of instructions required. Due to differences in lowering
929  // between the different processors this count is not exact.
930  // Start by assuming a shift and a add/sub for every non-zero entry (hence
931  // every non-zero entry requires 1 shift and 1 add/sub except for the first
932  // entry).
933  int32_t InstrRequired = 2 * NonzeroEntries - 1;
934  // Correct possible over-adding due to shift by 0 (which is not emitted).
935  if (std::abs(MulAmt) % 2 == 1)
936  --InstrRequired;
937  // Return if the form generated would exceed the instruction threshold.
938  if (InstrRequired > LanaiLowerConstantMulThreshold)
939  return SDValue();
940 
941  SDValue Res;
942  SDLoc DL(Op);
943  SDValue V = Op->getOperand(0);
944 
945  // Initialize the running sum. Set the running sum to the maximal shifted
946  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
947  // term NAF).
948  if (HighestOne == -1)
949  Res = DAG.getConstant(0, DL, MVT::i32);
950  else {
951  Res = DAG.getNode(ISD::SHL, DL, VT, V,
952  DAG.getConstant(HighestOne, DL, MVT::i32));
953  SignedDigit[HighestOne] = 0;
954  }
955 
956  // Assemble multiplication from shift, add, sub using NAF form and running
957  // sum.
958  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
959  ++I) {
960  if (SignedDigit[I] == 0)
961  continue;
962 
963  // Shifted multiplicand (v<<i).
964  SDValue Op =
965  DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
966  if (SignedDigit[I] == 1)
967  Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
968  else if (SignedDigit[I] == -1)
969  Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
970  }
971  return Res;
972 }
973 
975  SDValue LHS = Op.getOperand(0);
976  SDValue RHS = Op.getOperand(1);
977  SDValue Cond = Op.getOperand(2);
978  SDLoc DL(Op);
979 
981  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
982  SDValue Flag =
983  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
984 
985  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
986 }
987 
989  SelectionDAG &DAG) const {
990  SDValue LHS = Op.getOperand(0);
991  SDValue RHS = Op.getOperand(1);
992  SDValue TrueV = Op.getOperand(2);
993  SDValue FalseV = Op.getOperand(3);
994  SDValue Cond = Op.getOperand(4);
995  SDLoc DL(Op);
996 
998  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
999  SDValue Flag =
1000  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
1001 
1002  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1003  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1004  Flag);
1005 }
1006 
1008  MachineFunction &MF = DAG.getMachineFunction();
1010 
1011  SDLoc DL(Op);
1012  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1013  getPointerTy(DAG.getDataLayout()));
1014 
1015  // vastart just stores the address of the VarArgsFrameIndex slot into the
1016  // memory location argument.
1017  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1018  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1019  MachinePointerInfo(SV));
1020 }
1021 
1023  SelectionDAG &DAG) const {
1024  SDValue Chain = Op.getOperand(0);
1025  SDValue Size = Op.getOperand(1);
1026  SDLoc DL(Op);
1027 
1029 
1030  // Get a reference to the stack pointer.
1031  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1032 
1033  // Subtract the dynamic size from the actual stack size to
1034  // obtain the new stack size.
1035  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1036 
1037  // For Lanai, the outgoing memory arguments area should be on top of the
1038  // alloca area on the stack i.e., the outgoing memory arguments should be
1039  // at a lower address than the alloca area. Move the alloca area down the
1040  // stack by adding back the space reserved for outgoing arguments to SP
1041  // here.
1042  //
1043  // We do not know what the size of the outgoing args is at this point.
1044  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1045  // stack pointer. We replace this instruction with on that has the correct,
1046  // known offset in emitPrologue().
1047  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1048 
1049  // The Sub result contains the new stack start address, so it
1050  // must be placed in the stack pointer register.
1051  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1052 
1053  SDValue Ops[2] = {ArgAdjust, CopyChain};
1054  return DAG.getMergeValues(Ops, DL);
1055 }
1056 
1058  SelectionDAG &DAG) const {
1059  MachineFunction &MF = DAG.getMachineFunction();
1060  MachineFrameInfo &MFI = MF.getFrameInfo();
1061  MFI.setReturnAddressIsTaken(true);
1062 
1063  EVT VT = Op.getValueType();
1064  SDLoc DL(Op);
1065  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1066  if (Depth) {
1067  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1068  const unsigned Offset = -4;
1069  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1070  DAG.getIntPtrConstant(Offset, DL));
1071  return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1072  }
1073 
1074  // Return the link register, which contains the return address.
1075  // Mark it an implicit live-in.
1077  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1078 }
1079 
1081  SelectionDAG &DAG) const {
1083  MFI.setFrameAddressIsTaken(true);
1084 
1085  EVT VT = Op.getValueType();
1086  SDLoc DL(Op);
1087  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1088  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1089  while (Depth--) {
1090  const unsigned Offset = -8;
1091  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1092  DAG.getIntPtrConstant(Offset, DL));
1093  FrameAddr =
1094  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1095  }
1096  return FrameAddr;
1097 }
1098 
1099 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1100  switch (Opcode) {
1101  case LanaiISD::ADJDYNALLOC:
1102  return "LanaiISD::ADJDYNALLOC";
1103  case LanaiISD::RET_FLAG:
1104  return "LanaiISD::RET_FLAG";
1105  case LanaiISD::CALL:
1106  return "LanaiISD::CALL";
1107  case LanaiISD::SELECT_CC:
1108  return "LanaiISD::SELECT_CC";
1109  case LanaiISD::SETCC:
1110  return "LanaiISD::SETCC";
1111  case LanaiISD::SUBBF:
1112  return "LanaiISD::SUBBF";
1113  case LanaiISD::SET_FLAG:
1114  return "LanaiISD::SET_FLAG";
1115  case LanaiISD::BR_CC:
1116  return "LanaiISD::BR_CC";
1117  case LanaiISD::Wrapper:
1118  return "LanaiISD::Wrapper";
1119  case LanaiISD::HI:
1120  return "LanaiISD::HI";
1121  case LanaiISD::LO:
1122  return "LanaiISD::LO";
1123  case LanaiISD::SMALL:
1124  return "LanaiISD::SMALL";
1125  default:
1126  return nullptr;
1127  }
1128 }
1129 
1131  SelectionDAG &DAG) const {
1132  SDLoc DL(Op);
1133  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1134  const Constant *C = N->getConstVal();
1135  const LanaiTargetObjectFile *TLOF =
1136  static_cast<const LanaiTargetObjectFile *>(
1138 
1139  // If the code model is small or constant will be placed in the small section,
1140  // then assume address will fit in 21-bits.
1142  TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1144  C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG);
1145  return DAG.getNode(ISD::OR, DL, MVT::i32,
1146  DAG.getRegister(Lanai::R0, MVT::i32),
1148  } else {
1149  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1150  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1151 
1152  SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1153  N->getOffset(), OpFlagHi);
1154  SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1155  N->getOffset(), OpFlagLo);
1156  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1157  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1158  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1159  return Result;
1160  }
1161 }
1162 
1164  SelectionDAG &DAG) const {
1165  SDLoc DL(Op);
1166  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1167  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1168 
1169  const LanaiTargetObjectFile *TLOF =
1170  static_cast<const LanaiTargetObjectFile *>(
1172 
1173  // If the code model is small or global variable will be placed in the small
1174  // section, then assume address will fit in 21-bits.
1175  const GlobalObject *GO = GV->getAliaseeObject();
1176  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1178  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1179  return DAG.getNode(ISD::OR, DL, MVT::i32,
1180  DAG.getRegister(Lanai::R0, MVT::i32),
1182  } else {
1183  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1184  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1185 
1186  // Create the TargetGlobalAddress node, folding in the constant offset.
1188  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1190  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1191  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1192  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1193  return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1194  }
1195 }
1196 
1198  SelectionDAG &DAG) const {
1199  SDLoc DL(Op);
1200  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1201 
1202  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1203  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1204 
1205  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1206  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1207  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1208  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1209  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1210  return Result;
1211 }
1212 
1214  SelectionDAG &DAG) const {
1215  SDLoc DL(Op);
1216  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1217 
1218  // If the code model is small assume address will fit in 21-bits.
1221  JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1222  return DAG.getNode(ISD::OR, DL, MVT::i32,
1223  DAG.getRegister(Lanai::R0, MVT::i32),
1225  } else {
1226  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1227  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1228 
1229  SDValue Hi = DAG.getTargetJumpTable(
1230  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1231  SDValue Lo = DAG.getTargetJumpTable(
1232  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1233  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1234  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1235  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1236  return Result;
1237  }
1238 }
1239 
1241  SelectionDAG &DAG) const {
1242  EVT VT = Op.getValueType();
1243  unsigned VTBits = VT.getSizeInBits();
1244  SDLoc dl(Op);
1245  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1246  SDValue ShOpLo = Op.getOperand(0);
1247  SDValue ShOpHi = Op.getOperand(1);
1248  SDValue ShAmt = Op.getOperand(2);
1249 
1250  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1251  // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1252  // HiBitsForHi = ShOpHi << ShAmt
1253  // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1254  // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1255  // return (Hi << 32) | Lo;
1256 
1257  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1258  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1259  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1260 
1261  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1262  // wanted 0, so CSEL it directly.
1263  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1264  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1265  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1266 
1267  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1268  DAG.getConstant(VTBits, dl, MVT::i32));
1269  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1270  SDValue HiForNormalShift =
1271  DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1272 
1273  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1274 
1275  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1276  SDValue Hi =
1277  DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1278 
1279  // Lanai shifts of larger than register sizes are wrapped rather than
1280  // clamped, so we can't just emit "lo << b" if b is too big.
1281  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1282  SDValue Lo = DAG.getSelect(
1283  dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1284 
1285  SDValue Ops[2] = {Lo, Hi};
1286  return DAG.getMergeValues(Ops, dl);
1287 }
1288 
1290  SelectionDAG &DAG) const {
1291  MVT VT = Op.getSimpleValueType();
1292  unsigned VTBits = VT.getSizeInBits();
1293  SDLoc dl(Op);
1294  SDValue ShOpLo = Op.getOperand(0);
1295  SDValue ShOpHi = Op.getOperand(1);
1296  SDValue ShAmt = Op.getOperand(2);
1297 
1298  // Performs the following for a >> b:
1299  // unsigned r_high = a_high >> b;
1300  // r_high = (32 - b <= 0) ? 0 : r_high;
1301  //
1302  // unsigned r_low = a_low >> b;
1303  // r_low = (32 - b <= 0) ? r_high : r_low;
1304  // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1305  // return (unsigned long long)r_high << 32 | r_low;
1306  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1307  // mask the shift amount.
1308 
1309  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1310  SDValue NegatedPlus32 = DAG.getNode(
1311  ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1312  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1313 
1314  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1315  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1316 
1317  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1318  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1319  SDValue CarryBits =
1320  DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1321  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1322  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1323  DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1324 
1325  SDValue Ops[2] = {Lo, Hi};
1326  return DAG.getMergeValues(Ops, dl);
1327 }
1328 
1329 // Helper function that checks if N is a null or all ones constant.
1330 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1331  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1332 }
1333 
1334 // Return true if N is conditionally 0 or all ones.
1335 // Detects these expressions where cc is an i1 value:
1336 //
1337 // (select cc 0, y) [AllOnes=0]
1338 // (select cc y, 0) [AllOnes=0]
1339 // (zext cc) [AllOnes=0]
1340 // (sext cc) [AllOnes=0/1]
1341 // (select cc -1, y) [AllOnes=1]
1342 // (select cc y, -1) [AllOnes=1]
1343 //
1344 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1345 // all ones operand (AllOnes true).
1346 // * Invert is set when N is the all zero/ones constant when CC is false.
1347 // * OtherOp is set to the alternative value of N.
1348 //
1349 // For example, for (select cc X, Y) and AllOnes = 0 if:
1350 // * X = 0, Invert = False and OtherOp = Y
1351 // * Y = 0, Invert = True and OtherOp = X
1352 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1353  bool &Invert, SDValue &OtherOp,
1354  SelectionDAG &DAG) {
1355  switch (N->getOpcode()) {
1356  default:
1357  return false;
1358  case ISD::SELECT: {
1359  CC = N->getOperand(0);
1360  SDValue N1 = N->getOperand(1);
1361  SDValue N2 = N->getOperand(2);
1362  if (isZeroOrAllOnes(N1, AllOnes)) {
1363  Invert = false;
1364  OtherOp = N2;
1365  return true;
1366  }
1367  if (isZeroOrAllOnes(N2, AllOnes)) {
1368  Invert = true;
1369  OtherOp = N1;
1370  return true;
1371  }
1372  return false;
1373  }
1374  case ISD::ZERO_EXTEND: {
1375  // (zext cc) can never be the all ones value.
1376  if (AllOnes)
1377  return false;
1378  CC = N->getOperand(0);
1379  if (CC.getValueType() != MVT::i1)
1380  return false;
1381  SDLoc dl(N);
1382  EVT VT = N->getValueType(0);
1383  OtherOp = DAG.getConstant(1, dl, VT);
1384  Invert = true;
1385  return true;
1386  }
1387  case ISD::SIGN_EXTEND: {
1388  CC = N->getOperand(0);
1389  if (CC.getValueType() != MVT::i1)
1390  return false;
1391  SDLoc dl(N);
1392  EVT VT = N->getValueType(0);
1393  Invert = !AllOnes;
1394  if (AllOnes)
1395  // When looking for an AllOnes constant, N is an sext, and the 'other'
1396  // value is 0.
1397  OtherOp = DAG.getConstant(0, dl, VT);
1398  else
1399  OtherOp = DAG.getAllOnesConstant(dl, VT);
1400  return true;
1401  }
1402  }
1403 }
1404 
1405 // Combine a constant select operand into its use:
1406 //
1407 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1408 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1409 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1410 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1411 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1412 //
1413 // The transform is rejected if the select doesn't have a constant operand that
1414 // is null, or all ones when AllOnes is set.
1415 //
1416 // Also recognize sext/zext from i1:
1417 //
1418 // (add (zext cc), x) -> (select cc (add x, 1), x)
1419 // (add (sext cc), x) -> (select cc (add x, -1), x)
1420 //
1421 // These transformations eventually create predicated instructions.
1424  bool AllOnes) {
1425  SelectionDAG &DAG = DCI.DAG;
1426  EVT VT = N->getValueType(0);
1427  SDValue NonConstantVal;
1428  SDValue CCOp;
1429  bool SwapSelectOps;
1430  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1431  NonConstantVal, DAG))
1432  return SDValue();
1433 
1434  // Slct is now know to be the desired identity constant when CC is true.
1435  SDValue TrueVal = OtherOp;
1436  SDValue FalseVal =
1437  DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1438  // Unless SwapSelectOps says CC should be false.
1439  if (SwapSelectOps)
1441 
1442  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1443 }
1444 
1445 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1446 static SDValue
1448  bool AllOnes) {
1449  SDValue N0 = N->getOperand(0);
1450  SDValue N1 = N->getOperand(1);
1451  if (N0.getNode()->hasOneUse())
1452  if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1453  return Result;
1454  if (N1.getNode()->hasOneUse())
1455  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1456  return Result;
1457  return SDValue();
1458 }
1459 
1460 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1463  SDValue N0 = N->getOperand(0);
1464  SDValue N1 = N->getOperand(1);
1465 
1466  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1467  if (N1.getNode()->hasOneUse())
1468  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1469  return Result;
1470 
1471  return SDValue();
1472 }
1473 
1475  DAGCombinerInfo &DCI) const {
1476  switch (N->getOpcode()) {
1477  default:
1478  break;
1479  case ISD::ADD:
1480  case ISD::OR:
1481  case ISD::XOR:
1482  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1483  case ISD::AND:
1484  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1485  case ISD::SUB:
1486  return PerformSUBCombine(N, DCI);
1487  }
1488 
1489  return SDValue();
1490 }
1491 
1493  const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1494  const SelectionDAG &DAG, unsigned Depth) const {
1495  unsigned BitWidth = Known.getBitWidth();
1496  switch (Op.getOpcode()) {
1497  default:
1498  break;
1499  case LanaiISD::SETCC:
1500  Known = KnownBits(BitWidth);
1501  Known.Zero.setBits(1, BitWidth);
1502  break;
1503  case LanaiISD::SELECT_CC:
1504  KnownBits Known2;
1505  Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1506  Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1507  Known = KnownBits::commonBits(Known, Known2);
1508  break;
1509  }
1510 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::LPCC::ICC_UGT
@ ICC_UGT
Definition: LanaiCondCode.h:14
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
i
i
Definition: README.txt:29
llvm::LanaiISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: LanaiISelLowering.h:27
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1424
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3335
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
ValueTypes.h
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::LanaiTargetLowering::LowerBR_CC
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:871
llvm::LanaiTargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1197
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1788
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:943
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1435
PerformSUBCombine
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
Definition: LanaiISelLowering.cpp:1461
llvm::ISD::SETO
@ SETO
Definition: ISDOpcodes.h:1420
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
combineSelectAndUse
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
Definition: LanaiISelLowering.cpp:1422
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1432
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1436
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:5391
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:377
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:750
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::APInt::setBits
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
Definition: APInt.h:1317
llvm::Function
Definition: Function.h:60
llvm::LanaiTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: LanaiISelLowering.cpp:171
StringRef.h
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::LanaiRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: LanaiRegisterInfo.cpp:264
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::LPCC::ICC_LE
@ ICC_LE
Definition: LanaiCondCode.h:30
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1798
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:251
llvm::KnownBits::Zero
APInt Zero
Definition: KnownBits.h:24
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3333
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1679
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1431
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9121
LanaiBaseInfo.h
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4441
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3812
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:270
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::LanaiMachineFunctionInfo
Definition: LanaiMachineFunctionInfo.h:24
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
llvm::LanaiISD::Wrapper
@ Wrapper
Definition: LanaiISelLowering.h:54
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1426
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7817
llvm::LanaiTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: LanaiISelLowering.cpp:1474
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::LanaiII::MO_ABS_LO
@ MO_ABS_LO
Definition: LanaiBaseInfo.h:36
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2447
llvm::LanaiTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: LanaiISelLowering.cpp:280
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:62
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3097
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::LanaiTargetLowering::LowerSHL_PARTS
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1240
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
Lanai.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1391
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::LPCC::ICC_UGE
@ ICC_UGE
Definition: LanaiCondCode.h:20
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1414
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1422
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:462
llvm::LanaiISD::SET_FLAG
@ SET_FLAG
Definition: LanaiISelLowering.h:44
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1001
MachineRegisterInfo.h
KnownBits.h
llvm::LanaiII::MO_NO_FLAG
@ MO_NO_FLAG
Definition: LanaiBaseInfo.h:31
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
MachineValueType.h
llvm::LPCC::ICC_EQ
@ ICC_EQ
Definition: LanaiCondCode.h:22
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2439
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1461
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7767
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:4014
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
GlobalValue.h
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1125
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
TargetMachine.h
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
SelectionDAGNodes.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::SDNode::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: SelectionDAGNodes.h:706
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::LanaiTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: LanaiISelLowering.cpp:1099
llvm::LanaiISD::CALL
@ CALL
Definition: LanaiISelLowering.h:34
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1433
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::LanaiTargetLowering::LowerMUL
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:888
llvm::LanaiMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int Index)
Definition: LanaiMachineFunctionInfo.h:52
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::GlobalObject
Definition: GlobalObject.h:27
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
llvm::LPCC::CondCode
CondCode
Definition: LanaiCondCode.h:10
llvm::LPCC::ICC_GE
@ ICC_GE
Definition: LanaiCondCode.h:27
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3806
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:329
LanaiCondCode.h
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
isZeroOrAllOnes
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
Definition: LanaiISelLowering.cpp:1330
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2284
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::LPCC::ICC_LT
@ ICC_LT
Definition: LanaiCondCode.h:28
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3348
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1417
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::LPCC::ICC_GT
@ ICC_GT
Definition: LanaiCondCode.h:29
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1418
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1423
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:698
llvm::LanaiISD::LO
@ LO
Definition: LanaiISelLowering.h:58
CC_Lanai32_VarArg
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Definition: LanaiISelLowering.cpp:365
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:4037
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1427
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2301
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3350
llvm::SPIRV::Decoration::Alignment
@ Alignment
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::LanaiTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: LanaiISelLowering.cpp:232
llvm::LPCC::ICC_ULT
@ ICC_ULT
Definition: LanaiCondCode.h:18
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
TargetCallingConv.h
llvm::LanaiTargetLowering::LowerVASTART
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1007
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::LPCC::ICC_MI
@ ICC_MI
Definition: LanaiCondCode.h:26
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
RuntimeLibcalls.h
LanaiLowerConstantMulThreshold
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))
combineSelectAndUseCommutative
static SDValue combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
Definition: LanaiISelLowering.cpp:1447
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:4010
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1572
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LanaiTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: LanaiISelLowering.cpp:211
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::LanaiISD::RET_FLAG
@ RET_FLAG
Definition: LanaiISelLowering.h:30
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:776
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:4031
llvm::codeview::FrameCookieKind::Copy
@ Copy
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2250
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8851
llvm::LanaiTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: LanaiISelLowering.cpp:251
llvm::TargetLoweringBase::setPrefFunctionAlignment
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
Definition: TargetLowering.h:2453
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4446
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:4035
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:645
ArrayRef.h
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:100
llvm::LanaiISD::SELECT_CC
@ SELECT_CC
Definition: LanaiISelLowering.h:38
llvm::SelectionDAG::getAllOnesConstant
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
Definition: SelectionDAG.h:637
llvm::LanaiTargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1163
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1391
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1415
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4009
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LPCC::ICC_PL
@ ICC_PL
Definition: LanaiCondCode.h:25
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:883
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1425
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1411
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::TargetMachine::getObjFileLowering
virtual TargetLoweringObjectFile * getObjFileLowering() const
Definition: TargetMachine.h:136
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4442
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::LPCC::ICC_NE
@ ICC_NE
Definition: LanaiCondCode.h:21
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:955
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:677
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
isConditionalZeroOrAllOnes
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
Definition: LanaiISelLowering.cpp:1352
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:4039
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:4034
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:714
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::SelectionDAG::getSelect
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
Definition: SelectionDAG.h:1108
llvm::LanaiISD::SETCC
@ SETCC
Definition: LanaiISelLowering.h:41
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:5026
llvm::LanaiTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: LanaiISelLowering.cpp:1492
llvm::LanaiSubtarget
Definition: LanaiSubtarget.h:29
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::SelectionDAG::getBlockAddress
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:2114
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::LanaiMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex() const
Definition: LanaiMachineFunctionInfo.h:51
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3385
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LanaiTargetObjectFile::isConstantInSmallSection
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
Definition: LanaiTargetObjectFile.cpp:114
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5103
llvm::LPCC::ICC_ULE
@ ICC_ULE
Definition: LanaiCondCode.h:16
llvm::CCState::CheckReturn
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
Definition: CallingConvLower.cpp:96
llvm::GlobalValue::getAliaseeObject
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:352
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1391
llvm::LanaiTargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1130
LanaiTargetObjectFile.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:708
llvm::LanaiTargetLowering::LowerSRL_PARTS
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1289
NumFixedArgs
static unsigned NumFixedArgs
Definition: LanaiISelLowering.cpp:364
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
IntCondCCodeToICC
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
Definition: LanaiISelLowering.cpp:806
llvm::EVT::getEVTString
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:152
CallingConv.h
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:4025
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1434
llvm::LanaiISD::SMALL
@ SMALL
Definition: LanaiISelLowering.h:61
llvm::LanaiSubtarget::getRegisterInfo
const LanaiRegisterInfo * getRegisterInfo() const override
Definition: LanaiSubtarget.h:54
llvm::isAllOnesConstant
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
Definition: SelectionDAG.cpp:10531
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
LanaiISelLowering.h
llvm::SelectionDAG::computeKnownBits
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
Definition: SelectionDAG.cpp:2898
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2318
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
CallingConvLower.h
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:10521
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
MachineFrameInfo.h
llvm::LanaiMachineFunctionInfo::setSRetReturnReg
void setSRetReturnReg(Register Reg)
Definition: LanaiMachineFunctionInfo.h:49
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:531
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4429
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:452
llvm::LanaiTargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1057
Casting.h
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1829
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::ISD::SETUO
@ SETUO
Definition: ISDOpcodes.h:1421
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:175
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
StringSwitch.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4431
llvm::LanaiTargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:974
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:942
LanaiMachineFunctionInfo.h
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
llvm::LanaiISD::SUBBF
@ SUBBF
Definition: LanaiISelLowering.h:47
llvm::LanaiTargetObjectFile
Definition: LanaiTargetObjectFile.h:15
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
CodeGen.h
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2218
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1416
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::LanaiTargetLowering::LanaiTargetLowering
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
Definition: LanaiISelLowering.cpp:73
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::LanaiISD::BR_CC
@ BR_CC
Definition: LanaiISelLowering.h:50
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1277
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:2017
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::LanaiTargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1213
llvm::KnownBits::commonBits
static KnownBits commonBits(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits common to LHS and RHS.
Definition: KnownBits.h:308
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2076
llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1022
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:891
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:4038
RegName
#define RegName(no)
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:652
DerivedTypes.h
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1419
llvm::LanaiTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: LanaiISelLowering.cpp:529
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:4032
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.h:225
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1077
llvm::KnownBits::getBitWidth
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
llvm::LanaiRegisterInfo::getRARegister
unsigned getRARegister() const
Definition: LanaiRegisterInfo.cpp:254
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::LanaiISD::HI
@ HI
Definition: LanaiISelLowering.h:57
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:371
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
raw_ostream.h
llvm::LanaiTargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:1080
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7111
MachineFunction.h
LanaiSubtarget.h
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:62
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1053
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3383
llvm::codegen::getCodeModel
CodeModel::Model getCodeModel()
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
Debug.h
llvm::LanaiTargetLowering::LowerSELECT_CC
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Definition: LanaiISelLowering.cpp:988
llvm::LanaiII::MO_ABS_HI
@ MO_ABS_HI
Definition: LanaiBaseInfo.h:35
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:354
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::SelectionDAG::getSetCC
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:1079
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::LanaiMachineFunctionInfo::getSRetReturnReg
Register getSRetReturnReg() const
Definition: LanaiMachineFunctionInfo.h:48
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:7531
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::LLT
Definition: LowLevelTypeImpl.h:39