LLVM  9.0.0svn
LanaiISelLowering.cpp
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1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LanaiTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LanaiISelLowering.h"
14 #include "Lanai.h"
15 #include "LanaiCondCode.h"
17 #include "LanaiSubtarget.h"
18 #include "LanaiTargetObjectFile.h"
20 #include "llvm/ADT/APInt.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalValue.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/KnownBits.h"
49 #include <cassert>
50 #include <cmath>
51 #include <cstdint>
52 #include <cstdlib>
53 #include <utility>
54 
55 #define DEBUG_TYPE "lanai-lower"
56 
57 using namespace llvm;
58 
59 // Limit on number of instructions the lowered multiplication may have before a
60 // call to the library function should be generated instead. The threshold is
61 // currently set to 14 as this was the smallest threshold that resulted in all
62 // constant multiplications being lowered. A threshold of 5 covered all cases
63 // except for one multiplication which required 14. mulsi3 requires 16
64 // instructions (including the prologue and epilogue but excluding instructions
65 // at call site). Until we can inline mulsi3, generating at most 14 instructions
66 // will be faster than invoking mulsi3.
68  "lanai-constant-mul-threshold", cl::Hidden,
69  cl::desc("Maximum number of instruction to generate when lowering constant "
70  "multiplication instead of calling library function [default=14]"),
71  cl::init(14));
72 
74  const LanaiSubtarget &STI)
75  : TargetLowering(TM) {
76  // Set up the register classes.
77  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78 
79  // Compute derived properties from the register classes
80  TRI = STI.getRegisterInfo();
82 
84 
91 
96 
100 
105 
112 
118 
124 
129 
133 
134  // Extended load operations for i1 types must be promoted
135  for (MVT VT : MVT::integer_valuetypes()) {
139  }
140 
146 
147  // Function alignments (log2)
150 
151  setJumpIsExpensive(true);
152 
153  // TODO: Setting the minimum jump table entries needed before a
154  // switch is transformed to a jump table to 100 to avoid creating jump tables
155  // as this was causing bad performance compared to a large group of if
156  // statements. Re-evaluate this on new benchmarks.
158 
159  // Use fast calling convention for library functions.
160  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
161  setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
162  }
163 
164  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
166  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
168  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
170 
171  // Booleans always contain 0 or 1.
173 }
174 
176  SelectionDAG &DAG) const {
177  switch (Op.getOpcode()) {
178  case ISD::MUL:
179  return LowerMUL(Op, DAG);
180  case ISD::BR_CC:
181  return LowerBR_CC(Op, DAG);
182  case ISD::ConstantPool:
183  return LowerConstantPool(Op, DAG);
184  case ISD::GlobalAddress:
185  return LowerGlobalAddress(Op, DAG);
186  case ISD::BlockAddress:
187  return LowerBlockAddress(Op, DAG);
188  case ISD::JumpTable:
189  return LowerJumpTable(Op, DAG);
190  case ISD::SELECT_CC:
191  return LowerSELECT_CC(Op, DAG);
192  case ISD::SETCC:
193  return LowerSETCC(Op, DAG);
194  case ISD::SHL_PARTS:
195  return LowerSHL_PARTS(Op, DAG);
196  case ISD::SRL_PARTS:
197  return LowerSRL_PARTS(Op, DAG);
198  case ISD::VASTART:
199  return LowerVASTART(Op, DAG);
201  return LowerDYNAMIC_STACKALLOC(Op, DAG);
202  case ISD::RETURNADDR:
203  return LowerRETURNADDR(Op, DAG);
204  case ISD::FRAMEADDR:
205  return LowerFRAMEADDR(Op, DAG);
206  default:
207  llvm_unreachable("unimplemented operand");
208  }
209 }
210 
211 //===----------------------------------------------------------------------===//
212 // Lanai Inline Assembly Support
213 //===----------------------------------------------------------------------===//
214 
215 unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
216  SelectionDAG & /*DAG*/) const {
217  // Only unallocatable registers should be matched here.
218  unsigned Reg = StringSwitch<unsigned>(RegName)
219  .Case("pc", Lanai::PC)
220  .Case("sp", Lanai::SP)
221  .Case("fp", Lanai::FP)
222  .Case("rr1", Lanai::RR1)
223  .Case("r10", Lanai::R10)
224  .Case("rr2", Lanai::RR2)
225  .Case("r11", Lanai::R11)
226  .Case("rca", Lanai::RCA)
227  .Default(0);
228 
229  if (Reg)
230  return Reg;
231  report_fatal_error("Invalid register name global variable");
232 }
233 
234 std::pair<unsigned, const TargetRegisterClass *>
236  StringRef Constraint,
237  MVT VT) const {
238  if (Constraint.size() == 1)
239  // GCC Constraint Letters
240  switch (Constraint[0]) {
241  case 'r': // GENERAL_REGS
242  return std::make_pair(0U, &Lanai::GPRRegClass);
243  default:
244  break;
245  }
246 
247  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
248 }
249 
250 // Examine constraint type and operand type and determine a weight value.
251 // This object must already have been set up with the operand type
252 // and the current alternative constraint selected.
255  AsmOperandInfo &Info, const char *Constraint) const {
256  ConstraintWeight Weight = CW_Invalid;
257  Value *CallOperandVal = Info.CallOperandVal;
258  // If we don't have a value, we can't do a match,
259  // but allow it at the lowest weight.
260  if (CallOperandVal == nullptr)
261  return CW_Default;
262  // Look at the constraint type.
263  switch (*Constraint) {
264  case 'I': // signed 16 bit immediate
265  case 'J': // integer zero
266  case 'K': // unsigned 16 bit immediate
267  case 'L': // immediate in the range 0 to 31
268  case 'M': // signed 32 bit immediate where lower 16 bits are 0
269  case 'N': // signed 26 bit immediate
270  case 'O': // integer zero
271  if (isa<ConstantInt>(CallOperandVal))
272  Weight = CW_Constant;
273  break;
274  default:
275  Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
276  break;
277  }
278  return Weight;
279 }
280 
281 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
282 // vector. If it is invalid, don't add anything to Ops.
284  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
285  SelectionDAG &DAG) const {
286  SDValue Result(nullptr, 0);
287 
288  // Only support length 1 constraints for now.
289  if (Constraint.length() > 1)
290  return;
291 
292  char ConstraintLetter = Constraint[0];
293  switch (ConstraintLetter) {
294  case 'I': // Signed 16 bit constant
295  // If this fails, the parent routine will give an error
296  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
297  if (isInt<16>(C->getSExtValue())) {
298  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
299  Op.getValueType());
300  break;
301  }
302  }
303  return;
304  case 'J': // integer zero
305  case 'O':
306  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
307  if (C->getZExtValue() == 0) {
308  Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
309  break;
310  }
311  }
312  return;
313  case 'K': // unsigned 16 bit immediate
314  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
315  if (isUInt<16>(C->getZExtValue())) {
316  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
317  Op.getValueType());
318  break;
319  }
320  }
321  return;
322  case 'L': // immediate in the range 0 to 31
323  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
324  if (C->getZExtValue() <= 31) {
325  Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
326  Op.getValueType());
327  break;
328  }
329  }
330  return;
331  case 'M': // signed 32 bit immediate where lower 16 bits are 0
332  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
333  int64_t Val = C->getSExtValue();
334  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
335  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
336  break;
337  }
338  }
339  return;
340  case 'N': // signed 26 bit immediate
341  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
342  int64_t Val = C->getSExtValue();
343  if ((Val >= -33554432) && (Val <= 33554431)) {
344  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
345  break;
346  }
347  }
348  return;
349  default:
350  break; // This will fall through to the generic implementation
351  }
352 
353  if (Result.getNode()) {
354  Ops.push_back(Result);
355  return;
356  }
357 
358  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
359 }
360 
361 //===----------------------------------------------------------------------===//
362 // Calling Convention Implementation
363 //===----------------------------------------------------------------------===//
364 
365 #include "LanaiGenCallingConv.inc"
366 
367 static unsigned NumFixedArgs;
368 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
369  CCValAssign::LocInfo LocInfo,
370  ISD::ArgFlagsTy ArgFlags, CCState &State) {
371  // Handle fixed arguments with default CC.
372  // Note: Both the default and fast CC handle VarArg the same and hence the
373  // calling convention of the function is not considered here.
374  if (ValNo < NumFixedArgs) {
375  return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
376  }
377 
378  // Promote i8/i16 args to i32
379  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
380  LocVT = MVT::i32;
381  if (ArgFlags.isSExt())
382  LocInfo = CCValAssign::SExt;
383  else if (ArgFlags.isZExt())
384  LocInfo = CCValAssign::ZExt;
385  else
386  LocInfo = CCValAssign::AExt;
387  }
388 
389  // VarArgs get passed on stack
390  unsigned Offset = State.AllocateStack(4, 4);
391  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
392  return false;
393 }
394 
395 SDValue LanaiTargetLowering::LowerFormalArguments(
396  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
397  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
398  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
399  switch (CallConv) {
400  case CallingConv::C:
401  case CallingConv::Fast:
402  return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
403  default:
404  report_fatal_error("Unsupported calling convention");
405  }
406 }
407 
408 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
409  SmallVectorImpl<SDValue> &InVals) const {
410  SelectionDAG &DAG = CLI.DAG;
411  SDLoc &DL = CLI.DL;
413  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
415  SDValue Chain = CLI.Chain;
416  SDValue Callee = CLI.Callee;
417  bool &IsTailCall = CLI.IsTailCall;
418  CallingConv::ID CallConv = CLI.CallConv;
419  bool IsVarArg = CLI.IsVarArg;
420 
421  // Lanai target does not yet support tail call optimization.
422  IsTailCall = false;
423 
424  switch (CallConv) {
425  case CallingConv::Fast:
426  case CallingConv::C:
427  return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
428  OutVals, Ins, DL, DAG, InVals);
429  default:
430  report_fatal_error("Unsupported calling convention");
431  }
432 }
433 
434 // LowerCCCArguments - transform physical registers into virtual registers and
435 // generate load operations for arguments places on the stack.
436 SDValue LanaiTargetLowering::LowerCCCArguments(
437  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
438  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
439  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
441  MachineFrameInfo &MFI = MF.getFrameInfo();
442  MachineRegisterInfo &RegInfo = MF.getRegInfo();
444 
445  // Assign locations to all of the incoming arguments.
447  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
448  *DAG.getContext());
449  if (CallConv == CallingConv::Fast) {
450  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
451  } else {
452  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
453  }
454 
455  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
456  CCValAssign &VA = ArgLocs[i];
457  if (VA.isRegLoc()) {
458  // Arguments passed in registers
459  EVT RegVT = VA.getLocVT();
460  switch (RegVT.getSimpleVT().SimpleTy) {
461  case MVT::i32: {
462  unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
463  RegInfo.addLiveIn(VA.getLocReg(), VReg);
464  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
465 
466  // If this is an 8/16-bit value, it is really passed promoted to 32
467  // bits. Insert an assert[sz]ext to capture this, then truncate to the
468  // right size.
469  if (VA.getLocInfo() == CCValAssign::SExt)
470  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
471  DAG.getValueType(VA.getValVT()));
472  else if (VA.getLocInfo() == CCValAssign::ZExt)
473  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
474  DAG.getValueType(VA.getValVT()));
475 
476  if (VA.getLocInfo() != CCValAssign::Full)
477  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
478 
479  InVals.push_back(ArgValue);
480  break;
481  }
482  default:
483  LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
484  << RegVT.getEVTString() << "\n");
485  llvm_unreachable("unhandled argument type");
486  }
487  } else {
488  // Sanity check
489  assert(VA.isMemLoc());
490  // Load the argument to a virtual register
491  unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
492  // Check that the argument fits in stack slot
493  if (ObjSize > 4) {
494  errs() << "LowerFormalArguments Unhandled argument type: "
495  << EVT(VA.getLocVT()).getEVTString() << "\n";
496  }
497  // Create the frame index object for this incoming parameter...
498  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
499 
500  // Create the SelectionDAG nodes corresponding to a load
501  // from this parameter
502  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
503  InVals.push_back(DAG.getLoad(
504  VA.getLocVT(), DL, Chain, FIN,
506  }
507  }
508 
509  // The Lanai ABI for returning structs by value requires that we copy
510  // the sret argument into rv for the return. Save the argument into
511  // a virtual register so that we can access it from the return points.
512  if (MF.getFunction().hasStructRetAttr()) {
513  unsigned Reg = LanaiMFI->getSRetReturnReg();
514  if (!Reg) {
516  LanaiMFI->setSRetReturnReg(Reg);
517  }
518  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
519  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
520  }
521 
522  if (IsVarArg) {
523  // Record the frame index of the first variable argument
524  // which is a value necessary to VASTART.
525  int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
526  LanaiMFI->setVarArgsFrameIndex(FI);
527  }
528 
529  return Chain;
530 }
531 
532 SDValue
533 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
534  bool IsVarArg,
536  const SmallVectorImpl<SDValue> &OutVals,
537  const SDLoc &DL, SelectionDAG &DAG) const {
538  // CCValAssign - represent the assignment of the return value to a location
540 
541  // CCState - Info about the registers and stack slot.
542  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
543  *DAG.getContext());
544 
545  // Analize return values.
546  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
547 
548  SDValue Flag;
549  SmallVector<SDValue, 4> RetOps(1, Chain);
550 
551  // Copy the result values into the output registers.
552  for (unsigned i = 0; i != RVLocs.size(); ++i) {
553  CCValAssign &VA = RVLocs[i];
554  assert(VA.isRegLoc() && "Can only return in registers!");
555 
556  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
557 
558  // Guarantee that all emitted copies are stuck together with flags.
559  Flag = Chain.getValue(1);
560  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
561  }
562 
563  // The Lanai ABI for returning structs by value requires that we copy
564  // the sret argument into rv for the return. We saved the argument into
565  // a virtual register in the entry block, so now we copy the value out
566  // and into rv.
570  unsigned Reg = LanaiMFI->getSRetReturnReg();
571  assert(Reg &&
572  "SRetReturnReg should have been set in LowerFormalArguments().");
573  SDValue Val =
574  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
575 
576  Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
577  Flag = Chain.getValue(1);
578  RetOps.push_back(
579  DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
580  }
581 
582  RetOps[0] = Chain; // Update chain
583 
584  unsigned Opc = LanaiISD::RET_FLAG;
585  if (Flag.getNode())
586  RetOps.push_back(Flag);
587 
588  // Return Void
589  return DAG.getNode(Opc, DL, MVT::Other,
590  ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
591 }
592 
593 // LowerCCCCallTo - functions arguments are copied from virtual regs to
594 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
595 SDValue LanaiTargetLowering::LowerCCCCallTo(
596  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
597  bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
598  const SmallVectorImpl<SDValue> &OutVals,
599  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
600  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
601  // Analyze operands of the call, assigning locations to each operand.
603  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
604  *DAG.getContext());
607 
608  NumFixedArgs = 0;
609  if (IsVarArg && G) {
610  const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
611  if (CalleeFn)
612  NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
613  }
614  if (NumFixedArgs)
615  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
616  else {
617  if (CallConv == CallingConv::Fast)
618  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
619  else
620  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
621  }
622 
623  // Get a count of how many bytes are to be pushed on the stack.
624  unsigned NumBytes = CCInfo.getNextStackOffset();
625 
626  // Create local copies for byval args.
627  SmallVector<SDValue, 8> ByValArgs;
628  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
629  ISD::ArgFlagsTy Flags = Outs[I].Flags;
630  if (!Flags.isByVal())
631  continue;
632 
633  SDValue Arg = OutVals[I];
634  unsigned Size = Flags.getByValSize();
635  unsigned Align = Flags.getByValAlign();
636 
637  int FI = MFI.CreateStackObject(Size, Align, false);
638  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
639  SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
640 
641  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
642  /*IsVolatile=*/false,
643  /*AlwaysInline=*/false,
644  /*isTailCall=*/false, MachinePointerInfo(),
646  ByValArgs.push_back(FIPtr);
647  }
648 
649  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
650 
652  SmallVector<SDValue, 12> MemOpChains;
653  SDValue StackPtr;
654 
655  // Walk the register/memloc assignments, inserting copies/loads.
656  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
657  CCValAssign &VA = ArgLocs[I];
658  SDValue Arg = OutVals[I];
659  ISD::ArgFlagsTy Flags = Outs[I].Flags;
660 
661  // Promote the value if needed.
662  switch (VA.getLocInfo()) {
663  case CCValAssign::Full:
664  break;
665  case CCValAssign::SExt:
666  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
667  break;
668  case CCValAssign::ZExt:
669  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
670  break;
671  case CCValAssign::AExt:
672  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
673  break;
674  default:
675  llvm_unreachable("Unknown loc info!");
676  }
677 
678  // Use local copy if it is a byval arg.
679  if (Flags.isByVal())
680  Arg = ByValArgs[J++];
681 
682  // Arguments that can be passed on register must be kept at RegsToPass
683  // vector
684  if (VA.isRegLoc()) {
685  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
686  } else {
687  assert(VA.isMemLoc());
688 
689  if (StackPtr.getNode() == nullptr)
690  StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
691  getPointerTy(DAG.getDataLayout()));
692 
693  SDValue PtrOff =
694  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
695  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
696 
697  MemOpChains.push_back(
698  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
699  }
700  }
701 
702  // Transform all store nodes into one single node because all store nodes are
703  // independent of each other.
704  if (!MemOpChains.empty())
705  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
706  ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
707 
708  SDValue InFlag;
709 
710  // Build a sequence of copy-to-reg nodes chained together with token chain and
711  // flag operands which copy the outgoing args into registers. The InFlag in
712  // necessary since all emitted instructions must be stuck together.
713  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
714  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
715  RegsToPass[I].second, InFlag);
716  InFlag = Chain.getValue(1);
717  }
718 
719  // If the callee is a GlobalAddress node (quite common, every direct call is)
720  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
721  // Likewise ExternalSymbol -> TargetExternalSymbol.
722  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
723  if (G) {
724  Callee = DAG.getTargetGlobalAddress(
725  G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
726  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
727  Callee = DAG.getTargetExternalSymbol(
728  E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
729  }
730 
731  // Returns a chain & a flag for retval copy to use.
732  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
734  Ops.push_back(Chain);
735  Ops.push_back(Callee);
736 
737  // Add a register mask operand representing the call-preserved registers.
738  // TODO: Should return-twice functions be handled?
739  const uint32_t *Mask =
740  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
741  assert(Mask && "Missing call preserved mask for calling convention");
742  Ops.push_back(DAG.getRegisterMask(Mask));
743 
744  // Add argument registers to the end of the list so that they are
745  // known live into the call.
746  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
747  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
748  RegsToPass[I].second.getValueType()));
749 
750  if (InFlag.getNode())
751  Ops.push_back(InFlag);
752 
753  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
754  ArrayRef<SDValue>(&Ops[0], Ops.size()));
755  InFlag = Chain.getValue(1);
756 
757  // Create the CALLSEQ_END node.
758  Chain = DAG.getCALLSEQ_END(
759  Chain,
760  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
761  DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
762  DL);
763  InFlag = Chain.getValue(1);
764 
765  // Handle result values, copying them out of physregs into vregs that we
766  // return.
767  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
768  InVals);
769 }
770 
771 // LowerCallResult - Lower the result values of a call into the
772 // appropriate copies out of appropriate physical registers.
773 SDValue LanaiTargetLowering::LowerCallResult(
774  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
775  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
776  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
777  // Assign locations to each value returned by this call.
779  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
780  *DAG.getContext());
781 
782  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
783 
784  // Copy all of the result registers out of their specified physreg.
785  for (unsigned I = 0; I != RVLocs.size(); ++I) {
786  Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
787  RVLocs[I].getValVT(), InFlag)
788  .getValue(1);
789  InFlag = Chain.getValue(2);
790  InVals.push_back(Chain.getValue(0));
791  }
792 
793  return Chain;
794 }
795 
796 //===----------------------------------------------------------------------===//
797 // Custom Lowerings
798 //===----------------------------------------------------------------------===//
799 
801  SDValue &RHS, SelectionDAG &DAG) {
802  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
803 
804  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
805  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
806  // and Lanai only supports integer comparisons, so only provide definitions
807  // for them.
808  switch (SetCCOpcode) {
809  case ISD::SETEQ:
810  return LPCC::ICC_EQ;
811  case ISD::SETGT:
812  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
813  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
814  // X > -1 -> X >= 0 -> is_plus(X)
815  RHS = DAG.getConstant(0, DL, RHS.getValueType());
816  return LPCC::ICC_PL;
817  }
818  return LPCC::ICC_GT;
819  case ISD::SETUGT:
820  return LPCC::ICC_UGT;
821  case ISD::SETLT:
822  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
823  if (RHSC->getZExtValue() == 0)
824  // X < 0 -> is_minus(X)
825  return LPCC::ICC_MI;
826  return LPCC::ICC_LT;
827  case ISD::SETULT:
828  return LPCC::ICC_ULT;
829  case ISD::SETLE:
830  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
831  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
832  // X <= -1 -> X < 0 -> is_minus(X)
833  RHS = DAG.getConstant(0, DL, RHS.getValueType());
834  return LPCC::ICC_MI;
835  }
836  return LPCC::ICC_LE;
837  case ISD::SETULE:
838  return LPCC::ICC_ULE;
839  case ISD::SETGE:
840  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
841  if (RHSC->getZExtValue() == 0)
842  // X >= 0 -> is_plus(X)
843  return LPCC::ICC_PL;
844  return LPCC::ICC_GE;
845  case ISD::SETUGE:
846  return LPCC::ICC_UGE;
847  case ISD::SETNE:
848  return LPCC::ICC_NE;
849  case ISD::SETONE:
850  case ISD::SETUNE:
851  case ISD::SETOGE:
852  case ISD::SETOLE:
853  case ISD::SETOLT:
854  case ISD::SETOGT:
855  case ISD::SETOEQ:
856  case ISD::SETUEQ:
857  case ISD::SETO:
858  case ISD::SETUO:
859  llvm_unreachable("Unsupported comparison.");
860  default:
861  llvm_unreachable("Unknown integer condition code!");
862  }
863 }
864 
866  SDValue Chain = Op.getOperand(0);
867  SDValue Cond = Op.getOperand(1);
868  SDValue LHS = Op.getOperand(2);
869  SDValue RHS = Op.getOperand(3);
870  SDValue Dest = Op.getOperand(4);
871  SDLoc DL(Op);
872 
873  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
874  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
875  SDValue Flag =
876  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
877 
878  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
879  TargetCC, Flag);
880 }
881 
883  EVT VT = Op->getValueType(0);
884  if (VT != MVT::i32)
885  return SDValue();
886 
888  if (!C)
889  return SDValue();
890 
891  int64_t MulAmt = C->getSExtValue();
892  int32_t HighestOne = -1;
893  uint32_t NonzeroEntries = 0;
894  int SignedDigit[32] = {0};
895 
896  // Convert to non-adjacent form (NAF) signed-digit representation.
897  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
898  // minimal Hamming weight representation of a number (on average 1/3 of the
899  // digits will be non-zero vs 1/2 for regular binary representation). And as
900  // the non-zero digits will be the only digits contributing to the instruction
901  // count, this is desirable. The next loop converts it to NAF (following the
902  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
903  // choosing the non-zero coefficients such that the resulting quotient is
904  // divisible by 2 which will cause the next coefficient to be zero.
905  int64_t E = std::abs(MulAmt);
906  int S = (MulAmt < 0 ? -1 : 1);
907  int I = 0;
908  while (E > 0) {
909  int ZI = 0;
910  if (E % 2 == 1) {
911  ZI = 2 - (E % 4);
912  if (ZI != 0)
913  ++NonzeroEntries;
914  }
915  SignedDigit[I] = S * ZI;
916  if (SignedDigit[I] == 1)
917  HighestOne = I;
918  E = (E - ZI) / 2;
919  ++I;
920  }
921 
922  // Compute number of instructions required. Due to differences in lowering
923  // between the different processors this count is not exact.
924  // Start by assuming a shift and a add/sub for every non-zero entry (hence
925  // every non-zero entry requires 1 shift and 1 add/sub except for the first
926  // entry).
927  int32_t InstrRequired = 2 * NonzeroEntries - 1;
928  // Correct possible over-adding due to shift by 0 (which is not emitted).
929  if (std::abs(MulAmt) % 2 == 1)
930  --InstrRequired;
931  // Return if the form generated would exceed the instruction threshold.
932  if (InstrRequired > LanaiLowerConstantMulThreshold)
933  return SDValue();
934 
935  SDValue Res;
936  SDLoc DL(Op);
937  SDValue V = Op->getOperand(0);
938 
939  // Initialize the running sum. Set the running sum to the maximal shifted
940  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
941  // term NAF).
942  if (HighestOne == -1)
943  Res = DAG.getConstant(0, DL, MVT::i32);
944  else {
945  Res = DAG.getNode(ISD::SHL, DL, VT, V,
946  DAG.getConstant(HighestOne, DL, MVT::i32));
947  SignedDigit[HighestOne] = 0;
948  }
949 
950  // Assemble multiplication from shift, add, sub using NAF form and running
951  // sum.
952  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
953  ++I) {
954  if (SignedDigit[I] == 0)
955  continue;
956 
957  // Shifted multiplicand (v<<i).
958  SDValue Op =
959  DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
960  if (SignedDigit[I] == 1)
961  Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
962  else if (SignedDigit[I] == -1)
963  Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
964  }
965  return Res;
966 }
967 
969  SDValue LHS = Op.getOperand(0);
970  SDValue RHS = Op.getOperand(1);
971  SDValue Cond = Op.getOperand(2);
972  SDLoc DL(Op);
973 
974  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
975  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
976  SDValue Flag =
977  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
978 
979  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
980 }
981 
983  SelectionDAG &DAG) const {
984  SDValue LHS = Op.getOperand(0);
985  SDValue RHS = Op.getOperand(1);
986  SDValue TrueV = Op.getOperand(2);
987  SDValue FalseV = Op.getOperand(3);
988  SDValue Cond = Op.getOperand(4);
989  SDLoc DL(Op);
990 
991  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
992  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
993  SDValue Flag =
994  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
995 
996  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
997  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
998  Flag);
999 }
1000 
1002  MachineFunction &MF = DAG.getMachineFunction();
1004 
1005  SDLoc DL(Op);
1006  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1007  getPointerTy(DAG.getDataLayout()));
1008 
1009  // vastart just stores the address of the VarArgsFrameIndex slot into the
1010  // memory location argument.
1011  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1012  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1013  MachinePointerInfo(SV));
1014 }
1015 
1017  SelectionDAG &DAG) const {
1018  SDValue Chain = Op.getOperand(0);
1019  SDValue Size = Op.getOperand(1);
1020  SDLoc DL(Op);
1021 
1022  unsigned SPReg = getStackPointerRegisterToSaveRestore();
1023 
1024  // Get a reference to the stack pointer.
1025  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1026 
1027  // Subtract the dynamic size from the actual stack size to
1028  // obtain the new stack size.
1029  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1030 
1031  // For Lanai, the outgoing memory arguments area should be on top of the
1032  // alloca area on the stack i.e., the outgoing memory arguments should be
1033  // at a lower address than the alloca area. Move the alloca area down the
1034  // stack by adding back the space reserved for outgoing arguments to SP
1035  // here.
1036  //
1037  // We do not know what the size of the outgoing args is at this point.
1038  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1039  // stack pointer. We replace this instruction with on that has the correct,
1040  // known offset in emitPrologue().
1041  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1042 
1043  // The Sub result contains the new stack start address, so it
1044  // must be placed in the stack pointer register.
1045  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1046 
1047  SDValue Ops[2] = {ArgAdjust, CopyChain};
1048  return DAG.getMergeValues(Ops, DL);
1049 }
1050 
1052  SelectionDAG &DAG) const {
1053  MachineFunction &MF = DAG.getMachineFunction();
1054  MachineFrameInfo &MFI = MF.getFrameInfo();
1055  MFI.setReturnAddressIsTaken(true);
1056 
1057  EVT VT = Op.getValueType();
1058  SDLoc DL(Op);
1059  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1060  if (Depth) {
1061  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1062  const unsigned Offset = -4;
1063  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1064  DAG.getIntPtrConstant(Offset, DL));
1065  return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1066  }
1067 
1068  // Return the link register, which contains the return address.
1069  // Mark it an implicit live-in.
1070  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1071  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1072 }
1073 
1075  SelectionDAG &DAG) const {
1077  MFI.setFrameAddressIsTaken(true);
1078 
1079  EVT VT = Op.getValueType();
1080  SDLoc DL(Op);
1081  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1082  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1083  while (Depth--) {
1084  const unsigned Offset = -8;
1085  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1086  DAG.getIntPtrConstant(Offset, DL));
1087  FrameAddr =
1088  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1089  }
1090  return FrameAddr;
1091 }
1092 
1093 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1094  switch (Opcode) {
1095  case LanaiISD::ADJDYNALLOC:
1096  return "LanaiISD::ADJDYNALLOC";
1097  case LanaiISD::RET_FLAG:
1098  return "LanaiISD::RET_FLAG";
1099  case LanaiISD::CALL:
1100  return "LanaiISD::CALL";
1101  case LanaiISD::SELECT_CC:
1102  return "LanaiISD::SELECT_CC";
1103  case LanaiISD::SETCC:
1104  return "LanaiISD::SETCC";
1105  case LanaiISD::SUBBF:
1106  return "LanaiISD::SUBBF";
1107  case LanaiISD::SET_FLAG:
1108  return "LanaiISD::SET_FLAG";
1109  case LanaiISD::BR_CC:
1110  return "LanaiISD::BR_CC";
1111  case LanaiISD::Wrapper:
1112  return "LanaiISD::Wrapper";
1113  case LanaiISD::HI:
1114  return "LanaiISD::HI";
1115  case LanaiISD::LO:
1116  return "LanaiISD::LO";
1117  case LanaiISD::SMALL:
1118  return "LanaiISD::SMALL";
1119  default:
1120  return nullptr;
1121  }
1122 }
1123 
1125  SelectionDAG &DAG) const {
1126  SDLoc DL(Op);
1127  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1128  const Constant *C = N->getConstVal();
1129  const LanaiTargetObjectFile *TLOF =
1130  static_cast<const LanaiTargetObjectFile *>(
1132 
1133  // If the code model is small or constant will be placed in the small section,
1134  // then assume address will fit in 21-bits.
1136  TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1139  return DAG.getNode(ISD::OR, DL, MVT::i32,
1140  DAG.getRegister(Lanai::R0, MVT::i32),
1141  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1142  } else {
1143  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1144  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1145 
1147  N->getOffset(), OpFlagHi);
1149  N->getOffset(), OpFlagLo);
1150  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1151  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1152  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1153  return Result;
1154  }
1155 }
1156 
1158  SelectionDAG &DAG) const {
1159  SDLoc DL(Op);
1160  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1161  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1162 
1163  const LanaiTargetObjectFile *TLOF =
1164  static_cast<const LanaiTargetObjectFile *>(
1166 
1167  // If the code model is small or global variable will be placed in the small
1168  // section, then assume address will fit in 21-bits.
1169  const GlobalObject *GO = GV->getBaseObject();
1170  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1172  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1173  return DAG.getNode(ISD::OR, DL, MVT::i32,
1174  DAG.getRegister(Lanai::R0, MVT::i32),
1175  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1176  } else {
1177  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1178  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1179 
1180  // Create the TargetGlobalAddress node, folding in the constant offset.
1182  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1184  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1185  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1186  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1187  return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1188  }
1189 }
1190 
1192  SelectionDAG &DAG) const {
1193  SDLoc DL(Op);
1194  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1195 
1196  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1197  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1198 
1199  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1200  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1201  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1202  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1203  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1204  return Result;
1205 }
1206 
1208  SelectionDAG &DAG) const {
1209  SDLoc DL(Op);
1210  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1211 
1212  // If the code model is small assume address will fit in 21-bits.
1216  return DAG.getNode(ISD::OR, DL, MVT::i32,
1217  DAG.getRegister(Lanai::R0, MVT::i32),
1218  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1219  } else {
1220  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1221  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1222 
1224  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1226  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1227  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1228  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1229  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1230  return Result;
1231  }
1232 }
1233 
1235  SelectionDAG &DAG) const {
1236  EVT VT = Op.getValueType();
1237  unsigned VTBits = VT.getSizeInBits();
1238  SDLoc dl(Op);
1239  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1240  SDValue ShOpLo = Op.getOperand(0);
1241  SDValue ShOpHi = Op.getOperand(1);
1242  SDValue ShAmt = Op.getOperand(2);
1243 
1244  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1245  // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1246  // HiBitsForHi = ShOpHi << ShAmt
1247  // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1248  // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1249  // return (Hi << 32) | Lo;
1250 
1251  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1252  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1253  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1254 
1255  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1256  // wanted 0, so CSEL it directly.
1257  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1258  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1259  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1260 
1261  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1262  DAG.getConstant(VTBits, dl, MVT::i32));
1263  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1264  SDValue HiForNormalShift =
1265  DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1266 
1267  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1268 
1269  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1270  SDValue Hi =
1271  DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1272 
1273  // Lanai shifts of larger than register sizes are wrapped rather than
1274  // clamped, so we can't just emit "lo << b" if b is too big.
1275  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1276  SDValue Lo = DAG.getSelect(
1277  dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1278 
1279  SDValue Ops[2] = {Lo, Hi};
1280  return DAG.getMergeValues(Ops, dl);
1281 }
1282 
1284  SelectionDAG &DAG) const {
1285  MVT VT = Op.getSimpleValueType();
1286  unsigned VTBits = VT.getSizeInBits();
1287  SDLoc dl(Op);
1288  SDValue ShOpLo = Op.getOperand(0);
1289  SDValue ShOpHi = Op.getOperand(1);
1290  SDValue ShAmt = Op.getOperand(2);
1291 
1292  // Performs the following for a >> b:
1293  // unsigned r_high = a_high >> b;
1294  // r_high = (32 - b <= 0) ? 0 : r_high;
1295  //
1296  // unsigned r_low = a_low >> b;
1297  // r_low = (32 - b <= 0) ? r_high : r_low;
1298  // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1299  // return (unsigned long long)r_high << 32 | r_low;
1300  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1301  // mask the shift amount.
1302 
1303  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1304  SDValue NegatedPlus32 = DAG.getNode(
1305  ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1306  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1307 
1308  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1309  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1310 
1311  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1312  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1313  SDValue CarryBits =
1314  DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1315  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1316  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1317  DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1318 
1319  SDValue Ops[2] = {Lo, Hi};
1320  return DAG.getMergeValues(Ops, dl);
1321 }
1322 
1323 // Helper function that checks if N is a null or all ones constant.
1324 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1325  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1326 }
1327 
1328 // Return true if N is conditionally 0 or all ones.
1329 // Detects these expressions where cc is an i1 value:
1330 //
1331 // (select cc 0, y) [AllOnes=0]
1332 // (select cc y, 0) [AllOnes=0]
1333 // (zext cc) [AllOnes=0]
1334 // (sext cc) [AllOnes=0/1]
1335 // (select cc -1, y) [AllOnes=1]
1336 // (select cc y, -1) [AllOnes=1]
1337 //
1338 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1339 // all ones operand (AllOnes true).
1340 // * Invert is set when N is the all zero/ones constant when CC is false.
1341 // * OtherOp is set to the alternative value of N.
1342 //
1343 // For example, for (select cc X, Y) and AllOnes = 0 if:
1344 // * X = 0, Invert = False and OtherOp = Y
1345 // * Y = 0, Invert = True and OtherOp = X
1346 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1347  bool &Invert, SDValue &OtherOp,
1348  SelectionDAG &DAG) {
1349  switch (N->getOpcode()) {
1350  default:
1351  return false;
1352  case ISD::SELECT: {
1353  CC = N->getOperand(0);
1354  SDValue N1 = N->getOperand(1);
1355  SDValue N2 = N->getOperand(2);
1356  if (isZeroOrAllOnes(N1, AllOnes)) {
1357  Invert = false;
1358  OtherOp = N2;
1359  return true;
1360  }
1361  if (isZeroOrAllOnes(N2, AllOnes)) {
1362  Invert = true;
1363  OtherOp = N1;
1364  return true;
1365  }
1366  return false;
1367  }
1368  case ISD::ZERO_EXTEND: {
1369  // (zext cc) can never be the all ones value.
1370  if (AllOnes)
1371  return false;
1372  CC = N->getOperand(0);
1373  if (CC.getValueType() != MVT::i1)
1374  return false;
1375  SDLoc dl(N);
1376  EVT VT = N->getValueType(0);
1377  OtherOp = DAG.getConstant(1, dl, VT);
1378  Invert = true;
1379  return true;
1380  }
1381  case ISD::SIGN_EXTEND: {
1382  CC = N->getOperand(0);
1383  if (CC.getValueType() != MVT::i1)
1384  return false;
1385  SDLoc dl(N);
1386  EVT VT = N->getValueType(0);
1387  Invert = !AllOnes;
1388  if (AllOnes)
1389  // When looking for an AllOnes constant, N is an sext, and the 'other'
1390  // value is 0.
1391  OtherOp = DAG.getConstant(0, dl, VT);
1392  else
1393  OtherOp =
1395  return true;
1396  }
1397  }
1398 }
1399 
1400 // Combine a constant select operand into its use:
1401 //
1402 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1403 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1404 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1405 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1406 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1407 //
1408 // The transform is rejected if the select doesn't have a constant operand that
1409 // is null, or all ones when AllOnes is set.
1410 //
1411 // Also recognize sext/zext from i1:
1412 //
1413 // (add (zext cc), x) -> (select cc (add x, 1), x)
1414 // (add (sext cc), x) -> (select cc (add x, -1), x)
1415 //
1416 // These transformations eventually create predicated instructions.
1419  bool AllOnes) {
1420  SelectionDAG &DAG = DCI.DAG;
1421  EVT VT = N->getValueType(0);
1422  SDValue NonConstantVal;
1423  SDValue CCOp;
1424  bool SwapSelectOps;
1425  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1426  NonConstantVal, DAG))
1427  return SDValue();
1428 
1429  // Slct is now know to be the desired identity constant when CC is true.
1430  SDValue TrueVal = OtherOp;
1431  SDValue FalseVal =
1432  DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1433  // Unless SwapSelectOps says CC should be false.
1434  if (SwapSelectOps)
1435  std::swap(TrueVal, FalseVal);
1436 
1437  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1438 }
1439 
1440 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1441 static SDValue
1443  bool AllOnes) {
1444  SDValue N0 = N->getOperand(0);
1445  SDValue N1 = N->getOperand(1);
1446  if (N0.getNode()->hasOneUse())
1447  if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1448  return Result;
1449  if (N1.getNode()->hasOneUse())
1450  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1451  return Result;
1452  return SDValue();
1453 }
1454 
1455 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1458  SDValue N0 = N->getOperand(0);
1459  SDValue N1 = N->getOperand(1);
1460 
1461  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1462  if (N1.getNode()->hasOneUse())
1463  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1464  return Result;
1465 
1466  return SDValue();
1467 }
1468 
1470  DAGCombinerInfo &DCI) const {
1471  switch (N->getOpcode()) {
1472  default:
1473  break;
1474  case ISD::ADD:
1475  case ISD::OR:
1476  case ISD::XOR:
1477  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1478  case ISD::AND:
1479  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1480  case ISD::SUB:
1481  return PerformSUBCombine(N, DCI);
1482  }
1483 
1484  return SDValue();
1485 }
1486 
1488  const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1489  const SelectionDAG &DAG, unsigned Depth) const {
1490  unsigned BitWidth = Known.getBitWidth();
1491  switch (Op.getOpcode()) {
1492  default:
1493  break;
1494  case LanaiISD::SETCC:
1495  Known = KnownBits(BitWidth);
1496  Known.Zero.setBits(1, BitWidth);
1497  break;
1498  case LanaiISD::SELECT_CC:
1499  KnownBits Known2;
1500  Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1501  Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1502  Known.Zero &= Known2.Zero;
1503  Known.One &= Known2.One;
1504  break;
1505  }
1506 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
Definition: APInt.h:1417
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:952
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:851
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
This class represents lattice values for constants.
Definition: AllocatorList.h:23
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:965
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:39
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:459
bool isMemLoc() const
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:581
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:480
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
bool hasOneUse() const
Return true if there is exactly one use of this node.
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))
Shift and rotation operations.
Definition: ISDOpcodes.h:434
static SDValue combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void addLoc(const CCValAssign &V)
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
SimpleValueType SimpleTy
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:462
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
int64_t getSExtValue() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:581
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned getByValSize() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Machine Value Type.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:759
const SDValue & getOperand(unsigned Num) const
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:839
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:750
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static unsigned NumFixedArgs
Extended Value Type.
Definition: ValueTypes.h:33
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:644
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:638
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
virtual TargetLoweringObjectFile * getObjFileLowering() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:672
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:437
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:684
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:163
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
CodeModel::Model getCodeModel() const
Returns the code model.
amdgpu Simplify well known AMD library false FunctionCallee Callee
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:666
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:755
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:710
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:510
unsigned getRARegister() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
uint32_t Size
Definition: Profile.cpp:46
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
unsigned getOpcode() const
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const GlobalObject * getBaseObject() const
Definition: Globals.cpp:260
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
LLVM Value Representation.
Definition: Value.h:72
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue getRegister(unsigned Reg, EVT VT)
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:467
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
unsigned getNumOperands() const
Conversion operators.
Definition: ISDOpcodes.h:489
const SDValue & getOperand(unsigned i) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const LanaiRegisterInfo * getRegisterInfo() const override
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVMContext * getContext() const
Definition: SelectionDAG.h:409
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:627
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:404
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:651