LLVM  14.0.0git
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ARMISelLowering.cpp File Reference
#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <string>
#include <tuple>
#include <utility>
#include <vector>

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "arm-isel"
 
#define MAKE_CASE(V)
 

Typedefs

using RCPair = std::pair< unsigned, const TargetRegisterClass * >
 

Enumerations

enum  ShuffleOpCodes {
  OP_COPY = 0, OP_VREV, OP_VDUP0, OP_VDUP1,
  OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2,
  OP_VEXT3, OP_VUZPL, OP_VUZPR, OP_VZIPL,
  OP_VZIPR, OP_VTRNL, OP_VTRNR
}
 
enum  HABaseType {
  HA_UNKNOWN = 0, HA_FLOAT, HA_DOUBLE, HA_VECT64,
  HA_VECT128
}
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
 STATISTIC (NumMovwMovt, "Number of GAs materialized with movw + movt")
 
 STATISTIC (NumLoopByVals, "Number of loops generated for byval arguments")
 
 STATISTIC (NumConstpoolPromoted, "Number of constants with their storage promoted into constant pools")
 
static bool isSRL16 (const SDValue &Op)
 
static bool isSRA16 (const SDValue &Op)
 
static bool isSHL16 (const SDValue &Op)
 
static bool isS16 (const SDValue &Op, SelectionDAG &DAG)
 
static ARMCC::CondCodes IntCCToARMCC (ISD::CondCode CC)
 IntCCToARMCC - Convert a DAG integer condition code to an ARM CC. More...
 
static void FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
 FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. More...
 
static bool canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls)
 
static bool MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
 MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack. More...
 
static SDValue LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
 
static SDValue LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG)
 
static bool allUsersAreInFunction (const Value *V, const Function *F)
 Return true if all users of V are within function F, looking through ConstantExprs. More...
 
static SDValue promoteToConstantPool (const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl)
 
static SDValue LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerVASTART (SDValue Op, SelectionDAG &DAG)
 
static bool isFloatingPointZero (SDValue Op)
 isFloatingPointZero - Return true if this is +0.0. More...
 
static SDValue ConvertBooleanCarryToCarryFlag (SDValue BoolCarry, SelectionDAG &DAG)
 
static SDValue ConvertCarryFlagToBooleanCarry (SDValue Flags, EVT VT, SelectionDAG &DAG)
 
static SDValue LowerADDSUBSAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static void checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
 
static bool isGTorGE (ISD::CondCode CC)
 
static bool isLTorLE (ISD::CondCode CC)
 
static bool isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)
 
static SDValue LowerSaturatingConditional (SDValue Op, SelectionDAG &DAG)
 
static bool isLowerSaturatingConditional (const SDValue &Op, SDValue &V, SDValue &SatK)
 
static bool canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
 canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence. More...
 
static SDValue bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)
 
static void expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
 
static SDValue LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
 
static void ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static SDValue CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG)
 BC is a bitcast that is about to be turned into a VMOVDRR. More...
 
static SDValue getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
 getZeroVector - Returns a vector of specified type with all zero elements. More...
 
static SDValue LowerCTTZ (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerCTPOP (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static bool getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
 Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More...
 
static bool isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
 isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More...
 
static bool isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
 isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More...
 
static SDValue LowerShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue Expand64BitShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerVSETCC (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerSETCCCARRY (SDValue Op, SelectionDAG &DAG)
 
static SDValue isVMOVModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type)
 isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV). More...
 
static bool isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
 
static bool isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
 
static bool isVTBLMask (ArrayRef< int > M, EVT VT)
 
static unsigned SelectPairHalf (unsigned Elements, ArrayRef< int > Mask, unsigned Index)
 
static bool isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static unsigned isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF)
 Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't. More...
 
static bool isReverseMask (ArrayRef< int > M, EVT VT)
 
static bool isVMOVNMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
 
static bool isVMOVNTruncMask (ArrayRef< int > M, EVT ToVT, bool rev)
 
static SDValue LowerBuildVectorOfFPTrunc (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerBuildVectorOfFPExt (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl)
 
static SDValue LowerBUILD_VECTOR_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerBUILD_VECTORToVIDUP (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static bool isLegalMVEShuffleOp (unsigned PFEntry)
 
static SDValue GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
 GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...
 
static SDValue LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
 
static SDValue LowerReverse_VECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG)
 
static EVT getVectorTyFromPredicateVector (EVT VT)
 
static SDValue PromoteMVEPredVector (SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG)
 
static SDValue LowerVECTOR_SHUFFLE_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerVECTOR_SHUFFLEUsingMovs (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
 
static SDValue LowerVECTOR_SHUFFLEUsingOneOff (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
 
static SDValue LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerINSERT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerEXTRACT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerCONCAT_VECTORS_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerTruncatei1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerTruncate (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerVectorExtend (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static bool isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
 isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size. More...
 
static bool isSignExtended (SDNode *N, SelectionDAG &DAG)
 isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements. More...
 
static bool isZeroExtended (SDNode *N, SelectionDAG &DAG)
 isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements. More...
 
static EVT getExtensionTo64Bits (const EVT &OrigVT)
 
static SDValue AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
 AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits. More...
 
static SDValue SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
 SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension. More...
 
static SDValue SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
 SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value. More...
 
static bool isAddSubSExt (SDNode *N, SelectionDAG &DAG)
 
static bool isAddSubZExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue LowerMUL (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG)
 
static SDValue LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG)
 
static SDValue LowerSDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerUDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerADDSUBCARRY (SDValue Op, SelectionDAG &DAG)
 
static SDValue WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain)
 
static SDValue LowerPredicateLoad (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerPredicateStore (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerSTORE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static bool isZeroVector (SDValue N)
 
static SDValue LowerMLOAD (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVecReduce (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerVecReduceF (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)
 
static void ReplaceREADCYCLECOUNTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue createGPRPairNode (SelectionDAG &DAG, SDValue V)
 
static void ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static void ReplaceLongIntrinsic (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static MachineBasicBlockOtherSucc (MachineBasicBlock *MBB, MachineBasicBlock *Succ)
 
static unsigned getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
 Return the load opcode for a given load size. More...
 
static unsigned getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
 Return the store opcode for a given store size. More...
 
static void emitPostLd (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
 Emit a post-increment load operation with given size. More...
 
static void emitPostSt (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
 Emit a post-increment store operation with given size. More...
 
static bool checkAndUpdateCPSRKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
 
static Register genTPEntry (MachineBasicBlock *TpEntry, MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpExit, Register OpSizeReg, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI)
 Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop. More...
 
static void genTPLoopBody (MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpEntry, MachineBasicBlock *TpExit, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI, Register OpSrcReg, Register OpDestReg, Register ElementCountReg, Register TotalIterationsReg, bool IsMemcpy)
 Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd. More...
 
static void attachMEMCPYScratchRegs (const ARMSubtarget *Subtarget, MachineInstr &MI, const SDNode *Node)
 Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM. More...
 
static bool isZeroOrAllOnes (SDValue N, bool AllOnes)
 
static bool isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
 
static bool IsVUZPShuffleNode (SDNode *N)
 
static SDValue AddCombineToVPADD (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineVUZPToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineBUILD_VECTORToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue findMUL_LOHI (SDValue V)
 
static SDValue AddCombineTo64BitSMLAL16 (SDNode *AddcNode, SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineTo64bitMLAL (SDNode *AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineTo64bitUMAAL (SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformUMLALCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue PerformAddcSubcCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformAddeSubeCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformVQDMULHCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformVSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformABSCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformADDECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL. More...
 
static SDValue PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1. More...
 
static SDValue TryDistrubutionADDVecReduce (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformADDVecReduce (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue PerformSHLSimplify (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
 
static SDValue PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. More...
 
static SDValue PerformSubCSINCCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. More...
 
static SDValue PerformVMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding. More...
 
static SDValue PerformMVEVMULLCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue CombineANDShift (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformORCombineToSMULWBT (SDNode *OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformORCombineToBFI (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static bool isValidMVECond (unsigned CC, bool IsFloat)
 
static ARMCC::CondCodes getVCMPCondCode (SDValue N)
 
static bool CanInvertMVEVCMP (SDValue N)
 
static SDValue PerformORCombine_i1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue PerformORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformORCombine - Target-specific dag combine xforms for ISD::OR. More...
 
static SDValue PerformXORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask)
 
static bool BitsProperlyConcatenate (const APInt &A, const APInt &B)
 
static SDValue FindBFIToCombineWith (SDNode *N)
 
static SDValue PerformBFICombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformVMOVRRDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD. More...
 
static SDValue PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
 PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR. More...
 
static SDValue PerformVMOVhrCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVMOVrhCombine (SDNode *N, SelectionDAG &DAG)
 
static bool hasNormalLoadOperand (SDNode *N)
 hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads. More...
 
static SDValue PerformBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR. More...
 
static SDValue PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 Target-specific dag combine xforms for ARMISD::BUILD_VECTOR. More...
 
static SDValue PerformPREDICATE_CASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVECTOR_REG_CASTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue PerformVCMPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT. More...
 
static SDValue PerformExtractEltToVMOVRRD (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformExtractEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
 
static SDValue PerformSignExtendInregCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue FlattenVectorShuffle (ShuffleVectorSDNode *N, SelectionDAG &DAG)
 
static SDValue PerformInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformShuffleVMOVNCombine (ShuffleVectorSDNode *N, SelectionDAG &DAG)
 
static SDValue PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
 PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE. More...
 
static SDValue CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates. More...
 
static SDValue PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformMVEVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static bool CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs. More...
 
static SDValue PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE. More...
 
static SDValue PerformVDUPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP. More...
 
static SDValue PerformLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformTruncatingStoreCombine (StoreSDNode *St, SelectionDAG &DAG)
 
static SDValue PerformSplittingToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
 
static SDValue PerformSplittingMVETruncToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
 
static SDValue PerformExtractFpToIntStores (StoreSDNode *St, SelectionDAG &DAG)
 
static SDValue PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE. More...
 
static SDValue PerformVCVTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2. More...
 
static SDValue PerformVDIVCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2. More...
 
static SDValue PerformVECREDUCE_ADDCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue PerformVMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVQMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformLongShiftCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformShiftCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
 PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them. More...
 
static SDValue PerformSplittingToWideningLoad (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. More...
 
static SDValue PerformFPExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue PerformMinMaxCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates. More...
 
static const APIntisPowerOf2Constant (SDValue V)
 
static SDValue SearchLoopIntrinsic (SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate)
 
static SDValue PerformHWLoopCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
 
static SDValue PerformBITCASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
 
static SDValue PerformSplittingMVEEXTToWideningLoad (SDNode *N, SelectionDAG &DAG)
 
static bool areExtractExts (Value *Ext1, Value *Ext2)
 Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements. More...
 
static bool isLegalT1AddressImmediate (int64_t V, EVT VT)
 
static bool isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
 
static bool isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
 isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type. More...
 
static bool getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 
static bool getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 
static bool getMVEIndexedAddressParts (SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 
static RTLIB::Libcall getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT)
 
static TargetLowering::ArgListTy getDivRemArgList (const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget)
 
static bool isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members)
 

Variables

static cl::opt< bool > ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
 
static cl::opt< bool > EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))
 
static cl::opt< unsigned > ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
 
static cl::opt< unsigned > ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
 
cl::opt< unsigned > MVEMaxSupportedInterleaveFactor ("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))
 
static const MCPhysReg GPRArgRegs []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "arm-isel"

Definition at line 121 of file ARMISelLowering.cpp.

◆ MAKE_CASE

#define MAKE_CASE (   V)
Value:
case V: \
return #V;

Typedef Documentation

◆ RCPair

using RCPair = std::pair<unsigned, const TargetRegisterClass *>

Definition at line 19463 of file ARMISelLowering.cpp.

Enumeration Type Documentation

◆ HABaseType

enum HABaseType
Enumerator
HA_UNKNOWN 
HA_FLOAT 
HA_DOUBLE 
HA_VECT64 
HA_VECT128 

Definition at line 20957 of file ARMISelLowering.cpp.

◆ ShuffleOpCodes

Enumerator
OP_COPY 
OP_VREV 
OP_VDUP0 
OP_VDUP1 
OP_VDUP2 
OP_VDUP3 
OP_VEXT1 
OP_VEXT2 
OP_VEXT3 
OP_VUZPL 
OP_VUZPR 
OP_VZIPL 
OP_VZIPR 
OP_VTRNL 
OP_VTRNR 

Definition at line 8161 of file ARMISelLowering.cpp.

Function Documentation

◆ AddCombineBUILD_VECTORToVPADDL()

static SDValue AddCombineBUILD_VECTORToVPADDL ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ AddCombineTo64bitMLAL()

static SDValue AddCombineTo64bitMLAL ( SDNode AddeSubeNode,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ AddCombineTo64BitSMLAL16()

static SDValue AddCombineTo64BitSMLAL16 ( SDNode AddcNode,
SDNode AddeNode,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ AddCombineTo64bitUMAAL()

static SDValue AddCombineTo64bitUMAAL ( SDNode AddeNode,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ AddCombineToVPADD()

static SDValue AddCombineToVPADD ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ AddCombineVUZPToVPADDL()

static SDValue AddCombineVUZPToVPADDL ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ AddRequiredExtensionForVMULL()

static SDValue AddRequiredExtensionForVMULL ( SDValue  N,
SelectionDAG DAG,
const EVT OrigTy,
const EVT ExtTy,
unsigned  ExtOpcode 
)
static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.

We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 9215 of file ARMISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.

Referenced by SkipExtensionForVMULL().

◆ allUsersAreInFunction()

static bool allUsersAreInFunction ( const Value V,
const Function F 
)
static

Return true if all users of V are within function F, looking through ConstantExprs.

Definition at line 3690 of file ARMISelLowering.cpp.

References llvm::append_range(), F, I, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::Value::users().

Referenced by promoteToConstantPool().

◆ areExtractExts()

static bool areExtractExts ( Value Ext1,
Value Ext2 
)
static

Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.

Definition at line 18301 of file ARMISelLowering.cpp.

References llvm::MipsISD::Ext, llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().

Referenced by llvm::ARMTargetLowering::shouldSinkOperands().

◆ attachMEMCPYScratchRegs()

static void attachMEMCPYScratchRegs ( const ARMSubtarget Subtarget,
MachineInstr MI,
const SDNode Node 
)
static

Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.

This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.

Definition at line 12002 of file ARMISelLowering.cpp.

◆ bitcastf32Toi32()

static SDValue bitcastf32Toi32 ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ BitsProperlyConcatenate()

static bool BitsProperlyConcatenate ( const APInt A,
const APInt B 
)
static

Definition at line 14390 of file ARMISelLowering.cpp.

References B.

Referenced by FindBFIToCombineWith().

◆ canChangeToInt()

static bool canChangeToInt ( SDValue  Op,
bool &  SeenZero,
const ARMSubtarget Subtarget 
)
static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 5492 of file ARMISelLowering.cpp.

References llvm::MVT::f32, isFloatingPointZero(), llvm::ARMSubtarget::isFPBrccSlow(), llvm::ISD::isNormalLoad(), and N.

◆ canGuaranteeTCO()

static bool canGuaranteeTCO ( CallingConv::ID  CC,
bool  GuaranteeTailCalls 
)
static

◆ CanInvertMVEVCMP()

static bool CanInvertMVEVCMP ( SDValue  N)
static

◆ checkAndUpdateCPSRKill()

static bool checkAndUpdateCPSRKill ( MachineBasicBlock::iterator  SelectItr,
MachineBasicBlock BB,
const TargetRegisterInfo TRI 
)
static

◆ checkVSELConstraints()

static void checkVSELConstraints ( ISD::CondCode  CC,
ARMCC::CondCodes CondCode,
bool &  swpCmpOps,
bool &  swpVselOps 
)
static

◆ CombineANDShift()

static SDValue CombineANDShift ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ CombineBaseUpdate()

static SDValue CombineBaseUpdate ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.

For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.

Definition at line 15250 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, Addr, assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::User::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasPredecessorHelper(), i, llvm::MVT::i32, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isStore(), llvm_unreachable, llvm::ISD::LOAD, llvm::makeArrayRef(), n, N, llvm::MVT::Other, llvm::ISD::STORE, llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD1x2_UPD, llvm::ARMISD::VLD1x3_UPD, llvm::ARMISD::VLD1x4_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST1x2_UPD, llvm::ARMISD::VST1x3_UPD, llvm::ARMISD::VST1x4_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, and llvm::ARMISD::VST4LN_UPD.

Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().

◆ combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode N,
SDValue  Slct,
SDValue  OtherOp,
TargetLowering::DAGCombinerInfo DCI,
bool  AllOnes = false 
)
static

◆ combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode N,
bool  AllOnes,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ CombineVLDDUP()

static bool CombineVLDDUP ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ CombineVMOVDRRCandidateWithVecOp()

static SDValue CombineVMOVDRRCandidateWithVecOp ( const SDNode BC,
SelectionDAG DAG 
)
static

BC is a bitcast that is about to be turned into a VMOVDRR.

When DstVT, the destination type of BC, is on the vector register bank and the source of bitcast, Op, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return The node that would replace BT, if the combine is possible.

Definition at line 6099 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::MVT::i32, Index, and llvm::EVT::isVector().

◆ ConvertBooleanCarryToCarryFlag()

static SDValue ConvertBooleanCarryToCarryFlag ( SDValue  BoolCarry,
SelectionDAG DAG 
)
static

◆ ConvertCarryFlagToBooleanCarry()

static SDValue ConvertCarryFlagToBooleanCarry ( SDValue  Flags,
EVT  VT,
SelectionDAG DAG 
)
static

◆ createGPRPairNode()

static SDValue createGPRPairNode ( SelectionDAG DAG,
SDValue  V 
)
static

◆ emitPostLd()

static void emitPostLd ( MachineBasicBlock BB,
MachineBasicBlock::iterator  Pos,
const TargetInstrInfo TII,
const DebugLoc dl,
unsigned  LdSize,
unsigned  Data,
unsigned  AddrIn,
unsigned  AddrOut,
bool  IsThumb1,
bool  IsThumb2 
)
static

Emit a post-increment load operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11006 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), BB, llvm::BuildMI(), llvm::Data, llvm::RegState::Define, getLdOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

◆ emitPostSt()

static void emitPostSt ( MachineBasicBlock BB,
MachineBasicBlock::iterator  Pos,
const TargetInstrInfo TII,
const DebugLoc dl,
unsigned  StSize,
unsigned  Data,
unsigned  AddrIn,
unsigned  AddrOut,
bool  IsThumb1,
bool  IsThumb2 
)
static

Emit a post-increment store operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11047 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), BB, llvm::BuildMI(), llvm::Data, getStOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

◆ Expand64BitShift()

static SDValue Expand64BitShift ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ expandf64Toi32()

static void expandf64Toi32 ( SDValue  Op,
SelectionDAG DAG,
SDValue RetVal1,
SDValue RetVal2 
)
static

◆ ExpandREAD_REGISTER()

static void ExpandREAD_REGISTER ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
)
static

◆ FindBFIToCombineWith()

static SDValue FindBFIToCombineWith ( SDNode N)
static

◆ findMUL_LOHI()

static SDValue findMUL_LOHI ( SDValue  V)
static

◆ FlattenVectorShuffle()

static SDValue FlattenVectorShuffle ( ShuffleVectorSDNode N,
SelectionDAG DAG 
)
static

◆ FPCCToARMCC()

static void FPCCToARMCC ( ISD::CondCode  CC,
ARMCC::CondCodes CondCode,
ARMCC::CondCodes CondCode2 
)
static

◆ GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle ( unsigned  PFEntry,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
const SDLoc dl 
)
static

◆ genTPEntry()

static Register genTPEntry ( MachineBasicBlock TpEntry,
MachineBasicBlock TpLoopBody,
MachineBasicBlock TpExit,
Register  OpSizeReg,
const TargetInstrInfo TII,
DebugLoc  Dl,
MachineRegisterInfo MRI 
)
static

◆ genTPLoopBody()

static void genTPLoopBody ( MachineBasicBlock TpLoopBody,
MachineBasicBlock TpEntry,
MachineBasicBlock TpExit,
const TargetInstrInfo TII,
DebugLoc  Dl,
MachineRegisterInfo MRI,
Register  OpSrcReg,
Register  OpDestReg,
Register  ElementCountReg,
Register  TotalIterationsReg,
bool  IsMemcpy 
)
static

◆ getARMIndexedAddressParts()

static bool getARMIndexedAddressParts ( SDNode Ptr,
EVT  VT,
bool  isSEXTLoad,
SDValue Base,
SDValue Offset,
bool &  isInc,
SelectionDAG DAG 
)
static

◆ getDivRemArgList()

static TargetLowering::ArgListTy getDivRemArgList ( const SDNode N,
LLVMContext Context,
const ARMSubtarget Subtarget 
)
static

◆ getDivRemLibcall()

static RTLIB::Libcall getDivRemLibcall ( const SDNode N,
MVT::SimpleValueType  SVT 
)
static

◆ getExtensionTo64Bits()

static EVT getExtensionTo64Bits ( const EVT OrigVT)
static

◆ getLdOpcode()

static unsigned getLdOpcode ( unsigned  LdSize,
bool  IsThumb1,
bool  IsThumb2 
)
static

Return the load opcode for a given load size.

If load size >= 8, neon opcode will be returned.

Definition at line 10968 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

◆ getMVEIndexedAddressParts()

static bool getMVEIndexedAddressParts ( SDNode Ptr,
EVT  VT,
Align  Alignment,
bool  isSEXTLoad,
bool  IsMasked,
bool  isLE,
SDValue Base,
SDValue Offset,
bool &  isInc,
SelectionDAG DAG 
)
static

◆ getStOpcode()

static unsigned getStOpcode ( unsigned  StSize,
bool  IsThumb1,
bool  IsThumb2 
)
static

Return the store opcode for a given store size.

If store size >= 8, neon opcode will be returned.

Definition at line 10987 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

◆ getT2IndexedAddressParts()

static bool getT2IndexedAddressParts ( SDNode Ptr,
EVT  VT,
bool  isSEXTLoad,
SDValue Base,
SDValue Offset,
bool &  isInc,
SelectionDAG DAG 
)
static

◆ getVCMPCondCode()

static ARMCC::CondCodes getVCMPCondCode ( SDValue  N)
static

◆ getVectorTyFromPredicateVector()

static EVT getVectorTyFromPredicateVector ( EVT  VT)
static

◆ getVShiftImm()

static bool getVShiftImm ( SDValue  Op,
unsigned  ElementBits,
int64_t &  Cnt 
)
static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 6460 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

◆ getZeroVector()

static SDValue getZeroVector ( EVT  VT,
SelectionDAG DAG,
const SDLoc dl 
)
static

getZeroVector - Returns a vector of specified type with all zero elements.

Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 6211 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::EVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ARMISD::VMOVIMM.

Referenced by LowerCTTZ(), and LowerShift().

◆ hasNormalLoadOperand()

static bool hasNormalLoadOperand ( SDNode N)
static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.

If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 14692 of file ARMISelLowering.cpp.

References i, llvm::ISD::isNormalLoad(), and N.

Referenced by PerformBUILD_VECTORCombine().

◆ IntCCToARMCC()

static ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode  CC)
static

◆ isAddSubSExt()

static bool isAddSubSExt ( SDNode N,
SelectionDAG DAG 
)
static

Definition at line 9312 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.

Referenced by LowerMUL().

◆ isAddSubZExt()

static bool isAddSubZExt ( SDNode N,
SelectionDAG DAG 
)
static

Definition at line 9323 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.

Referenced by LowerMUL().

◆ isConditionalZeroOrAllOnes()

static bool isConditionalZeroOrAllOnes ( SDNode N,
bool  AllOnes,
SDValue CC,
bool &  Invert,
SDValue OtherOp,
SelectionDAG DAG 
)
static

◆ isExtendedBUILD_VECTOR()

static bool isExtendedBUILD_VECTOR ( SDNode N,
SelectionDAG DAG,
bool  isSigned 
)
static

isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.

Definition at line 9123 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::numbers::e, llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), i, llvm::DataLayout::isBigEndian(), llvm::isIntN(), llvm::isUIntN(), llvm::ConstantSDNode::isZero(), N, llvm::MVT::v2i64, and llvm::MVT::v4i32.

Referenced by isSignExtended(), and isZeroExtended().

◆ isFloatingPointZero()

static bool isFloatingPointZero ( SDValue  Op)
static

◆ isGTorGE()

static bool isGTorGE ( ISD::CondCode  CC)
static

Definition at line 5174 of file ARMISelLowering.cpp.

References llvm::ISD::SETGE, and llvm::ISD::SETGT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

◆ isHomogeneousAggregate()

static bool isHomogeneousAggregate ( Type Ty,
HABaseType Base,
uint64_t Members 
)
static

◆ isLegalAddressImmediate()

static bool isLegalAddressImmediate ( int64_t  V,
EVT  VT,
const ARMSubtarget Subtarget 
)
static

◆ isLegalMVEShuffleOp()

static bool isLegalMVEShuffleOp ( unsigned  PFEntry)
static

◆ isLegalT1AddressImmediate()

static bool isLegalT1AddressImmediate ( int64_t  V,
EVT  VT 
)
static

◆ isLegalT2AddressImmediate()

static bool isLegalT2AddressImmediate ( int64_t  V,
EVT  VT,
const ARMSubtarget Subtarget 
)
static

◆ isLowerSaturate()

static bool isLowerSaturate ( const SDValue  LHS,
const SDValue  RHS,
const SDValue  TrueVal,
const SDValue  FalseVal,
const ISD::CondCode  CC,
const SDValue  K 
)
static

◆ isLowerSaturatingConditional()

static bool isLowerSaturatingConditional ( const SDValue Op,
SDValue V,
SDValue SatK 
)
static

◆ isLTorLE()

static bool isLTorLE ( ISD::CondCode  CC)
static

Definition at line 5178 of file ARMISelLowering.cpp.

References llvm::ISD::SETLE, and llvm::ISD::SETLT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

◆ isNEONTwoResultShuffleMask()

static unsigned isNEONTwoResultShuffleMask ( ArrayRef< int ShuffleMask,
EVT  VT,
unsigned &  WhichResult,
bool &  isV_UNDEF 
)
static

Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.

Definition at line 7407 of file ARMISelLowering.cpp.

References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isPowerOf2Constant()

static const APInt* isPowerOf2Constant ( SDValue  V)
static

◆ isReverseMask()

static bool isReverseMask ( ArrayRef< int M,
EVT  VT 
)
static

◆ isS16()

static bool isS16 ( const SDValue Op,
SelectionDAG DAG 
)
static

◆ isSHL16()

static bool isSHL16 ( const SDValue Op)
static

Definition at line 1953 of file ARMISelLowering.cpp.

References llvm::ISD::SHL.

Referenced by isS16(), and PerformORCombineToSMULWBT().

◆ isSignExtended()

static bool isSignExtended ( SDNode N,
SelectionDAG DAG 
)
static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 9176 of file ARMISelLowering.cpp.

References isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), N, and llvm::ISD::SIGN_EXTEND.

Referenced by isAddSubSExt(), and LowerMUL().

◆ IsSingleInstrConstant()

static SDValue IsSingleInstrConstant ( SDValue  N,
SelectionDAG DAG,
const ARMSubtarget ST,
const SDLoc dl 
)
static

◆ isSingletonVEXTMask()

static bool isSingletonVEXTMask ( ArrayRef< int M,
EVT  VT,
unsigned &  Imm 
)
static

Definition at line 7108 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), i, and M.

Referenced by LowerVECTOR_SHUFFLE().

◆ isSRA16()

static bool isSRA16 ( const SDValue Op)
static

Definition at line 1945 of file ARMISelLowering.cpp.

References llvm::ISD::SRA.

Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().

◆ isSRL16()

static bool isSRL16 ( const SDValue Op)
static

Definition at line 1937 of file ARMISelLowering.cpp.

References llvm::ISD::SRL.

Referenced by PerformORCombineToSMULWBT().

◆ isValidMVECond()

static bool isValidMVECond ( unsigned  CC,
bool  IsFloat 
)
static

◆ isVEXTMask()

static bool isVEXTMask ( ArrayRef< int M,
EVT  VT,
bool &  ReverseVEXT,
unsigned &  Imm 
)
static

◆ isVMOVModifiedImm()

static SDValue isVMOVModifiedImm ( uint64_t  SplatBits,
uint64_t  SplatUndef,
unsigned  SplatBitSize,
SelectionDAG DAG,
const SDLoc dl,
EVT VT,
EVT  VectorVT,
VMOVModImmType  type 
)
static

◆ isVMOVNMask()

static bool isVMOVNMask ( ArrayRef< int M,
EVT  VT,
bool  Top,
bool  SingleSource 
)
static

◆ isVMOVNTruncMask()

static bool isVMOVNTruncMask ( ArrayRef< int M,
EVT  ToVT,
bool  rev 
)
static

◆ isVShiftLImm()

static bool isVShiftLImm ( SDValue  Op,
EVT  VT,
bool  isLong,
int64_t &  Cnt 
)
static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 6481 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by LowerShift(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), and PerformShiftCombine().

◆ isVShiftRImm()

static bool isVShiftRImm ( SDValue  Op,
EVT  VT,
bool  isNarrow,
bool  isIntrinsic,
int64_t &  Cnt 
)
static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 6495 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by LowerShift(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), and PerformShiftCombine().

◆ isVTBLMask()

static bool isVTBLMask ( ArrayRef< int M,
EVT  VT 
)
static

Definition at line 7172 of file ARMISelLowering.cpp.

References M, and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().

◆ isVTRN_v_undef_Mask()

static bool isVTRN_v_undef_Mask ( ArrayRef< int M,
EVT  VT,
unsigned &  WhichResult 
)
static

isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 7239 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, j(), M, and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVTRNMask()

static bool isVTRNMask ( ArrayRef< int M,
EVT  VT,
unsigned &  WhichResult 
)
static

◆ isVUZP_v_undef_Mask()

static bool isVUZP_v_undef_Mask ( ArrayRef< int M,
EVT  VT,
unsigned &  WhichResult 
)
static

isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 7301 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), j(), M, and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVUZPMask()

static bool isVUZPMask ( ArrayRef< int M,
EVT  VT,
unsigned &  WhichResult 
)
static

◆ IsVUZPShuffleNode()

static bool IsVUZPShuffleNode ( SDNode N)
static

◆ isVZIP_v_undef_Mask()

static bool isVZIP_v_undef_Mask ( ArrayRef< int M,
EVT  VT,
unsigned &  WhichResult 
)
static

isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 7375 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), j(), M, and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVZIPMask()

static bool isVZIPMask ( ArrayRef< int M,
EVT  VT,
unsigned &  WhichResult 
)
static

◆ isZeroExtended()

static bool isZeroExtended ( SDNode N,
SelectionDAG DAG 
)
static

isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 9186 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), N, and llvm::ISD::ZERO_EXTEND.

Referenced by isAddSubZExt(), and LowerMUL().

◆ isZeroOrAllOnes()

static bool isZeroOrAllOnes ( SDValue  N,
bool  AllOnes 
)
inlinestatic

◆ isZeroVector()

static bool isZeroVector ( SDValue  N)
static

◆ LowerADDSUBCARRY()

static SDValue LowerADDSUBCARRY ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerADDSUBSAT()

static SDValue LowerADDSUBSAT ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerATOMIC_FENCE()

static SDValue LowerATOMIC_FENCE ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerAtomicLoadStore()

static SDValue LowerAtomicLoadStore ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerBUILD_VECTOR_i1()

static SDValue LowerBUILD_VECTOR_i1 ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerBUILD_VECTORToVIDUP()

static SDValue LowerBUILD_VECTORToVIDUP ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerBuildVectorOfFPExt()

static SDValue LowerBuildVectorOfFPExt ( SDValue  BV,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerBuildVectorOfFPTrunc()

static SDValue LowerBuildVectorOfFPTrunc ( SDValue  BV,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerCONCAT_VECTORS()

static SDValue LowerCONCAT_VECTORS ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerCONCAT_VECTORS_i1()

static SDValue LowerCONCAT_VECTORS_i1 ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerCTPOP()

static SDValue LowerCTPOP ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerCTTZ()

static SDValue LowerCTTZ ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerEXTRACT_SUBVECTOR()

static SDValue LowerEXTRACT_SUBVECTOR ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerEXTRACT_VECTOR_ELT()

static SDValue LowerEXTRACT_VECTOR_ELT ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerEXTRACT_VECTOR_ELT_i1()

static SDValue LowerEXTRACT_VECTOR_ELT_i1 ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerFP_TO_INT_SAT()

static SDValue LowerFP_TO_INT_SAT ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerINSERT_VECTOR_ELT_i1()

static SDValue LowerINSERT_VECTOR_ELT_i1 ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerInterruptReturn()

static SDValue LowerInterruptReturn ( SmallVectorImpl< SDValue > &  RetOps,
const SDLoc DL,
SelectionDAG DAG 
)
static

◆ LowerMLOAD()

static SDValue LowerMLOAD ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerMUL()

static SDValue LowerMUL ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerPredicateLoad()

static SDValue LowerPredicateLoad ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerPredicateStore()

static SDValue LowerPredicateStore ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerPREFETCH()

static SDValue LowerPREFETCH ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerReverse_VECTOR_SHUFFLE()

static SDValue LowerReverse_VECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerSaturatingConditional()

static SDValue LowerSaturatingConditional ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerSDIV()

static SDValue LowerSDIV ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerSDIV_v4i16()

static SDValue LowerSDIV_v4i16 ( SDValue  N0,
SDValue  N1,
const SDLoc dl,
SelectionDAG DAG 
)
static

◆ LowerSDIV_v4i8()

static SDValue LowerSDIV_v4i8 ( SDValue  X,
SDValue  Y,
const SDLoc dl,
SelectionDAG DAG 
)
static

◆ LowerSETCCCARRY()

static SDValue LowerSETCCCARRY ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerShift()

static SDValue LowerShift ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerSTORE()

static SDValue LowerSTORE ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerTruncate()

static SDValue LowerTruncate ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerTruncatei1()

static SDValue LowerTruncatei1 ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerUDIV()

static SDValue LowerUDIV ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerVASTART()

static SDValue LowerVASTART ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerVecReduce()

static SDValue LowerVecReduce ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerVecReduceF()

static SDValue LowerVecReduceF ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

Definition at line 10062 of file ARMISelLowering.cpp.

References LowerVecReduce(), and llvm::ARM_MB::ST.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerVECTOR_SHUFFLE()

static SDValue LowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

Definition at line 8571 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::numbers::e, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), i, llvm::MVT::i32, int, isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SDValue::isUndef(), isVEXTMask(), isVMOVNMask(), llvm::isVREVMask(), LowerReverse_VECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), PerfectShuffleTable, llvm::ISD::SCALAR_TO_VECTOR, llvm::ARM_MB::ST, std::swap(), llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VMOVN, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ARMISD::VREV64.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerVECTOR_SHUFFLE_i1()

static SDValue LowerVECTOR_SHUFFLE_i1 ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerVECTOR_SHUFFLEUsingMovs()

static SDValue LowerVECTOR_SHUFFLEUsingMovs ( SDValue  Op,
ArrayRef< int ShuffleMask,
SelectionDAG DAG 
)
static

◆ LowerVECTOR_SHUFFLEUsingOneOff()

static SDValue LowerVECTOR_SHUFFLEUsingOneOff ( SDValue  Op,
ArrayRef< int ShuffleMask,
SelectionDAG DAG 
)
static

◆ LowerVECTOR_SHUFFLEv8i8()

static SDValue LowerVECTOR_SHUFFLEv8i8 ( SDValue  Op,
ArrayRef< int ShuffleMask,
SelectionDAG DAG 
)
static

◆ LowerVectorExtend()

static SDValue LowerVectorExtend ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ LowerVectorFP_TO_INT()

static SDValue LowerVectorFP_TO_INT ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerVectorINT_TO_FP()

static SDValue LowerVectorINT_TO_FP ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerVSETCC()

static SDValue LowerVSETCC ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ LowerWRITE_REGISTER()

static SDValue LowerWRITE_REGISTER ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ MatchingStackOffset()

static bool MatchingStackOffset ( SDValue  Arg,
unsigned  Offset,
ISD::ArgFlagsTy  Flags,
MachineFrameInfo MFI,
const MachineRegisterInfo MRI,
const TargetInstrInfo TII 
)
static

◆ OtherSucc()

static MachineBasicBlock* OtherSucc ( MachineBasicBlock MBB,
MachineBasicBlock Succ 
)
static

◆ ParseBFI()

static SDValue ParseBFI ( SDNode N,
APInt ToMask,
APInt FromMask 
)
static

◆ PerformABSCombine()

static SDValue PerformABSCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformADDCombine()

static SDValue PerformADDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 13547 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, N, PerformADDCombineWithOperands(), PerformADDVecReduce(), and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDCombineWithOperands()

static SDValue PerformADDCombineWithOperands ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.

This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 13130 of file ARMISelLowering.cpp.

References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.

Referenced by PerformADDCombine().

◆ PerformAddcSubcCombine()

static SDValue PerformAddcSubcCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformADDECombine()

static SDValue PerformADDECombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.

Definition at line 13113 of file ARMISelLowering.cpp.

References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), N, and PerformAddeSubeCombine().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformAddeSubeCombine()

static SDValue PerformAddeSubeCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformADDVecReduce()

static SDValue PerformADDVecReduce ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ PerformANDCombine()

static SDValue PerformANDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformARMBUILD_VECTORCombine()

static SDValue PerformARMBUILD_VECTORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformBFICombine()

static SDValue PerformBFICombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformBITCASTCombine()

static SDValue PerformBITCASTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget ST 
)
static

◆ PerformBUILD_VECTORCombine()

static SDValue PerformBUILD_VECTORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformExtendCombine()

static SDValue PerformExtendCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ PerformExtractEltCombine()

static SDValue PerformExtractEltCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget ST 
)
static

◆ PerformExtractEltToVMOVRRD()

static SDValue PerformExtractEltToVMOVRRD ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformExtractFpToIntStores()

static SDValue PerformExtractFpToIntStores ( StoreSDNode St,
SelectionDAG DAG 
)
static

◆ PerformFPExtendCombine()

static SDValue PerformFPExtendCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ PerformHWLoopCombine()

static SDValue PerformHWLoopCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget ST 
)
static

◆ PerformInsertEltCombine()

static SDValue PerformInsertEltCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformInsertSubvectorCombine()

static SDValue PerformInsertSubvectorCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformLOADCombine()

static SDValue PerformLOADCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformLongShiftCombine()

static SDValue PerformLongShiftCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformMinMaxCombine()

static SDValue PerformMinMaxCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ PerformMULCombine()

static SDValue PerformMULCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformMVEVLDCombine()

static SDValue PerformMVEVLDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformMVEVMULLCombine()

static SDValue PerformMVEVMULLCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ PerformORCombine()

static SDValue PerformORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformORCombine_i1()

static SDValue PerformORCombine_i1 ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ PerformORCombineToBFI()

static SDValue PerformORCombineToBFI ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformORCombineToSMULWBT()

static SDValue PerformORCombineToSMULWBT ( SDNode OR,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformPREDICATE_CASTCombine()

static SDValue PerformPREDICATE_CASTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformSELECTCombine()

static SDValue PerformSELECTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformShiftCombine()

static SDValue PerformShiftCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget ST 
)
static

◆ PerformSHLSimplify()

static SDValue PerformSHLSimplify ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget ST 
)
static

◆ PerformShuffleVMOVNCombine()

static SDValue PerformShuffleVMOVNCombine ( ShuffleVectorSDNode N,
SelectionDAG DAG 
)
static

◆ PerformSignExtendInregCombine()

static SDValue PerformSignExtendInregCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformSplittingMVEEXTToWideningLoad()

static SDValue PerformSplittingMVEEXTToWideningLoad ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformSplittingMVETruncToNarrowingStores()

static SDValue PerformSplittingMVETruncToNarrowingStores ( StoreSDNode St,
SelectionDAG DAG 
)
static

◆ PerformSplittingToNarrowingStores()

static SDValue PerformSplittingToNarrowingStores ( StoreSDNode St,
SelectionDAG DAG 
)
static

◆ PerformSplittingToWideningLoad()

static SDValue PerformSplittingToWideningLoad ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformSTORECombine()

static SDValue PerformSTORECombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 16050 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::ARMSubtarget::hasMVEIntegerOps(), llvm::ARMSubtarget::hasNEON(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, PerformExtractFpToIntStores(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformTruncatingStoreCombine(), llvm::SPII::Store, and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSUBCombine()

static SDValue PerformSUBCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformSubCSINCCombine()

static SDValue PerformSubCSINCCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformTruncatingStoreCombine()

static SDValue PerformTruncatingStoreCombine ( StoreSDNode St,
SelectionDAG DAG 
)
static

◆ PerformUMLALCombine()

static SDValue PerformUMLALCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ PerformVCMPCombine()

static SDValue PerformVCMPCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ PerformVCVTCombine()

static SDValue PerformVCVTCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 16139 of file ARMISelLowering.cpp.

References llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::TRUNCATE, llvm::MVT::v2i32, and llvm::MVT::v4i32.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDIVCombine()

static SDValue PerformVDIVCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3

Definition at line 16196 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDUPCombine()

static SDValue PerformVDUPCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ PerformVDUPLANECombine()

static SDValue PerformVDUPLANECombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformVECREDUCE_ADDCombine()

static SDValue PerformVECREDUCE_ADDCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ PerformVECTOR_REG_CASTCombine()

static SDValue PerformVECTOR_REG_CASTCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

◆ PerformVECTOR_SHUFFLECombine()

static SDValue PerformVECTOR_SHUFFLECombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformVLDCombine()

static SDValue PerformVLDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformVMOVDRRCombine()

static SDValue PerformVMOVDRRCombine ( SDNode N,
SelectionDAG DAG 
)
static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.

This is also used for BUILD_VECTORs with 2 operands.

Definition at line 14594 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), N, and llvm::ARMISD::VMOVRRD.

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMOVhrCombine()

static SDValue PerformVMOVhrCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformVMOVNCombine()

static SDValue PerformVMOVNCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformVMOVrhCombine()

static SDValue PerformVMOVrhCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformVMOVRRDCombine()

static SDValue PerformVMOVRRDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformVMULCombine()

static SDValue PerformVMULCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.

vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 13643 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ARMSubtarget::hasVMLxForwarding(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

◆ PerformVQDMULHCombine()

static SDValue PerformVQDMULHCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ PerformVQMOVNCombine()

static SDValue PerformVQMOVNCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ PerformVSELECTCombine()

static SDValue PerformVSELECTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PerformXORCombine()

static SDValue PerformXORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

◆ PromoteMVEPredVector()

static SDValue PromoteMVEPredVector ( SDLoc  dl,
SDValue  Pred,
EVT  VT,
SelectionDAG DAG 
)
static

◆ promoteToConstantPool()

static SDValue promoteToConstantPool ( const ARMTargetLowering TLI,
const GlobalValue GV,
SelectionDAG DAG,
EVT  PtrVT,
const SDLoc dl 
)
static

◆ ReplaceCMP_SWAP_64Results()

static void ReplaceCMP_SWAP_64Results ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
)
static

◆ ReplaceLongIntrinsic()

static void ReplaceLongIntrinsic ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
)
static

◆ ReplaceREADCYCLECOUNTER()

static void ReplaceREADCYCLECOUNTER ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

◆ SearchLoopIntrinsic()

static SDValue SearchLoopIntrinsic ( SDValue  N,
ISD::CondCode CC,
int Imm,
bool &  Negate 
)
static

Definition at line 17250 of file ARMISelLowering.cpp.

References llvm::ISD::INTRINSIC_W_CHAIN, N, llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by PerformHWLoopCombine().

◆ SelectPairHalf()

static unsigned SelectPairHalf ( unsigned  Elements,
ArrayRef< int Mask,
unsigned  Index 
)
static

◆ SkipExtensionForVMULL()

static SDValue SkipExtensionForVMULL ( SDNode N,
SelectionDAG DAG 
)
static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.

The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 9261 of file ARMISelLowering.cpp.

References AddRequiredExtensionForVMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), i, llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), llvm::ARM_MB::LD, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::MVT::v2i32, llvm::MVT::v4i32, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

Referenced by LowerMUL().

◆ SkipLoadExtensionForVMULL()

static SDValue SkipLoadExtensionForVMULL ( LoadSDNode LD,
SelectionDAG DAG 
)
static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.

If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 9237 of file ARMISelLowering.cpp.

References getExtensionTo64Bits(), llvm::SelectionDAG::getExtLoad(), llvm::SelectionDAG::getLoad(), and llvm::ARM_MB::LD.

Referenced by SkipExtensionForVMULL().

◆ STATISTIC() [1/4]

STATISTIC ( NumConstpoolPromoted  ,
"Number of constants with their storage promoted into constant pools"   
)

◆ STATISTIC() [2/4]

STATISTIC ( NumLoopByVals  ,
"Number of loops generated for byval arguments  
)

◆ STATISTIC() [3/4]

STATISTIC ( NumMovwMovt  ,
"Number of GAs materialized with movw + movt"   
)

◆ STATISTIC() [4/4]

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ TryDistrubutionADDVecReduce()

static SDValue TryDistrubutionADDVecReduce ( SDNode N,
SelectionDAG DAG 
)
static

◆ WinDBZCheckDenominator()

static SDValue WinDBZCheckDenominator ( SelectionDAG DAG,
SDNode N,
SDValue  InChain 
)
static

Variable Documentation

◆ ARMInterworking

cl::opt<bool> ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
static

◆ ConstpoolPromotionMaxSize

cl::opt<unsigned> ConstpoolPromotionMaxSize("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
static

Referenced by promoteToConstantPool().

◆ ConstpoolPromotionMaxTotal

cl::opt<unsigned> ConstpoolPromotionMaxTotal("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
static

Referenced by promoteToConstantPool().

◆ EnableConstpoolPromotion

cl::opt<bool> EnableConstpoolPromotion("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))
static

Referenced by promoteToConstantPool().

◆ GPRArgRegs

const MCPhysReg GPRArgRegs[]
static
Initial value:
= {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
}

Definition at line 154 of file ARMISelLowering.cpp.

Referenced by f64AssignAAPCS().

◆ MVEMaxSupportedInterleaveFactor

cl::opt<unsigned> MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))
R2
#define R2(n)