LLVM
15.0.0git
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#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <string>
#include <tuple>
#include <utility>
#include <vector>
Go to the source code of this file.
Classes | |
struct | BaseUpdateTarget |
Load/store instruction that can be merged with a base address update. More... | |
struct | BaseUpdateUser |
Macros | |
#define | DEBUG_TYPE "arm-isel" |
#define | MAKE_CASE(V) |
Typedefs | |
using | RCPair = std::pair< unsigned, const TargetRegisterClass * > |
Enumerations | |
enum | ShuffleOpCodes { OP_COPY = 0, OP_VREV, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, OP_VTRNL, OP_VTRNR } |
enum | HABaseType { HA_UNKNOWN = 0, HA_FLOAT, HA_DOUBLE, HA_VECT64, HA_VECT128 } |
Functions | |
STATISTIC (NumTailCalls, "Number of tail calls") | |
STATISTIC (NumMovwMovt, "Number of GAs materialized with movw + movt") | |
STATISTIC (NumLoopByVals, "Number of loops generated for byval arguments") | |
STATISTIC (NumConstpoolPromoted, "Number of constants with their storage promoted into constant pools") | |
static bool | isSRL16 (const SDValue &Op) |
static bool | isSRA16 (const SDValue &Op) |
static bool | isSHL16 (const SDValue &Op) |
static bool | isS16 (const SDValue &Op, SelectionDAG &DAG) |
static ARMCC::CondCodes | IntCCToARMCC (ISD::CondCode CC) |
IntCCToARMCC - Convert a DAG integer condition code to an ARM CC. More... | |
static void | FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2) |
FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. More... | |
static bool | canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls) |
static bool | MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII) |
MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack. More... | |
static SDValue | LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG) |
static SDValue | LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG) |
static bool | allUsersAreInFunction (const Value *V, const Function *F) |
Return true if all users of V are within function F, looking through ConstantExprs. More... | |
static SDValue | promoteToConstantPool (const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl) |
static SDValue | LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | LowerVASTART (SDValue Op, SelectionDAG &DAG) |
static bool | isFloatingPointZero (SDValue Op) |
isFloatingPointZero - Return true if this is +0.0. More... | |
static SDValue | ConvertBooleanCarryToCarryFlag (SDValue BoolCarry, SelectionDAG &DAG) |
static SDValue | ConvertCarryFlagToBooleanCarry (SDValue Flags, EVT VT, SelectionDAG &DAG) |
static SDValue | LowerADDSUBSAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static void | checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) |
static bool | isGTorGE (ISD::CondCode CC) |
static bool | isLTorLE (ISD::CondCode CC) |
static bool | isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K) |
static SDValue | LowerSaturatingConditional (SDValue Op, SelectionDAG &DAG) |
static bool | isLowerSaturatingConditional (const SDValue &Op, SDValue &V, SDValue &SatK) |
static bool | canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget) |
canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence. More... | |
static SDValue | bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG) |
static void | expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2) |
static SDValue | LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG) |
static SDValue | LowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG) |
static void | ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) |
static SDValue | CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG) |
BC is a bitcast that is about to be turned into a VMOVDRR. More... | |
static SDValue | getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl) |
getZeroVector - Returns a vector of specified type with all zero elements. More... | |
static SDValue | LowerCTTZ (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerCTPOP (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static bool | getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt) |
Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More... | |
static bool | isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt) |
isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More... | |
static bool | isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt) |
isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More... | |
static SDValue | LowerShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | Expand64BitShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerVSETCC (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerSETCCCARRY (SDValue Op, SelectionDAG &DAG) |
static SDValue | isVMOVModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type) |
isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified
immediate" operand (e.g., VMOV). More... | |
static bool | isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm) |
static bool | isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm) |
static bool | isVTBLMask (ArrayRef< int > M, EVT VT) |
static unsigned | SelectPairHalf (unsigned Elements, ArrayRef< int > Mask, unsigned Index) |
static bool | isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
static bool | isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
static bool | isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
static bool | isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
static bool | isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
static bool | isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
static unsigned | isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF) |
Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't. More... | |
static bool | isReverseMask (ArrayRef< int > M, EVT VT) |
static bool | isVMOVNMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource) |
static bool | isVMOVNTruncMask (ArrayRef< int > M, EVT ToVT, bool rev) |
static SDValue | LowerBuildVectorOfFPTrunc (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerBuildVectorOfFPExt (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl) |
static SDValue | LowerBUILD_VECTOR_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerBUILD_VECTORToVIDUP (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static bool | IsQRMVEInstruction (const SDNode *N, const SDNode *Op) |
static bool | isLegalMVEShuffleOp (unsigned PFEntry) |
static SDValue | GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) |
GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More... | |
static SDValue | LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG) |
static SDValue | LowerReverse_VECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG) |
static EVT | getVectorTyFromPredicateVector (EVT VT) |
static SDValue | PromoteMVEPredVector (SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG) |
static SDValue | LowerVECTOR_SHUFFLE_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerVECTOR_SHUFFLEUsingMovs (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG) |
static SDValue | LowerVECTOR_SHUFFLEUsingOneOff (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG) |
static SDValue | LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerINSERT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerEXTRACT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerCONCAT_VECTORS_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerTruncatei1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerTruncate (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | LowerVectorExtend (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static bool | isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned) |
isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size. More... | |
static bool | isSignExtended (SDNode *N, SelectionDAG &DAG) |
isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements. More... | |
static bool | isZeroExtended (SDNode *N, SelectionDAG &DAG) |
isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements. More... | |
static EVT | getExtensionTo64Bits (const EVT &OrigVT) |
static SDValue | AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) |
AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits. More... | |
static SDValue | SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG) |
SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension. More... | |
static SDValue | SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG) |
SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value. More... | |
static bool | isAddSubSExt (SDNode *N, SelectionDAG &DAG) |
static bool | isAddSubZExt (SDNode *N, SelectionDAG &DAG) |
static SDValue | LowerMUL (SDValue Op, SelectionDAG &DAG) |
static SDValue | LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG) |
static SDValue | LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG) |
static SDValue | LowerSDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerUDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerADDSUBCARRY (SDValue Op, SelectionDAG &DAG) |
static SDValue | WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain) |
static SDValue | LowerPredicateLoad (SDValue Op, SelectionDAG &DAG) |
static SDValue | LowerPredicateStore (SDValue Op, SelectionDAG &DAG) |
static SDValue | LowerSTORE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static bool | isZeroVector (SDValue N) |
static SDValue | LowerMLOAD (SDValue Op, SelectionDAG &DAG) |
static SDValue | LowerVecReduce (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerVecReduceF (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG) |
static void | ReplaceREADCYCLECOUNTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | createGPRPairNode (SelectionDAG &DAG, SDValue V) |
static void | ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) |
static void | ReplaceLongIntrinsic (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) |
static MachineBasicBlock * | OtherSucc (MachineBasicBlock *MBB, MachineBasicBlock *Succ) |
static unsigned | getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2) |
Return the load opcode for a given load size. More... | |
static unsigned | getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2) |
Return the store opcode for a given store size. More... | |
static void | emitPostLd (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) |
Emit a post-increment load operation with given size. More... | |
static void | emitPostSt (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) |
Emit a post-increment store operation with given size. More... | |
static bool | checkAndUpdateCPSRKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI) |
static Register | genTPEntry (MachineBasicBlock *TpEntry, MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpExit, Register OpSizeReg, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI) |
Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop. More... | |
static void | genTPLoopBody (MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpEntry, MachineBasicBlock *TpExit, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI, Register OpSrcReg, Register OpDestReg, Register ElementCountReg, Register TotalIterationsReg, bool IsMemcpy) |
Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd. More... | |
static void | attachMEMCPYScratchRegs (const ARMSubtarget *Subtarget, MachineInstr &MI, const SDNode *Node) |
Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM. More... | |
static bool | isZeroOrAllOnes (SDValue N, bool AllOnes) |
static bool | isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) |
static SDValue | combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false) |
static SDValue | combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI) |
static bool | IsVUZPShuffleNode (SDNode *N) |
static SDValue | AddCombineToVPADD (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | AddCombineVUZPToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | AddCombineBUILD_VECTORToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | findMUL_LOHI (SDValue V) |
static SDValue | AddCombineTo64BitSMLAL16 (SDNode *AddcNode, SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | AddCombineTo64bitMLAL (SDNode *AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | AddCombineTo64bitUMAAL (SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformUMLALCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformAddcSubcCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformAddeSubeCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformVQDMULHCombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformVSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformVSetCCToVCTPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformABSCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformADDECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL. More... | |
static SDValue | PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1. More... | |
static SDValue | TryDistrubutionADDVecReduce (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformADDVecReduce (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformSHLSimplify (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST) |
static SDValue | PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. More... | |
static SDValue | PerformSubCSINCCombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. More... | |
static SDValue | PerformVMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding. More... | |
static SDValue | PerformMVEVMULLCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | CombineANDShift (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformORCombineToSMULWBT (SDNode *OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformORCombineToBFI (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static bool | isValidMVECond (unsigned CC, bool IsFloat) |
static ARMCC::CondCodes | getVCMPCondCode (SDValue N) |
static bool | CanInvertMVEVCMP (SDValue N) |
static SDValue | PerformORCombine_i1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformORCombine - Target-specific dag combine xforms for ISD::OR. More... | |
static SDValue | PerformXORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask) |
static bool | BitsProperlyConcatenate (const APInt &A, const APInt &B) |
static SDValue | FindBFIToCombineWith (SDNode *N) |
static SDValue | PerformBFICombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | IsCMPZCSINC (SDNode *Cmp, ARMCC::CondCodes &CC) |
static SDValue | PerformCMPZCombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformCSETCombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformVMOVRRDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD. More... | |
static SDValue | PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG) |
PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR. More... | |
static SDValue | PerformVMOVhrCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformVMOVrhCombine (SDNode *N, SelectionDAG &DAG) |
static bool | hasNormalLoadOperand (SDNode *N) |
hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads. More... | |
static SDValue | PerformBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR. More... | |
static SDValue | PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
Target-specific dag combine xforms for ARMISD::BUILD_VECTOR. More... | |
static SDValue | PerformPREDICATE_CASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformVECTOR_REG_CASTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | PerformVCMPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT. More... | |
static SDValue | PerformExtractEltToVMOVRRD (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformExtractEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST) |
static SDValue | PerformSignExtendInregCombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | FlattenVectorShuffle (ShuffleVectorSDNode *N, SelectionDAG &DAG) |
static SDValue | PerformInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformShuffleVMOVNCombine (ShuffleVectorSDNode *N, SelectionDAG &DAG) |
static SDValue | PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG) |
PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE. More... | |
static bool | TryCombineBaseUpdate (struct BaseUpdateTarget &Target, struct BaseUpdateUser &User, bool SimpleConstIncOnly, TargetLowering::DAGCombinerInfo &DCI) |
static unsigned | getPointerConstIncrement (unsigned Opcode, SDValue Ptr, SDValue Inc, const SelectionDAG &DAG) |
static bool | findPointerConstIncrement (SDNode *N, SDValue *Ptr, SDValue *CInc) |
static bool | isValidBaseUpdate (SDNode *N, SDNode *User) |
static SDValue | CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates. More... | |
static SDValue | PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformMVEVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static bool | CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs. More... | |
static SDValue | PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE. More... | |
static SDValue | PerformVDUPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP. More... | |
static SDValue | PerformLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
static SDValue | PerformTruncatingStoreCombine (StoreSDNode *St, SelectionDAG &DAG) |
static SDValue | PerformSplittingToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG) |
static SDValue | PerformSplittingMVETruncToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG) |
static SDValue | PerformExtractFpToIntStores (StoreSDNode *St, SelectionDAG &DAG) |
static SDValue | PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) |
PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE. More... | |
static SDValue | PerformVCVTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2. More... | |
static SDValue | PerformFAddVSelectCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformVDIVCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2. More... | |
static SDValue | PerformVECREDUCE_ADDCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | PerformVMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformVQMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
static SDValue | PerformLongShiftCombine (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformShiftCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST) |
PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them. More... | |
static SDValue | PerformSplittingToWideningLoad (SDNode *N, SelectionDAG &DAG) |
static SDValue | PerformExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. More... | |
static SDValue | PerformFPExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
static SDValue | PerformMinMaxToSatCombine (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) |
static SDValue | PerformMinMaxCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) |
PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates. More... | |
static const APInt * | isPowerOf2Constant (SDValue V) |
static SDValue | SearchLoopIntrinsic (SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate) |
static SDValue | PerformHWLoopCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST) |
static SDValue | PerformBITCASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST) |
static SDValue | PerformSplittingMVEEXTToWideningLoad (SDNode *N, SelectionDAG &DAG) |
static bool | areExtractExts (Value *Ext1, Value *Ext2) |
Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements. More... | |
static bool | isLegalT1AddressImmediate (int64_t V, EVT VT) |
static bool | isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget) |
static bool | isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget) |
isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type. More... | |
static bool | getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) |
static bool | getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) |
static bool | getMVEIndexedAddressParts (SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) |
static RTLIB::Libcall | getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT) |
static TargetLowering::ArgListTy | getDivRemArgList (const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget) |
static bool | isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members) |
Variables | |
static cl::opt< bool > | ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true)) |
static cl::opt< bool > | EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false)) |
static cl::opt< unsigned > | ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64)) |
static cl::opt< unsigned > | ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128)) |
cl::opt< unsigned > | MVEMaxSupportedInterleaveFactor ("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2)) |
static const MCPhysReg | GPRArgRegs [] |
#define DEBUG_TYPE "arm-isel" |
Definition at line 121 of file ARMISelLowering.cpp.
#define MAKE_CASE | ( | V | ) |
using RCPair = std::pair<unsigned, const TargetRegisterClass *> |
Definition at line 20081 of file ARMISelLowering.cpp.
enum HABaseType |
Enumerator | |
---|---|
HA_UNKNOWN | |
HA_FLOAT | |
HA_DOUBLE | |
HA_VECT64 | |
HA_VECT128 |
Definition at line 21575 of file ARMISelLowering.cpp.
enum ShuffleOpCodes |
Enumerator | |
---|---|
OP_COPY | |
OP_VREV | |
OP_VDUP0 | |
OP_VDUP1 | |
OP_VDUP2 | |
OP_VDUP3 | |
OP_VEXT1 | |
OP_VEXT2 | |
OP_VEXT3 | |
OP_VUZPL | |
OP_VUZPR | |
OP_VZIPL | |
OP_VZIPR | |
OP_VTRNL | |
OP_VTRNR |
Definition at line 8254 of file ARMISelLowering.cpp.
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Definition at line 12474 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, C1, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::numbers::e, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), i, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, N, llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.
Referenced by PerformADDCombineWithOperands().
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Definition at line 12655 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, AddCombineTo64BitSMLAL16(), llvm::ARMISD::ADDE, assert(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasAnyUseOfValue(), llvm::MVT::i32, llvm::SDNode::isPredecessorOf(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::SMLAL, llvm::ARMISD::SMMLAR, llvm::ARMISD::SMMLSR, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::ARMISD::UMLAL, llvm::ISD::UMUL_LOHI, and llvm::ARMSubtarget::useMulOps().
Referenced by AddCombineTo64bitUMAAL(), and PerformAddeSubeCombine().
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Definition at line 12578 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::BinaryOperator::getOpcode(), llvm::User::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasBaseDSP(), llvm::MVT::i32, isS16(), isSRA16(), Mul, llvm::ISD::MUL, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SMLAL(), llvm::ARMISD::SMLALBB, llvm::ARMISD::SMLALBT, llvm::ARMISD::SMLALTB, llvm::ARMISD::SMLALTT, and llvm::ISD::SRA.
Referenced by AddCombineTo64bitMLAL().
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Definition at line 12821 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, AddCombineTo64bitMLAL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::isNullConstant(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::UMAAL, and llvm::ARMISD::UMLAL.
Referenced by PerformADDECombine().
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Definition at line 12393 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::INTRINSIC_WO_CHAIN, IsVUZPShuffleNode(), and N.
Referenced by PerformADDCombineWithOperands().
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Definition at line 12421 of file ARMISelLowering.cpp.
References Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), N, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by PerformADDCombineWithOperands().
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AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.
We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.
Definition at line 9339 of file ARMISelLowering.cpp.
References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.
Referenced by SkipExtensionForVMULL().
Return true if all users of V are within function F, looking through ConstantExprs.
Definition at line 3728 of file ARMISelLowering.cpp.
References llvm::append_range(), F, I, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::Value::users().
Referenced by promoteToConstantPool().
Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.
Definition at line 18910 of file ARMISelLowering.cpp.
References llvm::MipsISD::Ext, llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().
Referenced by llvm::ARMTargetLowering::shouldSinkOperands().
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Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.
This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.
Definition at line 12125 of file ARMISelLowering.cpp.
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Definition at line 5551 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::MVT::i32, isFloatingPointZero(), and llvm_unreachable.
Definition at line 14588 of file ARMISelLowering.cpp.
References B.
Referenced by FindBFIToCombineWith().
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canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.
Definition at line 5530 of file ARMISelLowering.cpp.
References llvm::MVT::f32, isFloatingPointZero(), llvm::ISD::isNormalLoad(), and N.
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Definition at line 2303 of file ARMISelLowering.cpp.
References llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.
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Definition at line 14389 of file ARMISelLowering.cpp.
References llvm::ARMCC::getOppositeCondition(), getVCMPCondCode(), isValidMVECond(), and N.
Referenced by PerformORCombine_i1(), and PerformXORCombine().
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Definition at line 11571 of file ARMISelLowering.cpp.
References BB, llvm::MachineInstr::definesRegister(), llvm::MachineInstr::readsRegister(), and TRI.
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 5136 of file ARMISelLowering.cpp.
References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ARMCC::VS.
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Definition at line 14023 of file ARMISelLowering.cpp.
References C1, llvm::countLeadingZeros(), llvm::countTrailingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::isShiftedMask_32(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by PerformANDCombine().
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CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.
For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.
Definition at line 15905 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, llvm::TargetLowering::DAGCombinerInfo::DAG, findPointerConstIncrement(), llvm::SelectionDAG::getConstant(), llvm::User::getNumOperands(), llvm::User::getOperand(), getPointerConstIncrement(), I, llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isStore(), isValidBaseUpdate(), LHS, N, llvm::SmallVectorImpl< T >::resize(), RHS, llvm::stable_sort(), llvm::ISD::STORE, std::swap(), and TryCombineBaseUpdate().
Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().
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Definition at line 12342 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::tgtok::FalseVal, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), isConditionalZeroOrAllOnes(), N, llvm::ISD::SELECT, std::swap(), and llvm::tgtok::TrueVal.
Referenced by combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), and PerformSUBCombine().
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Definition at line 12368 of file ARMISelLowering.cpp.
References combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.
Referenced by PerformANDCombine(), PerformORCombine(), and PerformXORCombine().
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CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
If so, combine them to a vldN-dup operation and return true.
Definition at line 16128 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), llvm::makeArrayRef(), n, N, llvm::MVT::Other, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VDUPLANE, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.
Referenced by PerformVDUPLANECombine().
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BC
is a bitcast that is about to be turned into a VMOVDRR.
When DstVT
, the destination type of BC
, is on the vector register bank and the source of bitcast, Op
, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return
The node that would replace BT
, if the combine is possible.
Definition at line 6135 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::MVT::i32, and llvm::EVT::isVector().
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Definition at line 4952 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, and llvm::ARMISD::SUBC.
Referenced by LowerADDSUBCARRY(), and LowerSETCCCARRY().
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Definition at line 4965 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDE, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), and llvm::MVT::i32.
Referenced by LowerADDSUBCARRY().
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Definition at line 10228 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::ISD::SRL, std::swap(), and llvm::MVT::Untyped.
Referenced by ReplaceCMP_SWAP_64Results().
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Emit a post-increment load operation with given size.
The instructions will be added to BB at Pos.
Definition at line 11133 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), BB, llvm::BuildMI(), llvm::Data, llvm::RegState::Define, getLdOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.
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Emit a post-increment store operation with given size.
The instructions will be added to BB at Pos.
Definition at line 11174 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), BB, llvm::BuildMI(), llvm::Data, getStOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.
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Definition at line 6589 of file ARMISelLowering.cpp.
References llvm::ARMISD::ASRL, assert(), llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::MVT::i32, llvm::MVT::i64, llvm::isOneConstant(), llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, N, llvm::ARMISD::RRX, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ARMISD::SRA_FLAG, llvm::ISD::SRL, llvm::ARMISD::SRL_FLAG, llvm::ARM_MB::ST, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 5563 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::commonAlignment(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, isFloatingPointZero(), and llvm_unreachable.
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Definition at line 6110 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::MVT::Other, llvm::ISD::READ_REGISTER, and Results.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
Definition at line 14594 of file ARMISelLowering.cpp.
References llvm::ARMISD::BFI, BitsProperlyConcatenate(), From, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), N, and ParseBFI().
Referenced by PerformBFICombine().
Definition at line 12571 of file ARMISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.
Referenced by AddCombineTo64bitMLAL().
Definition at line 15861 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, N, llvm::ISD::OR, and llvm::ARMISD::VLD1_UPD.
Referenced by CombineBaseUpdate().
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Definition at line 15354 of file ARMISelLowering.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::numbers::e, llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), i, llvm::SDValue::isUndef(), llvm::ISD::MULHS, llvm::ISD::MULHU, N, llvm::ArrayRef< T >::size(), and llvm::ARMISD::VQDMULH.
Referenced by PerformVECTOR_SHUFFLECombine().
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FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
Definition at line 2016 of file ARMISelLowering.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARMCC::VC, and llvm::ARMCC::VS.
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GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 8340 of file ARMISelLowering.cpp.
References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, LHS, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, RHS, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.
Referenced by LowerVECTOR_SHUFFLE().
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Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.
Definition at line 11600 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Kill, MRI, llvm::predOps(), and TII.
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
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Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.
These are used by later passes to generate tail predicated loops.
Definition at line 11638 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), MRI, llvm::ARMVCC::None, llvm::predOps(), llvm::ARMVCC::Then, and TII.
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 19441 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARM_AM::getShiftOpcForNode(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, int, llvm::ISD::isSEXTLoad(), llvm::ARM_AM::no_shift, RHS, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().
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Definition at line 20342 of file ARMISelLowering.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), N, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.
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Definition at line 20324 of file ARMISelLowering.cpp.
References assert(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, N, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.
Definition at line 9319 of file ARMISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.
Referenced by AddRequiredExtensionForVMULL(), and SkipLoadExtensionForVMULL().
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Return the load opcode for a given load size.
If load size >= 8, neon opcode will be returned.
Definition at line 11095 of file ARMISelLowering.cpp.
Referenced by emitPostLd().
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Definition at line 19525 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), int, RHS, llvm::ISD::SUB, llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::MVT::v8i8.
Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().
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Definition at line 15839 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::ISD::OR, and llvm::ARMISD::VLD1_UPD.
Referenced by CombineBaseUpdate().
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Return the store opcode for a given store size.
If store size >= 8, neon opcode will be returned.
Definition at line 11114 of file ARMISelLowering.cpp.
Referenced by emitPostSt().
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Definition at line 19500 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), int, RHS, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().
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Definition at line 14380 of file ARMISelLowering.cpp.
References llvm_unreachable, N, llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.
Referenced by CanInvertMVEVCMP(), and PerformXORCombine().
Definition at line 8438 of file ARMISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v16i1, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::MVT::v8i1, and llvm::MVT::v8i16.
Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_i1(), LowerINSERT_VECTOR_ELT_i1(), and PromoteMVEPredVector().
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Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
Definition at line 6496 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().
Referenced by isVShiftLImm(), and isVShiftRImm().
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getZeroVector - Returns a vector of specified type with all zero elements.
Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.
Definition at line 6247 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::EVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ARMISD::VMOVIMM.
Referenced by LowerCTTZ(), and LowerShift().
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hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.
If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.
Definition at line 14959 of file ARMISelLowering.cpp.
References i, llvm::ISD::isNormalLoad(), and N.
Referenced by PerformBUILD_VECTORCombine().
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IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
Definition at line 1999 of file ARMISelLowering.cpp.
References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by LowerSETCCCARRY().
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Definition at line 9436 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.
Referenced by LowerMUL().
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Definition at line 9447 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.
Referenced by LowerMUL().
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Definition at line 14701 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::ARMISD::CSINC, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::SDNode::hasOneUse(), llvm::isNullConstant(), and llvm::isOneConstant().
Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), PerformCMPZCombine(), and PerformCSETCombine().
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Definition at line 12269 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::MVT::i1, isZeroOrAllOnes(), LLVM_FALLTHROUGH, N, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by combineSelectAndUse().
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isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.
Definition at line 9247 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::numbers::e, llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), i, llvm::DataLayout::isBigEndian(), llvm::isIntN(), llvm::isUIntN(), llvm::ConstantSDNode::isZero(), N, llvm::MVT::v2i64, and llvm::MVT::v4i32.
Referenced by isSignExtended(), and isZeroExtended().
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isFloatingPointZero - Return true if this is +0.0.
Definition at line 4654 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::HexagonISD::CP, llvm::MVT::f64, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), llvm::isNullConstant(), llvm::ARMISD::VMOVIMM, and llvm::ARMISD::Wrapper.
Referenced by bitcastf32Toi32(), canChangeToInt(), and expandf64Toi32().
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Definition at line 5212 of file ARMISelLowering.cpp.
References llvm::ISD::SETGE, and llvm::ISD::SETGT.
Referenced by isLowerSaturate(), and LowerSaturatingConditional().
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Definition at line 21583 of file ARMISelLowering.cpp.
References llvm::sampleprof::Base, HA_DOUBLE, HA_FLOAT, HA_UNKNOWN, HA_VECT128, HA_VECT64, i, llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), and llvm::ARM_MB::ST.
Referenced by llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters().
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isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.
Definition at line 19234 of file ARMISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::isUInt< 8 >(), and llvm::MVT::SimpleTy.
Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().
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Definition at line 8272 of file ARMISelLowering.cpp.
References OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, and OP_VREV.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
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Definition at line 19154 of file ARMISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, and llvm::MVT::SimpleTy.
Referenced by isLegalAddressImmediate().
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Definition at line 19180 of file ARMISelLowering.cpp.
References llvm::MVT::f16, llvm::MVT::f32, llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::isUInt< 8 >(), llvm::EVT::isVector(), llvm::max(), and llvm::MVT::SimpleTy.
Referenced by isLegalAddressImmediate().
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Definition at line 5226 of file ARMISelLowering.cpp.
References llvm::tgtok::FalseVal, isGTorGE(), isLTorLE(), LHS, RHS, and llvm::tgtok::TrueVal.
Referenced by isLowerSaturatingConditional().
Definition at line 5318 of file ARMISelLowering.cpp.
References llvm::tgtok::FalseVal, isLowerSaturate(), LHS, RHS, and llvm::tgtok::TrueVal.
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Definition at line 5216 of file ARMISelLowering.cpp.
References llvm::ISD::SETLE, and llvm::ISD::SETLT.
Referenced by isLowerSaturate(), and LowerSaturatingConditional().
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Check if ShuffleMask
is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
Definition at line 7443 of file ARMISelLowering.cpp.
References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
Definition at line 17725 of file ARMISelLowering.cpp.
References llvm::APInt::isPowerOf2().
Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), and llvm::ARMTargetLowering::PerformCMOVToBFICombine().
Definition at line 7742 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::MUL, N, llvm::ISD::SADDSAT, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.
Definition at line 7466 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::ShuffleVectorInst::isReverse(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ARMTargetLowering::isShuffleMaskLegal(), LowerVECTOR_SHUFFLE(), and LowerVECTOR_SHUFFLE_i1().
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Definition at line 1992 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::ComputeNumSignBits(), isSHL16(), and isSRA16().
Referenced by AddCombineTo64BitSMLAL16(), and PerformORCombineToSMULWBT().
Definition at line 1980 of file ARMISelLowering.cpp.
References llvm::ISD::SHL.
Referenced by isS16(), and PerformORCombineToSMULWBT().
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isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.
Definition at line 9300 of file ARMISelLowering.cpp.
References isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), N, and llvm::ISD::SIGN_EXTEND.
Referenced by isAddSubSExt(), and LowerMUL().
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Definition at line 7627 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getSOImmVal(), llvm::MVT::i32, N, and llvm::ARM_MB::ST.
Definition at line 7144 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, llvm::RISCVMatInt::Imm, and M.
Referenced by LowerVECTOR_SHUFFLE().
Definition at line 1972 of file ARMISelLowering.cpp.
References llvm::ISD::SRA.
Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().
Definition at line 1964 of file ARMISelLowering.cpp.
References llvm::ISD::SRL.
Referenced by PerformORCombineToSMULWBT().
Definition at line 15885 of file ARMISelLowering.cpp.
References llvm::SDNode::hasPredecessorHelper(), and N.
Referenced by CombineBaseUpdate().
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Definition at line 14363 of file ARMISelLowering.cpp.
References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LT, and llvm::ARMCC::NE.
Referenced by CanInvertMVEVCMP(), and PerformVCMPCombine().
Definition at line 7172 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, llvm::RISCVMatInt::Imm, and M.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
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isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).
If so, return the encoded value.
Definition at line 6884 of file ARMISelLowering.cpp.
References assert(), llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::RISCVMatInt::Imm, llvm::X86II::ImmMask, llvm::EVT::is128BitVector(), llvm::DataLayout::isBigEndian(), llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::MVEVMVNModImm, llvm::OtherModImm, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::VMOVModImm.
Referenced by PerformANDCombine(), and PerformORCombine().
Definition at line 7480 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, M, N, llvm::MVT::v16i8, and llvm::MVT::v8i16.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
Definition at line 7504 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), i, and M.
Referenced by llvm::ARMTargetLowering::PerformMVETruncCombine(), and PerformShuffleVMOVNCombine().
isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.
Definition at line 6517 of file ARMISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
Referenced by LowerShift(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), and PerformShiftCombine().
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isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.
Definition at line 6531 of file ARMISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
Referenced by LowerShift(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), and PerformShiftCombine().
Definition at line 7208 of file ARMISelLowering.cpp.
References M, and llvm::MVT::v8i8.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().
isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
Definition at line 7275 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, j(), M, and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 7243 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, j(), M, and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
Definition at line 7337 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), j(), M, and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 7307 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), j(), M, and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
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Definition at line 12381 of file ARMISelLowering.cpp.
References N, llvm::MVT::v2i32, llvm::ARMISD::VTRN, and llvm::ARMISD::VUZP.
Referenced by AddCombineToVPADD(), and AddCombineVUZPToVPADDL().
isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
Definition at line 7411 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), j(), M, and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 7378 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), j(), M, and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
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isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.
Definition at line 9310 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), N, and llvm::ISD::ZERO_EXTEND.
Referenced by isAddSubZExt(), and LowerMUL().
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Definition at line 12253 of file ARMISelLowering.cpp.
References llvm::isAllOnesConstant(), llvm::isNullConstant(), and N.
Referenced by combineSelectAndUse(), and isConditionalZeroOrAllOnes().
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Definition at line 10089 of file ARMISelLowering.cpp.
References llvm::ISD::isBuildVectorAllZeros(), llvm::isNullConstant(), N, and llvm::ARMISD::VMOVIMM.
Referenced by LowerMLOAD(), PerformSUBCombine(), and PerformVCMPCombine().
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Definition at line 9716 of file ARMISelLowering.cpp.
References llvm::ISD::ADDCARRY, llvm::ARMISD::ADDE, ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::ISD::MERGE_VALUES, N, llvm::ISD::SUB, and llvm::ARMISD::SUBE.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 5013 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSimpleVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isSimple(), llvm::ARMISD::QADD16b, llvm::ARMISD::QADD8b, llvm::ARMISD::QSUB16b, llvm::ARMISD::QSUB8b, llvm::ISD::SADDSAT, llvm::MVT::SimpleTy, llvm::ISD::SSUBSAT, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, llvm::ARMISD::UQADD16b, llvm::ARMISD::UQADD8b, llvm::ARMISD::UQSUB16b, llvm::ARMISD::UQSUB8b, and llvm::ISD::USUBSAT.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 4189 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isMClass(), llvm::ARMISD::MEMBARRIER_MCR, llvm::MVT::Other, llvm::Release, llvm::SyncScope::SingleThread, and llvm::ARM_MB::SY.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 10195 of file ARMISelLowering.cpp.
References llvm::isStrongerThanMonotonic().
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 7644 of file ARMISelLowering.cpp.
References llvm::all_of(), assert(), llvm::sampleprof::Base, llvm::MipsISD::Ext, false, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), i, llvm::MVT::i1, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), llvm::ARMISD::PREDICATE_CAST, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ARM_MB::ST.
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Definition at line 7707 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), I, llvm::MVT::i32, N, llvm::ARM_MB::ST, and llvm::ARMISD::VIDUP.
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Definition at line 7585 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), i, llvm::MVT::i32, llvm::ARM_MB::ST, llvm::MVT::v4f32, llvm::MVT::v8f16, and llvm::ARMISD::VCVTL.
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Definition at line 7532 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), i, llvm::MVT::i32, llvm::ARM_MB::ST, llvm::MVT::v4f32, llvm::MVT::v8f16, and llvm::ARMISD::VCVTN.
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Definition at line 9056 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::MVT::f64, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), LowerCONCAT_VECTORS_i1(), llvm::ARM_MB::ST, and llvm::MVT::v2f64.
Referenced by llvm::ARMTargetLowering::LowerOperation(), LowerSDIV(), and LowerUDIV().
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Definition at line 8983 of file ARMISelLowering.cpp.
References assert(), llvm::numbers::e, E, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), i, I, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::isPowerOf2_32(), j(), llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::SmallVectorImpl< T >::resize(), llvm::ARM_MB::ST, llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by LowerCONCAT_VECTORS().
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Definition at line 6460 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), N, llvm::ARM_MB::ST, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i8.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 6404 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITREVERSE, llvm::tgtok::Bits, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isVector(), N, llvm::ARM_MB::ST, llvm::ISD::SUB, llvm::ARMISD::VMOVIMM, and X.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9081 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), i, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, j(), llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::ARM_MB::ST, llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::ARMISD::VCMPZ.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8962 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::i32, LowerEXTRACT_VECTOR_ELT_i1(), llvm::ARM_MB::ST, and llvm::ARMISD::VGETLANEu.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8944 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getVectorTyFromPredicateVector(), llvm::MVT::i32, llvm::ARMISD::PREDICATE_CAST, Shift, llvm::ISD::SRL, and llvm::ARM_MB::ST.
Referenced by LowerEXTRACT_VECTOR_ELT().
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Definition at line 5870 of file ARMISelLowering.cpp.
References DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMIN, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8f16, and llvm::MVT::v8i16.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 8881 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::BFI, llvm::AMDGPUISD::BFI, llvm::MipsISD::Ext, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getValueType(), getVectorTyFromPredicateVector(), llvm::MVT::i1, llvm::MVT::i32, llvm::BitmaskEnumDetail::Mask(), llvm::ARMISD::PREDICATE_CAST, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ARM_MB::ST.
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Definition at line 3094 of file ARMISelLowering.cpp.
References DL, F, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::SmallVectorImpl< T >::insert(), llvm::ARMISD::INTRET_FLAG, llvm::MVT::Other, and llvm::report_fatal_error().
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Definition at line 10095 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::MVT::i32, llvm::SDValue::isUndef(), isZeroVector(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9458 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), SkipExtensionForVMULL(), std::swap(), llvm::MVT::v2i64, llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9962 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ARM_MB::LD, llvm::SPII::Load, llvm::ISD::NON_EXTLOAD, llvm::ARMISD::PREDICATE_CAST, llvm::ISD::SRL, llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 10019 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), I, llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ARMISD::PREDICATE_CAST, llvm::ISD::SRL, llvm::ARM_MB::ST, llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.
Referenced by LowerSTORE().
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Definition at line 4226 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::MVT::Other, and llvm::ARMISD::PRELOAD.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8419 of file ARMISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), i, llvm::MVT::v16i8, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::ARMISD::VREV64.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 5252 of file ARMISelLowering.cpp.
References llvm::countTrailingOnes(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), isGTorGE(), isLTorLE(), llvm::isPowerOf2_64(), llvm::max(), llvm::min(), llvm::ISD::SELECT_CC, llvm::ARMISD::SSAT, llvm::ARMISD::USAT, and llvm::NVPTX::PTXLdStInstCode::V2.
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Definition at line 9603 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, llvm::ARM_MB::ST, llvm::ISD::TRUNCATE, llvm::MVT::v4i16, llvm::MVT::v8i16, and llvm::MVT::v8i8.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9564 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.
Referenced by LowerSDIV(), and LowerUDIV().
Definition at line 9533 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, X, and Y.
Referenced by LowerSDIV().
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Definition at line 6851 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::CMOV, Cond, ConvertBooleanCarryToCarryFlag(), DL, get, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, IntCCToARMCC(), LHS, RHS, llvm::ISD::SUB, and llvm::ARMISD::SUBE.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 6546 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::MVT::i32, llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHLs, llvm::ARMISD::VSHLu, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 10057 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isLittleEndian(), llvm::ARMSubtarget::isThumb1Only(), LowerPredicateStore(), N, llvm::MVT::Other, llvm::ARM_MB::ST, llvm::ARMISD::STRD, llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9151 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::MVT::i1, LowerTruncatei1(), llvm::ARMISD::MVETRUNC, N, llvm::SelectionDAG::SplitVectorOperand(), llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::MVT::v8i32.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 9135 of file ARMISelLowering.cpp.
References llvm::And, llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, llvm::ISD::SETNE, llvm::ARM_MB::ST, llvm::MVT::v16i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.
Referenced by LowerTruncate().
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Definition at line 9639 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), llvm::ISD::SINT_TO_FP, llvm::ARM_MB::ST, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 4253 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ARMFunctionInfo::getVarArgsFrameIndex().
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 10122 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::MUL, llvm::ISD::OR, llvm::ARM_MB::ST, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_XOR, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ISD::XOR.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and LowerVecReduceF().
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Definition at line 10188 of file ARMISelLowering.cpp.
References LowerVecReduce(), and llvm::ARM_MB::ST.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8672 of file ARMISelLowering.cpp.
References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::numbers::e, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), i, llvm::MVT::i32, llvm::RISCVMatInt::Imm, int, isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SDValue::isUndef(), isVEXTMask(), isVMOVNMask(), llvm::isVREVMask(), LowerReverse_VECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), PerfectShuffleTable, llvm::ISD::SCALAR_TO_VECTOR, llvm::ARM_MB::ST, std::swap(), llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VMOVN, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ARMISD::VREV64.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8488 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::i32, isReverseMask(), llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::ISD::SRL, srl, llvm::ARM_MB::ST, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 8535 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), i, llvm::MVT::i32, llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v8f16, and llvm::MVT::v8i16.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 8621 of file ARMISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), i, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::BitmaskEnumDetail::Mask(), and llvm::NVPTX::PTXLdStInstCode::V2.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 8399 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), I, llvm::MVT::i32, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8i8, llvm::ARMISD::VTBL1, and llvm::ARMISD::VTBL2.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 9211 of file ARMISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::MipsISD::Ext, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i8, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, llvm::ISD::SIGN_EXTEND, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::MVT::v8i32.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 5801 of file ARMISelLowering.cpp.
References llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::TRUNCATE, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, and llvm::MVT::v8i16.
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Definition at line 5907 of file ARMISelLowering.cpp.
References assert(), llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::ISD::ZERO_EXTEND.
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Definition at line 6671 of file ARMISelLowering.cpp.
References llvm::ARMCC::AL, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), llvm::ARMCC::LE, LLVM_FALLTHROUGH, llvm_unreachable, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARM_MB::ST, std::swap(), llvm::ARMISD::VCMP, llvm::ARMISD::VCMPZ, llvm::ARMISD::VREV64, and llvm::ARMISD::VTST.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 3388 of file ARMISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::Other, and llvm::ISD::WRITE_REGISTER.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.
Definition at line 2903 of file ARMISelLowering.cpp.
References Arg, assert(), llvm::ISD::CopyFromReg, llvm::tgtok::Def, llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::Register::isVirtualRegister(), llvm::max(), MRI, and TII.
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Definition at line 11086 of file ARMISelLowering.cpp.
References llvm_unreachable, MBB, S, and llvm::MachineBasicBlock::successors().
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
Definition at line 14565 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::BFI, llvm::APInt::countPopulation(), From, llvm::APInt::getBitWidth(), llvm::APInt::getLowBitsSet(), N, Shift, and llvm::ISD::SRL.
Referenced by FindBFIToCombineWith(), and PerformBFICombine().
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Definition at line 13276 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::expandABS(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::isOperationLegal(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
Definition at line 13745 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, N, PerformADDCombineWithOperands(), PerformADDVecReduce(), and PerformSHLSimplify().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.
This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.
Definition at line 13308 of file ARMISelLowering.cpp.
References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.
Referenced by PerformADDCombine().
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Definition at line 12898 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::isNullConstant(), llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), LHS, llvm::min(), N, RHS, and llvm::ARMISD::SUBC.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.
Definition at line 13291 of file ARMISelLowering.cpp.
References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), N, and PerformAddeSubeCombine().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 12931 of file ARMISelLowering.cpp.
References AddCombineTo64bitMLAL(), llvm::ARMISD::ADDE, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb1Only(), N, RHS, llvm::ISD::SMUL_LOHI, and llvm::ARMISD::SUBE.
Referenced by PerformADDECombine(), and llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13474 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BUILD_PAIR, E, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), I, llvm::MVT::i32, llvm::MVT::i64, M, N, S, TryDistrubutionADDVecReduce(), llvm::ARMISD::VADDLVAps, llvm::ARMISD::VADDLVApu, llvm::ARMISD::VADDLVAs, llvm::ARMISD::VADDLVAu, llvm::ARMISD::VADDLVps, llvm::ARMISD::VADDLVpu, llvm::ARMISD::VADDLVs, llvm::ARMISD::VADDLVu, llvm::ARMISD::VMLALVAps, llvm::ARMISD::VMLALVApu, llvm::ARMISD::VMLALVAs, llvm::ARMISD::VMLALVAu, llvm::ARMISD::VMLALVps, llvm::ARMISD::VMLALVpu, llvm::ARMISD::VMLALVs, and llvm::ARMISD::VMLALVu.
Referenced by PerformADDCombine().
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Definition at line 14127 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, CombineANDShift(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformSHLSimplify(), llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v8i1, and llvm::ARMISD::VBICIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
Definition at line 15004 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14625 of file ARMISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::ARMISD::BFI, llvm::countLeadingZeros(), llvm::APInt::countLeadingZeros(), llvm::countTrailingZeros(), llvm::APInt::countTrailingZeros(), FindBFIToCombineWith(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::BitmaskEnumDetail::Mask(), N, ParseBFI(), and llvm::ISD::SRL.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 18227 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::DataLayout::isBigEndian(), N, PerformExtractEltToVMOVRRD(), llvm::ARM_MB::ST, llvm::ARMISD::VDUP, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMOVFPIMM, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.
Definition at line 14971 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), i, llvm::MVT::i64, N, and PerformVMOVDRRCombine().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14734 of file ARMISelLowering.cpp.
References Cond, llvm::ARMCC::EQ, IsCMPZCSINC(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14747 of file ARMISelLowering.cpp.
References Cond, llvm::ARMCC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMCC::getOppositeCondition(), llvm::MVT::i32, IsCMPZCSINC(), N, and llvm::ARMCC::NE.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
Definition at line 17524 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, N, PerformSplittingToWideningLoad(), llvm::ISD::SIGN_EXTEND, llvm::ARM_MB::ST, llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15276 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm::ARMISD::MVETRUNC, N, PerformExtractEltToVMOVRRD(), llvm::ARM_MB::ST, llvm::MVT::v2f64, llvm::MVT::v4i32, llvm::ARMISD::VDUP, llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVhr, llvm::ARMISD::VMOVrh, and X.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15215 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MipsISD::Ext, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::find_if(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SDNode::use_begin(), llvm::SDNode::use_size(), llvm::SDNode::uses(), llvm::MVT::v2f64, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVRRD.
Referenced by PerformBITCASTCombine(), and PerformExtractEltCombine().
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Definition at line 16524 of file ARMISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNodeIfExists(), llvm::SDNode::getOpcode(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), llvm::SPII::Store, and llvm::ARMISD::VGETLANEu.
Referenced by PerformSTORECombine().
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Definition at line 16695 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, DL, llvm::FAdd, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNodeFlags::hasNoSignedZeros(), N, std::swap(), llvm::MVT::v4f32, llvm::MVT::v8f16, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17567 of file ARMISelLowering.cpp.
References N, PerformSplittingToWideningLoad(), and llvm::ARM_MB::ST.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17866 of file ARMISelLowering.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::ISD::BR, llvm::ISD::BR_CC, llvm::ISD::BRCOND, Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::RISCVMatInt::Imm, llvm::ARMISD::LE, llvm::ARMISD::LOOP_DEC, N, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), SearchLoopIntrinsic(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::TokenFactor, llvm::ARMISD::WLS, and llvm::ARMISD::WLSSETUP.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.
Definition at line 15186 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isNormalLoad(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15397 of file ARMISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16288 of file ARMISelLowering.cpp.
References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17110 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, Merge, N, and llvm::SelectionDAG::ReplaceAllUsesWith().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.
Definition at line 17619 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::LegacyLegalizeActions::Bitcast, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::MVT::i32, llvm::ISD::isConstantSplatVector(), N, PerformMinMaxToSatCombine(), PerformVQDMULHCombine(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ARM_MB::ST, std::swap(), llvm::ISD::UMIN, llvm::MVT::v16i8, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VQMOVNs, and llvm::ARMISD::VQMOVNu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17578 of file ARMISelLowering.cpp.
References llvm::APInt::countTrailingOnes(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb2(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ARMISD::SSAT, std::swap(), and llvm::ARMISD::USAT.
Referenced by PerformMinMaxCombine().
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Definition at line 13937 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isPowerOf2_32(), llvm::ARMSubtarget::isThumb1Only(), llvm::Log2_32(), N, PerformMVEVMULLCombine(), PerformVMULCombine(), llvm::ISD::SHL, llvm::ISD::SUB, and llvm::MVT::v2i64.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16002 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasPredecessorHelper(), i, llvm::MVT::i32, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm_unreachable, llvm::makeArrayRef(), n, N, llvm::MVT::Other, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VST2_UPD, and llvm::ARMISD::VST4_UPD.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13872 of file ARMISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isAllOnesConstant(), llvm::ARMSubtarget::isLittle(), llvm::isNullConstant(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.
Referenced by PerformMULCombine().
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PerformORCombine - Target-specific dag combine xforms for ISD::OR.
Definition at line 14420 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), PerformSHLSimplify(), llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v2i32, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::MVT::v8i1, llvm::ARMISD::VBSP, and llvm::ARMISD::VORRIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14394 of file ARMISelLowering.cpp.
References llvm::And, llvm::ISD::AND, CanInvertMVEVCMP(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), N, llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.
Referenced by PerformORCombine().
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Definition at line 14237 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ARMISD::BFI, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::countTrailingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ARM::isBitFieldInvertedMask(), llvm::ARMSubtarget::isThumb1Only(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by PerformORCombine().
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Definition at line 14177 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::i32, isS16(), isSHL16(), isSRA16(), isSRL16(), llvm::ISD::OR, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SHL, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SMULWB, llvm::ARMISD::SMULWT, and llvm::ISD::SRL.
Referenced by PerformORCombine().
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Definition at line 15095 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i32, llvm::isBitwiseNot(), N, llvm::ARMISD::PREDICATE_CAST, llvm::TargetLowering::SimplifyDemandedBits(), X, and llvm::ISD::XOR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 12959 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::tgtok::FalseVal, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::i32, LHS, N, Reduction, RHS, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULT, std::swap(), llvm::tgtok::TrueVal, llvm::ISD::TRUNCATE, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ARMISD::VMAXVs, llvm::ARMISD::VMAXVu, llvm::ARMISD::VMINVs, and llvm::ARMISD::VMINVu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.
As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.
Definition at line 17366 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::countLeadingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARM_MB::ST, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13640 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ARMISD::CMP, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), llvm::SDValue::dump(), llvm::dump(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MVT::i32, llvm::RISCVMatInt::Imm, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LLVM_DEBUG, llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ARM_MB::ST, llvm::ISD::SUB, X, and llvm::ISD::XOR.
Referenced by PerformADDCombine(), PerformANDCombine(), PerformORCombine(), and PerformXORCombine().
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Definition at line 15438 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, isVMOVNTruncMask(), llvm::ARMISD::MVETRUNC, N, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVN.
Referenced by PerformVECTOR_SHUFFLECombine().
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Definition at line 15337 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), N, llvm::ARMISD::VGETLANEs, and llvm::ARMISD::VGETLANEu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 18367 of file ARMISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTLOAD, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), i, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isVector(), llvm::ARM_MB::LD, llvm::ARMISD::MVESEXT, N, llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.
Referenced by llvm::ARMTargetLowering::PerformMVEExtCombine().
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Definition at line 16482 of file ARMISelLowering.cpp.
References DL, llvm::TypeSize::Fixed(), llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), i, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), llvm::ARMISD::MVETRUNC, llvm::MVT::Other, llvm::SPII::Store, and llvm::ISD::TokenFactor.
Referenced by PerformSTORECombine().
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Definition at line 16389 of file ARMISelLowering.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::f16, llvm::MVT::f32, llvm::TypeSize::Fixed(), llvm::ISD::FP_ROUND, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), i, I, llvm::MVT::i32, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), M, llvm::MVT::Other, llvm::SPII::Store, llvm::ISD::TokenFactor, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::ARMISD::VCVTN, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by PerformSTORECombine().
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Definition at line 17443 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::MVT::f16, llvm::MVT::f32, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDValue::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), i, llvm::MVT::i32, llvm::MVT::i8, llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ARM_MB::LD, llvm::ISD::LOAD, N, llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, llvm::MVT::v4f32, llvm::MVT::v8f16, llvm::ARMISD::VCVTL, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ISD::ZEXTLOAD.
Referenced by PerformExtendCombine(), and PerformFPExtendCombine().
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PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.
Definition at line 16558 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, PerformExtractFpToIntStores(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformTruncatingStoreCombine(), llvm::SPII::Store, and llvm::ARMISD::VMOVDRR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
Definition at line 13788 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, combineSelectAndUse(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, isZeroVector(), N, PerformSubCSINCCombine(), llvm::ISD::SUB, llvm::ARMISD::VDUP, and llvm::ARMISD::VMOVIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13768 of file ARMISelLowering.cpp.
References llvm::AArch64ISD::CSINC, llvm::ARMISD::CSINC, llvm::ARMISD::CSINV, llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::isNullConstant(), N, llvm::ISD::SUB, and X.
Referenced by PerformSUBCombine().
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Definition at line 16304 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, DL, E, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), i, I, llvm::MVT::i8, llvm::MVT::integer_valuetypes(), llvm::DataLayout::isBigEndian(), llvm::isPowerOf2_32(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MVT::Other, and llvm::ISD::TokenFactor.
Referenced by PerformSTORECombine().
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Definition at line 12876 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::isNullConstant(), N, and llvm::ARMISD::UMAAL.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15153 of file ARMISelLowering.cpp.
References Cond, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), getSwappedCondition(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), isValidMVECond(), isZeroVector(), N, llvm::ARMISD::VCMP, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VDUP.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3
Definition at line 16647 of file ARMISelLowering.cpp.
References llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::TRUNCATE, llvm::MVT::v2i32, and llvm::MVT::v4i32.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3
Definition at line 16747 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
Definition at line 16250 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::ARM_MB::LD, N, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::VDUP, llvm::ARMISD::VLD1DUP, and llvm::ARMISD::VMOVrh.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.
Definition at line 16207 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeVMOVModImm(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::RISCVMatInt::Imm, llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ARMISD::VDUP, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16797 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::any_of(), assert(), B, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::EVT::changeVectorElementType(), llvm::MipsISD::Ext, llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::BinaryOperator::getOpcode(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::is128BitVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::BitmaskEnumDetail::Mask(), Mul, llvm::ISD::MUL, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, llvm::ARM_MB::ST, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VECREDUCE_ADD, llvm::ARMISD::VMLALVAs, llvm::ARMISD::VMLALVAu, llvm::ARMISD::VMLALVs, llvm::ARMISD::VMLALVu, and llvm::ISD::VSELECT.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15128 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), N, llvm::ARM_MB::ST, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.
Definition at line 15463 of file ARMISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, FlattenVectorShuffle(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), n, N, and PerformShuffleVMOVNCombine().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15994 of file ARMISelLowering.cpp.
References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.
This is also used for BUILD_VECTORs with 2 operands.
Definition at line 14861 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), N, and llvm::ARMISD::VMOVRRD.
Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14877 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CopyFromReg, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::MVT::i16, llvm::SPII::Load, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::ARMISD::VMOVrh.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17054 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::isUndef(), N, llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::ARMISD::VQMOVNs, and llvm::ARMISD::VQMOVNu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14924 of file ARMISelLowering.cpp.
References llvm::APFloat::bitcastToAPInt(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::ISD::isNormalLoad(), llvm::SPII::Load, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::VGETLANEu, and llvm::ISD::ZEXTLOAD.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
Definition at line 14769 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::commonAlignment(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::ISD::FrameIndex, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::DataLayout::isBigEndian(), llvm::ARMSubtarget::isLittle(), llvm::ISD::isNormalLoad(), llvm::ARM_MB::LD, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), std::swap(), llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVDRR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.
vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2
Definition at line 13841 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().
Referenced by PerformMULCombine().
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Definition at line 13070 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::BinaryOperator::getOpcode(), llvm::User::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), I, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::isConstOrConstSplat(), llvm::EVT::isPow2VectorType(), llvm::EVT::isVector(), Mul, llvm::ISD::MUL, N, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::TRUNCATE, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VQDMULH, and llvm::ISD::VSELECT.
Referenced by PerformMinMaxCombine(), and PerformVSELECTCombine().
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Definition at line 17094 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), N, and llvm::TargetLowering::SimplifyDemandedVectorElts().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13178 of file ARMISelLowering.cpp.
References Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::isConstOrConstSplat(), LHS, N, PerformVQDMULHCombine(), RHS, llvm::ISD::VSELECT, and llvm::ISD::XOR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13218 of file ARMISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, llvm::ISD::SETUGE, llvm::ISD::SETULT, and std::swap().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14520 of file ARMISelLowering.cpp.
References CanInvertMVEVCMP(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::ARMSubtarget::getTargetLowering(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), getVCMPCondCode(), llvm::MVT::i32, llvm::TargetLowering::isConstTrueVal(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), N, PerformSHLSimplify(), llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 8453 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), getVectorTyFromPredicateVector(), llvm::MVT::i32, llvm::ARMISD::PREDICATE_CAST, llvm::MVT::v16i1, llvm::MVT::v16i8, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.
Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), and LowerVECTOR_SHUFFLE_i1().
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Definition at line 3744 of file ARMISelLowering.cpp.
References Align, allUsersAreInFunction(), ConstpoolPromotionMaxSize, ConstpoolPromotionMaxTotal, copy, llvm::ARMConstantPoolConstant::Create(), EnableConstpoolPromotion, llvm::TargetOptions::EnableFastISel, F, llvm::ConstantDataArray::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPreferredAlign(), llvm::ARMFunctionInfo::getPromotedConstpoolIncrease(), llvm::ARMTargetLowering::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstantPool(), llvm::DataLayout::getTypeAllocSize(), llvm::MVT::i32, llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMFunctionInfo::markGlobalAsPromotedToConstantPool(), llvm::TargetMachine::Options, S, llvm::ARMFunctionInfo::setPromotedConstpoolIncrease(), and llvm::ARMISD::Wrapper.
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Definition at line 10246 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_PAIR, createGPRPairNode(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, isBigEndian(), llvm::DataLayout::isBigEndian(), N, llvm::MVT::Other, Results, llvm::SelectionDAG::setNodeMemRefs(), and llvm::MVT::Untyped.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 10447 of file ARMISelLowering.cpp.
References llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, N, Results, llvm::ARMISD::SMLALD, llvm::ARMISD::SMLALDX, llvm::ARMISD::SMLSLD, and llvm::ARMISD::SMLSLDX.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 10205 of file ARMISelLowering.cpp.
References llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, N, llvm::MVT::Other, and Results.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 17829 of file ARMISelLowering.cpp.
References llvm::RISCVMatInt::Imm, llvm::ISD::INTRINSIC_W_CHAIN, N, llvm::ISD::SETCC, and llvm::ISD::XOR.
Referenced by PerformHWLoopCombine().
Definition at line 7215 of file ARMISelLowering.cpp.
References llvm::BitmaskEnumDetail::Mask().
Referenced by isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), and isVZIPMask().
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SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.
The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.
Definition at line 9385 of file ARMISelLowering.cpp.
References AddRequiredExtensionForVMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), i, llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), llvm::ARM_MB::LD, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::MVT::v2i32, llvm::MVT::v4i32, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().
Referenced by LowerMUL().
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SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.
If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.
Definition at line 9361 of file ARMISelLowering.cpp.
References getExtensionTo64Bits(), llvm::SelectionDAG::getExtLoad(), llvm::SelectionDAG::getLoad(), and llvm::ARM_MB::LD.
Referenced by SkipExtensionForVMULL().
STATISTIC | ( | NumConstpoolPromoted | , |
"Number of constants with their storage promoted into constant pools" | |||
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Definition at line 15536 of file ARMISelLowering.cpp.
References Align, assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MemSDNode::getAlign(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), i, llvm::MVT::i32, llvm_unreachable, llvm::ISD::LOAD, llvm::makeArrayRef(), n, N, llvm::MVT::Other, llvm::ISD::STORE, llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD1x2_UPD, llvm::ARMISD::VLD1x3_UPD, llvm::ARMISD::VLD1x4_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST1x2_UPD, llvm::ARMISD::VST1x3_UPD, llvm::ARMISD::VST1x4_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, and llvm::ARMISD::VST4LN_UPD.
Referenced by CombineBaseUpdate().
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Definition at line 13329 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::MemSDNode::getChain(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::PatternMatch::match(), llvm::ISD::MUL, N, llvm::ARMISD::VADDVs, llvm::ARMISD::VADDVu, llvm::ISD::VECREDUCE_ADD, llvm::ARMISD::VMLAVs, llvm::ARMISD::VMLAVu, and X.
Referenced by PerformADDVecReduce().
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Definition at line 9927 of file ARMISelLowering.cpp.
References DL, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, N, llvm::ISD::OR, llvm::MVT::Other, and llvm::ARMISD::WIN__DBZCHK.
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Referenced by promoteToConstantPool().
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Referenced by promoteToConstantPool().
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Referenced by promoteToConstantPool().
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Definition at line 154 of file ARMISelLowering.cpp.
Referenced by f64AssignAAPCS().
cl::opt<unsigned> MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2)) |
Referenced by canTailPredicateLoop(), and llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().