#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <string>
#include <tuple>
#include <utility>
#include <vector>

Macros
#define	DEBUG_TYPE "arm-isel"

Typedefs
using	RCPair = std::pair< unsigned, const TargetRegisterClass * >

Enumerations
enum	ShuffleOpCodes { OP_COPY = 0, OP_VREV, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, OP_VTRNL, OP_VTRNR }

enum	HABaseType { HA_UNKNOWN = 0, HA_FLOAT, HA_DOUBLE, HA_VECT64, HA_VECT128 }

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")

	STATISTIC (NumMovwMovt, "Number of GAs materialized with movw + movt")

	STATISTIC (NumLoopByVals, "Number of loops generated for byval arguments")

	STATISTIC (NumConstpoolPromoted, "Number of constants with their storage promoted into constant pools")

static bool	isSRL16 (const SDValue &Op)

static bool	isSRA16 (const SDValue &Op)

static bool	isSHL16 (const SDValue &Op)

static bool	isS16 (const SDValue &Op, SelectionDAG &DAG)

static ARMCC::CondCodes	IntCCToARMCC (ISD::CondCode CC)
	IntCCToARMCC - Convert a DAG integer condition code to an ARM CC. More...

static void	FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN)
	FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. More...

static bool	MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo MRI, const TargetInstrInfo TII)
	MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack. More...

static SDValue	LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)

static SDValue	LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG)

static bool	allUsersAreInFunction (const Value V, const Function F)
	Return true if all users of V are within function F, looking through ConstantExprs. More...

static SDValue	promoteToConstantPool (const ARMTargetLowering TLI, const GlobalValue GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl)

static SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)

static SDValue	LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)

static SDValue	LowerVASTART (SDValue Op, SelectionDAG &DAG)

static bool	isFloatingPointZero (SDValue Op)
	isFloatingPointZero - Return true if this is +0.0. More...

static SDValue	ConvertBooleanCarryToCarryFlag (SDValue BoolCarry, SelectionDAG &DAG)

static SDValue	ConvertCarryFlagToBooleanCarry (SDValue Flags, EVT VT, SelectionDAG &DAG)

static void	checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)

static bool	isGTorGE (ISD::CondCode CC)

static bool	isLTorLE (ISD::CondCode CC)

static bool	isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)

static bool	isUpperSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)

static bool	isSaturatingConditional (const SDValue &Op, SDValue &V, uint64_t &K, bool &usat)

static bool	isLowerSaturatingConditional (const SDValue &Op, SDValue &V, SDValue &SatK)

static bool	canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
	canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence. More...

static SDValue	bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)

static void	expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)

static SDValue	LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)

static void	ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)

static SDValue	CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG)
	`BC` is a bitcast that is about to be turned into a VMOVDRR. More...

static SDValue	ExpandBITCAST (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
	ExpandBITCAST - If the target supports VFP, this function is called to expand a bit convert where either the source or destination type is i64 to use a VMOVDRR or VMOVRRD node. More...

static SDValue	getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	getZeroVector - Returns a vector of specified type with all zero elements. More...

static SDValue	LowerCTTZ (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)

static SDValue	LowerCTPOP (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)

static bool	getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
	Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More...

static bool	isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
	isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More...

static bool	isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
	isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More...

static SDValue	LowerShift (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)

static SDValue	Expand64BitShift (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)

static SDValue	LowerVSETCC (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerSETCCCARRY (SDValue Op, SelectionDAG &DAG)

static SDValue	isNEONModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, bool is128Bits, NEONModImmType type)
	isNEONModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV). More...

static bool	isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)

static bool	isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)

static bool	isVREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize)
	isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize. More...

static bool	isVTBLMask (ArrayRef< int > M, EVT VT)

static unsigned	SelectPairHalf (unsigned Elements, ArrayRef< int > Mask, unsigned Index)

static bool	isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)

static bool	isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...

static bool	isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)

static bool	isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...

static bool	isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)

static bool	isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...

static unsigned	isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF)
	Check if `ShuffleMask` is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't. More...

static bool	isReverseMask (ArrayRef< int > M, EVT VT)

static SDValue	IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl)

static bool	isLegalMVEShuffleOp (unsigned PFEntry)

static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...

static SDValue	LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)

static SDValue	LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue	LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG)

static bool	isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
	isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size. More...

static bool	isSignExtended (SDNode *N, SelectionDAG &DAG)
	isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements. More...

static bool	isZeroExtended (SDNode *N, SelectionDAG &DAG)
	isZeroExtended - Check if a node is a vector value that is zero-extended or a constant BUILD_VECTOR with zero-extended elements. More...

static EVT	getExtensionTo64Bits (const EVT &OrigVT)

static SDValue	AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
	AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits. More...

static SDValue	SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
	SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension. More...

static SDValue	SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
	SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value. More...

static bool	isAddSubSExt (SDNode *N, SelectionDAG &DAG)

static bool	isAddSubZExt (SDNode *N, SelectionDAG &DAG)

static SDValue	LowerMUL (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG)

static SDValue	LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG)

static SDValue	LowerSDIV (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerUDIV (SDValue Op, SelectionDAG &DAG)

static SDValue	LowerADDSUBCARRY (SDValue Op, SelectionDAG &DAG)

static SDValue	WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain)

static SDValue	LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)

static void	ReplaceREADCYCLECOUNTER (SDNode N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget Subtarget)

static SDValue	createGPRPairNode (SelectionDAG &DAG, SDValue V)

static void	ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)

static SDValue	LowerFPOWI (SDValue Op, const ARMSubtarget &Subtarget, SelectionDAG &DAG)

static void	ReplaceLongIntrinsic (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)

static MachineBasicBlock *	OtherSucc (MachineBasicBlock MBB, MachineBasicBlock Succ)

static unsigned	getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
	Return the load opcode for a given load size. More...

static unsigned	getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
	Return the store opcode for a given store size. More...

static void	emitPostLd (MachineBasicBlock BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment load operation with given size. More...

static void	emitPostSt (MachineBasicBlock BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment store operation with given size. More...

static bool	checkAndUpdateCPSRKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock BB, const TargetRegisterInfo TRI)

static void	attachMEMCPYScratchRegs (const ARMSubtarget Subtarget, MachineInstr &MI, const SDNode Node)
	Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM. More...

static bool	isZeroOrAllOnes (SDValue N, bool AllOnes)

static bool	isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)

static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)

static SDValue	combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)

static bool	IsVUZPShuffleNode (SDNode *N)

static SDValue	AddCombineToVPADD (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	AddCombineVUZPToVPADDL (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	AddCombineBUILD_VECTORToVPADDL (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	findMUL_LOHI (SDValue V)

static SDValue	AddCombineTo64BitSMLAL16 (SDNode AddcNode, SDNode AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)

static SDValue	AddCombineTo64bitMLAL (SDNode AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	AddCombineTo64bitUMAAL (SDNode AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformUMLALCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)

static SDValue	PerformAddcSubcCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformAddeSubeCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformABSCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformADDECombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL. More...

static SDValue	PerformADDCombineWithOperands (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1. More...

static SDValue	PerformSHLSimplify (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)

static SDValue	PerformADDCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. More...

static SDValue	PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. More...

static SDValue	PerformVMULCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding. More...

static SDValue	PerformMULCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	CombineANDShift (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformANDCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformORCombineToSMULWBT (SDNode OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformORCombineToBFI (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	PerformORCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformORCombine - Target-specific dag combine xforms for ISD::OR. More...

static SDValue	PerformXORCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)

static SDValue	ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask)

static bool	BitsProperlyConcatenate (const APInt &A, const APInt &B)

static SDValue	FindBFIToCombineWith (SDNode *N)

static SDValue	PerformBFICombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)

static SDValue	PerformVMOVRRDCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD. More...

static SDValue	PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
	PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR. More...

static bool	hasNormalLoadOperand (SDNode *N)
	hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads. More...

static SDValue	PerformBUILD_VECTORCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR. More...

static SDValue	PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	Target-specific dag combine xforms for ARMISD::BUILD_VECTOR. More...

static SDValue	PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT. More...

static SDValue	PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
	PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE. More...

static SDValue	CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates. More...

static SDValue	PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)

static bool	CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs. More...

static SDValue	PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE. More...

static SDValue	PerformVDUPCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP. More...

static SDValue	PerformLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)

static SDValue	PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE. More...

static SDValue	PerformVCVTCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
	PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2. More...

static SDValue	PerformVDIVCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
	PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2. More...

static SDValue	PerformIntrinsicCombine (SDNode *N, SelectionDAG &DAG)
	PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. More...

static SDValue	PerformShiftCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)
	PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them. More...

static SDValue	PerformExtendCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
	PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. More...

static const APInt *	isPowerOf2Constant (SDValue V)

static SDValue	PerformHWLoopCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)

static bool	memOpAlign (unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)

static bool	areExtractExts (Value Ext1, Value Ext2)
	Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements. More...

static bool	isLegalT1AddressImmediate (int64_t V, EVT VT)

static bool	isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)

static bool	isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
	isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type. More...

static bool	getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)

static bool	getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)

static RTLIB::Libcall	getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT)

static TargetLowering::ArgListTy	getDivRemArgList (const SDNode N, LLVMContext Context, const ARMSubtarget *Subtarget)

static bool	isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members)

Variables
static cl::opt< bool >	ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))

static cl::opt< bool >	EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))

static cl::opt< unsigned >	ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))

static cl::opt< unsigned >	ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))

static const MCPhysReg	GPRArgRegs []

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-isel"

Definition at line 118 of file ARMISelLowering.cpp.

Typedef Documentation

◆ RCPair

using RCPair = std::pair<unsigned, const TargetRegisterClass *>

Definition at line 14430 of file ARMISelLowering.cpp.

Enumeration Type Documentation

◆ HABaseType

enum HABaseType

Enumerator
HA_UNKNOWN
HA_FLOAT
HA_DOUBLE
HA_VECT64
HA_VECT128

Definition at line 15735 of file ARMISelLowering.cpp.

◆ ShuffleOpCodes

enum ShuffleOpCodes

Enumerator
OP_COPY
OP_VREV
OP_VDUP0
OP_VDUP1
OP_VDUP2
OP_VDUP3
OP_VEXT1
OP_VEXT2
OP_VEXT3
OP_VUZPL
OP_VUZPR
OP_VZIPL
OP_VZIPR
OP_VTRNL
OP_VTRNR

Definition at line 7108 of file ARMISelLowering.cpp.

Function Documentation

◆ AddCombineBUILD_VECTORToVPADDL()

static SDValue AddCombineBUILD_VECTORToVPADDL	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10265 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.

Referenced by PerformADDCombineWithOperands().

◆ AddCombineTo64bitMLAL()

static SDValue AddCombineTo64bitMLAL	(	SDNode *	AddeSubeNode,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10449 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, AddCombineTo64BitSMLAL16(), llvm::ARMISD::ADDE, assert(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasAnyUseOfValue(), llvm::ARMSubtarget::hasDSP(), llvm::ARMSubtarget::hasV6Ops(), llvm::MVT::i32, llvm::SDNode::isPredecessorOf(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::SMLAL, llvm::ARMISD::SMMLAR, llvm::ARMISD::SMMLSR, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::ARMISD::UMLAL, llvm::ISD::UMUL_LOHI, and llvm::ARMSubtarget::useMulOps().

Referenced by AddCombineTo64bitUMAAL(), and PerformAddeSubeCombine().

◆ AddCombineTo64BitSMLAL16()

static SDValue AddCombineTo64BitSMLAL16	(	SDNode *	AddcNode,
		SDNode *	AddeNode,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

◆ AddCombineTo64bitUMAAL()

static SDValue AddCombineTo64bitUMAAL	(	SDNode *	AddeNode,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10615 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, AddCombineTo64bitMLAL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasDSP(), llvm::ARMSubtarget::hasV6Ops(), llvm::MVT::i32, llvm::isNullConstant(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::UMAAL, and llvm::ARMISD::UMLAL.

Referenced by PerformADDECombine().

◆ AddCombineToVPADD()

static SDValue AddCombineToVPADD	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10184 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by PerformADDCombineWithOperands().

◆ AddCombineVUZPToVPADDL()

static SDValue AddCombineVUZPToVPADDL	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10212 of file ARMISelLowering.cpp.

References Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by PerformADDCombineWithOperands().

◆ AddRequiredExtensionForVMULL()

static SDValue AddRequiredExtensionForVMULL	(	SDValue	N,
		SelectionDAG &	DAG,
		const EVT &	OrigTy,
		const EVT &	ExtTy,
		unsigned	ExtOpcode
	)

static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.

We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 7637 of file ARMISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), and llvm::EVT::is128BitVector().

Referenced by SkipExtensionForVMULL().

◆ allUsersAreInFunction()

static bool allUsersAreInFunction	(	const Value *	V,
		const Function *	F
	)

static

Return true if all users of V are within function F, looking through ConstantExprs.

Definition at line 3217 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SmallVectorBase::empty(), F(), I, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::Value::users().

Referenced by promoteToConstantPool().

◆ areExtractExts()

static bool areExtractExts	(	Value *	Ext1,
		Value *	Ext2
	)

static

Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.

Definition at line 13600 of file ARMISelLowering.cpp.

References llvm::MipsISD::Ext, llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().

Referenced by llvm::ARMTargetLowering::shouldSinkOperands().

◆ attachMEMCPYScratchRegs()

static void attachMEMCPYScratchRegs	(	const ARMSubtarget *	Subtarget,
		MachineInstr &	MI,
		const SDNode *	Node
	)

static

Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.

This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.

Definition at line 9915 of file ARMISelLowering.cpp.

◆ bitcastf32Toi32()

static SDValue bitcastf32Toi32	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 4765 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::MVT::i32, isFloatingPointZero(), and llvm_unreachable.

Referenced by expandf64Toi32().

◆ BitsProperlyConcatenate()

static bool BitsProperlyConcatenate	(	const APInt &	A,
		const APInt &	B
	)

static

Definition at line 11616 of file ARMISelLowering.cpp.

References llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), and llvm::APInt::getBitWidth().

Referenced by FindBFIToCombineWith().

◆ canChangeToInt()

static bool canChangeToInt	(	SDValue	Op,
		bool &	SeenZero,
		const ARMSubtarget *	Subtarget
	)

static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 4744 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), isFloatingPointZero(), llvm::ARMSubtarget::isFPBrccSlow(), and llvm::ISD::isNormalLoad().

Referenced by expandf64Toi32().

◆ checkAndUpdateCPSRKill()

static bool checkAndUpdateCPSRKill	(	MachineBasicBlock::iterator	SelectItr,
		MachineBasicBlock *	BB,
		const TargetRegisterInfo *	TRI
	)

static

Definition at line 9591 of file ARMISelLowering.cpp.

References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

◆ checkVSELConstraints()

static void checkVSELConstraints	(	ISD::CondCode	CC,
		ARMCC::CondCodes &	CondCode,
		bool &	swpCmpOps,
		bool &	swpVselOps
	)

static

◆ CombineANDShift()

static SDValue CombineANDShift	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

◆ CombineBaseUpdate()

static SDValue CombineBaseUpdate	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.

For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.

Definition at line 12007 of file ARMISelLowering.cpp.

Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().

◆ combineSelectAndUse()

static SDValue combineSelectAndUse	(	SDNode *	N,
		SDValue	Slct,
		SDValue	OtherOp,
		TargetLowering::DAGCombinerInfo &	DCI,
		bool	AllOnes = `false`
	)

static

Definition at line 10133 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), isConditionalZeroOrAllOnes(), llvm::ISD::SELECT, and std::swap().

Referenced by combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), and PerformSUBCombine().

◆ combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative	(	SDNode *	N,
		bool	AllOnes,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

Definition at line 10159 of file ARMISelLowering.cpp.

References combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and llvm::SDNode::hasOneUse().

Referenced by PerformANDCombine(), PerformORCombine(), and PerformXORCombine().

◆ CombineVLDDUP()

static bool CombineVLDDUP	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.

If so, combine them to a vldN-dup operation and return true.

Definition at line 12235 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), llvm::makeArrayRef(), llvm::MVT::Other, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VDUPLANE, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.

Referenced by PerformVDUPLANECombine().

◆ CombineVMOVDRRCandidateWithVecOp()

static SDValue CombineVMOVDRRCandidateWithVecOp	(	const SDNode *	BC,
		SelectionDAG &	DAG
	)

static

BC is a bitcast that is about to be turned into a VMOVDRR.

When DstVT, the destination type of BC, is on the vector register bank and the source of bitcast, Op, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return The node that would replace BT, if the combine is possible.

Definition at line 5294 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, and llvm::EVT::isVector().

Referenced by ExpandBITCAST().

◆ ConvertBooleanCarryToCarryFlag()

static SDValue ConvertBooleanCarryToCarryFlag	(	SDValue	BoolCarry,
		SelectionDAG &	DAG
	)

static

Definition at line 4218 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, and llvm::ARMISD::SUBC.

Referenced by LowerADDSUBCARRY().

◆ ConvertCarryFlagToBooleanCarry()

static SDValue ConvertCarryFlagToBooleanCarry	(	SDValue	Flags,
		EVT	VT,
		SelectionDAG &	DAG
	)

static

◆ createGPRPairNode()

static SDValue createGPRPairNode	(	SelectionDAG &	DAG,
		SDValue	V
	)

static

Definition at line 8291 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::ISD::SRL, std::swap(), and llvm::MVT::Untyped.

Referenced by ReplaceCMP_SWAP_64Results().

◆ emitPostLd()

static void emitPostLd	(	MachineBasicBlock *	BB,
		MachineBasicBlock::iterator	Pos,
		const TargetInstrInfo *	TII,
		const DebugLoc &	dl,
		unsigned	LdSize,
		unsigned	Data,
		unsigned	AddrIn,
		unsigned	AddrOut,
		bool	IsThumb1,
		bool	IsThumb2
	)

static

Emit a post-increment load operation with given size.

The instructions will be added to BB at Pos.

Definition at line 9151 of file ARMISelLowering.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, llvm::RegState::Define, llvm::MCInstrInfo::get(), getLdOpcode(), llvm::predOps(), and llvm::t1CondCodeOp().

Referenced by emitPostSt().

◆ emitPostSt()

static void emitPostSt	(	MachineBasicBlock *	BB,
		MachineBasicBlock::iterator	Pos,
		const TargetInstrInfo *	TII,
		const DebugLoc &	dl,
		unsigned	StSize,
		unsigned	Data,
		unsigned	AddrIn,
		unsigned	AddrOut,
		bool	IsThumb1,
		bool	IsThumb2
	)

static

Emit a post-increment store operation with given size.

The instructions will be added to BB at Pos.

Definition at line 9192 of file ARMISelLowering.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), C, llvm::condCodeOp(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, emitPostLd(), llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::FrameSetup, llvm::MCInstrInfo::get(), llvm::ConstantInt::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetMachine::getCodeModel(), llvm::MachinePointerInfo::getConstantPool(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::ARMSubtarget::getInstrInfo(), llvm::Type::getInt32Ty(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::DataLayout::getPrefTypeAlignment(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getStOpcode(), llvm::TargetLoweringBase::getTargetMachine(), llvm::DataLayout::getTypeAllocSize(), llvm::Function::hasFnAttribute(), llvm::ARMSubtarget::hasNEON(), llvm::RegState::Implicit, llvm::MachineFunction::insert(), Int32Ty, llvm::ARMSubtarget::isTargetWindows(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::CodeModel::Kernel, llvm::RegState::Kill, llvm::CodeModel::Large, llvm_unreachable, llvm::CodeModel::Medium, llvm::MachineMemOperand::MOLoad, MRI, llvm::ARMCC::NE, llvm::predOps(), llvm::MachineFunction::push_back(), R4, Reg, llvm::MachineOperand::setIsDef(), llvm::MachineInstrBuilder::setMIFlags(), llvm::MachineOperand::setReg(), llvm::CodeModel::Small, llvm::MachineBasicBlock::splice(), llvm::t1CondCodeOp(), TII, llvm::CodeModel::Tiny, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::ARMSubtarget::useMovt().

◆ Expand64BitShift()

static SDValue Expand64BitShift	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST
	)

static

Definition at line 5761 of file ARMISelLowering.cpp.

References llvm::ARMISD::ASRL, assert(), llvm::ISD::BUILD_PAIR, llvm::dyn_cast(), llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::ARMSubtarget::hasMVEIntegerOps(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), llvm::MipsISD::Lo, llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, llvm::ARMISD::RRX, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ARMISD::SRA_FLAG, llvm::ISD::SRL, llvm::ARMISD::SRL_FLAG, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ ExpandBITCAST()

static SDValue ExpandBITCAST	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

ExpandBITCAST - If the target supports VFP, this function is called to expand a bit convert where either the source or destination type is i64 to use a VMOVDRR or VMOVRRD node.

This should not be done when the non-i64 operand type is illegal (e.g., v2f32 for a target that doesn't support vectors), since the legalizer won't know what to do with that.

Definition at line 5342 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_PAIR, CombineVMOVDRRCandidateWithVecOp(), llvm::ISD::CopyFromReg, llvm::ISD::CopyToReg, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasFullFP16(), llvm::MipsISD::Hi, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MipsISD::Lo, llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ARMISD::RET_FLAG, llvm::SDNode::use_begin(), llvm::SDNode::use_size(), llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVhr, llvm::ARMISD::VMOVrh, llvm::ARMISD::VMOVRRD, llvm::ARMISD::VREV64, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ expandf64Toi32()

static void expandf64Toi32	(	SDValue	Op,
		SelectionDAG &	DAG,
		SDValue &	RetVal1,
		SDValue &	RetVal2
	)

static

◆ ExpandREAD_REGISTER()

static void ExpandREAD_REGISTER	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)

static

Definition at line 5269 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::READ_REGISTER.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ FindBFIToCombineWith()

static SDValue FindBFIToCombineWith ( SDNode * N )

static

Definition at line 11622 of file ARMISelLowering.cpp.

References llvm::ARMISD::BFI, BitsProperlyConcatenate(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), and ParseBFI().

Referenced by PerformBFICombine().

◆ findMUL_LOHI()

static SDValue findMUL_LOHI ( SDValue V )

static

Definition at line 10362 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.

Referenced by AddCombineTo64bitMLAL().

◆ FPCCToARMCC()

static void FPCCToARMCC	(	ISD::CondCode	CC,
		ARMCC::CondCodes &	CondCode,
		ARMCC::CondCodes &	CondCode2,
		bool &	InvalidOnQNaN
	)

static

FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.

Definition at line 1728 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::CallingConv::ARM_AAPCS, llvm::CallingConv::ARM_AAPCS_VFP, llvm::CallingConv::ARM_APCS, llvm::CallingConv::C, llvm::CallingConv::CXX_FAST_TLS, llvm::ARMCC::EQ, llvm::CallingConv::Fast, llvm::TargetOptions::FloatABIType, llvm::ARMCC::GE, llvm::TargetLoweringBase::getTargetMachine(), llvm::CallingConv::GHC, llvm::ARMCC::GT, llvm::FloatABI::Hard, llvm::ARMSubtarget::hasVFP2Base(), llvm::ARMCC::HI, llvm::ARMSubtarget::isAAPCS_ABI(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::TargetMachine::Options, llvm::ARMCC::PL, llvm::CallingConv::PreserveMost, llvm::report_fatal_error(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::CallingConv::Swift, llvm::ARMCC::VC, and llvm::ARMCC::VS.

Referenced by isLowerSaturatingConditional().

◆ GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle	(	unsigned	PFEntry,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	dl
	)

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 7189 of file ARMISelLowering.cpp.

References assert(), llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by LowerVECTOR_SHUFFLE().

◆ getARMIndexedAddressParts()

static bool getARMIndexedAddressParts	(	SDNode *	Ptr,
		EVT	VT,
		bool	isSEXTLoad,
		SDValue &	Base,
		SDValue &	Offset,
		bool &	isInc,
		SelectionDAG &	DAG
	)

static

Definition at line 13947 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARM_AM::getShiftOpcForNode(), llvm::SDNode::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ARM_AM::no_shift, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

◆ getDivRemArgList()

static TargetLowering::ArgListTy getDivRemArgList	(	const SDNode *	N,
		LLVMContext *	Context,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 14691 of file ARMISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::SDNode::getOpcode(), llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.

◆ getDivRemLibcall()

static RTLIB::Libcall getDivRemLibcall	(	const SDNode *	N,
		MVT::SimpleValueType	SVT
	)

static

Definition at line 14673 of file ARMISelLowering.cpp.

References assert(), llvm::SDNode::getOpcode(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.

◆ getExtensionTo64Bits()

static EVT getExtensionTo64Bits ( const EVT & OrigVT )

static

Definition at line 7617 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.

Referenced by AddRequiredExtensionForVMULL(), and SkipLoadExtensionForVMULL().

◆ getLdOpcode()

static unsigned getLdOpcode	(	unsigned	LdSize,
		bool	IsThumb1,
		bool	IsThumb2
	)

static

Return the load opcode for a given load size.

If load size >= 8, neon opcode will be returned.

Definition at line 9113 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

◆ getStOpcode()

static unsigned getStOpcode	(	unsigned	StSize,
		bool	IsThumb1,
		bool	IsThumb2
	)

static

Return the store opcode for a given store size.

If store size >= 8, neon opcode will be returned.

Definition at line 9132 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

◆ getT2IndexedAddressParts()

static bool getT2IndexedAddressParts	(	SDNode *	Ptr,
		EVT	VT,
		bool	isSEXTLoad,
		SDValue &	Base,
		SDValue &	Offset,
		bool &	isInc,
		SelectionDAG &	DAG
	)

static

Definition at line 14006 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

◆ getVShiftImm()

static bool getVShiftImm	(	SDValue	Op,
		unsigned	ElementBits,
		int64_t &	Cnt
	)

static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 5668 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

◆ getZeroVector()

static SDValue getZeroVector	(	EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	dl
	)

static

getZeroVector - Returns a vector of specified type with all zero elements.

Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 5464 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::ARMISD::CMOV, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::isVector(), llvm::MipsISD::Lo, llvm::ISD::OR, llvm::ISD::SETGE, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SUB, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ARMISD::VMOVIMM.

Referenced by LowerCTTZ(), and LowerShift().

◆ hasNormalLoadOperand()

static bool hasNormalLoadOperand ( SDNode * N )

static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.

If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 11789 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isNormalLoad(), and isVolatile().

Referenced by PerformBUILD_VECTORCombine().

◆ IntCCToARMCC()

static ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode CC )

static

IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.

Definition at line 1711 of file ARMISelLowering.cpp.

References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by expandf64Toi32(), isFloatingPointZero(), and isLowerSaturatingConditional().

◆ isAddSubSExt()

static bool isAddSubSExt	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 7733 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isSignExtended(), and llvm::ISD::SUB.

Referenced by LowerMUL().

◆ isAddSubZExt()

static bool isAddSubZExt	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 7744 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isZeroExtended(), and llvm::ISD::SUB.

Referenced by LowerMUL().

◆ isConditionalZeroOrAllOnes()

static bool isConditionalZeroOrAllOnes	(	SDNode *	N,
		bool	AllOnes,
		SDValue &	CC,
		bool &	Invert,
		SDValue &	OtherOp,
		SelectionDAG &	DAG
	)

static

Definition at line 10059 of file ARMISelLowering.cpp.

References llvm::APInt::getAllOnesValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i1, isZeroOrAllOnes(), LLVM_FALLTHROUGH, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineSelectAndUse().

◆ isExtendedBUILD_VECTOR()

static bool isExtendedBUILD_VECTOR	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	isSigned
	)

static

isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.

Definition at line 7546 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, C, llvm::dyn_cast(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), llvm::DataLayout::isBigEndian(), llvm::isIntN(), llvm::isUIntN(), llvm::MVT::v2i64, and llvm::MVT::v4i32.

Referenced by isSignExtended(), and isZeroExtended().

◆ isFloatingPointZero()

static bool isFloatingPointZero ( SDValue Op )

static

isFloatingPointZero - Return true if this is +0.0.

Definition at line 3980 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ARMISD::ADDC, assert(), llvm::ISD::BITCAST, C, llvm::ARMISD::CMOV, llvm::ARMISD::CMP, llvm::ARMISD::CMPFP, llvm::ARMISD::CMPFPw0, llvm::ARMISD::CMPZ, llvm::HexagonISD::CP, llvm::ARMCC::EQ, llvm::MVT::f64, llvm::ARMISD::FMSTAT, llvm::ARMCC::GE, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::ISD::getSetCCSwappedOperands(), llvm::ARM_AM::getShiftOpcForNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::ARMSubtarget::hasFP64(), llvm::ARMCC::HS, llvm::MVT::i32, IntCCToARMCC(), llvm::ISD::isEXTLoad(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ISD::isNON_EXTLoad(), llvm::isNullConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::ARMCC::LT, llvm::ISD::MERGE_VALUES, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARM_AM::no_shift, llvm::ARMCC::PL, llvm::ISD::SADDO, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SSUBO, llvm::ISD::SUB, std::swap(), llvm::ISD::UADDO, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ARMCC::VC, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::Wrapper.

Referenced by bitcastf32Toi32(), canChangeToInt(), expandf64Toi32(), and isLowerSaturatingConditional().

◆ isGTorGE()

static bool isGTorGE ( ISD::CondCode CC )

static

Definition at line 4424 of file ARMISelLowering.cpp.

References llvm::ISD::SETGE, and llvm::ISD::SETGT.

Referenced by isLowerSaturate(), and isUpperSaturate().

◆ isHomogeneousAggregate()

static bool isHomogeneousAggregate	(	Type *	Ty,
		HABaseType &	Base,
		uint64_t &	Members
	)

static

Definition at line 15743 of file ARMISelLowering.cpp.

References HA_DOUBLE, HA_FLOAT, HA_UNKNOWN, HA_VECT128, HA_VECT64, llvm::Type::isDoubleTy(), and llvm::Type::isFloatTy().

Referenced by llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters().

◆ isLegalAddressImmediate()

static bool isLegalAddressImmediate	(	int64_t	V,
		EVT	VT,
		const ARMSubtarget *	Subtarget
	)

static

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 13765 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::isUInt< 8 >(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().

◆ isLegalMVEShuffleOp()

static bool isLegalMVEShuffleOp ( unsigned PFEntry )

static

Definition at line 7126 of file ARMISelLowering.cpp.

References OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, and OP_VREV.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isLegalT1AddressImmediate()

static bool isLegalT1AddressImmediate	(	int64_t	V,
		EVT	VT
	)

static

Definition at line 13685 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

◆ isLegalT2AddressImmediate()

static bool isLegalT2AddressImmediate	(	int64_t	V,
		EVT	VT,
		const ARMSubtarget *	Subtarget
	)

static

◆ isLowerSaturate()

static bool isLowerSaturate	(	const SDValue	LHS,
		const SDValue	RHS,
		const SDValue	TrueVal,
		const SDValue	FalseVal,
		const ISD::CondCode	CC,
		const SDValue	K
	)

static

Definition at line 4438 of file ARMISelLowering.cpp.

References isGTorGE(), and isLTorLE().

Referenced by isLowerSaturatingConditional(), and isSaturatingConditional().

◆ isLowerSaturatingConditional()

static bool isLowerSaturatingConditional	(	const SDValue &	Op,
		SDValue &	V,
		SDValue &	SatK
	)

static

Definition at line 4573 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::ISD::AND, checkVSELConstraints(), llvm::countTrailingOnes(), llvm::ARMCC::EQ, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, FPCCToARMCC(), llvm::ARMCC::GE, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::ARMCC::GT, llvm::ARMSubtarget::hasFP64(), llvm::ARMSubtarget::hasFPARMv8Base(), llvm::ARMSubtarget::hasFullFP16(), llvm::ARMSubtarget::hasV6Ops(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i32, IntCCToARMCC(), llvm::isAllOnesConstant(), isFloatingPointZero(), isLowerSaturate(), llvm::isNullConstant(), isSaturatingConditional(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb2(), llvm::ARMCC::LE, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::OR, llvm::ARMCC::PL, llvm::ISD::SETNE, llvm::TargetLowering::softenSetCCOperands(), llvm::ISD::SRA, llvm::ARMISD::SSAT, std::swap(), llvm::ARMISD::USAT, llvm::ARMCC::VC, llvm::ARMCC::VS, and llvm::ISD::XOR.

◆ isLTorLE()

static bool isLTorLE ( ISD::CondCode CC )

static

Definition at line 4428 of file ARMISelLowering.cpp.

References llvm::ISD::SETLE, and llvm::ISD::SETLT.

Referenced by isLowerSaturate(), and isUpperSaturate().

◆ isNEONModifiedImm()

static SDValue isNEONModifiedImm	(	uint64_t	SplatBits,
		uint64_t	SplatUndef,
		unsigned	SplatBitSize,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT &	VT,
		bool	is128Bits,
		NEONModImmType	type
	)

static

isNEONModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).

If so, return the encoded value.

Definition at line 6033 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::ARM_AM::createNEONModImm(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ARMSubtarget::genExecuteOnly(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::ARM_AM::getFP32Imm(), llvm::ARM_AM::getFP64Imm(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::ARMSubtarget::hasFP64(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasVFP3Base(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::X86II::ImmMask, llvm::DataLayout::isBigEndian(), llvm::ARMTargetLowering::isFPImmLegal(), llvm::ARMSubtarget::isLittle(), llvm_unreachable, llvm::MipsISD::Lo, llvm::APInt::lshr(), llvm::MVEVMVNModImm, llvm::OtherModImm, llvm::MVT::SimpleTy, llvm::ARM_MB::ST, std::swap(), llvm::APInt::trunc(), llvm::ARMSubtarget::useNEONForSinglePrecisionFP(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVFPIMM, llvm::ARMISD::VMOVIMM, llvm::VMOVModImm, llvm::ARMISD::VMOVSR, llvm::ARMISD::VMVNIMM, and llvm::VMVNModImm.

Referenced by IsSingleInstrConstant(), PerformANDCombine(), and PerformORCombine().

◆ isNEONTwoResultShuffleMask()

static unsigned isNEONTwoResultShuffleMask	(	ArrayRef< int >	ShuffleMask,
		EVT	VT,
		unsigned &	WhichResult,
		bool &	isV_UNDEF
	)

static

Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.

Definition at line 6615 of file ARMISelLowering.cpp.

References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isPowerOf2Constant()

static const APInt* isPowerOf2Constant ( SDValue V )

static

Definition at line 12933 of file ARMISelLowering.cpp.

References C, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), and llvm::APInt::isPowerOf2().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), and llvm::ARMTargetLowering::PerformCMOVToBFICombine().

◆ isReverseMask()

static bool isReverseMask	(	ArrayRef< int >	M,
		EVT	VT
	)

static

Returns: true if this is a reverse operation on an vector.

Definition at line 6638 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and llvm::ArrayRef< T >::size().

Referenced by llvm::ShuffleVectorInst::isReverse(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ShuffleVectorInst::isSelect(), llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isS16()

static bool isS16	(	const SDValue &	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 1704 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SDValue::getOperand(), isSHL16(), and isSRA16().

Referenced by AddCombineTo64BitSMLAL16(), and PerformORCombineToSMULWBT().

◆ isSaturatingConditional()

static bool isSaturatingConditional	(	const SDValue &	Op,
		SDValue &	V,
		uint64_t &	K,
		bool &	usat
	)

static

Definition at line 4474 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), isLowerSaturate(), llvm::isPowerOf2_64(), isUpperSaturate(), llvm::max(), llvm::ISD::SELECT_CC, llvm::ISD::SIGN_EXTEND_INREG, and llvm::NVPTX::PTXLdStInstCode::V2.

Referenced by isLowerSaturatingConditional().

◆ isSHL16()

static bool isSHL16 ( const SDValue & Op )

static

Definition at line 1692 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::ISD::SHL.

Referenced by isS16(), and PerformORCombineToSMULWBT().

◆ isSignExtended()

static bool isSignExtended	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 7599 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), and llvm::ISD::SIGN_EXTEND.

Referenced by isAddSubSExt(), and LowerMUL().

◆ IsSingleInstrConstant()

static SDValue IsSingleInstrConstant	(	SDValue	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST,
		const SDLoc &	dl
	)

static

Definition at line 6655 of file ARMISelLowering.cpp.

◆ isSingletonVEXTMask()

static bool isSingletonVEXTMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	Imm
	)

static

Definition at line 6287 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by LowerVECTOR_SHUFFLE().

◆ isSRA16()

static bool isSRA16 ( const SDValue & Op )

static

Definition at line 1684 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::ISD::SRA.

Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().

◆ isSRL16()

static bool isSRL16 ( const SDValue & Op )

static

Definition at line 1676 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::ISD::SRL.

Referenced by PerformORCombineToSMULWBT().

◆ isUpperSaturate()

static bool isUpperSaturate	(	const SDValue	LHS,
		const SDValue	RHS,
		const SDValue	TrueVal,
		const SDValue	FalseVal,
		const ISD::CondCode	CC,
		const SDValue	K
	)

static

Definition at line 4448 of file ARMISelLowering.cpp.

References isGTorGE(), and isLTorLE().

Referenced by isSaturatingConditional().

◆ isVEXTMask()

static bool isVEXTMask	(	ArrayRef< int >	M,
		EVT	VT,
		bool &	ReverseVEXT,
		unsigned &	Imm
	)

static

Definition at line 6315 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isVREVMask()

static bool isVREVMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned	BlockSize
	)

static

isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize.

(The order of the elements within each block of the vector is reversed.)

Definition at line 6354 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), and llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isVShiftLImm()

static bool isVShiftLImm	(	SDValue	Op,
		EVT	VT,
		bool	isLong,
		int64_t &	Cnt
	)

static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 5689 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by LowerShift(), PerformIntrinsicCombine(), and PerformShiftCombine().

◆ isVShiftRImm()

static bool isVShiftRImm	(	SDValue	Op,
		EVT	VT,
		bool	isNarrow,
		bool	isIntrinsic,
		int64_t &	Cnt
	)

static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 5703 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by LowerShift(), PerformIntrinsicCombine(), and PerformShiftCombine().

◆ isVTBLMask()

static bool isVTBLMask	(	ArrayRef< int >	M,
		EVT	VT
	)

static

Definition at line 6380 of file ARMISelLowering.cpp.

References llvm::ArrayRef< T >::size(), and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().

◆ isVTRN_v_undef_Mask()

static bool isVTRN_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)

static

isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 6447 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), SelectPairHalf(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

◆ isVTRNMask()

static bool isVTRNMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)

static

Definition at line 6415 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), SelectPairHalf(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

◆ isVUZP_v_undef_Mask()

static bool isVUZP_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)

static

isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 6509 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), SelectPairHalf(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

◆ isVUZPMask()

static bool isVUZPMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)

static

Definition at line 6479 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), SelectPairHalf(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

◆ IsVUZPShuffleNode()

static bool IsVUZPShuffleNode ( SDNode * N )

static

Definition at line 10172 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::v2i32, llvm::ARMISD::VTRN, and llvm::ARMISD::VUZP.

Referenced by AddCombineToVPADD(), and AddCombineVUZPToVPADDL().

◆ isVZIP_v_undef_Mask()

static bool isVZIP_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)

static

isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 6583 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), SelectPairHalf(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

◆ isVZIPMask()

static bool isVZIPMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)

static

Definition at line 6550 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), SelectPairHalf(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

◆ isZeroExtended()

static bool isZeroExtended	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

isZeroExtended - Check if a node is a vector value that is zero-extended or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 7609 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), and llvm::ISD::ZERO_EXTEND.

Referenced by isAddSubZExt(), and LowerMUL().

◆ isZeroOrAllOnes()

static bool isZeroOrAllOnes	(	SDValue	N,
		bool	AllOnes
	)

inlinestatic

Definition at line 10043 of file ARMISelLowering.cpp.

References llvm::isAllOnesConstant(), and llvm::isNullConstant().

Referenced by isConditionalZeroOrAllOnes().

◆ LowerADDSUBCARRY()

static SDValue LowerADDSUBCARRY	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 8011 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerATOMIC_FENCE()

static SDValue LowerATOMIC_FENCE	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

◆ LowerAtomicLoadStore()

static SDValue LowerAtomicLoadStore	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 8258 of file ARMISelLowering.cpp.

References llvm::isStrongerThanMonotonic().

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerCONCAT_VECTORS()

static SDValue LowerCONCAT_VECTORS	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

◆ LowerCTPOP()

static SDValue LowerCTPOP	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST
	)

static

◆ LowerCTTZ()

static SDValue LowerCTTZ	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST
	)

static

◆ LowerEXTRACT_VECTOR_ELT()

static SDValue LowerEXTRACT_VECTOR_ELT	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 7508 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::i32, and llvm::ARMISD::VGETLANEu.

Referenced by llvm::PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters(), llvm::X86TargetLowering::getMaxSupportedInterleaveFactor(), llvm::NVPTXTargetLowering::isCheapToSpeculateCtlz(), llvm::HexagonTargetLowering::isCtlzFast(), llvm::ARMTargetLowering::LowerOperation(), and llvm::AArch64TargetLowering::supportSwiftError().

◆ LowerFPOWI()

static SDValue LowerFPOWI	(	SDValue	Op,
		const ARMSubtarget &	Subtarget,
		SelectionDAG &	DAG
	)

static

Definition at line 8336 of file ARMISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::Exponent, llvm::MVT::f32, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExternalSymbol(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ARMSubtarget::getTargetTriple(), llvm::Triple::isOSMSVCRT(), and llvm::ISD::SINT_TO_FP.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerInterruptReturn()

static SDValue LowerInterruptReturn	(	SmallVectorImpl< SDValue > &	RetOps,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

Definition at line 2605 of file ARMISelLowering.cpp.

References llvm::CCState::AnalyzeReturn(), Arg, assert(), llvm::CCValAssign::BCvt, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::ARMTargetLowering::CCAssignFnForReturn(), contains(), Copies, llvm::ISD::CopyToReg, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::ISD::EXTRACT_VECTOR_ELT, F(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyToReg(), llvm::MVT::getFloatingPointVT(), llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), llvm::SelectionDAG::getRegister(), llvm::ARMSubtarget::getRegisterInfo(), llvm::SDValue::getValue(), llvm::Attribute::getValueAsString(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::Function::hasFnAttribute(), llvm::ARMSubtarget::hasFullFP16(), llvm::SDNode::hasNUsesOfValue(), llvm::SDNode::hasOneUse(), I, llvm::MVT::i16, llvm::MVT::i32, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SmallVectorImpl< T >::insert(), llvm::ARMISD::INTRET_FLAG, llvm::ARMSubtarget::isLittle(), llvm::ARMSubtarget::isMClass(), llvm::CCValAssign::isRegLoc(), llvm::CallInst::isTailCall(), llvm::ARMSubtarget::isTargetHardFloat(), llvm::ARMSubtarget::isThumb1Only(), llvm_unreachable, N, llvm::CCValAssign::needsCustom(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::report_fatal_error(), llvm::ARMISD::RET_FLAG, llvm::ARMFunctionInfo::setReturnRegsCount(), llvm::SmallVectorBase::size(), llvm::SmallPtrSetImplBase::size(), llvm::ARMSubtarget::supportsTailCall(), TRI, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::MVT::v2f64, llvm::ARMISD::VMOVRRD, and llvm::ISD::ZERO_EXTEND.

◆ LowerMUL()

static SDValue LowerMUL	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

◆ LowerPREFETCH()

static SDValue LowerPREFETCH	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 3621 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::ARMSubtarget::hasMPExtension(), llvm::ARMSubtarget::hasV5TEOps(), llvm::ARMSubtarget::hasV7Ops(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::MVT::Other, and llvm::ARMISD::PRELOAD.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()

static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 7268 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::v16i8, llvm::MVT::v8i16, llvm::ARMISD::VEXT, and llvm::ARMISD::VREV64.

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerSDIV()

static SDValue LowerSDIV	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 7900 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::MVT::v4i16, llvm::MVT::v8i16, and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerSDIV_v4i16()

static SDValue LowerSDIV_v4i16	(	SDValue	N0,
		SDValue	N1,
		const SDLoc &	dl,
		SelectionDAG &	DAG
	)

static

Definition at line 7861 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.

Referenced by LowerSDIV(), and LowerUDIV().

◆ LowerSDIV_v4i8()

static SDValue LowerSDIV_v4i8	(	SDValue	X,
		SDValue	Y,
		const SDLoc &	dl,
		SelectionDAG &	DAG
	)

static

Definition at line 7830 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, X, and Y.

Referenced by LowerSDIV().

◆ LowerSETCCCARRY()

static SDValue LowerSETCCCARRY	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 6000 of file ARMISelLowering.cpp.

References llvm::SDValue::getOperand().

Referenced by llvm::X86TargetLowering::getMaxSupportedInterleaveFactor(), and llvm::ARMTargetLowering::LowerOperation().

◆ LowerShift()

static SDValue LowerShift	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST
	)

static

◆ LowerUDIV()

static SDValue LowerUDIV	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

◆ LowerVASTART()

static SDValue LowerVASTART	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 3648 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerVECTOR_SHUFFLE()

static SDValue LowerVECTOR_SHUFFLE	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST
	)

static

Definition at line 7285 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::TargetLoweringBase::getTypeAction(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SDValue::isUndef(), llvm::SDNode::isUndef(), isVEXTMask(), isVREVMask(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerVECTOR_SHUFFLEv8i8(), PerfectShuffleTable, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, std::swap(), llvm::TargetLoweringBase::TypePromoteFloat, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ARMISD::VREV64.

Referenced by llvm::PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters(), llvm::HexagonTargetLowering::isCtlzFast(), llvm::ARMTargetLowering::LowerOperation(), and llvm::AArch64TargetLowering::supportSwiftError().

◆ LowerVECTOR_SHUFFLEv8i8()

static SDValue LowerVECTOR_SHUFFLEv8i8	(	SDValue	Op,
		ArrayRef< int >	ShuffleMask,
		SelectionDAG &	DAG
	)

static

Definition at line 7247 of file ARMISelLowering.cpp.

References llvm::ArrayRef< T >::begin(), E, llvm::ArrayRef< T >::end(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), I, llvm::MVT::i32, llvm::SDNode::isUndef(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8i8, llvm::ARMISD::VTBL1, and llvm::ARMISD::VTBL2.

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerVectorFP_TO_INT()

static SDValue LowerVectorFP_TO_INT	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

◆ LowerVectorINT_TO_FP()

static SDValue LowerVectorINT_TO_FP	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 5066 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::ARM_AM::createNEONModImm(), llvm::StringSwitch< T, R >::Default(), llvm::Depth, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, first, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFrameInfo(), llvm::ARMBaseRegisterInfo::getFrameRegister(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMTargetLowering::getRegClassFor(), llvm::RTLIB::getSINTTOFP(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::RTLIB::getUINTTOFP(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasNEON(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::EVT::isVector(), llvm_unreachable, llvm::MipsISD::Lo, llvm::TargetLowering::makeLibCall(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::OR, Reg, llvm::report_fatal_error(), llvm::ISD::SCALAR_TO_VECTOR, llvm::MachineFrameInfo::setFrameAddressIsTaken(), llvm::MachineFrameInfo::setReturnAddressIsTaken(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2i32, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVIMM, llvm::ARMISD::VMOVRRD, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHRuIMM, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

◆ LowerVSETCC()

static SDValue LowerVSETCC	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 5842 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, std::swap(), llvm::ARMISD::VCEQ, llvm::ARMISD::VCEQZ, llvm::ARMISD::VCGE, llvm::ARMISD::VCGEU, llvm::ARMISD::VCGEZ, llvm::ARMISD::VCGT, llvm::ARMISD::VCGTU, llvm::ARMISD::VCGTZ, llvm::ARMISD::VCLEZ, llvm::ARMISD::VCLTZ, llvm::ARMISD::VREV64, and llvm::ARMISD::VTST.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::AArch64TargetLowering::supportSwiftError().

◆ LowerWRITE_REGISTER()

static SDValue LowerWRITE_REGISTER	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 2876 of file ARMISelLowering.cpp.

References assert(), C, llvm::HexagonISD::CP, llvm::ISD::EXTRACT_ELEMENT, llvm::ARMSubtarget::genExecuteOnly(), llvm::ConstantPoolSDNode::getAlignment(), llvm::SelectionDAG::getConstant(), llvm::ConstantPoolSDNode::getConstVal(), llvm::SelectionDAG::getDataLayout(), getFunction(), llvm::MachineFunction::getFunctionNumber(), llvm::MachineFunction::getInfo(), llvm::ConstantPoolSDNode::getMachineCPVal(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::GlobalValue::getParent(), llvm::DataLayout::getPrivateGlobalPrefix(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::ConstantPoolSDNode::getType(), llvm::SDValue::getValueType(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::GlobalValue::InternalLinkage, llvm::ConstantPoolSDNode::isMachineConstantPoolEntry(), llvm::MipsISD::Lo, llvm::MVT::Other, llvm::ARMISD::Wrapper, and llvm::ISD::WRITE_REGISTER.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ MatchingStackOffset()

static bool MatchingStackOffset	(	SDValue	Arg,
		unsigned	Offset,
		ISD::ArgFlagsTy	Flags,
		MachineFrameInfo &	MFI,
		const MachineRegisterInfo *	MRI,
		const TargetInstrInfo *	TII
	)

static

MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.

Definition at line 2427 of file ARMISelLowering.cpp.

References llvm::CCState::AnalyzeCallOperands(), assert(), C, Callee, llvm::ARMTargetLowering::CCAssignFnForCall(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::CCState::CheckReturn(), Context, llvm::ISD::CopyFromReg, llvm::tgtok::Def, llvm::dyn_cast(), llvm::SmallVectorBase::empty(), G, llvm::ARMFunctionInfo::getArgRegsSaveSize(), llvm::Function::getCallingConv(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::FrameIndexSDNode::getIndex(), llvm::MachineFunction::getInfo(), llvm::ARMSubtarget::getInstrInfo(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::CCState::getNextStackOffset(), llvm::SDValue::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getReg(), llvm::MachineFunction::getRegInfo(), llvm::ARMSubtarget::getRegisterInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetMachine::getTargetTriple(), llvm::SDValue::getValueSizeInBits(), llvm::MachineRegisterInfo::getVRegDef(), llvm::GlobalValue::hasExternalWeakLinkage(), llvm::Function::hasFnAttribute(), llvm::CCValAssign::Indirect, llvm::ISD::ArgFlagsTy::isByVal(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::TargetInstrInfo::isLoadFromStackSlot(), llvm::Triple::isOSBinFormatELF(), llvm::Triple::isOSBinFormatMachO(), llvm::Triple::isOSWindows(), llvm::CCValAssign::isRegLoc(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::max(), MRI, llvm::CCValAssign::needsCustom(), llvm::TargetLowering::parametersInCSRMatch(), llvm::CCState::resultsCompatible(), llvm::SmallVectorBase::size(), llvm::ARMSubtarget::supportsTailCall(), TII, TRI, TT, and llvm::MVT::v2f64.

◆ memOpAlign()

static bool memOpAlign	(	unsigned	DstAlign,
		unsigned	SrcAlign,
		unsigned	AlignCheck
	)

static

Definition at line 13506 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::getOptimalMemOpType().

◆ OtherSucc()

static MachineBasicBlock* OtherSucc	(	MachineBasicBlock *	MBB,
		MachineBasicBlock *	Succ
	)

static

Definition at line 9103 of file ARMISelLowering.cpp.

References E, I, llvm_unreachable, llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

◆ ParseBFI()

static SDValue ParseBFI	(	SDNode *	N,
		APInt &	ToMask,
		APInt &	FromMask
	)

static

Definition at line 11593 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::BFI, llvm::APInt::countPopulation(), From, llvm::APInt::getBitWidth(), llvm::APInt::getLimitedValue(), llvm::APInt::getLowBitsSet(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ISD::SRL.

Referenced by FindBFIToCombineWith(), and PerformBFICombine().

◆ PerformABSCombine()

static SDValue PerformABSCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10753 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::expandABS(), llvm::SDNode::getOpcode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), and llvm::TargetLoweringBase::isOperationLegal().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDCombine()

static SDValue PerformADDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 10971 of file ARMISelLowering.cpp.

References llvm::SDNode::getOperand(), PerformADDCombineWithOperands(), and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDCombineWithOperands()

static SDValue PerformADDCombineWithOperands	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.

This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 10789 of file ARMISelLowering.cpp.

References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), and llvm::SDNode::hasOneUse().

Referenced by PerformADDCombine().

◆ PerformAddcSubcCombine()

static SDValue PerformAddcSubcCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10692 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getVTList(), llvm::MVT::i32, llvm::isNullConstant(), llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ARMISD::SUBC.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDECombine()

static SDValue PerformADDECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.

Definition at line 10772 of file ARMISelLowering.cpp.

References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), and PerformAddeSubeCombine().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformAddeSubeCombine()

static SDValue PerformAddeSubeCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10725 of file ARMISelLowering.cpp.

References AddCombineTo64bitMLAL(), llvm::ARMISD::ADDE, C, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getVTList(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb1Only(), llvm::ISD::SMUL_LOHI, and llvm::ARMISD::SUBE.

Referenced by PerformADDECombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformANDCombine()

static SDValue PerformANDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

◆ PerformARMBUILD_VECTORCombine()

static SDValue PerformARMBUILD_VECTORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.

Definition at line 11834 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::SDValue::isUndef(), and llvm::SDNode::use_begin().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformBFICombine()

static SDValue PerformBFICombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

◆ PerformBUILD_VECTORCombine()

static SDValue PerformBUILD_VECTORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.

Definition at line 11801 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), llvm::MVT::i64, PerformVMOVDRRCombine(), and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformExtendCombine()

static SDValue PerformExtendCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST
	)

static

PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.

Definition at line 12895 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformHWLoopCombine()

static SDValue PerformHWLoopCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST
	)

static

Definition at line 13031 of file ARMISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SETCC, llvm::ARMISD::WLS, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformInsertEltCombine()

static SDValue PerformInsertEltCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.

Definition at line 11926 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isNormalLoad(), and isVolatile().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformIntrinsicCombine()

static SDValue PerformIntrinsicCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.

Definition at line 12649 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformLOADCombine()

static SDValue PerformLOADCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

Definition at line 12373 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::EVT::isVector().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformMULCombine()

static SDValue PerformMULCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

◆ PerformORCombine()

static SDValue PerformORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformORCombine - Target-specific dag combine xforms for ISD::OR.

Definition at line 11473 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::APInt::getZExtValue(), llvm::ARMSubtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), isNEONModifiedImm(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::OtherModImm, PerformORCombineToBFI(), PerformORCombineToSMULWBT(), PerformSHLSimplify(), llvm::MVT::v2i32, llvm::MVT::v4i32, llvm::ARMISD::VBSL, and llvm::ARMISD::VORRIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformORCombineToBFI()

static SDValue PerformORCombineToBFI	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

◆ PerformORCombineToSMULWBT()

static SDValue PerformORCombineToSMULWBT	(	SDNode *	OR,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

◆ PerformShiftCombine()

static SDValue PerformShiftCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST
	)

static

PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.

As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.

Definition at line 12808 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BSWAP, C, llvm::countLeadingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::ARMSubtarget::hasMVEIntegerOps(), llvm::SDNode::hasOneUse(), llvm::ARMSubtarget::hasV6Ops(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::MVT::v2i64, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSHLSimplify()

static SDValue PerformSHLSimplify	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST
	)

static

Definition at line 10866 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ARMISD::CMP, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), llvm::SDValue::dump(), llvm::SDNode::dump(), llvm::dyn_cast(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), LLVM_DEBUG, llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SUB, llvm::SDNode::uses(), X, and llvm::ISD::XOR.

Referenced by PerformADDCombine(), PerformANDCombine(), PerformORCombine(), and PerformXORCombine().

◆ PerformSTORECombine()

static SDValue PerformSTORECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 12387 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSUBCombine()

static SDValue PerformSUBCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

Definition at line 10991 of file ARMISelLowering.cpp.

References combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and llvm::SDNode::hasOneUse().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformUMLALCombine()

static SDValue PerformUMLALCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 10670 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasDSP(), llvm::ARMSubtarget::hasV6Ops(), llvm::MVT::i32, llvm::isNullConstant(), and llvm::ARMISD::UMAAL.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVCVTCombine()

static SDValue PerformVCVTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 12541 of file ARMISelLowering.cpp.

References C, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::TRUNCATE, llvm::MVT::v2i32, and llvm::MVT::v4i32.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDIVCombine()

static SDValue PerformVDIVCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3

Definition at line 12598 of file ARMISelLowering.cpp.

References C, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDUPCombine()

static SDValue PerformVDUPCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.

Definition at line 12345 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::LSBaseSDNode::isUnindexed(), llvm::ARM_MB::LD, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ARMISD::VLD1DUP.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDUPLANECombine()

static SDValue PerformVDUPLANECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.

Definition at line 12314 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeNEONModImm(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDNode::getValueType(), llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVECTOR_SHUFFLECombine()

static SDValue PerformVECTOR_SHUFFLECombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.

Definition at line 11952 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVLDCombine()

static SDValue PerformVLDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

Definition at line 12223 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMOVDRRCombine()

static SDValue PerformVMOVDRRCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.

This is also used for BUILD_VECTORs with 2 operands.

Definition at line 11769 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SDNode::getValueType(), and llvm::ARMISD::VMOVRRD.

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMOVRRDCombine()

static SDValue PerformVMOVRRDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.

Definition at line 11725 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::ISD::FrameIndex, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::ARMSubtarget::hasFP64(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ISD::isNormalLoad(), isVolatile(), llvm::ARM_MB::LD, std::swap(), and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMULCombine()

static SDValue PerformVMULCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.

vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 11019 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasVMLxForwarding(), llvm::ISD::MUL, llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

◆ PerformXORCombine()

static SDValue PerformXORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 11569 of file ARMISelLowering.cpp.

References combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ promoteToConstantPool()

static SDValue promoteToConstantPool	(	const ARMTargetLowering *	TLI,
		const GlobalValue *	GV,
		SelectionDAG &	DAG,
		EVT	PtrVT,
		const SDLoc &	dl
	)

static

Definition at line 3236 of file ARMISelLowering.cpp.

References allUsersAreInFunction(), llvm::StringRef::bytes_begin(), llvm::StringRef::bytes_end(), ConstpoolPromotionMaxSize, ConstpoolPromotionMaxTotal, llvm::copy(), llvm::ARMConstantPoolConstant::Create(), llvm::dyn_cast(), EnableConstpoolPromotion, llvm::TargetOptions::EnableFastISel, F(), llvm::ConstantDataArray::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPreferredAlignment(), llvm::ARMFunctionInfo::getPromotedConstpoolIncrease(), llvm::ARMTargetLowering::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstantPool(), llvm::DataLayout::getTypeAllocSize(), llvm::MVT::i32, llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMFunctionInfo::markGlobalAsPromotedToConstantPool(), llvm::TargetMachine::Options, llvm::ARMFunctionInfo::setPromotedConstpoolIncrease(), llvm::StringRef::size(), and llvm::ARMISD::Wrapper.

Referenced by llvm::ARMTargetLowering::isReadOnly().

◆ ReplaceCMP_SWAP_64Results()

static void ReplaceCMP_SWAP_64Results	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)

static

◆ ReplaceLongIntrinsic()

static void ReplaceLongIntrinsic	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)

static

Definition at line 8471 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MipsISD::Lo, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ARMISD::SMLALD, llvm::ARMISD::SMLALDX, llvm::ARMISD::SMLSLD, and llvm::ARMISD::SMLSLDX.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ ReplaceREADCYCLECOUNTER()

static void ReplaceREADCYCLECOUNTER	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget
	)

static

Definition at line 8268 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::Other, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ SelectPairHalf()

static unsigned SelectPairHalf	(	unsigned	Elements,
		ArrayRef< int >	Mask,
		unsigned	Index
	)

static

Definition at line 6387 of file ARMISelLowering.cpp.

References llvm::ArrayRef< T >::size().

Referenced by isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), and isVZIPMask().

◆ SkipExtensionForVMULL()

static SDValue SkipExtensionForVMULL	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.

The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 7683 of file ARMISelLowering.cpp.

References AddRequiredExtensionForVMULL(), assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, C, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), llvm::ARM_MB::LD, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerMUL().

◆ SkipLoadExtensionForVMULL()

static SDValue SkipLoadExtensionForVMULL	(	LoadSDNode *	LD,
		SelectionDAG &	DAG
	)

static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.

If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 7659 of file ARMISelLowering.cpp.

References llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), getExtensionTo64Bits(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), and llvm::MemSDNode::getPointerInfo().

Referenced by SkipExtensionForVMULL().

◆ STATISTIC() [1/4]

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

◆ STATISTIC() [2/4]

STATISTIC	(	NumMovwMovt	,
		"Number of GAs materialized with movw + movt"
	)

◆ STATISTIC() [3/4]

STATISTIC	(	NumLoopByVals	,
		"Number of loops generated for byval arguments"
	)

◆ STATISTIC() [4/4]

STATISTIC	(	NumConstpoolPromoted	,
		"Number of constants with their storage promoted into constant pools"
	)

◆ WinDBZCheckDenominator()

static SDValue WinDBZCheckDenominator	(	SelectionDAG &	DAG,
		SDNode *	N,
		SDValue	InChain
	)

static

Variable Documentation

◆ ARMInterworking

cl::opt<bool> ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))

static

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn().

◆ ConstpoolPromotionMaxSize

cl::opt<unsigned> ConstpoolPromotionMaxSize("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))

static

Referenced by promoteToConstantPool().

◆ ConstpoolPromotionMaxTotal

cl::opt<unsigned> ConstpoolPromotionMaxTotal("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))

static

Referenced by promoteToConstantPool().

◆ EnableConstpoolPromotion

cl::opt<bool> EnableConstpoolPromotion("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))

static

Referenced by promoteToConstantPool().

◆ GPRArgRegs

const MCPhysReg GPRArgRegs[]

static

Initial value:

= {
  ARM::R0, ARM::R1, ARM::R2, ARM::R3
}

Definition at line 146 of file ARMISelLowering.cpp.

Referenced by llvm::AArch64TargetLowering::CCAssignFnForReturn(), and f64AssignAAPCS().

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Typedef Documentation

◆ RCPair

Enumeration Type Documentation

◆ HABaseType

◆ ShuffleOpCodes

Function Documentation

◆ AddCombineBUILD_VECTORToVPADDL()

◆ AddCombineTo64bitMLAL()

◆ AddCombineTo64BitSMLAL16()

◆ AddCombineTo64bitUMAAL()

◆ AddCombineToVPADD()

◆ AddCombineVUZPToVPADDL()

◆ AddRequiredExtensionForVMULL()

◆ allUsersAreInFunction()

◆ areExtractExts()

◆ attachMEMCPYScratchRegs()

◆ bitcastf32Toi32()

◆ BitsProperlyConcatenate()

◆ canChangeToInt()

◆ checkAndUpdateCPSRKill()

◆ checkVSELConstraints()

◆ CombineANDShift()

◆ CombineBaseUpdate()

◆ combineSelectAndUse()

◆ combineSelectAndUseCommutative()

◆ CombineVLDDUP()

◆ CombineVMOVDRRCandidateWithVecOp()

◆ ConvertBooleanCarryToCarryFlag()

◆ ConvertCarryFlagToBooleanCarry()

◆ createGPRPairNode()

◆ emitPostLd()

◆ emitPostSt()

◆ Expand64BitShift()

◆ ExpandBITCAST()

◆ expandf64Toi32()

◆ ExpandREAD_REGISTER()

◆ FindBFIToCombineWith()

◆ findMUL_LOHI()

◆ FPCCToARMCC()

◆ GeneratePerfectShuffle()

◆ getARMIndexedAddressParts()

◆ getDivRemArgList()

◆ getDivRemLibcall()

◆ getExtensionTo64Bits()

◆ getLdOpcode()

◆ getStOpcode()

◆ getT2IndexedAddressParts()

◆ getVShiftImm()

◆ getZeroVector()

◆ hasNormalLoadOperand()

◆ IntCCToARMCC()

◆ isAddSubSExt()

◆ isAddSubZExt()

◆ isConditionalZeroOrAllOnes()

◆ isExtendedBUILD_VECTOR()

◆ isFloatingPointZero()

◆ isGTorGE()

◆ isHomogeneousAggregate()

◆ isLegalAddressImmediate()

◆ isLegalMVEShuffleOp()

◆ isLegalT1AddressImmediate()

◆ isLegalT2AddressImmediate()

◆ isLowerSaturate()

◆ isLowerSaturatingConditional()

◆ isLTorLE()

◆ isNEONModifiedImm()

◆ isNEONTwoResultShuffleMask()

◆ isPowerOf2Constant()

◆ isReverseMask()

◆ isS16()

◆ isSaturatingConditional()

◆ isSHL16()

◆ isSignExtended()