ARMISelLowering.cpp File Reference

#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <optional>
#include <string>
#include <tuple>
#include <utility>
#include <vector>

Go to the source code of this file.

Classes
struct	BaseUpdateTarget
	Load/store instruction that can be merged with a base address update. More...
struct	BaseUpdateUser

Macros
#define	DEBUG_TYPE   "arm-isel"
#define	MAKE_CASE(V)

Typedefs
using	RCPair = std::pair< unsigned, const TargetRegisterClass * >

Enumerations
enum	ShuffleOpCodes {   OP_COPY = 0 , OP_VREV , OP_VDUP0 , OP_VDUP1 ,   OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 ,   OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL ,   OP_VZIPR , OP_VTRNL , OP_VTRNR }
enum	HABaseType {   HA_UNKNOWN = 0 , HA_FLOAT , HA_DOUBLE , HA_VECT64 ,   HA_VECT128 }

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
	STATISTIC (NumMovwMovt, "Number of GAs materialized with movw + movt")
	STATISTIC (NumLoopByVals, "Number of loops generated for byval arguments")
	STATISTIC (NumConstpoolPromoted, "Number of constants with their storage promoted into constant pools")
static bool	isSRL16 (const SDValue &Op)
static bool	isSRA16 (const SDValue &Op)
static bool	isSHL16 (const SDValue &Op)
static bool	isS16 (const SDValue &Op, SelectionDAG &DAG)
static ARMCC::CondCodes	IntCCToARMCC (ISD::CondCode CC)
	IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
static void	FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
	FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
static bool	canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls)
static bool	MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
	MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.
static SDValue	LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG)
static bool	allUsersAreInFunction (const Value *V, const Function *F)
	Return true if all users of V are within function F, looking through ConstantExprs.
static SDValue	promoteToConstantPool (const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl)
static SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVASTART (SDValue Op, SelectionDAG &DAG)
static bool	isFloatingPointZero (SDValue Op)
	isFloatingPointZero - Return true if this is +0.0.
static SDValue	ConvertBooleanCarryToCarryFlag (SDValue BoolCarry, SelectionDAG &DAG)
static SDValue	ConvertCarryFlagToBooleanCarry (SDValue Flags, EVT VT, SelectionDAG &DAG)
static SDValue	LowerADDSUBSAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static void	checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
static bool	isGTorGE (ISD::CondCode CC)
static bool	isLTorLE (ISD::CondCode CC)
static bool	isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)
static SDValue	LowerSaturatingConditional (SDValue Op, SelectionDAG &DAG)
static bool	isLowerSaturatingConditional (const SDValue &Op, SDValue &V, SDValue &SatK)
static bool	canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
	canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.
static SDValue	bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)
static void	expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
static SDValue	LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
static void	ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static SDValue	CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG)
	BC is a bitcast that is about to be turned into a VMOVDRR.
static SDValue	getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	getZeroVector - Returns a vector of specified type with all zero elements.
static SDValue	LowerCTTZ (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCTPOP (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static bool	getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
	Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
static bool	isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
	isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
static bool	isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
	isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
static SDValue	LowerShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	Expand64BitShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVSETCC (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerSETCCCARRY (SDValue Op, SelectionDAG &DAG)
static SDValue	isVMOVModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type)
	isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).
static bool	isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
static bool	isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
static bool	isVTBLMask (ArrayRef< int > M, EVT VT)
static unsigned	SelectPairHalf (unsigned Elements, ArrayRef< int > Mask, unsigned Index)
static bool	isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static unsigned	isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF)
	Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
static bool	isReverseMask (ArrayRef< int > M, EVT VT)
static bool	isTruncMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
static bool	isVMOVNMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
static bool	isVMOVNTruncMask (ArrayRef< int > M, EVT ToVT, bool rev)
static SDValue	LowerBuildVectorOfFPTrunc (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerBuildVectorOfFPExt (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl)
static SDValue	LowerBUILD_VECTOR_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerBUILD_VECTORToVIDUP (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static bool	IsQRMVEInstruction (const SDNode *N, const SDNode *Op)
static bool	isLegalMVEShuffleOp (unsigned PFEntry)
static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
static SDValue	LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerReverse_VECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG)
static EVT	getVectorTyFromPredicateVector (EVT VT)
static SDValue	PromoteMVEPredVector (SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVECTOR_SHUFFLEUsingMovs (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLEUsingOneOff (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerINSERT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCONCAT_VECTORS_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerTruncatei1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerTruncate (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVectorExtend (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static bool	isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
	isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.
static bool	isSignExtended (SDNode *N, SelectionDAG &DAG)
	isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.
static bool	isZeroExtended (SDNode *N, SelectionDAG &DAG)
	isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.
static EVT	getExtensionTo64Bits (const EVT &OrigVT)
static SDValue	AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
	AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.
static SDValue	SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
	SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.
static SDValue	SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
	SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.
static bool	isAddSubSExt (SDNode *N, SelectionDAG &DAG)
static bool	isAddSubZExt (SDNode *N, SelectionDAG &DAG)
static SDValue	LowerMUL (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerSDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerUDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerADDSUBCARRY (SDValue Op, SelectionDAG &DAG)
static SDValue	WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain)
static SDValue	LowerPredicateLoad (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerPredicateStore (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSTORE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static bool	isZeroVector (SDValue N)
static SDValue	LowerMLOAD (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerVecReduce (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVecReduceF (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVecReduceMinMax (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)
static void	ReplaceREADCYCLECOUNTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	createGPRPairNode (SelectionDAG &DAG, SDValue V)
static void	ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static void	ReplaceLongIntrinsic (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static MachineBasicBlock *	OtherSucc (MachineBasicBlock *MBB, MachineBasicBlock *Succ)
static unsigned	getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
	Return the load opcode for a given load size.
static unsigned	getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
	Return the store opcode for a given store size.
static void	emitPostLd (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment load operation with given size.
static void	emitPostSt (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment store operation with given size.
static bool	checkAndUpdateCPSRKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
static Register	genTPEntry (MachineBasicBlock *TpEntry, MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpExit, Register OpSizeReg, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI)
	Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.
static void	genTPLoopBody (MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpEntry, MachineBasicBlock *TpExit, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI, Register OpSrcReg, Register OpDestReg, Register ElementCountReg, Register TotalIterationsReg, bool IsMemcpy)
	Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.
static void	attachMEMCPYScratchRegs (const ARMSubtarget *Subtarget, MachineInstr &MI, const SDNode *Node)
	Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.
static bool	isZeroOrAllOnes (SDValue N, bool AllOnes)
static bool	isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
static SDValue	combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
static bool	IsVUZPShuffleNode (SDNode *N)
static SDValue	AddCombineToVPADD (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineVUZPToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineBUILD_VECTORToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	findMUL_LOHI (SDValue V)
static SDValue	AddCombineTo64BitSMLAL16 (SDNode *AddcNode, SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineTo64bitMLAL (SDNode *AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineTo64bitUMAAL (SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformUMLALCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformAddcSubcCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformAddeSubeCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformVQDMULHCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformVSetCCToVCTPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformABSCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformADDECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.
static SDValue	PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.
static SDValue	TryDistrubutionADDVecReduce (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformADDVecReduce (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformSHLSimplify (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
static SDValue	PerformSubCSINCCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
static SDValue	PerformVMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.
static SDValue	PerformMVEVMULLCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	CombineANDShift (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformORCombineToSMULWBT (SDNode *OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformORCombineToBFI (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static bool	isValidMVECond (unsigned CC, bool IsFloat)
static ARMCC::CondCodes	getVCMPCondCode (SDValue N)
static bool	CanInvertMVEVCMP (SDValue N)
static SDValue	PerformORCombine_i1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformORCombine - Target-specific dag combine xforms for ISD::OR.
static SDValue	PerformXORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask)
static bool	BitsProperlyConcatenate (const APInt &A, const APInt &B)
static SDValue	FindBFIToCombineWith (SDNode *N)
static SDValue	PerformBFICombine (SDNode *N, SelectionDAG &DAG)
static SDValue	IsCMPZCSINC (SDNode *Cmp, ARMCC::CondCodes &CC)
static SDValue	PerformCMPZCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformCSETCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVMOVRRDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
static SDValue	PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
	PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.
static SDValue	PerformVMOVhrCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVMOVrhCombine (SDNode *N, SelectionDAG &DAG)
static bool	hasNormalLoadOperand (SDNode *N)
	hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.
static SDValue	PerformBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.
static SDValue	PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
static SDValue	PerformPREDICATE_CASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVECTOR_REG_CASTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	PerformVCMPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.
static SDValue	PerformExtractEltToVMOVRRD (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformExtractEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformSignExtendInregCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformShuffleVMOVNCombine (ShuffleVectorSDNode *N, SelectionDAG &DAG)
static SDValue	PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
	PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.
static bool	TryCombineBaseUpdate (struct BaseUpdateTarget &Target, struct BaseUpdateUser &User, bool SimpleConstIncOnly, TargetLowering::DAGCombinerInfo &DCI)
static unsigned	getPointerConstIncrement (unsigned Opcode, SDValue Ptr, SDValue Inc, const SelectionDAG &DAG)
static bool	findPointerConstIncrement (SDNode *N, SDValue *Ptr, SDValue *CInc)
static bool	isValidBaseUpdate (SDNode *N, SDNode *User)
static SDValue	CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.
static SDValue	PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformMVEVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool	CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
static SDValue	PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.
static SDValue	PerformVDUPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
	PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
static SDValue	PerformLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformTruncatingStoreCombine (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSplittingToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSplittingMVETruncToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformExtractFpToIntStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.
static SDValue	PerformVCVTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
	PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.
static SDValue	PerformFAddVSelectCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformVDIVCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
	PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.
static SDValue	PerformVECREDUCE_ADDCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	PerformReduceShuffleCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVQMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVQDMULHCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformLongShiftCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformShiftCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
	PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.
static SDValue	PerformSplittingToWideningLoad (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
	PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
static SDValue	PerformFPExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	PerformMinMaxToSatCombine (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformMinMaxCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
	PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.
static const APInt *	isPowerOf2Constant (SDValue V)
static SDValue	SearchLoopIntrinsic (SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate)
static SDValue	PerformHWLoopCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformBITCASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformSplittingMVEEXTToWideningLoad (SDNode *N, SelectionDAG &DAG)
static bool	areExtractExts (Value *Ext1, Value *Ext2)
	Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.
static bool	isLegalT1AddressImmediate (int64_t V, EVT VT)
static bool	isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
static bool	isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
	isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.
static bool	getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	getMVEIndexedAddressParts (SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static RTLIB::Libcall	getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT)
static TargetLowering::ArgListTy	getDivRemArgList (const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget)
static bool	isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members)

Variables
static cl::opt< bool >	ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
static cl::opt< bool >	EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))
static cl::opt< unsigned >	ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
static cl::opt< unsigned >	ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
cl::opt< unsigned >	MVEMaxSupportedInterleaveFactor ("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))
static const MCPhysReg	GPRArgRegs []

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "arm-isel"

Definition at line 122 of file ARMISelLowering.cpp.

MAKE_CASE

#define MAKE_CASE

(

V

)

Value:

  case V:                                                                      \
    return #V;

Typedef Documentation

RCPair

using RCPair = std::pair<unsigned, const TargetRegisterClass *>

Definition at line 20287 of file ARMISelLowering.cpp.

Enumeration Type Documentation

HABaseType

enum HABaseType

Enumerator
HA_UNKNOWN
HA_FLOAT
HA_DOUBLE
HA_VECT64
HA_VECT128

Definition at line 21838 of file ARMISelLowering.cpp.

ShuffleOpCodes

enum ShuffleOpCodes

Enumerator
OP_COPY
OP_VREV
OP_VDUP0
OP_VDUP1
OP_VDUP2
OP_VDUP3
OP_VEXT1
OP_VEXT2
OP_VEXT3
OP_VUZPL
OP_VUZPR
OP_VZIPL
OP_VZIPR
OP_VTRNL
OP_VTRNR

Definition at line 8301 of file ARMISelLowering.cpp.

Function Documentation

AddCombineBUILD_VECTORToVPADDL()

static SDValue AddCombineBUILD_VECTORToVPADDL ( SDNode *  N, SDValue  N0, SDValue  N1, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 12621 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.

Referenced by PerformADDCombineWithOperands().

AddCombineTo64bitMLAL()

static SDValue AddCombineTo64bitMLAL ( SDNode *  AddeSubeNode, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 12802 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, AddCombineTo64BitSMLAL16(), llvm::ARMISD::ADDE, assert(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasAnyUseOfValue(), llvm::MVT::i32, llvm::SDNode::isPredecessorOf(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::SMLAL, llvm::ARMISD::SMMLAR, llvm::ARMISD::SMMLSR, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::ARMISD::UMLAL, llvm::ISD::UMUL_LOHI, and llvm::ARMSubtarget::useMulOps().

Referenced by AddCombineTo64bitUMAAL(), and PerformAddeSubeCombine().

AddCombineTo64BitSMLAL16()

static SDValue AddCombineTo64BitSMLAL16 ( SDNode *  AddcNode, SDNode *  AddeNode, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 12725 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasBaseDSP(), llvm::Hi, llvm::MVT::i32, isS16(), isSRA16(), llvm::Lo, llvm::Mul, llvm::ISD::MUL, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::SMLALBB, llvm::ARMISD::SMLALBT, llvm::ARMISD::SMLALTB, llvm::ARMISD::SMLALTT, and llvm::ISD::SRA.

Referenced by AddCombineTo64bitMLAL().

AddCombineTo64bitUMAAL()

static SDValue AddCombineTo64bitUMAAL ( SDNode *  AddeNode, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 12968 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, AddCombineTo64bitMLAL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::isNullConstant(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::UMAAL, and llvm::ARMISD::UMLAL.

Referenced by PerformADDECombine().

AddCombineToVPADD()

static SDValue AddCombineToVPADD ( SDNode *  N, SDValue  N0, SDValue  N1, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 12540 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::INTRINSIC_WO_CHAIN, IsVUZPShuffleNode(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by PerformADDCombineWithOperands().

AddCombineVUZPToVPADDL()

static SDValue AddCombineVUZPToVPADDL ( SDNode *  N, SDValue  N0, SDValue  N1, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 12568 of file ARMISelLowering.cpp.

References Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by PerformADDCombineWithOperands().

AddRequiredExtensionForVMULL()

static SDValue AddRequiredExtensionForVMULL ( SDValue  N, SelectionDAG &  DAG, const EVT &  OrigTy, const EVT &  ExtTy, unsigned  ExtOpcode  )

static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.

We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 9413 of file ARMISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.

Referenced by SkipExtensionForVMULL().

allUsersAreInFunction()

static bool allUsersAreInFunction ( const Value *  V, const Function *  F  )

static

Return true if all users of V are within function F, looking through ConstantExprs.

Definition at line 3770 of file ARMISelLowering.cpp.

References llvm::append_range(), llvm::SmallVectorBase< Size_T >::empty(), F, I, and llvm::SmallVectorImpl< T >::pop_back_val().

Referenced by promoteToConstantPool().

areExtractExts()

static bool areExtractExts ( Value *  Ext1, Value *  Ext2  )

static

Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.

Definition at line 19120 of file ARMISelLowering.cpp.

References llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().

attachMEMCPYScratchRegs()

static void attachMEMCPYScratchRegs ( const ARMSubtarget *  Subtarget, MachineInstr &  MI, const SDNode *  Node  )

static

Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.

This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.

Definition at line 12272 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::MachineFunction::getRegInfo(), I, llvm::ARMSubtarget::isThumb1Only(), MI, and MRI.

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection().

bitcastf32Toi32()

static SDValue bitcastf32Toi32 ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 5586 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::MVT::i32, isFloatingPointZero(), and llvm_unreachable.

BitsProperlyConcatenate()

static bool BitsProperlyConcatenate ( const APInt &  A, const APInt &  B  )

static

Definition at line 14770 of file ARMISelLowering.cpp.

References A, and B.

Referenced by FindBFIToCombineWith().

canChangeToInt()

static bool canChangeToInt ( SDValue  Op, bool &  SeenZero, const ARMSubtarget *  Subtarget  )

static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 5565 of file ARMISelLowering.cpp.

References llvm::MVT::f32, isFloatingPointZero(), llvm::ISD::isNormalLoad(), and N.

canGuaranteeTCO()

static bool canGuaranteeTCO ( CallingConv::ID  CC, bool  GuaranteeTailCalls  )

static

Definition at line 2323 of file ARMISelLowering.cpp.

References CC, llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.

CanInvertMVEVCMP()

static bool CanInvertMVEVCMP ( SDValue  N )

static

Definition at line 14571 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::getOppositeCondition(), getVCMPCondCode(), isValidMVECond(), and N.

Referenced by PerformORCombine_i1(), and PerformXORCombine().

checkAndUpdateCPSRKill()

static bool checkAndUpdateCPSRKill ( MachineBasicBlock::iterator  SelectItr, MachineBasicBlock *  BB, const TargetRegisterInfo *  TRI  )

static

Definition at line 11718 of file ARMISelLowering.cpp.

References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::successors(), and TRI.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

checkVSELConstraints()

static void checkVSELConstraints ( ISD::CondCode  CC, ARMCC::CondCodes &  CondCode, bool &  swpCmpOps, bool &  swpVselOps  )

static

Definition at line 5171 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ARMCC::VS.

CombineANDShift()

static SDValue CombineANDShift ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 14205 of file ARMISelLowering.cpp.

References llvm::countl_zero(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::isShiftedMask_32(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by PerformANDCombine().

CombineBaseUpdate()

static SDValue CombineBaseUpdate ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.

For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.

Definition at line 16054 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorTemplateCommon< T, typename >::end(), findPointerConstIncrement(), llvm::SelectionDAG::getConstant(), llvm::User::getNumOperands(), llvm::User::getOperand(), getPointerConstIncrement(), I, llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isStore(), isValidBaseUpdate(), LHS, N, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::resize(), RHS, llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::STORE, std::swap(), and TryCombineBaseUpdate().

Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().

combineSelectAndUse()

static SDValue combineSelectAndUse ( SDNode *  N, SDValue  Slct, SDValue  OtherOp, TargetLowering::DAGCombinerInfo &  DCI, bool  AllOnes = false  )

static

Definition at line 12489 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), isConditionalZeroOrAllOnes(), N, llvm::ISD::SELECT, and std::swap().

Referenced by combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), performSUBCombine(), and PerformSUBCombine().

combineSelectAndUseCommutative()

static SDValue combineSelectAndUseCommutative ( SDNode *  N, bool  AllOnes, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 12515 of file ARMISelLowering.cpp.

References llvm::AllOnes, combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.

Referenced by performADDCombine(), PerformANDCombine(), performANDCombine(), llvm::LanaiTargetLowering::PerformDAGCombine(), PerformORCombine(), performORCombine(), performXORCombine(), and PerformXORCombine().

CombineVLDDUP()

static bool CombineVLDDUP ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.

If so, combine them to a vldN-dup operation and return true.

Definition at line 16277 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), N, llvm::MVT::Other, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VDUPLANE, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.

Referenced by PerformVDUPLANECombine().

CombineVMOVDRRCandidateWithVecOp()

static SDValue CombineVMOVDRRCandidateWithVecOp ( const SDNode *  BC, SelectionDAG &  DAG  )

static

BC is a bitcast that is about to be turned into a VMOVDRR.

When DstVT, the destination type of BC, is on the vector register bank and the source of bitcast, Op, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return The node that would replace BT, if the combine is possible.

Definition at line 6170 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::MVT::i32, and llvm::EVT::isVector().

ConvertBooleanCarryToCarryFlag()

static SDValue ConvertBooleanCarryToCarryFlag ( SDValue  BoolCarry, SelectionDAG &  DAG  )

static

Definition at line 4987 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, and llvm::ARMISD::SUBC.

Referenced by LowerADDSUBCARRY(), and LowerSETCCCARRY().

ConvertCarryFlagToBooleanCarry()

static SDValue ConvertCarryFlagToBooleanCarry ( SDValue  Flags, EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 5000 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDE, DL, Flags, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), and llvm::MVT::i32.

Referenced by LowerADDSUBCARRY().

createGPRPairNode()

static SDValue createGPRPairNode ( SelectionDAG &  DAG, SDValue  V  )

static

Definition at line 10374 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::ISD::SRL, std::swap(), and llvm::MVT::Untyped.

emitPostLd()

static void emitPostLd ( MachineBasicBlock *  BB, MachineBasicBlock::iterator  Pos, const TargetInstrInfo *  TII, const DebugLoc &  dl, unsigned  LdSize, unsigned  Data, unsigned  AddrIn, unsigned  AddrOut, bool  IsThumb1, bool  IsThumb2  )

static

Emit a post-increment load operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11280 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, llvm::RegState::Define, getLdOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

emitPostSt()

static void emitPostSt ( MachineBasicBlock *  BB, MachineBasicBlock::iterator  Pos, const TargetInstrInfo *  TII, const DebugLoc &  dl, unsigned  StSize, unsigned  Data, unsigned  AddrIn, unsigned  AddrOut, bool  IsThumb1, bool  IsThumb2  )

static

Emit a post-increment store operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11321 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, getStOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

Expand64BitShift()

static SDValue Expand64BitShift ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 6621 of file ARMISelLowering.cpp.

References llvm::ARMISD::ASRL, assert(), llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::isOneConstant(), llvm::Lo, llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, N, llvm::ARMISD::RRX, llvm::ISD::SHL, llvm::SelectionDAG::SplitScalar(), llvm::ISD::SRA, llvm::ARMISD::SRA_FLAG, llvm::ISD::SRL, llvm::ARMISD::SRL_FLAG, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

expandf64Toi32()

static void expandf64Toi32 ( SDValue  Op, SelectionDAG &  DAG, SDValue &  RetVal1, SDValue &  RetVal2  )

static

Definition at line 5598 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::commonAlignment(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, isFloatingPointZero(), llvm_unreachable, and Ptr.

ExpandREAD_REGISTER()

static void ExpandREAD_REGISTER ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG  )

static

Definition at line 6145 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, N, llvm::MVT::Other, llvm::ISD::READ_REGISTER, and Results.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

FindBFIToCombineWith()

static SDValue FindBFIToCombineWith ( SDNode *  N )

static

Definition at line 14776 of file ARMISelLowering.cpp.

References llvm::ARMISD::BFI, BitsProperlyConcatenate(), From, N, and ParseBFI().

Referenced by PerformBFICombine().

findMUL_LOHI()

static SDValue findMUL_LOHI ( SDValue  V )

static

Definition at line 12718 of file ARMISelLowering.cpp.

References llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.

Referenced by AddCombineTo64bitMLAL().

findPointerConstIncrement()

static bool findPointerConstIncrement ( SDNode *  N, SDValue *  Ptr, SDValue *  CInc  )

static

Definition at line 16010 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, N, llvm::ISD::OR, Ptr, and llvm::ARMISD::VLD1_UPD.

Referenced by CombineBaseUpdate().

FPCCToARMCC()

static void FPCCToARMCC ( ISD::CondCode  CC, ARMCC::CondCodes &  CondCode, ARMCC::CondCodes &  CondCode2  )

static

FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.

Definition at line 2036 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARMCC::VC, and llvm::ARMCC::VS.

GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle ( unsigned  PFEntry, SDValue  LHS, SDValue  RHS, SelectionDAG &  DAG, const SDLoc &  dl  )

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 8392 of file ARMISelLowering.cpp.

References assert(), GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, LHS, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, RHS, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

genTPEntry()

static Register genTPEntry ( MachineBasicBlock *  TpEntry, MachineBasicBlock *  TpLoopBody, MachineBasicBlock *  TpExit, Register  OpSizeReg, const TargetInstrInfo *  TII, DebugLoc  Dl, MachineRegisterInfo &  MRI  )

static

Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.

Definition at line 11747 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::Kill, MRI, llvm::predOps(), and TII.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

genTPLoopBody()

static void genTPLoopBody ( MachineBasicBlock *  TpLoopBody, MachineBasicBlock *  TpEntry, MachineBasicBlock *  TpExit, const TargetInstrInfo *  TII, DebugLoc  Dl, MachineRegisterInfo &  MRI, Register  OpSrcReg, Register  OpDestReg, Register  ElementCountReg, Register  TotalIterationsReg, bool  IsMemcpy  )

static

Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.

These are used by later passes to generate tail predicated loops.

Definition at line 11785 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), MRI, llvm::ARMVCC::None, llvm::predOps(), llvm::ARMVCC::Then, and TII.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

getARMIndexedAddressParts()

static bool getARMIndexedAddressParts ( SDNode *  Ptr, EVT  VT, bool  isSEXTLoad, SDValue &  Base, SDValue &  Offset, bool &  isInc, SelectionDAG &  DAG  )

static

Definition at line 19639 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getShiftOpcForNode(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ARM_AM::no_shift, llvm::Offset, Ptr, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

getDivRemArgList()

static TargetLowering::ArgListTy getDivRemArgList ( const SDNode *  N, LLVMContext *  Context, const ARMSubtarget *  Subtarget  )

static

Definition at line 20560 of file ARMISelLowering.cpp.

References assert(), Context, llvm::EVT::getTypeForEVT(), isSigned(), llvm::ARMSubtarget::isTargetWindows(), N, llvm::ISD::SDIVREM, llvm::ISD::SREM, std::swap(), llvm::ISD::UDIVREM, and llvm::ISD::UREM.

getDivRemLibcall()

static RTLIB::Libcall getDivRemLibcall ( const SDNode *  N, MVT::SimpleValueType  SVT  )

static

Definition at line 20542 of file ARMISelLowering.cpp.

References assert(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, isSigned(), llvm_unreachable, N, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.

getExtensionTo64Bits()

static EVT getExtensionTo64Bits ( const EVT &  OrigVT )

static

Definition at line 9393 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.

getLdOpcode()

static unsigned getLdOpcode ( unsigned  LdSize, bool  IsThumb1, bool  IsThumb2  )

static

Return the load opcode for a given load size.

If load size >= 8, neon opcode will be returned.

Definition at line 11242 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

getMVEIndexedAddressParts()

static bool getMVEIndexedAddressParts ( SDNode *  Ptr, EVT  VT, Align  Alignment, bool  isSEXTLoad, bool  IsMasked, bool  isLE, SDValue &  Base, SDValue &  Offset, bool &  isInc, SelectionDAG &  DAG  )

static

Definition at line 19723 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::Offset, Ptr, RHS, llvm::ISD::SUB, llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

getPointerConstIncrement()

static unsigned getPointerConstIncrement ( unsigned  Opcode, SDValue  Ptr, SDValue  Inc, const SelectionDAG &  DAG  )

static

Definition at line 15988 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::ISD::OR, Ptr, and llvm::ARMISD::VLD1_UPD.

Referenced by CombineBaseUpdate().

getStOpcode()

static unsigned getStOpcode ( unsigned  StSize, bool  IsThumb1, bool  IsThumb2  )

static

Return the store opcode for a given store size.

If store size >= 8, neon opcode will be returned.

Definition at line 11261 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

getT2IndexedAddressParts()

static bool getT2IndexedAddressParts ( SDNode *  Ptr, EVT  VT, bool  isSEXTLoad, SDValue &  Base, SDValue &  Offset, bool &  isInc, SelectionDAG &  DAG  )

static

Definition at line 19698 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::Offset, Ptr, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

getVCMPCondCode()

static ARMCC::CondCodes getVCMPCondCode ( SDValue  N )

static

Definition at line 14562 of file ARMISelLowering.cpp.

References llvm_unreachable, N, llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.

Referenced by CanInvertMVEVCMP(), and PerformXORCombine().

getVectorTyFromPredicateVector()

static EVT getVectorTyFromPredicateVector ( EVT  VT )

static

Definition at line 8488 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v16i1, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::MVT::v8i1, and llvm::MVT::v8i16.

Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_i1(), LowerINSERT_VECTOR_ELT_i1(), and PromoteMVEPredVector().

getVShiftImm()

static bool getVShiftImm ( SDValue  Op, unsigned  ElementBits, int64_t &  Cnt  )

static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 6528 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

getZeroVector()

static SDValue getZeroVector ( EVT  VT, SelectionDAG &  DAG, const SDLoc &  dl  )

static

getZeroVector - Returns a vector of specified type with all zero elements.

Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 6279 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::EVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ARMISD::VMOVIMM.

Referenced by canonicalizeShuffleMaskWithHorizOp(), combineArithReduction(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), createVariablePermute(), getAVX2GatherNode(), getGatherNode(), getNullFPConstForNullVal(), getScalarMaskingNode(), getShuffleVectorZeroOrUndef(), getVectorMaskingNode(), LowerAVXCONCAT_VECTORS(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerCTTZ(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerSCALAR_TO_VECTOR(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleToEXPAND(), lowerShuffleWithSHUFPD(), lowerV16I8Shuffle(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), matchBinaryPermuteShuffle(), matchShuffleWithUNPCK(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), and widenSubVector().

hasNormalLoadOperand()

static bool hasNormalLoadOperand ( SDNode *  N )

static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.

If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 15155 of file ARMISelLowering.cpp.

References llvm::ISD::isNormalLoad(), and N.

Referenced by PerformBUILD_VECTORCombine().

IntCCToARMCC()

static ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode  CC )

static

IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.

Definition at line 2019 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by LowerSETCCCARRY().

isAddSubSExt()

static bool isAddSubSExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 9510 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.

isAddSubZExt()

static bool isAddSubZExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 9521 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.

IsCMPZCSINC()

static SDValue IsCMPZCSINC ( SDNode *  Cmp, ARMCC::CondCodes &  CC  )

static

Definition at line 14882 of file ARMISelLowering.cpp.

References llvm::ISD::AND, CC, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::ARMISD::CSINC, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::SDNode::hasOneUse(), llvm::isNullConstant(), and llvm::isOneConstant().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), PerformCMPZCombine(), and PerformCSETCombine().

isConditionalZeroOrAllOnes()

static bool isConditionalZeroOrAllOnes ( SDNode *  N, bool  AllOnes, SDValue &  CC, bool &  Invert, SDValue &  OtherOp, SelectionDAG &  DAG  )

static

Definition at line 12416 of file ARMISelLowering.cpp.

References llvm::AllOnes, CC, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::MVT::i1, isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineSelectAndUse().

isExtendedBUILD_VECTOR()

static bool isExtendedBUILD_VECTOR ( SDNode *  N, SelectionDAG &  DAG, bool  isSigned  )

static

isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.

Definition at line 9321 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), llvm::DataLayout::isBigEndian(), llvm::isIntN(), isSigned(), llvm::isUIntN(), llvm::ConstantSDNode::isZero(), N, llvm::MVT::v2i64, and llvm::MVT::v4i32.

isFloatingPointZero()

static bool isFloatingPointZero ( SDValue  Op )

static

isFloatingPointZero - Return true if this is +0.0.

Definition at line 4689 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f64, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), llvm::isNullConstant(), llvm::ARMISD::VMOVIMM, and llvm::ARMISD::Wrapper.

Referenced by bitcastf32Toi32(), canChangeToInt(), and expandf64Toi32().

isGTorGE()

static bool isGTorGE ( ISD::CondCode  CC )

static

Definition at line 5247 of file ARMISelLowering.cpp.

References CC, llvm::ISD::SETGE, and llvm::ISD::SETGT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

isHomogeneousAggregate()

static bool isHomogeneousAggregate ( Type *  Ty, HABaseType &  Base, uint64_t &  Members  )

static

Definition at line 21846 of file ARMISelLowering.cpp.

References llvm::sampleprof::Base, HA_DOUBLE, HA_FLOAT, HA_UNKNOWN, HA_VECT128, HA_VECT64, llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), and isHomogeneousAggregate().

Referenced by llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(), and isHomogeneousAggregate().

isLegalAddressImmediate()

static bool isLegalAddressImmediate ( int64_t  V, EVT  VT, const ARMSubtarget *  Subtarget  )

static

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 19432 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().

isLegalMVEShuffleOp()

static bool isLegalMVEShuffleOp ( unsigned  PFEntry )

static

Definition at line 8319 of file ARMISelLowering.cpp.

References OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, and OP_VREV.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isLegalT1AddressImmediate()

static bool isLegalT1AddressImmediate ( int64_t  V, EVT  VT  )

static

Definition at line 19352 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

isLegalT2AddressImmediate()

static bool isLegalT2AddressImmediate ( int64_t  V, EVT  VT, const ARMSubtarget *  Subtarget  )

static

Definition at line 19378 of file ARMISelLowering.cpp.

References llvm::MVT::f16, llvm::MVT::f32, llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

isLowerSaturate()

static bool isLowerSaturate ( const SDValue  LHS, const SDValue  RHS, const SDValue  TrueVal, const SDValue  FalseVal, const ISD::CondCode  CC, const SDValue  K  )

static

Definition at line 5261 of file ARMISelLowering.cpp.

References CC, isGTorGE(), isLTorLE(), LHS, and RHS.

Referenced by isLowerSaturatingConditional().

isLowerSaturatingConditional()

static bool isLowerSaturatingConditional ( const SDValue &  Op, SDValue &  V, SDValue &  SatK  )

static

Definition at line 5353 of file ARMISelLowering.cpp.

References CC, isLowerSaturate(), LHS, and RHS.

isLTorLE()

static bool isLTorLE ( ISD::CondCode  CC )

static

Definition at line 5251 of file ARMISelLowering.cpp.

References CC, llvm::ISD::SETLE, and llvm::ISD::SETLT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

isNEONTwoResultShuffleMask()

static unsigned isNEONTwoResultShuffleMask ( ArrayRef< int >  ShuffleMask, EVT  VT, unsigned &  WhichResult, bool &  isV_UNDEF  )

static

Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.

Definition at line 7470 of file ARMISelLowering.cpp.

References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isPowerOf2Constant()

static const APInt * isPowerOf2Constant ( SDValue  V )

static

Definition at line 17931 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, and llvm::APInt::isPowerOf2().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), and llvm::ARMTargetLowering::PerformCMOVToBFICombine().

IsQRMVEInstruction()

static bool IsQRMVEInstruction ( const SDNode *  N, const SDNode *  Op  )

static

Definition at line 7790 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::MUL, N, llvm::ISD::SADDSAT, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.

isReverseMask()

static bool isReverseMask ( ArrayRef< int >  M, EVT  VT  )

static

Returns

true if this is a reverse operation on an vector.

Definition at line 7493 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ShuffleVectorInst::isReverse(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ARMTargetLowering::isShuffleMaskLegal(), LowerVECTOR_SHUFFLE(), and LowerVECTOR_SHUFFLE_i1().

isS16()

static bool isS16 ( const SDValue &  Op, SelectionDAG &  DAG  )

static

Definition at line 2012 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), isSHL16(), and isSRA16().

Referenced by AddCombineTo64BitSMLAL16(), and PerformORCombineToSMULWBT().

isSHL16()

static bool isSHL16 ( const SDValue &  Op )

static

Definition at line 2000 of file ARMISelLowering.cpp.

References llvm::ISD::SHL.

Referenced by isS16(), and PerformORCombineToSMULWBT().

isSignExtended()

static bool isSignExtended ( SDNode *  N, SelectionDAG &  DAG  )

static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 9374 of file ARMISelLowering.cpp.

References isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), N, and llvm::ISD::SIGN_EXTEND.

IsSingleInstrConstant()

static SDValue IsSingleInstrConstant ( SDValue  N, SelectionDAG &  DAG, const ARMSubtarget *  ST, const SDLoc &  dl  )

static

Definition at line 7676 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getSOImmVal(), llvm::MVT::i32, and N.

isSingletonVEXTMask()

static bool isSingletonVEXTMask ( ArrayRef< int >  M, EVT  VT, unsigned &  Imm  )

static

Definition at line 7171 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by LowerVECTOR_SHUFFLE().

isSRA16()

static bool isSRA16 ( const SDValue &  Op )

static

Definition at line 1992 of file ARMISelLowering.cpp.

References llvm::ISD::SRA.

Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().

isSRL16()

static bool isSRL16 ( const SDValue &  Op )

static

Definition at line 1984 of file ARMISelLowering.cpp.

References llvm::ISD::SRL.

Referenced by PerformORCombineToSMULWBT().

isTruncMask()

static bool isTruncMask ( ArrayRef< int >  M, EVT  VT, bool  Top, bool  SingleSource  )

static

Definition at line 7507 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), llvm::Upper, llvm::MVT::v16i8, and llvm::MVT::v8i16.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isValidBaseUpdate()

static bool isValidBaseUpdate ( SDNode *  N, SDNode *  User  )

static

Definition at line 16034 of file ARMISelLowering.cpp.

References llvm::SDNode::hasPredecessorHelper(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by CombineBaseUpdate().

isValidMVECond()

static bool isValidMVECond ( unsigned  CC, bool  IsFloat  )

static

Definition at line 14545 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LT, and llvm::ARMCC::NE.

Referenced by CanInvertMVEVCMP(), and PerformVCMPCombine().

isVEXTMask()

static bool isVEXTMask ( ArrayRef< int >  M, EVT  VT, bool &  ReverseVEXT, unsigned &  Imm  )

static

Definition at line 7199 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isVMOVModifiedImm()

static SDValue isVMOVModifiedImm ( uint64_t  SplatBits, uint64_t  SplatUndef, unsigned  SplatBitSize, SelectionDAG &  DAG, const SDLoc &  dl, EVT &  VT, EVT  VectorVT, VMOVModImmType  type  )

static

isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).

If so, return the encoded value.

Definition at line 6911 of file ARMISelLowering.cpp.

References assert(), llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::DataLayout::isBigEndian(), llvm_unreachable, llvm::MVEVMVNModImm, llvm::OtherModImm, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::VMOVModImm.

Referenced by PerformANDCombine(), and PerformORCombine().

isVMOVNMask()

static bool isVMOVNMask ( ArrayRef< int >  M, EVT  VT, bool  Top, bool  SingleSource  )

static

Definition at line 7529 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), N, llvm::Offset, llvm::MVT::v16i8, and llvm::MVT::v8i16.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isVMOVNTruncMask()

static bool isVMOVNTruncMask ( ArrayRef< int >  M, EVT  ToVT, bool  rev  )

static

Definition at line 7553 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::PerformMVETruncCombine(), and PerformShuffleVMOVNCombine().

isVShiftLImm()

static bool isVShiftLImm ( SDValue  Op, EVT  VT, bool  isLong, int64_t &  Cnt  )

static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 6549 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

isVShiftRImm()

static bool isVShiftRImm ( SDValue  Op, EVT  VT, bool  isNarrow, bool  isIntrinsic, int64_t &  Cnt  )

static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 6563 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

isVTBLMask()

static bool isVTBLMask ( ArrayRef< int >  M, EVT  VT  )

static

Definition at line 7235 of file ARMISelLowering.cpp.

References llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().

isVTRN_v_undef_Mask()

static bool isVTRN_v_undef_Mask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 7302 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

isVTRNMask()

static bool isVTRNMask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

Definition at line 7270 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

isVUZP_v_undef_Mask()

static bool isVUZP_v_undef_Mask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 7364 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

isVUZPMask()

static bool isVUZPMask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

Definition at line 7334 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

IsVUZPShuffleNode()

static bool IsVUZPShuffleNode ( SDNode *  N )

static

Definition at line 12528 of file ARMISelLowering.cpp.

References N, llvm::MVT::v2i32, llvm::ARMISD::VTRN, and llvm::ARMISD::VUZP.

Referenced by AddCombineToVPADD(), and AddCombineVUZPToVPADDL().

isVZIP_v_undef_Mask()

static bool isVZIP_v_undef_Mask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 7438 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

isVZIPMask()

static bool isVZIPMask ( ArrayRef< int >  M, EVT  VT, unsigned &  WhichResult  )

static

Definition at line 7405 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

isZeroExtended()

static bool isZeroExtended ( SDNode *  N, SelectionDAG &  DAG  )

static

isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 9384 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), N, and llvm::ISD::ZERO_EXTEND.

isZeroOrAllOnes()

static bool isZeroOrAllOnes ( SDValue  N, bool  AllOnes  )

inlinestatic

Definition at line 12400 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::isAllOnesConstant(), llvm::isNullConstant(), and N.

Referenced by combineSelectAndUse(), and isConditionalZeroOrAllOnes().

isZeroVector()

static bool isZeroVector ( SDValue  N )

static

Definition at line 10161 of file ARMISelLowering.cpp.

References llvm::ISD::isBuildVectorAllZeros(), llvm::isNullConstant(), N, and llvm::ARMISD::VMOVIMM.

Referenced by findZeroVectorIdx(), LowerMLOAD(), PerformSUBCombine(), and PerformVCMPCombine().

LowerADDSUBCARRY()

static SDValue LowerADDSUBCARRY ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 9790 of file ARMISelLowering.cpp.

References llvm::ISD::ADDCARRY, llvm::ARMISD::ADDE, ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::ISD::MERGE_VALUES, N, llvm::ISD::SUB, and llvm::ARMISD::SUBE.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerADDSUBSAT()

static SDValue LowerADDSUBSAT ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 5048 of file ARMISelLowering.cpp.

References llvm::Add, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSimpleVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isSimple(), llvm::ARMISD::QADD16b, llvm::ARMISD::QADD8b, llvm::ARMISD::QSUB16b, llvm::ARMISD::QSUB8b, llvm::ISD::SADDSAT, llvm::MVT::SimpleTy, llvm::ISD::SSUBSAT, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, llvm::ARMISD::UQADD16b, llvm::ARMISD::UQADD8b, llvm::ARMISD::UQSUB16b, llvm::ARMISD::UQSUB8b, and llvm::ISD::USUBSAT.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerATOMIC_FENCE()

static SDValue LowerATOMIC_FENCE ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 4228 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isMClass(), llvm::ARMISD::MEMBARRIER_MCR, llvm::MVT::Other, llvm::Release, llvm::SyncScope::SingleThread, and llvm::ARM_MB::SY.

Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerAtomicLoadStore()

static SDValue LowerAtomicLoadStore ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 10341 of file ARMISelLowering.cpp.

References llvm::isStrongerThanMonotonic().

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerBUILD_VECTOR_i1()

static SDValue LowerBUILD_VECTOR_i1 ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 7693 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::sampleprof::Base, llvm::drop_begin(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SIGN_EXTEND_INREG.

LowerBUILD_VECTORToVIDUP()

static SDValue LowerBUILD_VECTORToVIDUP ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 7755 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), I, llvm::MVT::i32, N, and llvm::ARMISD::VIDUP.

LowerBuildVectorOfFPExt()

static SDValue LowerBuildVectorOfFPExt ( SDValue  BV, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 7634 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, Idx, llvm::Offset, llvm::MVT::v4f32, llvm::MVT::v8f16, and llvm::ARMISD::VCVTL.

LowerBuildVectorOfFPTrunc()

static SDValue LowerBuildVectorOfFPTrunc ( SDValue  BV, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 7581 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::i32, Idx, llvm::MVT::v4f32, llvm::MVT::v8f16, and llvm::ARMISD::VCVTN.

LowerCONCAT_VECTORS()

static SDValue LowerCONCAT_VECTORS ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9130 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::MVT::f64, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), LowerCONCAT_VECTORS_i1(), and llvm::MVT::v2f64.

Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerSDIV(), and LowerUDIV().

LowerCONCAT_VECTORS_i1()

static SDValue LowerCONCAT_VECTORS_i1 ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9057 of file ARMISelLowering.cpp.

References assert(), E, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), I, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::isPowerOf2_32(), llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::SmallVectorImpl< T >::resize(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::UNDEF, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VECTOR_REG_CAST.

Referenced by LowerCONCAT_VECTORS().

LowerCTPOP()

static SDValue LowerCTPOP ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 6492 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i8.

LowerCTTZ()

static SDValue LowerCTTZ ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 6436 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITREVERSE, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isVector(), N, llvm::ISD::SUB, llvm::ARMISD::VMOVIMM, and X.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerEXTRACT_SUBVECTOR()

static SDValue LowerEXTRACT_SUBVECTOR ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9155 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::ISD::UNDEF, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::ARMISD::VCMPZ.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerEXTRACT_VECTOR_ELT()

static SDValue LowerEXTRACT_VECTOR_ELT ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9036 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::i32, LowerEXTRACT_VECTOR_ELT_i1(), and llvm::ARMISD::VGETLANEu.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerEXTRACT_VECTOR_ELT_i1()

static SDValue LowerEXTRACT_VECTOR_ELT_i1 ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9018 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getVectorTyFromPredicateVector(), llvm::MVT::i32, llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SRL.

Referenced by LowerEXTRACT_VECTOR_ELT().

LowerFP_TO_INT_SAT()

static SDValue LowerFP_TO_INT_SAT ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 5905 of file ARMISelLowering.cpp.

References DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMIN, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8f16, and llvm::MVT::v8i16.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerINSERT_VECTOR_ELT_i1()

static SDValue LowerINSERT_VECTOR_ELT_i1 ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 8955 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::BFI, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getValueType(), getVectorTyFromPredicateVector(), llvm::MVT::i1, llvm::MVT::i32, llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SIGN_EXTEND_INREG.

LowerInterruptReturn()

static SDValue LowerInterruptReturn ( SmallVectorImpl< SDValue > &  RetOps, const SDLoc &  DL, SelectionDAG &  DAG  )

static

Definition at line 3133 of file ARMISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), DL, F, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::SmallVectorImpl< T >::insert(), llvm::ARMISD::INTRET_FLAG, llvm::MVT::Other, and llvm::report_fatal_error().

LowerMLOAD()

static SDValue LowerMLOAD ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 10167 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::MVT::i32, llvm::SDValue::isUndef(), isZeroVector(), N, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerMUL()

static SDValue LowerMUL ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 9532 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), SkipExtensionForVMULL(), std::swap(), llvm::MVT::v2i64, llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerPredicateLoad()

static SDValue LowerPredicateLoad ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 10034 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ISD::NON_EXTLOAD, llvm::ARMISD::PREDICATE_CAST, llvm::ISD::SRL, llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerPredicateStore()

static SDValue LowerPredicateStore ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 10091 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), I, llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ARMISD::PREDICATE_CAST, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SRL, llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.

Referenced by LowerSTORE().

LowerPREFETCH()

static SDValue LowerPREFETCH ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 4265 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::MVT::Other, and llvm::ARMISD::PRELOAD.

LowerReverse_VECTOR_SHUFFLE()

static SDValue LowerReverse_VECTOR_SHUFFLE ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 8469 of file ARMISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::v16i8, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::ARMISD::VREV64.

Referenced by LowerVECTOR_SHUFFLE().

LowerSaturatingConditional()

static SDValue LowerSaturatingConditional ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 5287 of file ARMISelLowering.cpp.

References llvm::countr_one(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), isGTorGE(), isLTorLE(), llvm::isPowerOf2_64(), llvm::ISD::SELECT_CC, llvm::ARMISD::SSAT, and llvm::ARMISD::USAT.

LowerSDIV()

static SDValue LowerSDIV ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9677 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::MVT::v4i16, llvm::MVT::v8i16, and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerSDIV_v4i16()

static SDValue LowerSDIV_v4i16 ( SDValue  N0, SDValue  N1, const SDLoc &  dl, SelectionDAG &  DAG  )

static

Definition at line 9638 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.

Referenced by LowerSDIV(), and LowerUDIV().

LowerSDIV_v4i8()

static SDValue LowerSDIV_v4i8 ( SDValue  X, SDValue  Y, const SDLoc &  dl, SelectionDAG &  DAG  )

static

Definition at line 9607 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, X, and Y.

Referenced by LowerSDIV().

LowerSETCCCARRY()

static SDValue LowerSETCCCARRY ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 6878 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::CMOV, Cond, ConvertBooleanCarryToCarryFlag(), DL, llvm::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, IntCCToARMCC(), LHS, RHS, llvm::ISD::SUB, and llvm::ARMISD::SUBE.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerShift()

static SDValue LowerShift ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 6578 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::MVT::i32, llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHLs, llvm::ARMISD::VSHLu, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.

Referenced by lowerBuildVectorToBitOp(), llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerSTORE()

static SDValue LowerSTORE ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 10129 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isLittleEndian(), llvm::ARMSubtarget::isThumb1Only(), llvm::Lo, LowerPredicateStore(), N, llvm::MVT::Other, llvm::ARMISD::STRD, llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::SparcTargetLowering::LowerOperation().

LowerTruncate()

static SDValue LowerTruncate ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 9225 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::Hi, llvm::MVT::i1, llvm::Lo, LowerTruncatei1(), llvm::ARMISD::MVETRUNC, N, llvm::SelectionDAG::SplitVectorOperand(), llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::MVT::v8i32.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerTruncatei1()

static SDValue LowerTruncatei1 ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9209 of file ARMISelLowering.cpp.

References llvm::And, llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, llvm::ISD::SETNE, llvm::MVT::v16i1, llvm::MVT::v4i1, and llvm::MVT::v8i1.

Referenced by LowerTruncate().

LowerUDIV()

static SDValue LowerUDIV ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 9713 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVASTART()

static SDValue LowerVASTART ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 4292 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), and llvm::SelectionDAG::getTargetLoweringInfo().

LowerVecReduce()

static SDValue LowerVecReduce ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 10194 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_XOR, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and LowerVecReduceF().

LowerVecReduceF()

static SDValue LowerVecReduceF ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 10260 of file ARMISelLowering.cpp.

References LowerVecReduce().

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVecReduceMinMax()

static SDValue LowerVecReduceMinMax ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 10267 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm_unreachable, llvm::Lo, llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SplitVector(), llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVECTOR_SHUFFLE()

static SDValue LowerVECTOR_SHUFFLE ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 8727 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, Cost, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::MVT::i32, isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), isTruncMask(), llvm::SDValue::isUndef(), isVEXTMask(), isVMOVNMask(), llvm::isVREVMask(), llvm::Lo, LowerReverse_VECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), llvm::ARMISD::MVETRUNC, PerfectShuffleTable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ArrayRef< T >::size(), llvm::ISD::SRL, std::swap(), llvm::MVT::v16i8, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VEXT, llvm::ARMISD::VMOVN, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ARMISD::VREV64.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVECTOR_SHUFFLE_i1()

static SDValue LowerVECTOR_SHUFFLE_i1 ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 8538 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::i32, isReverseMask(), llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::ISD::SRL, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VECTOR_REG_CAST.

Referenced by LowerVECTOR_SHUFFLE().

LowerVECTOR_SHUFFLEUsingMovs()

static SDValue LowerVECTOR_SHUFFLEUsingMovs ( SDValue  Op, ArrayRef< int >  ShuffleMask, SelectionDAG &  DAG  )

static

Definition at line 8590 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::i32, llvm::Length, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v8f16, and llvm::MVT::v8i16.

Referenced by LowerVECTOR_SHUFFLE().

LowerVECTOR_SHUFFLEUsingOneOff()

static SDValue LowerVECTOR_SHUFFLEUsingOneOff ( SDValue  Op, ArrayRef< int >  ShuffleMask, SelectionDAG &  DAG  )

static

Definition at line 8676 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, and llvm::ISD::INSERT_VECTOR_ELT.

Referenced by LowerVECTOR_SHUFFLE().

LowerVECTOR_SHUFFLEv8i8()

static SDValue LowerVECTOR_SHUFFLEv8i8 ( SDValue  Op, ArrayRef< int >  ShuffleMask, SelectionDAG &  DAG  )

static

Definition at line 8449 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), I, llvm::MVT::i32, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MVT::v8i8, llvm::ARMISD::VTBL1, and llvm::ARMISD::VTBL2.

Referenced by LowerVECTOR_SHUFFLE().

LowerVectorExtend()

static SDValue LowerVectorExtend ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 9285 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i8, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, llvm::ISD::SIGN_EXTEND, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::MVT::v8i32.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerVectorFP_TO_INT()

static SDValue LowerVectorFP_TO_INT ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 5836 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::TRUNCATE, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, and llvm::MVT::v8i16.

LowerVectorINT_TO_FP()

static SDValue LowerVectorINT_TO_FP ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 5942 of file ARMISelLowering.cpp.

References assert(), llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::ISD::ZERO_EXTEND.

LowerVSETCC()

static SDValue LowerVSETCC ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 6698 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, CC, llvm::EVT::changeVectorElementTypeToInteger(), llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, std::swap(), llvm::ARMISD::VCMP, llvm::ARMISD::VCMPZ, llvm::ARMISD::VREV64, and llvm::ARMISD::VTST.

Referenced by combineSetCC(), and llvm::ARMTargetLowering::LowerOperation().

LowerWRITE_REGISTER()

static SDValue LowerWRITE_REGISTER ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 3427 of file ARMISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::Lo, llvm::MVT::Other, llvm::SelectionDAG::SplitScalar(), and llvm::ISD::WRITE_REGISTER.

Referenced by llvm::ARMTargetLowering::LowerOperation().

MatchingStackOffset()

static bool MatchingStackOffset ( SDValue  Arg, unsigned  Offset, ISD::ArgFlagsTy  Flags, MachineFrameInfo &  MFI, const MachineRegisterInfo *  MRI, const TargetInstrInfo *  TII  )

static

MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.

Definition at line 2942 of file ARMISelLowering.cpp.

References Arg, assert(), llvm::ISD::CopyFromReg, Flags, llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::Register::isVirtual(), MRI, llvm::Offset, Ptr, and TII.

OtherSucc()

static MachineBasicBlock * OtherSucc ( MachineBasicBlock *  MBB, MachineBasicBlock *  Succ  )

static

Definition at line 11233 of file ARMISelLowering.cpp.

References llvm_unreachable, MBB, and llvm::MachineBasicBlock::successors().

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

ParseBFI()

static SDValue ParseBFI ( SDNode *  N, APInt &  ToMask, APInt &  FromMask  )

static

Definition at line 14747 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::BFI, From, llvm::APInt::getBitWidth(), llvm::APInt::getLimitedValue(), llvm::APInt::getLowBitsSet(), N, llvm::APInt::popcount(), and llvm::ISD::SRL.

Referenced by FindBFIToCombineWith(), and PerformBFICombine().

PerformABSCombine()

static SDValue PerformABSCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 13423 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::expandABS(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::isOperationLegal(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDCombine()

static SDValue PerformADDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 13927 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, N, PerformADDCombineWithOperands(), PerformADDVecReduce(), and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDCombineWithOperands()

static SDValue PerformADDCombineWithOperands ( SDNode *  N, SDValue  N0, SDValue  N1, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.

This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 13455 of file ARMISelLowering.cpp.

References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.

Referenced by PerformADDCombine().

PerformAddcSubcCombine()

static SDValue PerformAddcSubcCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 13045 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::isNullConstant(), llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), LHS, N, RHS, and llvm::ARMISD::SUBC.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDECombine()

static SDValue PerformADDECombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.

Definition at line 13438 of file ARMISelLowering.cpp.

References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), N, and PerformAddeSubeCombine().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformAddeSubeCombine()

static SDValue PerformAddeSubeCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 13078 of file ARMISelLowering.cpp.

References AddCombineTo64bitMLAL(), llvm::ARMISD::ADDE, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb1Only(), N, RHS, llvm::ISD::SMUL_LOHI, and llvm::ARMISD::SUBE.

Referenced by PerformADDECombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDVecReduce()

static SDValue PerformADDVecReduce ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 13621 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BUILD_PAIR, E, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), I, llvm::MVT::i32, llvm::MVT::i64, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::SplitScalar(), TryDistrubutionADDVecReduce(), llvm::ARMISD::VADDLVAps, llvm::ARMISD::VADDLVApu, llvm::ARMISD::VADDLVAs, llvm::ARMISD::VADDLVAu, llvm::ARMISD::VADDLVps, llvm::ARMISD::VADDLVpu, llvm::ARMISD::VADDLVs, llvm::ARMISD::VADDLVu, llvm::ARMISD::VMLALVAps, llvm::ARMISD::VMLALVApu, llvm::ARMISD::VMLALVAs, llvm::ARMISD::VMLALVAu, llvm::ARMISD::VMLALVps, llvm::ARMISD::VMLALVpu, llvm::ARMISD::VMLALVs, and llvm::ARMISD::VMLALVu.

Referenced by PerformADDCombine().

PerformANDCombine()

static SDValue PerformANDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 14309 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, CombineANDShift(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformSHLSimplify(), llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v4i1, llvm::MVT::v8i1, and llvm::ARMISD::VBICIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformARMBUILD_VECTORCombine()

static SDValue PerformARMBUILD_VECTORCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.

Definition at line 15200 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i32, Idx, llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformBFICombine()

static SDValue PerformBFICombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 14807 of file ARMISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::ARMISD::BFI, llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::countr_zero(), FindBFIToCombineWith(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), N, ParseBFI(), and llvm::ISD::SRL.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformBITCASTCombine()

static SDValue PerformBITCASTCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  ST  )

static

Definition at line 18422 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::DataLayout::isBigEndian(), N, PerformExtractEltToVMOVRRD(), llvm::ARMISD::VDUP, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMOVFPIMM, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformBUILD_VECTORCombine()

static SDValue PerformBUILD_VECTORCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.

Definition at line 15167 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), llvm::MVT::i64, N, PerformVMOVDRRCombine(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformCMPZCombine()

static SDValue PerformCMPZCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 14915 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, Cond, llvm::ARMCC::EQ, IsCMPZCSINC(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformCSETCombine()

static SDValue PerformCSETCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 14928 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, Cond, llvm::ARMCC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMCC::getOppositeCondition(), llvm::MVT::i32, IsCMPZCSINC(), N, and llvm::ARMCC::NE.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformExtendCombine()

static SDValue PerformExtendCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.

Definition at line 17730 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, N, PerformSplittingToWideningLoad(), llvm::ISD::SIGN_EXTEND, llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformExtractEltCombine()

static SDValue PerformExtractEltCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  ST  )

static

Definition at line 15472 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ARMISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, Idx, llvm::ARMISD::MVETRUNC, N, llvm::Offset, PerformExtractEltToVMOVRRD(), llvm::MVT::v2f64, llvm::MVT::v4i32, llvm::ARMISD::VDUP, llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVhr, llvm::ARMISD::VMOVrh, and X.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformExtractEltToVMOVRRD()

static SDValue PerformExtractEltToVMOVRRD ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 15411 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::find_if(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SDNode::use_begin(), llvm::SDNode::use_size(), llvm::SDNode::uses(), llvm::MVT::v2f64, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVRRD.

Referenced by PerformBITCASTCombine(), and PerformExtractEltCombine().

PerformExtractFpToIntStores()

static SDValue PerformExtractFpToIntStores ( StoreSDNode *  St, SelectionDAG &  DAG  )

static

Definition at line 16673 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNodeIfExists(), llvm::SDNode::getOpcode(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), and llvm::ARMISD::VGETLANEu.

Referenced by PerformSTORECombine().

PerformFAddVSelectCombine()

static SDValue PerformFAddVSelectCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 16844 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::FAdd, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNodeFlags::hasNoSignedZeros(), N, std::swap(), llvm::MVT::v4f32, llvm::MVT::v8f16, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformFPExtendCombine()

static SDValue PerformFPExtendCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 17773 of file ARMISelLowering.cpp.

References N, and PerformSplittingToWideningLoad().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformHWLoopCombine()

static SDValue PerformHWLoopCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  ST  )

static

Definition at line 18072 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BR, llvm::ISD::BR_CC, llvm::ISD::BRCOND, CC, Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, Int, llvm::ARMISD::LE, llvm::ARMISD::LOOP_DEC, N, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), SearchLoopIntrinsic(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULT, Size, llvm::ISD::TokenFactor, llvm::ARMISD::WLS, and llvm::ARMISD::WLSSETUP.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformInsertEltCombine()

static SDValue PerformInsertEltCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.

Definition at line 15382 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isNormalLoad(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformInsertSubvectorCombine()

static SDValue PerformInsertSubvectorCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 15548 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::Lo, and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformLOADCombine()

static SDValue PerformLOADCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 16437 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformLongShiftCombine()

static SDValue PerformLongShiftCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 17316 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, Merge, N, and llvm::SelectionDAG::ReplaceAllUsesWith().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMinMaxCombine()

static SDValue PerformMinMaxCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.

Definition at line 17825 of file ARMISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::MVT::i32, llvm::ISD::isConstantSplatVector(), N, PerformMinMaxToSatCombine(), PerformVQDMULHCombine(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, std::swap(), llvm::ISD::UMIN, llvm::MVT::v16i8, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VQMOVNs, and llvm::ARMISD::VQMOVNu.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMinMaxToSatCombine()

static SDValue PerformMinMaxToSatCombine ( SDValue  Op, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 17784 of file ARMISelLowering.cpp.

References llvm::APInt::countr_one(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb2(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ARMISD::SSAT, std::swap(), and llvm::ARMISD::USAT.

Referenced by PerformMinMaxCombine().

PerformMULCombine()

static SDValue PerformMULCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 14119 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::ARMSubtarget::isThumb1Only(), llvm::Log2_32(), N, PerformMVEVMULLCombine(), PerformVMULCombine(), llvm::ISD::SHL, llvm::ISD::SUB, and llvm::MVT::v2i64.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMVEVLDCombine()

static SDValue PerformMVEVLDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 16151 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasPredecessorHelper(), llvm::MVT::i32, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm_unreachable, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VST2_UPD, and llvm::ARMISD::VST4_UPD.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMVEVMULLCombine()

static SDValue PerformMVEVMULLCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 14054 of file ARMISelLowering.cpp.

References llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isAllOnesConstant(), llvm::ARMSubtarget::isLittle(), llvm::isNullConstant(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.

Referenced by PerformMULCombine().

PerformORCombine()

static SDValue PerformORCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformORCombine - Target-specific dag combine xforms for ISD::OR.

Definition at line 14602 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), PerformSHLSimplify(), llvm::MVT::v16i1, llvm::MVT::v2i1, llvm::MVT::v2i32, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::MVT::v8i1, llvm::ARMISD::VBSP, and llvm::ARMISD::VORRIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformORCombine_i1()

static SDValue PerformORCombine_i1 ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 14576 of file ARMISelLowering.cpp.

References llvm::And, llvm::ISD::AND, CanInvertMVEVCMP(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNode(), N, llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.

Referenced by PerformORCombine().

PerformORCombineToBFI()

static SDValue PerformORCombineToBFI ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 14419 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ARMISD::BFI, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ARM::isBitFieldInvertedMask(), llvm::ARMSubtarget::isThumb1Only(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by PerformORCombine().

PerformORCombineToSMULWBT()

static SDValue PerformORCombineToSMULWBT ( SDNode *  OR, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 14359 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::i32, isS16(), isSHL16(), isSRA16(), isSRL16(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SHL, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SMULWB, llvm::ARMISD::SMULWT, and llvm::ISD::SRL.

Referenced by PerformORCombine().

PerformPREDICATE_CASTCombine()

static SDValue PerformPREDICATE_CASTCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 15291 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i32, llvm::isBitwiseNot(), N, llvm::ARMISD::PREDICATE_CAST, llvm::TargetLowering::SimplifyDemandedBits(), X, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformReduceShuffleCombine()

static SDValue PerformReduceShuffleCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 17206 of file ARMISelLowering.cpp.

References E, llvm::SelectionDAG::getNode(), llvm::APInt::isAllOnes(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::APInt::setBit().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSELECTCombine()

static SDValue PerformSELECTCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 13106 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, CC, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::i32, LHS, N, Reduction, RHS, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULT, std::swap(), llvm::ISD::TRUNCATE, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ARMISD::VMAXVs, llvm::ARMISD::VMAXVu, llvm::ARMISD::VMINVs, and llvm::ARMISD::VMINVu.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformShiftCombine()

static SDValue PerformShiftCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  ST  )

static

PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.

As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.

Definition at line 17572 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSHLSimplify()

static SDValue PerformSHLSimplify ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  ST  )

static

Definition at line 13819 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ARMISD::CMP, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), llvm::SDValue::dump(), llvm::dump(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LLVM_DEBUG, llvm::APInt::lshrInPlace(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SUB, llvm::APInt::uge(), X, and llvm::ISD::XOR.

Referenced by PerformADDCombine(), PerformANDCombine(), PerformORCombine(), and PerformXORCombine().

PerformShuffleVMOVNCombine()

static SDValue PerformShuffleVMOVNCombine ( ShuffleVectorSDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 15589 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, isVMOVNTruncMask(), llvm::ARMISD::MVETRUNC, N, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVN.

Referenced by PerformVECTOR_SHUFFLECombine().

PerformSignExtendInregCombine()

static SDValue PerformSignExtendInregCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 15533 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), N, llvm::ARMISD::VGETLANEs, and llvm::ARMISD::VGETLANEu.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSplittingMVEEXTToWideningLoad()

static SDValue PerformSplittingMVEEXTToWideningLoad ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 18562 of file ARMISelLowering.cpp.

References assert(), llvm::CallingConv::C, DL, llvm::ISD::EXTLOAD, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isVector(), llvm::ARMISD::MVESEXT, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by llvm::ARMTargetLowering::PerformMVEExtCombine().

PerformSplittingMVETruncToNarrowingStores()

static SDValue PerformSplittingMVETruncToNarrowingStores ( StoreSDNode *  St, SelectionDAG &  DAG  )

static

Definition at line 16631 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, DL, llvm::TypeSize::Fixed(), llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), llvm::ARMISD::MVETRUNC, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

PerformSplittingToNarrowingStores()

static SDValue PerformSplittingToNarrowingStores ( StoreSDNode *  St, SelectionDAG &  DAG  )

static

Definition at line 16538 of file ARMISelLowering.cpp.

References assert(), llvm::CallingConv::C, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::f16, llvm::MVT::f32, llvm::TypeSize::Fixed(), llvm::ISD::FP_ROUND, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), I, llvm::MVT::i32, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::Shuffle, llvm::ISD::TokenFactor, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::ARMISD::VCVTN, and llvm::ARMISD::VECTOR_REG_CAST.

Referenced by PerformSTORECombine().

PerformSplittingToWideningLoad()

static SDValue PerformSplittingToWideningLoad ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 17649 of file ARMISelLowering.cpp.

References assert(), llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, DL, llvm::MVT::f16, llvm::MVT::f32, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDValue::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i8, llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::LOAD, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, llvm::MVT::v4f32, llvm::MVT::v8f16, llvm::ARMISD::VCVTL, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ISD::ZEXTLOAD.

Referenced by PerformExtendCombine(), and PerformFPExtendCombine().

PerformSTORECombine()

static SDValue PerformSTORECombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 16707 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, PerformExtractFpToIntStores(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformTruncatingStoreCombine(), and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSUBCombine()

static SDValue PerformSUBCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

Definition at line 13970 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, combineSelectAndUse(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, isZeroVector(), N, PerformSubCSINCCombine(), llvm::ISD::SUB, llvm::ARMISD::VDUP, and llvm::ARMISD::VMOVIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), and llvm::LanaiTargetLowering::PerformDAGCombine().

PerformSubCSINCCombine()

static SDValue PerformSubCSINCCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 13950 of file ARMISelLowering.cpp.

References llvm::ARMISD::CSINC, llvm::ARMISD::CSINV, llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::isNullConstant(), N, llvm::ISD::SUB, and X.

Referenced by PerformSUBCombine().

PerformTruncatingStoreCombine()

static SDValue PerformTruncatingStoreCombine ( StoreSDNode *  St, SelectionDAG &  DAG  )

static

Definition at line 16453 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, DL, E, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), I, llvm::MVT::i8, llvm::MVT::integer_valuetypes(), llvm::DataLayout::isBigEndian(), llvm::isPowerOf2_32(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

PerformUMLALCombine()

static SDValue PerformUMLALCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 13023 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::isNullConstant(), N, and llvm::ARMISD::UMAAL.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVCMPCombine()

static SDValue PerformVCMPCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 15349 of file ARMISelLowering.cpp.

References Cond, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), getSwappedCondition(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), isValidMVECond(), isZeroVector(), N, llvm::ARMISD::VCMP, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VDUP.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVCVTCombine()

static SDValue PerformVCVTCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 16796 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, isSigned(), N, llvm::ISD::TRUNCATE, llvm::MVT::v2i32, and llvm::MVT::v4i32.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVDIVCombine()

static SDValue PerformVDIVCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3

Definition at line 16896 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, isSigned(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVDUPCombine()

static SDValue PerformVDUPCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.

Definition at line 16399 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, N, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::VDUP, llvm::ARMISD::VLD1DUP, and llvm::ARMISD::VMOVrh.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVDUPLANECombine()

static SDValue PerformVDUPLANECombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.

Definition at line 16356 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeVMOVModImm(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ARMISD::VDUP, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECREDUCE_ADDCombine()

static SDValue PerformVECREDUCE_ADDCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 16946 of file ARMISelLowering.cpp.

References A, llvm::ISD::ADD, llvm::any_of(), assert(), B, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::EVT::changeVectorElementType(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::is128BitVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::Mul, llvm::ISD::MUL, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, RetTy, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ARMISD::VADDLVps, llvm::ARMISD::VADDLVpu, llvm::ARMISD::VADDLVs, llvm::ARMISD::VADDLVu, llvm::ARMISD::VADDVps, llvm::ARMISD::VADDVpu, llvm::ARMISD::VADDVs, llvm::ARMISD::VADDVu, llvm::ISD::VECREDUCE_ADD, llvm::ARMISD::VMLALVAs, llvm::ARMISD::VMLALVAu, llvm::ARMISD::VMLALVps, llvm::ARMISD::VMLALVpu, llvm::ARMISD::VMLALVs, llvm::ARMISD::VMLALVu, llvm::ARMISD::VMLAVps, llvm::ARMISD::VMLAVpu, llvm::ARMISD::VMLAVs, llvm::ARMISD::VMLAVu, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECTOR_REG_CASTCombine()

static SDValue PerformVECTOR_REG_CASTCombine ( SDNode *  N, SelectionDAG &  DAG, const ARMSubtarget *  ST  )

static

Definition at line 15324 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), N, and llvm::ARMISD::VECTOR_REG_CAST.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECTOR_SHUFFLECombine()

static SDValue PerformVECTOR_SHUFFLECombine ( SDNode *  N, SelectionDAG &  DAG  )

static

PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.

Definition at line 15614 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, PerformShuffleVMOVNCombine(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVLDCombine()

static SDValue PerformVLDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 16143 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVDRRCombine()

static SDValue PerformVMOVDRRCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.

This is also used for BUILD_VECTORs with 2 operands.

Definition at line 15042 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), N, and llvm::ARMISD::VMOVRRD.

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVhrCombine()

static SDValue PerformVMOVhrCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 15058 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CopyFromReg, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::MVT::i16, N, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::ARMISD::VMOVrh.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVNCombine()

static SDValue PerformVMOVNCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17239 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::isUndef(), N, llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::ARMISD::VQMOVNs, and llvm::ARMISD::VQMOVNu.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVrhCombine()

static SDValue PerformVMOVrhCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 15120 of file ARMISelLowering.cpp.

References llvm::CallingConv::C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::ISD::isNormalLoad(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::VGETLANEu, and llvm::ISD::ZEXTLOAD.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVRRDCombine()

static SDValue PerformVMOVRRDCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.

Definition at line 14950 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::commonAlignment(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::ISD::FrameIndex, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::DataLayout::isBigEndian(), llvm::ARMSubtarget::isLittle(), llvm::ISD::isNormalLoad(), N, llvm::Offset, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), std::swap(), llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMULCombine()

static SDValue PerformVMULCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.

vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 14023 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

PerformVQDMULHCombine() [1/2]

static SDValue PerformVQDMULHCombine ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 13217 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), I, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::isConstOrConstSplat(), llvm::EVT::isPow2VectorType(), llvm::EVT::isVector(), llvm::Mul, llvm::ISD::MUL, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::TRUNCATE, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VQDMULH, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), PerformMinMaxCombine(), and PerformVSELECTCombine().

PerformVQDMULHCombine() [2/2]

static SDValue PerformVQDMULHCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17295 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), llvm::Value::hasOneUse(), LHS, N, and RHS.

PerformVQMOVNCombine()

static SDValue PerformVQMOVNCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 17279 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), N, and llvm::TargetLowering::SimplifyDemandedVectorElts().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVSELECTCombine()

static SDValue PerformVSELECTCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 13325 of file ARMISelLowering.cpp.

References Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::isConstOrConstSplat(), LHS, N, PerformVQDMULHCombine(), RHS, llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVSetCCToVCTPCombine()

static SDValue PerformVSetCCToVCTPCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 13365 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, CC, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, llvm::ISD::SETUGE, llvm::ISD::SETULT, and std::swap().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformXORCombine()

static SDValue PerformXORCombine ( SDNode *  N, TargetLowering::DAGCombinerInfo &  DCI, const ARMSubtarget *  Subtarget  )

static

Definition at line 14702 of file ARMISelLowering.cpp.

References CanInvertMVEVCMP(), CC, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::ARMSubtarget::getTargetLowering(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), getVCMPCondCode(), llvm::MVT::i32, llvm::TargetLowering::isConstTrueVal(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), N, PerformSHLSimplify(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PromoteMVEPredVector()

static SDValue PromoteMVEPredVector ( SDLoc  dl, SDValue  Pred, EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 8503 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::ISD::BITCAST, llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), getVectorTyFromPredicateVector(), llvm::MVT::i32, llvm::ARMISD::PREDICATE_CAST, llvm::MVT::v16i1, llvm::MVT::v16i8, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.

Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), and LowerVECTOR_SHUFFLE_i1().

promoteToConstantPool()

static SDValue promoteToConstantPool ( const ARMTargetLowering *  TLI, const GlobalValue *  GV, SelectionDAG &  DAG, EVT  PtrVT, const SDLoc &  dl  )

static

Definition at line 3786 of file ARMISelLowering.cpp.

References allUsersAreInFunction(), llvm::StringRef::bytes_begin(), llvm::StringRef::bytes_end(), ConstpoolPromotionMaxSize, ConstpoolPromotionMaxTotal, llvm::ARMConstantPoolConstant::Create(), EnableConstpoolPromotion, llvm::TargetOptions::EnableFastISel, F, llvm::ConstantDataArray::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPreferredAlign(), llvm::ARMFunctionInfo::getPromotedConstpoolIncrease(), llvm::ARMTargetLowering::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstantPool(), llvm::DataLayout::getTypeAllocSize(), llvm::MVT::i32, llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMFunctionInfo::markGlobalAsPromotedToConstantPool(), llvm::TargetMachine::Options, llvm::ARMFunctionInfo::setPromotedConstpoolIncrease(), llvm::StringRef::size(), Size, and llvm::ARMISD::Wrapper.

ReplaceCMP_SWAP_64Results()

static void ReplaceCMP_SWAP_64Results ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG  )

static

Definition at line 10392 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_PAIR, createGPRPairNode(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::Lo, N, llvm::MVT::Other, Results, llvm::SelectionDAG::setNodeMemRefs(), and llvm::MVT::Untyped.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

ReplaceLongIntrinsic()

static void ReplaceLongIntrinsic ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG  )

static

Definition at line 10598 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::Lo, N, Results, llvm::ARMISD::SMLALD, llvm::ARMISD::SMLALDX, llvm::ARMISD::SMLSLD, llvm::ARMISD::SMLSLDX, and llvm::SelectionDAG::SplitScalar().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

ReplaceREADCYCLECOUNTER()

static void ReplaceREADCYCLECOUNTER ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const ARMSubtarget *  Subtarget  )

static

Definition at line 10351 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, N, llvm::MVT::Other, and Results.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

SearchLoopIntrinsic()

static SDValue SearchLoopIntrinsic ( SDValue  N, ISD::CondCode &  CC, int &  Imm, bool &  Negate  )

static

Definition at line 18035 of file ARMISelLowering.cpp.

References CC, llvm::ISD::INTRINSIC_W_CHAIN, N, SearchLoopIntrinsic(), llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by PerformHWLoopCombine(), and SearchLoopIntrinsic().

SelectPairHalf()

static unsigned SelectPairHalf ( unsigned  Elements, ArrayRef< int >  Mask, unsigned  Index  )

static

Definition at line 7242 of file ARMISelLowering.cpp.

Referenced by isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), and isVZIPMask().

SkipExtensionForVMULL()

static SDValue SkipExtensionForVMULL ( SDNode *  N, SelectionDAG &  DAG  )

static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.

The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 9459 of file ARMISelLowering.cpp.

References AddRequiredExtensionForVMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::MVT::v2i32, llvm::MVT::v4i32, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

Referenced by LowerMUL().

SkipLoadExtensionForVMULL()

static SDValue SkipLoadExtensionForVMULL ( LoadSDNode *  LD, SelectionDAG &  DAG  )

static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.

If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 9435 of file ARMISelLowering.cpp.

References getExtensionTo64Bits(), llvm::SelectionDAG::getExtLoad(), and llvm::SelectionDAG::getLoad().

Referenced by SkipExtensionForVMULL().

STATISTIC() [1/4]

STATISTIC	(	NumConstpoolPromoted	,
		"Number of constants with their storage promoted into constant pools"
	)

STATISTIC() [2/4]

STATISTIC	(	NumLoopByVals	,
		"Number of loops generated for byval arguments"
	)

STATISTIC() [3/4]

STATISTIC	(	NumMovwMovt	,
		"Number of GAs materialized with movw + movt"
	)

STATISTIC() [4/4]

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

TryCombineBaseUpdate()

static bool TryCombineBaseUpdate ( struct BaseUpdateTarget &  Target, struct BaseUpdateUser &  User, bool  SimpleConstIncOnly, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 15685 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MemSDNode::getAlign(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::LOAD, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::STORE, llvm::Align::value(), llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD1x2_UPD, llvm::ARMISD::VLD1x3_UPD, llvm::ARMISD::VLD1x4_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST1x2_UPD, llvm::ARMISD::VST1x3_UPD, llvm::ARMISD::VST1x4_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, and llvm::ARMISD::VST4LN_UPD.

Referenced by CombineBaseUpdate().

TryDistrubutionADDVecReduce()

static SDValue TryDistrubutionADDVecReduce ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 13476 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::MemSDNode::getChain(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::BaseIndexOffset::match(), llvm::ISD::MUL, N, llvm::ARMISD::VADDVs, llvm::ARMISD::VADDVu, llvm::ISD::VECREDUCE_ADD, llvm::ARMISD::VMLAVs, llvm::ARMISD::VMLAVu, and X.

Referenced by PerformADDVecReduce().

WinDBZCheckDenominator()

static SDValue WinDBZCheckDenominator ( SelectionDAG &  DAG, SDNode *  N, SDValue  InChain  )

static

Definition at line 10001 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::MVT::i32, llvm::Lo, N, llvm::ISD::OR, llvm::MVT::Other, llvm::SelectionDAG::SplitScalar(), and llvm::ARMISD::WIN__DBZCHK.

Variable Documentation

ARMInterworking

cl::opt< bool > ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true)) ( "arm-interworking"  , cl::Hidden  , cl::desc("Enable / disable ARM interworking (for debugging only)")  , cl::init(true)    )

static

ConstpoolPromotionMaxSize

cl::opt< unsigned > ConstpoolPromotionMaxSize("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64)) ( "arm-promote-constant-max-size"  , cl::Hidden  , cl::desc("Maximum size of constant to promote into a constant pool")  , cl::init(64)    )

static

Referenced by promoteToConstantPool().

ConstpoolPromotionMaxTotal

cl::opt< unsigned > ConstpoolPromotionMaxTotal("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128)) ( "arm-promote-constant-max-total"  , cl::Hidden  , cl::desc("Maximum size of ALL constants to promote into a constant pool")  , cl::init(128)    )

static

Referenced by promoteToConstantPool().

EnableConstpoolPromotion

cl::opt< bool > EnableConstpoolPromotion("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false)) ( "arm-promote-constant"  , cl::Hidden  , cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools")  , cl::init(false)    )

static

Referenced by promoteToConstantPool().

GPRArgRegs

const MCPhysReg GPRArgRegs[]

static

Initial value:

= {
  ARM::R0, ARM::R1, ARM::R2, ARM::R3
}

Definition at line 155 of file ARMISelLowering.cpp.

MVEMaxSupportedInterleaveFactor

cl::opt< unsigned > MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))	(	"mve-max-interleave-factor"	,
		cl::Hidden	,
		cl::desc("Maximum interleave factor for MVE VLDn to generate.")	,
		cl::init(2)
	)

Referenced by canTailPredicateLoop(), and llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().