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13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
24 #define GET_REGINFO_HEADER
25 #include "ARMGenRegisterInfo.inc"
50 case R0:
case R1:
case R2:
case R3:
51 case R4:
case R5:
case R6:
case R7:
52 case LR:
case SP:
case PC:
54 case R8:
case R9:
case R10:
case R11:
case R12:
56 return !SplitFramePushPop;
66 case R8:
case R9:
case R10:
case R11:
case R12:
68 return SplitFramePushPop;
75 bool SplitFramePushPop) {
79 case R0:
case R1:
case R2:
case R3:
80 case R4:
case R5:
case R6:
case R7:
81 case R8:
case R9:
case R10:
case R12:
90 bool SplitFramePushPop) {
105 case D15:
case D14:
case D13:
case D12:
106 case D11:
case D10:
case D9:
case D8:
107 case D7:
case D6:
case D5:
case D4:
108 case D3:
case D2:
case D1:
case D0:
109 case D31:
case D30:
case D29:
case D28:
110 case D27:
case D26:
case D25:
case D24:
111 case D23:
case D22:
case D21:
case D20:
112 case D19:
case D18:
case D17:
case D16:
121 for (
unsigned i = 0; CSRegs[
i]; ++
i)
122 if (
Reg == CSRegs[
i])
169 unsigned PhysReg)
const override;
173 unsigned Kind = 0)
const override;
196 int Idx)
const override;
199 int64_t
Offset)
const override;
201 int64_t
Offset)
const override;
203 int64_t
Offset)
const override;
228 int SPAdj,
unsigned FIOperandNum,
243 unsigned SrcSubReg)
const override;
250 #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
This is an optimization pass for GlobalISel generic memory operations.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
int getSEHRegNum(unsigned i) const
Reg
All possible values of the reg field in the ModR/M byte.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Register getBaseRegister() const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
unsigned getOpcode(int Op) const
static bool isSplitFPArea2Register(unsigned Reg, bool SplitFramePushPop)
Register getFrameRegister(const MachineFunction &MF) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool cannotEliminateFrame(const MachineFunction &MF) const
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const override
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Representation of each machine instruction.
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
const uint32_t * getNoPreservedMask() const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isARMArea2Register(unsigned Reg, bool SplitFramePushPop)
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
Wrapper class representing virtual and physical registers.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool canRealignStack(const MachineFunction &MF) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const override
static bool isARMArea3Register(unsigned Reg, bool SplitFramePushPop)
static bool isSplitFPArea1Register(unsigned Reg, bool SplitFramePushPop)
bool hasBasePointer(const MachineFunction &MF) const
void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const override
static bool isARMArea1Register(unsigned Reg, bool SplitFramePushPop)
isARMArea1Register - Returns true if the register is a low register (r0-r7) or a stack/pc register th...
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
Wrapper class representing physical registers. Should be passed by value.