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ARMBaseRegisterInfo.cpp
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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the base ARM implementation of TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARM.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMFrameLowering.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Support/Debug.h"
47 #include <cassert>
48 #include <utility>
49 
50 #define DEBUG_TYPE "arm-register-info"
51 
52 #define GET_REGINFO_TARGET_DESC
53 #include "ARMGenRegisterInfo.inc"
54 
55 using namespace llvm;
56 
58  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
59 
60 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
61  return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
62 }
63 
64 const MCPhysReg*
66  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
67  bool UseSplitPush = STI.splitFramePushPop(*MF);
68  const MCPhysReg *RegList =
69  STI.isTargetDarwin()
70  ? CSR_iOS_SaveList
71  : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
72 
73  const Function &F = MF->getFunction();
74  if (F.getCallingConv() == CallingConv::GHC) {
75  // GHC set of callee saved regs is empty as all those regs are
76  // used for passing STG regs around
77  return CSR_NoRegs_SaveList;
78  } else if (F.hasFnAttribute("interrupt")) {
79  if (STI.isMClass()) {
80  // M-class CPUs have hardware which saves the registers needed to allow a
81  // function conforming to the AAPCS to function as a handler.
82  return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
83  } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
84  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
85  // need to be saved to restore user-mode state.
86  return CSR_FIQ_SaveList;
87  } else {
88  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
89  // exception handling.
90  return CSR_GenericInt_SaveList;
91  }
92  }
93 
94  if (STI.getTargetLowering()->supportSwiftError() &&
95  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
96  if (STI.isTargetDarwin())
97  return CSR_iOS_SwiftError_SaveList;
98 
99  return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
100  CSR_AAPCS_SwiftError_SaveList;
101  }
102 
104  return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
105  ? CSR_iOS_CXX_TLS_PE_SaveList
106  : CSR_iOS_CXX_TLS_SaveList;
107  return RegList;
108 }
109 
111  const MachineFunction *MF) const {
112  assert(MF && "Invalid MachineFunction pointer.");
114  MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
115  return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
116  return nullptr;
117 }
118 
119 const uint32_t *
121  CallingConv::ID CC) const {
122  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
123  if (CC == CallingConv::GHC)
124  // This is academic because all GHC calls are (supposed to be) tail calls
125  return CSR_NoRegs_RegMask;
126 
127  if (STI.getTargetLowering()->supportSwiftError() &&
128  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
129  return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
130  : CSR_AAPCS_SwiftError_RegMask;
131 
132  if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
133  return CSR_iOS_CXX_TLS_RegMask;
134  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
135 }
136 
137 const uint32_t*
139  return CSR_NoRegs_RegMask;
140 }
141 
142 const uint32_t *
145  "only know about special TLS call on Darwin");
146  return CSR_iOS_TLSCall_RegMask;
147 }
148 
149 const uint32_t *
151  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
152  if (!STI.useSoftFloat() && STI.hasVFP2Base() && !STI.isThumb1Only())
153  return CSR_NoRegs_RegMask;
154  else
155  return CSR_FPRegs_RegMask;
156 }
157 
158 const uint32_t *
160  CallingConv::ID CC) const {
161  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
162  // This should return a register mask that is the same as that returned by
163  // getCallPreservedMask but that additionally preserves the register used for
164  // the first i32 argument (which must also be the register used to return a
165  // single i32 return value)
166  //
167  // In case that the calling convention does not use the same register for
168  // both or otherwise does not want to enable this optimization, the function
169  // should return NULL
170  if (CC == CallingConv::GHC)
171  // This is academic because all GHC calls are (supposed to be) tail calls
172  return nullptr;
173  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
174  : CSR_AAPCS_ThisReturn_RegMask;
175 }
176 
178  const MachineFunction *MF) const {
179  static const MCPhysReg IntraCallClobberedRegs[] = {ARM::R12};
180  return ArrayRef<MCPhysReg>(IntraCallClobberedRegs);
181 }
182 
185  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
186  const ARMFrameLowering *TFI = getFrameLowering(MF);
187 
188  // FIXME: avoid re-calculating this every time.
189  BitVector Reserved(getNumRegs());
190  markSuperRegs(Reserved, ARM::SP);
191  markSuperRegs(Reserved, ARM::PC);
192  markSuperRegs(Reserved, ARM::FPSCR);
193  markSuperRegs(Reserved, ARM::APSR_NZCV);
194  if (TFI->hasFP(MF))
195  markSuperRegs(Reserved, getFramePointerReg(STI));
196  if (hasBasePointer(MF))
197  markSuperRegs(Reserved, BasePtr);
198  // Some targets reserve R9.
199  if (STI.isR9Reserved())
200  markSuperRegs(Reserved, ARM::R9);
201  // Reserve D16-D31 if the subtarget doesn't support them.
202  if (!STI.hasD32()) {
203  static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
204  for (unsigned R = 0; R < 16; ++R)
205  markSuperRegs(Reserved, ARM::D16 + R);
206  }
207  const TargetRegisterClass &RC = ARM::GPRPairRegClass;
208  for (unsigned Reg : RC)
209  for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
210  if (Reserved.test(*SI))
211  markSuperRegs(Reserved, Reg);
212  // For v8.1m architecture
213  markSuperRegs(Reserved, ARM::ZR);
214 
215  assert(checkAllSuperRegsMarked(Reserved));
216  return Reserved;
217 }
218 
220 isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {
221  return !getReservedRegs(MF).test(PhysReg);
222 }
223 
224 const TargetRegisterClass *
226  const MachineFunction &) const {
227  const TargetRegisterClass *Super = RC;
229  do {
230  switch (Super->getID()) {
231  case ARM::GPRRegClassID:
232  case ARM::SPRRegClassID:
233  case ARM::DPRRegClassID:
234  case ARM::QPRRegClassID:
235  case ARM::QQPRRegClassID:
236  case ARM::QQQQPRRegClassID:
237  case ARM::GPRPairRegClassID:
238  return Super;
239  }
240  Super = *I++;
241  } while (Super);
242  return RC;
243 }
244 
245 const TargetRegisterClass *
247  const {
248  return &ARM::GPRRegClass;
249 }
250 
251 const TargetRegisterClass *
253  if (RC == &ARM::CCRRegClass)
254  return &ARM::rGPRRegClass; // Can't copy CCR registers.
255  return RC;
256 }
257 
258 unsigned
260  MachineFunction &MF) const {
261  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
262  const ARMFrameLowering *TFI = getFrameLowering(MF);
263 
264  switch (RC->getID()) {
265  default:
266  return 0;
267  case ARM::tGPRRegClassID: {
268  // hasFP ends up calling getMaxCallFrameComputed() which may not be
269  // available when getPressureLimit() is called as part of
270  // ScheduleDAGRRList.
271  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
272  ? TFI->hasFP(MF) : true;
273  return 5 - HasFP;
274  }
275  case ARM::GPRRegClassID: {
276  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
277  ? TFI->hasFP(MF) : true;
278  return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
279  }
280  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
281  case ARM::DPRRegClassID:
282  return 32 - 10;
283  }
284 }
285 
286 // Get the other register in a GPRPair.
287 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
288  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
289  if (ARM::GPRPairRegClass.contains(*Supers))
290  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
291  return 0;
292 }
293 
294 // Resolve the RegPairEven / RegPairOdd register allocator hints.
295 bool
297  ArrayRef<MCPhysReg> Order,
299  const MachineFunction &MF,
300  const VirtRegMap *VRM,
301  const LiveRegMatrix *Matrix) const {
302  const MachineRegisterInfo &MRI = MF.getRegInfo();
303  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
304 
305  unsigned Odd;
306  switch (Hint.first) {
307  case ARMRI::RegPairEven:
308  Odd = 0;
309  break;
310  case ARMRI::RegPairOdd:
311  Odd = 1;
312  break;
313  default:
314  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
315  return false;
316  }
317 
318  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
319  // Check if the other part of the pair has already been assigned, and provide
320  // the paired register as the first hint.
321  unsigned Paired = Hint.second;
322  if (Paired == 0)
323  return false;
324 
325  unsigned PairedPhys = 0;
326  if (Register::isPhysicalRegister(Paired)) {
327  PairedPhys = Paired;
328  } else if (VRM && VRM->hasPhys(Paired)) {
329  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
330  }
331 
332  // First prefer the paired physreg.
333  if (PairedPhys && is_contained(Order, PairedPhys))
334  Hints.push_back(PairedPhys);
335 
336  // Then prefer even or odd registers.
337  for (unsigned Reg : Order) {
338  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
339  continue;
340  // Don't provide hints that are paired to a reserved register.
341  unsigned Paired = getPairedGPR(Reg, !Odd, this);
342  if (!Paired || MRI.isReserved(Paired))
343  continue;
344  Hints.push_back(Reg);
345  }
346  return false;
347 }
348 
349 void
351  MachineFunction &MF) const {
353  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
354  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
355  Hint.first == (unsigned)ARMRI::RegPairEven) &&
356  Register::isVirtualRegister(Hint.second)) {
357  // If 'Reg' is one of the even / odd register pair and it's now changed
358  // (e.g. coalesced) into a different register. The other register of the
359  // pair allocation hint must be updated to reflect the relationship
360  // change.
361  unsigned OtherReg = Hint.second;
362  Hint = MRI->getRegAllocationHint(OtherReg);
363  // Make sure the pair has not already divorced.
364  if (Hint.second == Reg) {
365  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
366  if (Register::isVirtualRegister(NewReg))
367  MRI->setRegAllocationHint(NewReg,
368  Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
369  : ARMRI::RegPairOdd, OtherReg);
370  }
371  }
372 }
373 
375  const MachineFrameInfo &MFI = MF.getFrameInfo();
376  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
377  const ARMFrameLowering *TFI = getFrameLowering(MF);
378 
379  // If we have stack realignment and VLAs, we have no pointer to use to
380  // access the stack. If we have stack realignment, and a large call frame,
381  // we have no place to allocate the emergency spill slot.
382  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
383  return true;
384 
385  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
386  // negative range for ldr/str (255), and thumb1 is positive offsets only.
387  //
388  // It's going to be better to use the SP or Base Pointer instead. When there
389  // are variable sized objects, we can't reference off of the SP, so we
390  // reserve a Base Pointer.
391  //
392  // For Thumb2, estimate whether a negative offset from the frame pointer
393  // will be sufficient to reach the whole stack frame. If a function has a
394  // smallish frame, it's less likely to have lots of spills and callee saved
395  // space, so it's all more likely to be within range of the frame pointer.
396  // If it's wrong, the scavenger will still enable access to work, it just
397  // won't be optimal. (We should always be able to reach the emergency
398  // spill slot from the frame pointer.)
399  if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() &&
400  MFI.getLocalFrameSize() >= 128)
401  return true;
402  // For Thumb1, if sp moves, nothing is in range, so force a base pointer.
403  // This is necessary for correctness in cases where we need an emergency
404  // spill slot. (In Thumb1, we can't use a negative offset from the frame
405  // pointer.)
406  if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF))
407  return true;
408  return false;
409 }
410 
412  const MachineRegisterInfo *MRI = &MF.getRegInfo();
413  const ARMFrameLowering *TFI = getFrameLowering(MF);
414  // We can't realign the stack if:
415  // 1. Dynamic stack realignment is explicitly disabled,
416  // 2. There are VLAs in the function and the base pointer is disabled.
418  return false;
419  // Stack realignment requires a frame pointer. If we already started
420  // register allocation with frame pointer elimination, it is too late now.
422  return false;
423  // We may also need a base pointer if there are dynamic allocas or stack
424  // pointer adjustments around calls.
425  if (TFI->hasReservedCallFrame(MF))
426  return true;
427  // A base pointer is required and allowed. Check that it isn't too late to
428  // reserve it.
429  return MRI->canReserveReg(BasePtr);
430 }
431 
434  const MachineFrameInfo &MFI = MF.getFrameInfo();
436  return true;
437  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
438  || needsStackRealignment(MF);
439 }
440 
441 Register
443  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
444  const ARMFrameLowering *TFI = getFrameLowering(MF);
445 
446  if (TFI->hasFP(MF))
447  return getFramePointerReg(STI);
448  return ARM::SP;
449 }
450 
451 /// emitLoadConstPool - Emits a load from constpool to materialize the
452 /// specified immediate.
455  const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
456  ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
457  MachineFunction &MF = *MBB.getParent();
458  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
460  const Constant *C =
462  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
463 
464  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
465  .addReg(DestReg, getDefRegState(true), SubIdx)
466  .addConstantPoolIndex(Idx)
467  .addImm(0)
468  .add(predOps(Pred, PredReg))
469  .setMIFlags(MIFlags);
470 }
471 
474  return true;
475 }
476 
479  return true;
480 }
481 
484  return true;
485 }
486 
489  return true;
490 }
491 
492 int64_t ARMBaseRegisterInfo::
493 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
494  const MCInstrDesc &Desc = MI->getDesc();
495  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
496  int64_t InstrOffs = 0;
497  int Scale = 1;
498  unsigned ImmIdx = 0;
499  switch (AddrMode) {
502  case ARMII::AddrMode_i12:
503  InstrOffs = MI->getOperand(Idx+1).getImm();
504  Scale = 1;
505  break;
506  case ARMII::AddrMode5: {
507  // VFP address mode.
508  const MachineOperand &OffOp = MI->getOperand(Idx+1);
509  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
510  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
511  InstrOffs = -InstrOffs;
512  Scale = 4;
513  break;
514  }
515  case ARMII::AddrMode2:
516  ImmIdx = Idx+2;
517  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
518  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
519  InstrOffs = -InstrOffs;
520  break;
521  case ARMII::AddrMode3:
522  ImmIdx = Idx+2;
523  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
524  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
525  InstrOffs = -InstrOffs;
526  break;
527  case ARMII::AddrModeT1_s:
528  ImmIdx = Idx+1;
529  InstrOffs = MI->getOperand(ImmIdx).getImm();
530  Scale = 4;
531  break;
532  default:
533  llvm_unreachable("Unsupported addressing mode!");
534  }
535 
536  return InstrOffs * Scale;
537 }
538 
539 /// needsFrameBaseReg - Returns true if the instruction's frame index
540 /// reference would be better served by a base register other than FP
541 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
542 /// references it should create new base registers for.
545  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
546  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
547  }
548 
549  // It's the load/store FI references that cause issues, as it can be difficult
550  // to materialize the offset if it won't fit in the literal field. Estimate
551  // based on the size of the local frame and some conservative assumptions
552  // about the rest of the stack frame (note, this is pre-regalloc, so
553  // we don't know everything for certain yet) whether this offset is likely
554  // to be out of range of the immediate. Return true if so.
555 
556  // We only generate virtual base registers for loads and stores, so
557  // return false for everything else.
558  unsigned Opc = MI->getOpcode();
559  switch (Opc) {
560  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
561  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
562  case ARM::t2LDRi12: case ARM::t2LDRi8:
563  case ARM::t2STRi12: case ARM::t2STRi8:
564  case ARM::VLDRS: case ARM::VLDRD:
565  case ARM::VSTRS: case ARM::VSTRD:
566  case ARM::tSTRspi: case ARM::tLDRspi:
567  break;
568  default:
569  return false;
570  }
571 
572  // Without a virtual base register, if the function has variable sized
573  // objects, all fixed-size local references will be via the frame pointer,
574  // Approximate the offset and see if it's legal for the instruction.
575  // Note that the incoming offset is based on the SP value at function entry,
576  // so it'll be negative.
577  MachineFunction &MF = *MI->getParent()->getParent();
578  const ARMFrameLowering *TFI = getFrameLowering(MF);
579  MachineFrameInfo &MFI = MF.getFrameInfo();
581 
582  // Estimate an offset from the frame pointer.
583  // Conservatively assume all callee-saved registers get pushed. R4-R6
584  // will be earlier than the FP, so we ignore those.
585  // R7, LR
586  int64_t FPOffset = Offset - 8;
587  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
588  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
589  FPOffset -= 80;
590  // Estimate an offset from the stack pointer.
591  // The incoming offset is relating to the SP at the start of the function,
592  // but when we access the local it'll be relative to the SP after local
593  // allocation, so adjust our SP-relative offset by that allocation size.
594  Offset += MFI.getLocalFrameSize();
595  // Assume that we'll have at least some spill slots allocated.
596  // FIXME: This is a total SWAG number. We should run some statistics
597  // and pick a real one.
598  Offset += 128; // 128 bytes of spill slots
599 
600  // If there's a frame pointer and the addressing mode allows it, try using it.
601  // The FP is only available if there is no dynamic realignment. We
602  // don't know for sure yet whether we'll need that, so we guess based
603  // on whether there are any local variables that would trigger it.
604  unsigned StackAlign = TFI->getStackAlignment();
605  if (TFI->hasFP(MF) &&
606  !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
607  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
608  return false;
609  }
610  // If we can reference via the stack pointer, try that.
611  // FIXME: This (and the code that resolves the references) can be improved
612  // to only disallow SP relative references in the live range of
613  // the VLA(s). In practice, it's unclear how much difference that
614  // would make, but it may be worth doing.
615  if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
616  return false;
617 
618  // The offset likely isn't legal, we want to allocate a virtual base register.
619  return true;
620 }
621 
622 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
623 /// be a pointer to FrameIdx at the beginning of the basic block.
626  unsigned BaseReg, int FrameIdx,
627  int64_t Offset) const {
629  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
630  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
631 
633  DebugLoc DL; // Defaults to "unknown"
634  if (Ins != MBB->end())
635  DL = Ins->getDebugLoc();
636 
637  const MachineFunction &MF = *MBB->getParent();
639  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
640  const MCInstrDesc &MCID = TII.get(ADDriOpc);
641  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
642 
643  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
644  .addFrameIndex(FrameIdx).addImm(Offset);
645 
646  if (!AFI->isThumb1OnlyFunction())
648 }
649 
651  int64_t Offset) const {
652  MachineBasicBlock &MBB = *MI.getParent();
653  MachineFunction &MF = *MBB.getParent();
654  const ARMBaseInstrInfo &TII =
655  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
657  int Off = Offset; // ARM doesn't need the general 64-bit offsets
658  unsigned i = 0;
659 
660  assert(!AFI->isThumb1OnlyFunction() &&
661  "This resolveFrameIndex does not support Thumb1!");
662 
663  while (!MI.getOperand(i).isFI()) {
664  ++i;
665  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
666  }
667  bool Done = false;
668  if (!AFI->isThumbFunction())
669  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
670  else {
671  assert(AFI->isThumb2Function());
672  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this);
673  }
674  assert(Done && "Unable to resolve frame index!");
675  (void)Done;
676 }
677 
679  int64_t Offset) const {
680  const MCInstrDesc &Desc = MI->getDesc();
681  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
682  unsigned i = 0;
683  for (; !MI->getOperand(i).isFI(); ++i)
684  assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
685 
686  // AddrMode4 and AddrMode6 cannot handle any offset.
687  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
688  return Offset == 0;
689 
690  unsigned NumBits = 0;
691  unsigned Scale = 1;
692  bool isSigned = true;
693  switch (AddrMode) {
696  // i8 supports only negative, and i12 supports only positive, so
697  // based on Offset sign, consider the appropriate instruction
698  Scale = 1;
699  if (Offset < 0) {
700  NumBits = 8;
701  Offset = -Offset;
702  } else {
703  NumBits = 12;
704  }
705  break;
706  case ARMII::AddrMode5:
707  // VFP address mode.
708  NumBits = 8;
709  Scale = 4;
710  break;
711  case ARMII::AddrMode_i12:
712  case ARMII::AddrMode2:
713  NumBits = 12;
714  break;
715  case ARMII::AddrMode3:
716  NumBits = 8;
717  break;
718  case ARMII::AddrModeT1_s:
719  NumBits = (BaseReg == ARM::SP ? 8 : 5);
720  Scale = 4;
721  isSigned = false;
722  break;
723  default:
724  llvm_unreachable("Unsupported addressing mode!");
725  }
726 
727  Offset += getFrameIndexInstrOffset(MI, i);
728  // Make sure the offset is encodable for instructions that scale the
729  // immediate.
730  if ((Offset & (Scale-1)) != 0)
731  return false;
732 
733  if (isSigned && Offset < 0)
734  Offset = -Offset;
735 
736  unsigned Mask = (1 << NumBits) - 1;
737  if ((unsigned)Offset <= Mask * Scale)
738  return true;
739 
740  return false;
741 }
742 
743 void
745  int SPAdj, unsigned FIOperandNum,
746  RegScavenger *RS) const {
747  MachineInstr &MI = *II;
748  MachineBasicBlock &MBB = *MI.getParent();
749  MachineFunction &MF = *MBB.getParent();
750  const ARMBaseInstrInfo &TII =
751  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
752  const ARMFrameLowering *TFI = getFrameLowering(MF);
754  assert(!AFI->isThumb1OnlyFunction() &&
755  "This eliminateFrameIndex does not support Thumb1!");
756  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
757  unsigned FrameReg;
758 
759  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
760 
761  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
762  // call frame setup/destroy instructions have already been eliminated. That
763  // means the stack pointer cannot be used to access the emergency spill slot
764  // when !hasReservedCallFrame().
765 #ifndef NDEBUG
766  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
767  assert(TFI->hasReservedCallFrame(MF) &&
768  "Cannot use SP to access the emergency spill slot in "
769  "functions without a reserved call frame");
771  "Cannot use SP to access the emergency spill slot in "
772  "functions with variable sized frame objects");
773  }
774 #endif // NDEBUG
775 
776  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
777 
778  // Modify MI as necessary to handle as much of 'Offset' as possible
779  bool Done = false;
780  if (!AFI->isThumbFunction())
781  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
782  else {
783  assert(AFI->isThumb2Function());
784  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII, this);
785  }
786  if (Done)
787  return;
788 
789  // If we get here, the immediate doesn't fit into the instruction. We folded
790  // as much as possible above, handle the rest, providing a register that is
791  // SP+LargeImm.
792  assert(
793  (Offset ||
800  "This code isn't needed if offset already handled!");
801 
802  unsigned ScratchReg = 0;
803  int PIdx = MI.findFirstPredOperandIdx();
804  ARMCC::CondCodes Pred = (PIdx == -1)
806  Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
807 
808  const MCInstrDesc &MCID = MI.getDesc();
809  const TargetRegisterClass *RegClass =
810  TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
811 
812  if (Offset == 0 &&
813  (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
814  // Must be addrmode4/6.
815  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
816  else {
817  ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
818  if (!AFI->isThumbFunction())
819  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
820  Offset, Pred, PredReg, TII);
821  else {
822  assert(AFI->isThumb2Function());
823  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
824  Offset, Pred, PredReg, TII);
825  }
826  // Update the original instruction to use the scratch register.
827  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
828  }
829 }
830 
832  const TargetRegisterClass *SrcRC,
833  unsigned SubReg,
834  const TargetRegisterClass *DstRC,
835  unsigned DstSubReg,
836  const TargetRegisterClass *NewRC,
837  LiveIntervals &LIS) const {
838  auto MBB = MI->getParent();
839  auto MF = MBB->getParent();
840  const MachineRegisterInfo &MRI = MF->getRegInfo();
841  // If not copying into a sub-register this should be ok because we shouldn't
842  // need to split the reg.
843  if (!DstSubReg)
844  return true;
845  // Small registers don't frequently cause a problem, so we can coalesce them.
846  if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
847  getRegSizeInBits(*SrcRC) < 256)
848  return true;
849 
850  auto NewRCWeight =
852  auto SrcRCWeight =
854  auto DstRCWeight =
856  // If the source register class is more expensive than the destination, the
857  // coalescing is probably profitable.
858  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
859  return true;
860  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
861  return true;
862 
863  // If the register allocator isn't constrained, we can always allow coalescing
864  // unfortunately we don't know yet if we will be constrained.
865  // The goal of this heuristic is to restrict how many expensive registers
866  // we allow to coalesce in a given basic block.
867  auto AFI = MF->getInfo<ARMFunctionInfo>();
868  auto It = AFI->getCoalescedWeight(MBB);
869 
870  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
871  << It->second << "\n");
872  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
873  << NewRCWeight.RegWeight << "\n");
874 
875  // This number is the largest round number that which meets the criteria:
876  // (1) addresses PR18825
877  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
878  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
879  // In practice the SizeMultiplier will only factor in for straight line code
880  // that uses a lot of NEON vectors, which isn't terribly common.
881  unsigned SizeMultiplier = MBB->size()/100;
882  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
883  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
884  It->second += NewRCWeight.RegWeight;
885  return true;
886  }
887  return false;
888 }
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const MachineInstrBuilder & add(const MachineOperand &MO) const
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool hasD32() const
Definition: ARMSubtarget.h:679
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isReserved(Register PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
void push_back(const T &Elt)
Definition: SmallVector.h:211
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:531
unsigned Reg
Register getFrameRegister(const MachineFunction &MF) const override
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
A debug info location.
Definition: DebugLoc.h:33
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isThumb1Only() const
Definition: ARMSubtarget.h:757
ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const override
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:96
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
Live Register Matrix
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned SubReg
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP...
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
unsigned char getAM3Offset(unsigned AM3Opc)
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:777
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:690
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:769
bool isR9Reserved() const
Definition: ARMSubtarget.h:765
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
AddrOpc getAM2Op(unsigned AM2Opc)
unsigned getDefRegState(bool B)
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned char getAM5Offset(unsigned AM5Opc)
This file declares the machine register scavenger class.
const TargetRegisterInfo * getTargetRegisterInfo() const
AddrOpc getAM3Op(unsigned AM3Opc)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const MachineRegisterInfo * MRI
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isMClass() const
Definition: ARMSubtarget.h:760
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasBasePointer(const MachineFunction &MF) const
bool hasVFP2Base() const
Definition: ARMSubtarget.h:609
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static unsigned getFramePointerReg(const ARMSubtarget &STI)
MCSubRegIterator enumerates all sub-registers of Reg.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
std::pair< unsigned, unsigned > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool useSoftFloat() const
Definition: ARMSubtarget.h:754
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
bool isDebugValue() const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
Promote Memory to Register
Definition: Mem2Reg.cpp:109
unsigned getAM2Offset(unsigned AM2Opc)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:638
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool canRealignStack(const MachineFunction &MF) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
Register getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:102
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
TargetOptions Options
#define I(x, y, z)
Definition: MD5.cpp:58
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Align getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
bool isMaxCallFrameSizeComputed() const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
IRTranslator LLVM IR MI
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
AddrOpc getAM5Op(unsigned AM5Opc)
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1224