164#define DEBUG_TYPE "arm-frame-lowering"
170 cl::desc(
"Align ARM NEON spills in prolog and epilog"));
174 unsigned NumAlignedDPRCS2Regs);
233 if (CFSize >= ((1 << 12) - 1) / 2)
256 bool IsTailCallReturn =
false;
258 unsigned RetOpcode =
MBBI->getOpcode();
259 IsTailCallReturn = RetOpcode == ARM::TCRETURNdi ||
260 RetOpcode == ARM::TCRETURNri ||
261 RetOpcode == ARM::TCRETURNrinotr12;
265 int ArgumentPopSize = 0;
266 if (IsTailCallReturn) {
272 ArgumentPopSize = StackAdjust.
getImm();
281 return ArgumentPopSize;
287 F.needsUnwindTableEntry();
295 unsigned Opc =
MBBI->getOpcode();
321 case ARM::t2MOVi16: {
322 bool Wide =
MBBI->getOperand(1).getImm() >= 256;
326 NewInstr.
add(
MBBI->getOperand(0));
344 case ARM::t2MOVi32imm:
362 if (
MBBI->getOperand(0).getReg() == ARM::SP &&
363 MBBI->getOperand(2).getReg() == ARM::SP &&
364 MBBI->getOperand(3).getImm() == -4) {
365 unsigned Reg =
RegInfo->getSEHRegNum(
MBBI->getOperand(1).getReg());
375 case ARM::t2LDR_POST:
376 if (
MBBI->getOperand(1).getReg() == ARM::SP &&
377 MBBI->getOperand(2).getReg() == ARM::SP &&
378 MBBI->getOperand(3).getImm() == 4) {
379 unsigned Reg =
RegInfo->getSEHRegNum(
MBBI->getOperand(0).getReg());
389 case ARM::t2LDMIA_RET:
390 case ARM::t2LDMIA_UPD:
391 case ARM::t2STMDB_UPD: {
394 for (
unsigned i = 4, NumOps =
MBBI->getNumOperands(); i != NumOps; ++i) {
401 if (Reg >= 8 && Reg <= 13)
403 else if (Opc == ARM::t2LDMIA_UPD && Reg == 14)
410 case ARM::t2LDMIA_RET:
411 NewOpc = ARM::tPOP_RET;
413 case ARM::t2LDMIA_UPD:
416 case ARM::t2STMDB_UPD:
424 for (
unsigned i = 2, NumOps =
MBBI->getNumOperands(); i != NumOps; ++i)
425 NewInstr.
add(
MBBI->getOperand(i));
431 (Opc == ARM::t2LDMIA_RET) ? ARM::SEH_SaveRegs_Ret : ARM::SEH_SaveRegs;
438 case ARM::VSTMDDB_UPD:
439 case ARM::VLDMDIA_UPD: {
442 unsigned Reg =
RegInfo->getSEHRegNum(MO.getReg());
460 case ARM::t2SUBspImm:
461 case ARM::t2SUBspImm12:
462 case ARM::t2ADDspImm:
463 case ARM::t2ADDspImm12:
471 if (
MBBI->getOperand(1).getReg() == ARM::SP &&
473 unsigned Reg =
RegInfo->getSEHRegNum(
MBBI->getOperand(0).getReg());
477 }
else if (
MBBI->getOperand(0).getReg() == ARM::SP &&
479 unsigned Reg =
RegInfo->getSEHRegNum(
MBBI->getOperand(1).getReg());
489 case ARM::TCRETURNri:
490 case ARM::TCRETURNrinotr12:
496 case ARM::TCRETURNdi:
509 return std::prev(
MBBI);
517 Start = std::next(Start);
521 for (
auto MI = Start;
MI !=
End;) {
522 auto Next = std::next(
MI);
526 MI = std::next(Next);
543 Pred, PredReg,
TII, MIFlags);
546 Pred, PredReg,
TII, MIFlags);
554 unsigned PredReg = 0) {
556 MIFlags, Pred, PredReg);
561 switch (
MI.getOpcode()) {
562 case ARM::VSTMDDB_UPD:
566 case ARM::t2STMDB_UPD:
570 case ARM::STR_PRE_IMM:
579 for (
int i =
MI.getNumOperands() - 1; i >= 4; --i)
585 size_t StackSizeInBytes) {
591 F.getFnAttributeAsParsedInteger(
"stack-probe-size", StackProbeSize);
592 return (StackSizeInBytes >= StackProbeSize) &&
593 !
F.hasFnAttribute(
"no-stack-arg-probe");
598struct StackAdjustingInsts {
608 bool BeforeFPSet =
false) {
609 InstInfo
Info = {
I, SPAdjust, BeforeFPSet};
616 assert(
Info != Insts.
end() &&
"invalid sp adjusting instruction");
617 Info->SPAdjust += ExtraBytes;
623 unsigned CFAOffset = 0;
624 for (
auto &
Info : Insts) {
625 if (HasFP && !
Info.BeforeFPSet)
628 CFAOffset +=
Info.SPAdjust;
632 TII.get(TargetOpcode::CFI_INSTRUCTION))
653 const Align Alignment,
654 const bool MustBeSingleInstruction) {
656 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
657 const unsigned AlignMask = Alignment.
value() - 1U;
658 const unsigned NrBitsToZero =
Log2(Alignment);
675 }
else if (AlignMask <= 255) {
682 assert(!MustBeSingleInstruction &&
683 "Shouldn't call emitAligningInstructions demanding a single "
684 "instruction to be emitted for large stack alignment for a target "
722 int MaxRegBytes = 8 * 4;
726 MaxRegBytes = 11 * 4 + 8 * 8;
745 "This emitPrologue does not support Thumb1!");
751 int FPCXTSaveSize = 0;
762 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
763 int FramePtrSpillFI = 0;
771 StackAdjustingInsts DefCFAOffsetCandidates;
772 bool HasFP =
hasFP(MF);
779 DefCFAOffsetCandidates.addInst(std::prev(
MBBI), NumBytes,
true);
782 DefCFAOffsetCandidates.emitDefCFAOffsets(
MBB, dl,
TII, HasFP);
796 int FI =
I.getFrameIdx();
801 FramePtrSpillFI = FI;
832 int FI =
I.getFrameIdx();
854 FramePtrSpillFI = FI;
877 if (FPCXTSaveSize > 0) {
879 DefCFAOffsetCandidates.addInst(LastPush, FPCXTSaveSize,
true);
883 if (ArgRegsSaveSize) {
886 LastPush = std::prev(
MBBI);
887 DefCFAOffsetCandidates.addInst(LastPush, ArgRegsSaveSize,
true);
891 if (GPRCS1Size > 0) {
892 GPRCS1Push = LastPush =
MBBI++;
893 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size,
true);
897 unsigned FPCXTOffset = NumBytes - ArgRegsSaveSize - FPCXTSaveSize;
898 unsigned GPRCS1Offset = FPCXTOffset - GPRCS1Size;
899 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
901 unsigned DPRGapSize = GPRCS1Size + FPCXTSaveSize + ArgRegsSaveSize;
903 DPRGapSize += GPRCS2Size;
905 DPRGapSize %= DPRAlign.
value();
907 unsigned DPRCSOffset;
909 DPRCSOffset = GPRCS1Offset - DPRGapSize - DPRCSSize;
910 GPRCS2Offset = DPRCSOffset - GPRCS2Size;
912 DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
914 int FramePtrOffsetInPush = 0;
918 "Max FP estimation is wrong");
919 FramePtrOffsetInPush = FPOffset + ArgRegsSaveSize + FPCXTSaveSize;
929 GPRCS2Push = LastPush =
MBBI++;
930 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
936 assert(DPRGapSize == 4 &&
"unexpected alignment requirements for DPRs");
937 if (LastPush !=
MBB.
end() &&
939 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
943 DefCFAOffsetCandidates.addInst(std::prev(
MBBI), DPRGapSize);
951 while (
MBBI !=
MBB.
end() &&
MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
966 NumBytes = DPRCSOffset;
969 GPRCS2Push = LastPush =
MBBI++;
970 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
973 bool NeedsWinCFIStackAlloc = NeedsWinCFI;
975 NeedsWinCFIStackAlloc =
false;
980 if (NumWords < 65536) {
990 .
addImm(NumWords & 0xffff)
1000 switch (
TM.getCodeModel()) {
1032 if (NeedsWinCFIStackAlloc) {
1033 SEH =
BuildMI(MF, dl,
TII.get(ARM::SEH_StackAlloc))
1046 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
1050 DefCFAOffsetCandidates.addInst(std::prev(
MBBI), NumBytes);
1076 AfterPush = std::next(GPRCS1Push);
1078 int FPOffset = PushSize + FramePtrOffsetInPush;
1080 AfterPush = std::next(GPRCS2Push);
1089 if (FramePtrOffsetInPush + PushSize != 0) {
1092 FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush));
1093 BuildMI(
MBB, AfterPush, dl,
TII.get(TargetOpcode::CFI_INSTRUCTION))
1100 BuildMI(
MBB, AfterPush, dl,
TII.get(TargetOpcode::CFI_INSTRUCTION))
1122 if (GPRCS1Size > 0 && !NeedsWinCFI) {
1125 for (
const auto &Entry : CSI) {
1127 int FI = Entry.getFrameIdx();
1148 BuildMI(
MBB, Pos, dl,
TII.get(TargetOpcode::CFI_INSTRUCTION))
1156 if (GPRCS2Size > 0 && !NeedsWinCFI) {
1158 for (
const auto &Entry : CSI) {
1160 int FI = Entry.getFrameIdx();
1168 unsigned DwarfReg =
MRI->getDwarfRegNum(
1169 Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg,
true);
1173 BuildMI(
MBB, Pos, dl,
TII.get(TargetOpcode::CFI_INSTRUCTION))
1182 if (DPRCSSize > 0 && !NeedsWinCFI) {
1186 for (
const auto &Entry : CSI) {
1188 int FI = Entry.getFrameIdx();
1189 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
1191 unsigned DwarfReg =
MRI->getDwarfRegNum(Reg,
true);
1195 BuildMI(
MBB, Pos, dl,
TII.get(TargetOpcode::CFI_INSTRUCTION))
1207 DefCFAOffsetCandidates.emitDefCFAOffsets(
MBB, dl,
TII, HasFP);
1282 "This emitEpilogue does not support Thumb1!");
1312 if (NumBytes + IncomingArgStackToRestore != 0)
1314 NumBytes + IncomingArgStackToRestore,
1334 NumBytes -= (ReservedArgStack +
1359 "No scratch register to restore SP from FP!");
1381 }
else if (NumBytes &&
1394 while (
MBBI !=
MBB.
end() &&
MBBI->getOpcode() == ARM::VLDMDIA_UPD)
1399 "unexpected DPR alignment gap");
1408 if (ReservedArgStack || IncomingArgStackToRestore) {
1409 assert((
int)ReservedArgStack + IncomingArgStackToRestore >= 0 &&
1410 "attempting to restore negative stack amount");
1412 ReservedArgStack + IncomingArgStackToRestore,
1461 if (RegInfo->hasStackRealignment(MF)) {
1462 assert(
hasFP(MF) &&
"dynamic stack realignment without a FP!");
1466 }
else if (hasMovingSP) {
1468 "VLAs and dynamic stack alignment, but missing base pointer!");
1482 }
else if (hasMovingSP) {
1488 if (FPOffset >= -255 && FPOffset < 0) {
1507 }
else if (
Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1526 unsigned StmOpc,
unsigned StrOpc,
1527 bool NoGap,
bool (*Func)(
unsigned,
bool),
1528 unsigned NumAlignedDPRCS2Regs,
1529 unsigned MIFlags)
const {
1536 using RegAndKill = std::pair<unsigned, bool>;
1539 unsigned i = CSI.
size();
1541 unsigned LastReg = 0;
1542 for (; i != 0; --i) {
1547 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1551 bool isLiveIn =
MRI.isLiveIn(Reg);
1552 if (!isLiveIn && !
MRI.isReserved(Reg))
1557 if (NoGap && LastReg && LastReg != Reg-1)
1565 Regs.
push_back(std::make_pair(Reg, !isLiveIn));
1571 llvm::sort(Regs, [&](
const RegAndKill &LHS,
const RegAndKill &RHS) {
1572 return TRI.getEncodingValue(
LHS.first) <
TRI.getEncodingValue(
RHS.first);
1575 if (Regs.
size() > 1 || StrOpc== 0) {
1580 for (
unsigned i = 0, e = Regs.
size(); i < e; ++i)
1582 }
else if (Regs.
size() == 1) {
1603 unsigned LdmOpc,
unsigned LdrOpc,
1604 bool isVarArg,
bool NoGap,
1605 bool (*Func)(
unsigned,
bool),
1606 unsigned NumAlignedDPRCS2Regs)
const {
1613 bool isTailCall =
false;
1614 bool isInterrupt =
false;
1615 bool isTrap =
false;
1616 bool isCmseEntry =
false;
1618 DL =
MI->getDebugLoc();
1619 unsigned RetOpcode =
MI->getOpcode();
1621 (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri ||
1622 RetOpcode == ARM::TCRETURNrinotr12);
1624 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
1626 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
1627 RetOpcode == ARM::tTRAP;
1628 isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET);
1632 unsigned i = CSI.
size();
1634 unsigned LastReg = 0;
1635 bool DeleteRet =
false;
1636 for (; i != 0; --i) {
1642 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1644 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
1657 if (NoGap && LastReg && LastReg != Reg-1)
1667 llvm::sort(Regs, [&](
unsigned LHS,
unsigned RHS) {
1668 return TRI.getEncodingValue(LHS) <
TRI.getEncodingValue(RHS);
1671 if (Regs.
size() > 1 || LdrOpc == 0) {
1676 for (
unsigned i = 0, e = Regs.
size(); i < e; ++i)
1681 MI->eraseFromParent();
1685 }
else if (Regs.
size() == 1) {
1688 if (Regs[0] == ARM::PC)
1697 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1718 unsigned NumAlignedDPRCS2Regs,
1731 unsigned DNum =
I.getReg() - ARM::D8;
1732 if (DNum > NumAlignedDPRCS2Regs - 1)
1734 int FI =
I.getFrameIdx();
1762 unsigned Opc =
isThumb ? ARM::t2SUBri : ARM::SUBri;
1765 .
addImm(8 * NumAlignedDPRCS2Regs)
1781 Opc =
isThumb ? ARM::tMOVr : ARM::MOVr;
1790 unsigned NextReg = ARM::D8;
1794 if (NumAlignedDPRCS2Regs >= 6) {
1795 unsigned SupReg =
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1796 &ARM::QQPRRegClass);
1805 NumAlignedDPRCS2Regs -= 4;
1810 unsigned R4BaseReg = NextReg;
1813 if (NumAlignedDPRCS2Regs >= 4) {
1814 unsigned SupReg =
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1815 &ARM::QQPRRegClass);
1824 NumAlignedDPRCS2Regs -= 4;
1828 if (NumAlignedDPRCS2Regs >= 2) {
1829 unsigned SupReg =
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1838 NumAlignedDPRCS2Regs -= 2;
1842 if (NumAlignedDPRCS2Regs) {
1848 .
addImm((NextReg - R4BaseReg) * 2)
1860 unsigned NumAlignedDPRCS2Regs) {
1865 assert(
MI->mayStore() &&
"Expecting spill instruction");
1868 switch(NumAlignedDPRCS2Regs) {
1871 assert(
MI->mayStore() &&
"Expecting spill instruction");
1875 assert(
MI->mayStore() &&
"Expecting spill instruction");
1880 assert(
MI->killsRegister(ARM::R4,
nullptr) &&
"Missed kill flag");
1891 unsigned NumAlignedDPRCS2Regs,
1902 if (
I.getReg() == ARM::D8) {
1903 D8SpillFI =
I.getFrameIdx();
1915 unsigned Opc =
isThumb ? ARM::t2ADDri : ARM::ADDri;
1923 unsigned NextReg = ARM::D8;
1926 if (NumAlignedDPRCS2Regs >= 6) {
1927 unsigned SupReg =
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1928 &ARM::QQPRRegClass);
1936 NumAlignedDPRCS2Regs -= 4;
1941 unsigned R4BaseReg = NextReg;
1944 if (NumAlignedDPRCS2Regs >= 4) {
1945 unsigned SupReg =
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1946 &ARM::QQPRRegClass);
1953 NumAlignedDPRCS2Regs -= 4;
1957 if (NumAlignedDPRCS2Regs >= 2) {
1958 unsigned SupReg =
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1965 NumAlignedDPRCS2Regs -= 2;
1969 if (NumAlignedDPRCS2Regs)
1972 .
addImm(2 * (NextReg - R4BaseReg))
1988 unsigned PushOpc = AFI->
isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1990 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1991 unsigned FltOpc = ARM::VSTMDDB_UPD;
2000 return C.getReg() == ARM::FPCXTNS;
2009 emitPushInst(
MBB,
MI, CSI, PushOpc, PushOneOpc,
false,
2013 emitPushInst(
MBB,
MI, CSI, PushOpc, PushOneOpc,
false,
2027 if (NumAlignedDPRCS2Regs)
2046 if (NumAlignedDPRCS2Regs)
2049 unsigned PopOpc = AFI->
isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
2052 unsigned FltOpc = ARM::VLDMDIA_UPD;
2054 emitPopInst(
MBB,
MI, CSI, PopOpc, LdrOpc, isVarArg,
false,
2057 NumAlignedDPRCS2Regs);
2058 emitPopInst(
MBB,
MI, CSI, PopOpc, LdrOpc, isVarArg,
false,
2062 NumAlignedDPRCS2Regs);
2063 emitPopInst(
MBB,
MI, CSI, PopOpc, LdrOpc, isVarArg,
false,
2065 emitPopInst(
MBB,
MI, CSI, PopOpc, LdrOpc, isVarArg,
false,
2075 unsigned FnSize = 0;
2076 for (
auto &
MBB : MF) {
2077 for (
auto &
MI :
MBB)
2078 FnSize +=
TII.getInstSizeInBytes(
MI);
2082 FnSize += Table.MBBs.size() * 4;
2093 bool &HasNonSPFrameIndex) {
2098 unsigned Limit = (1 << 12) - 1;
2099 for (
auto &
MBB : MF) {
2100 for (
auto &
MI :
MBB) {
2101 if (
MI.isDebugInstr())
2103 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
2104 if (!
MI.getOperand(i).isFI())
2109 if (
MI.getOpcode() == ARM::ADDri) {
2110 Limit = std::min(Limit, (1U << 8) - 1);
2115 if (
MI.getOpcode() == ARM::t2ADDri ||
MI.getOpcode() == ARM::t2ADDri12)
2120 if (RegClass && !RegClass->
contains(ARM::SP))
2121 HasNonSPFrameIndex =
true;
2131 Limit = std::min(Limit, (1U << 8) - 1);
2134 Limit = std::min(Limit, ((1U << 8) - 1) * 2);
2139 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
2145 Limit = std::min(Limit, (1U << 8) - 1);
2153 Limit = std::min(Limit, ((1U << 7) - 1) * 1);
2156 Limit = std::min(Limit, ((1U << 7) - 1) * 2);
2159 Limit = std::min(Limit, ((1U << 7) - 1) * 4);
2162 llvm_unreachable(
"Unhandled addressing mode in stack size limit calculation");
2203 unsigned NumSpills = 0;
2204 for (; NumSpills < 8; ++NumSpills)
2205 if (!SavedRegs.
test(ARM::D8 + NumSpills))
2216 SavedRegs.
set(ARM::R4);
2222 if (
STI.hasV8_1MMainlineOps() &&
2238 return Subtarget.createAAPCSFrameChainLeaf() ||
2252 for (
const auto &
MBB : MF)
2253 for (
const auto &
MI :
MBB)
2254 if (
MI.getOpcode() == ARM::tSTRspi ||
MI.getOpcode() == ARM::tSTRi ||
2255 STI.genExecuteOnly())
2256 for (
const auto &
Op :
MI.operands())
2260 if (ARM::hGPRRegClass.
contains(Reg) && Reg != ARM::SP)
2275 bool CS1Spilled =
false;
2276 bool LRSpilled =
false;
2277 unsigned NumGPRSpills = 0;
2278 unsigned NumFPRSpills = 0;
2298 (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF)))
2299 SavedRegs.
set(ARM::R4);
2308 SavedRegs.
set(ARM::R4);
2309 SavedRegs.
set(ARM::LR);
2315 SavedRegs.
set(ARM::LR);
2323 if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF) ||
2324 MFI.estimateStackSize(MF) > 508)
2325 SavedRegs.
set(ARM::R4);
2337 CanEliminateFrame =
false;
2341 CanEliminateFrame =
false;
2346 for (
unsigned i = 0; CSRegs[i]; ++i) {
2347 unsigned Reg = CSRegs[i];
2348 bool Spilled =
false;
2349 if (SavedRegs.
test(Reg)) {
2351 CanEliminateFrame =
false;
2354 if (!ARM::GPRRegClass.
contains(Reg)) {
2356 if (ARM::SPRRegClass.
contains(Reg))
2358 else if (ARM::DPRRegClass.
contains(Reg))
2360 else if (ARM::QPRRegClass.
contains(Reg))
2381 case ARM::R0:
case ARM::R1:
2382 case ARM::R2:
case ARM::R3:
2383 case ARM::R4:
case ARM::R5:
2384 case ARM::R6:
case ARM::R7:
2397 case ARM::R0:
case ARM::R1:
2398 case ARM::R2:
case ARM::R3:
2399 case ARM::R4:
case ARM::R5:
2400 case ARM::R6:
case ARM::R7:
2411 bool ForceLRSpill =
false;
2416 if (FnSize >= (1 << 11)) {
2417 CanEliminateFrame =
false;
2418 ForceLRSpill =
true;
2436 unsigned EstimatedStackSize =
2437 MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
2440 int MaxFixedOffset = 0;
2441 for (
int I = MFI.getObjectIndexBegin();
I < 0; ++
I) {
2442 int MaxObjectOffset = MFI.getObjectOffset(
I) + MFI.getObjectSize(
I);
2443 MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset);
2446 bool HasFP =
hasFP(MF);
2449 EstimatedStackSize += 4;
2453 EstimatedStackSize += MaxFixedOffset;
2455 EstimatedStackSize += 16;
2457 unsigned EstimatedRSStackSizeLimit, EstimatedRSFixedSizeLimit;
2458 bool HasNonSPFrameIndex =
false;
2479 EstimatedRSStackSizeLimit = (1U << 5) * 4;
2481 EstimatedRSStackSizeLimit = (1U << 8) * 4;
2482 EstimatedRSFixedSizeLimit = (1U << 5) * 4;
2484 EstimatedRSStackSizeLimit =
2486 EstimatedRSFixedSizeLimit = EstimatedRSStackSizeLimit;
2490 bool HasLargeStack = EstimatedStackSize > EstimatedRSStackSizeLimit;
2496 bool HasMovingSP = MFI.hasVarSizedObjects() ||
2498 bool HasBPOrFixedSP = RegInfo->
hasBasePointer(MF) || !HasMovingSP;
2507 bool HasLargeArgumentList =
2508 HasFP && (MaxFixedOffset - MaxFPOffset) > (
int)EstimatedRSFixedSizeLimit;
2510 bool BigFrameOffsets = HasLargeStack || !HasBPOrFixedSP ||
2511 HasLargeArgumentList || HasNonSPFrameIndex;
2512 LLVM_DEBUG(
dbgs() <<
"EstimatedLimit: " << EstimatedRSStackSizeLimit
2513 <<
"; EstimatedStack: " << EstimatedStackSize
2514 <<
"; EstimatedFPStack: " << MaxFixedOffset - MaxFPOffset
2515 <<
"; BigFrameOffsets: " << BigFrameOffsets <<
"\n");
2516 if (BigFrameOffsets ||
2527 SavedRegs.
set(ARM::LR);
2530 auto LRPos =
llvm::find(UnspilledCS1GPRs, ARM::LR);
2531 if (LRPos != UnspilledCS1GPRs.
end())
2532 UnspilledCS1GPRs.
erase(LRPos);
2535 if (FPPos != UnspilledCS1GPRs.
end())
2536 UnspilledCS1GPRs.
erase(FPPos);
2554 unsigned NumExtraCSSpill = 0;
2571 int EntryRegDeficit = 0;
2572 for (
unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
2577 <<
" is unused argument register, EntryRegDeficit = "
2578 << EntryRegDeficit <<
"\n");
2585 <<
" return regs used, ExitRegDeficit = "
2586 << ExitRegDeficit <<
"\n");
2588 int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
2593 for (
unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
2594 if (SavedRegs.
test(Reg)) {
2597 <<
" is saved low register, RegDeficit = "
2598 << RegDeficit <<
"\n");
2604 <<
" is non-saved low register, adding to AvailableRegs\n");
2609 if (!HasFP ||
FramePtr != ARM::R7) {
2610 if (SavedRegs.
test(ARM::R7)) {
2613 << RegDeficit <<
"\n");
2618 <<
"%r7 is non-saved low register, adding to AvailableRegs\n");
2623 for (
unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
2624 if (SavedRegs.
test(Reg)) {
2627 <<
" is saved high register, RegDeficit = "
2628 << RegDeficit <<
"\n");
2635 if ((EntryRegDeficit > ExitRegDeficit) &&
2638 if (SavedRegs.
test(ARM::LR)) {
2641 << RegDeficit <<
"\n");
2644 LLVM_DEBUG(
dbgs() <<
"%lr is not saved, adding to AvailableRegs\n");
2653 LLVM_DEBUG(
dbgs() <<
"Final RegDeficit = " << RegDeficit <<
"\n");
2654 for (; RegDeficit > 0 && !AvailableRegs.
empty(); --RegDeficit) {
2657 <<
" to make up reg deficit\n");
2661 assert(!
MRI.isReserved(Reg) &&
"Should not be reserved");
2662 if (Reg != ARM::LR && !
MRI.isPhysRegUsed(Reg))
2668 LLVM_DEBUG(
dbgs() <<
"After adding spills, RegDeficit = " << RegDeficit
2678 if (!LRSpilled && CS1Spilled && !ExpensiveLRRestore) {
2679 SavedRegs.
set(ARM::LR);
2682 LRPos =
llvm::find(UnspilledCS1GPRs, (
unsigned)ARM::LR);
2683 if (LRPos != UnspilledCS1GPRs.
end())
2684 UnspilledCS1GPRs.
erase(LRPos);
2686 ForceLRSpill =
false;
2687 if (!
MRI.isReserved(ARM::LR) && !
MRI.isPhysRegUsed(ARM::LR) &&
2697 if (TargetAlign >=
Align(8) && (NumGPRSpills & 1)) {
2698 if (CS1Spilled && !UnspilledCS1GPRs.
empty()) {
2699 for (
unsigned Reg : UnspilledCS1GPRs) {
2705 (Reg == ARM::LR && !ExpensiveLRRestore)) {
2708 <<
" to make up alignment\n");
2709 if (!
MRI.isReserved(Reg) && !
MRI.isPhysRegUsed(Reg) &&
2716 unsigned Reg = UnspilledCS2GPRs.
front();
2719 <<
" to make up alignment\n");
2720 if (!
MRI.isReserved(Reg) && !
MRI.isPhysRegUsed(Reg))
2731 unsigned RegsNeeded = 0;
2740 if (RegsNeeded > NumExtraCSSpill) {
2743 unsigned NumExtras = TargetAlign.
value() / 4;
2745 while (NumExtras && !UnspilledCS1GPRs.
empty()) {
2747 if (!
MRI.isReserved(Reg) &&
2755 while (NumExtras && !UnspilledCS2GPRs.
empty()) {
2757 if (!
MRI.isReserved(Reg)) {
2763 if (NumExtras == 0) {
2764 for (
unsigned Reg : Extras) {
2766 if (!
MRI.isPhysRegUsed(Reg))
2770 while ((RegsNeeded > NumExtraCSSpill) && RS) {
2774 unsigned Size =
TRI->getSpillSize(RC);
2775 Align Alignment =
TRI->getSpillAlign(RC);
2777 MFI.CreateStackObject(
Size, Alignment,
false));
2784 SavedRegs.
set(ARM::LR);
2797 if (
Info.getReg() != ARM::LR)
2801 return !Term.isReturn() || Term.getOpcode() == ARM::LDMIA_RET ||
2802 Term.getOpcode() == ARM::t2LDMIA_RET ||
2803 Term.getOpcode() == ARM::tPOP_RET;
2806 Info.setRestored(
false);
2827 SavedRegs.
set(ARM::R0);
2832 std::vector<CalleeSavedInfo> &CSI)
const {
2835 if (
STI.hasV8_1MMainlineOps() &&
2837 CSI.emplace_back(ARM::FPCXTNS);
2838 CSI.back().setRestored(
false);
2852 [=](
const auto &CS) {
2854 return Reg == ARM::R10 || Reg == ARM::R11 ||
2855 Reg == ARM::R8 || Reg == ARM::R9 ||
2856 ARM::DPRRegClass.contains(Reg);
2866 static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}};
2867 NumEntries = std::size(FixedSpillOffsets);
2868 return FixedSpillOffsets;
2879 unsigned Opc =
I->getOpcode();
2880 bool IsDestroy = Opc ==
TII.getCallFrameDestroyOpcode();
2881 unsigned CalleePopAmount = IsDestroy ?
I->getOperand(1).getImm() : 0;
2884 "This eliminateCallFramePseudoInstr does not support Thumb1!");
2886 int PIdx =
I->findFirstPredOperandIdx();
2890 unsigned PredReg =
TII.getFramePred(*
I);
2894 if (IsDestroy && CalleePopAmount != -1U)
2900 unsigned Amount =
TII.getFrameSize(*
I);
2907 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
2911 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
2916 }
else if (CalleePopAmount != -1U) {
2930 unsigned Shifted = 0;
2935 while (!(
Value & 0xC0000000)) {
2940 bool Carry = (
Value & 0x00FFFFFF);
2941 Value = ((
Value & 0xFF000000) >> 24) + Carry;
2943 if (
Value & 0x0000100)
2987 bool Thumb = ST->isThumb();
2988 bool Thumb2 = ST->isThumb2();
2994 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
3013 unsigned ScratchReg0 = ARM::R4;
3014 unsigned ScratchReg1 = ARM::R5;
3015 unsigned MovOp = ST->useMovt() ? ARM::t2MOVi32imm : ARM::tMOVi32imm;
3032 if (BeforePrologueRegion.
insert(PredBB).second)
3035 }
while (!WalkList.
empty());
3045 BeforePrologueRegion.
insert(
B);
3047 for (
const auto &LI : PrologueMBB.
liveins()) {
3049 PredBB->addLiveIn(LI);
3055 BeforePrologueRegion.
erase(
B);
3100 BuildMI(PrevStackMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3103 nullptr,
MRI->getDwarfRegNum(ScratchReg1,
true), -4));
3104 BuildMI(PrevStackMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3107 nullptr,
MRI->getDwarfRegNum(ScratchReg0,
true), -8));
3108 BuildMI(PrevStackMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3117 }
else if (CompareStackPointer) {
3125 if (!CompareStackPointer && Thumb) {
3126 if (AlignedStackSize < 256) {
3130 .
addImm(AlignedStackSize)
3133 if (Thumb2 || ST->genExecuteOnly()) {
3135 .
addImm(AlignedStackSize);
3148 }
else if (!CompareStackPointer) {
3149 if (AlignedStackSize < 256) {
3152 .
addImm(AlignedStackSize)
3168 if (Thumb && ST->isThumb1Only()) {
3169 if (ST->genExecuteOnly()) {
3180 BuildMI(GetMBB,
DL,
TII.get(ARM::tLDRpci), ScratchReg0)
3193 BuildMI(McrMBB,
DL,
TII.get(Thumb ? ARM::t2MRC : ARM::MRC),
3203 assert(ST->isTargetAndroid() || ST->isTargetLinux());
3204 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
3208 BuildMI(GetMBB,
DL,
TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12),
3217 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
3224 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
3237 if (AlignedStackSize < 256) {
3238 BuildMI(AllocMBB,
DL,
TII.get(ARM::tMOVi8), ScratchReg0)
3240 .
addImm(AlignedStackSize)
3243 if (Thumb2 || ST->genExecuteOnly()) {
3245 .
addImm(AlignedStackSize);
3254 if (AlignedStackSize < 256) {
3256 .
addImm(AlignedStackSize)
3271 BuildMI(AllocMBB,
DL,
TII.get(ARM::tMOVi8), ScratchReg1)
3276 if (Thumb2 || ST->genExecuteOnly()) {
3283 *AllocMBB,
MBBI,
DL, ScratchReg1, 0,
3297 *AllocMBB,
MBBI,
DL, ScratchReg1, 0,
3319 BuildMI(AllocMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3322 nullptr,
MRI->getDwarfRegNum(ARM::LR,
true), -12));
3323 BuildMI(AllocMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3339 if (ST->isThumb1Only()) {
3383 BuildMI(AllocMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3409 BuildMI(PostStackMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3415 nullptr,
MRI->getDwarfRegNum(ScratchReg0,
true)));
3416 BuildMI(PostStackMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3419 nullptr,
MRI->getDwarfRegNum(ScratchReg1,
true)));
3420 BuildMI(PostStackMBB,
DL,
TII.get(TargetOpcode::CFI_INSTRUCTION))
3436#ifdef EXPENSIVE_CHECKS
unsigned const MachineRegisterInfo * MRI
static int64_t getArgumentStackToRestore(MachineFunction &MF, MachineBasicBlock &MBB)
Returns how much of the incoming argument stack area (in bytes) we should clean up in an epilogue.
static bool needsWinCFI(const MachineFunction &MF)
static unsigned estimateRSStackSizeLimit(MachineFunction &MF)
Look at each instruction that references stack frames and return the stack size limit beyond which so...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isThumb(const MCSubtargetInfo &STI)
static MachineBasicBlock::iterator skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs)
Skip past the code inserted by emitAlignedDPRCS2Spills, and return an iterator to the following instr...
static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const unsigned Reg, const Align Alignment, const bool MustBeSingleInstruction)
Emit an instruction sequence that will align the address in register Reg by zero-ing out the lower bi...
static uint32_t alignToARMConstant(uint32_t Value)
Get the minimum constant for ARM that is greater than or equal to the argument.
static void checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs)
static void insertSEHRange(MachineBasicBlock &MBB, MachineBasicBlock::iterator Start, const MachineBasicBlock::iterator &End, const ARMBaseInstrInfo &TII, unsigned MIFlags)
static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI)
Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers starting from d8.
static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI)
Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers starting from d8.
static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII)
static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI, const TargetInstrInfo &TII, unsigned Flags)
static bool canSpillOnFrameIndexAccess(const MachineFunction &MF, const TargetFrameLowering &TFI)
static bool requiresAAPCSFrameRecord(const MachineFunction &MF)
static bool WindowsRequiresStackProbe(const MachineFunction &MF, size_t StackSizeInBytes)
static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI, const MachineFunction &MF)
We need the offset of the frame pointer relative to other MachineFrameInfo offsets which are encoded ...
static MachineBasicBlock::iterator initMBBRange(MachineBasicBlock &MBB, const MachineBasicBlock::iterator &MBBI)
static int sizeOfSPAdjustment(const MachineInstr &MI)
static const uint64_t kSplitStackAvailable
static cl::opt< bool > SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), cl::desc("Align ARM NEON spills in prolog and epilog"))
static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
const HexagonInstrInfo * TII
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static const unsigned FramePtr
bool hasBasePointer(const MachineFunction &MF) const
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool cannotEliminateFrame(const MachineFunction &MF) const
Register getFrameRegister(const MachineFunction &MF) const override
bool canRealignStack(const MachineFunction &MF) const override
Register getBaseRegister() const
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
ARMConstantPoolValue - ARM specific constantpool value.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - Provide a base+offset reference to an FI slot for debug info.
static void updateLRRestored(MachineFunction &MF)
Update the IsRestored flag on LR if it is spilled, based on the return instructions.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
ARMFrameLowering(const ARMSubtarget &sti)
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool keepFramePointer(const MachineFunction &MF) const override
Return true if the target wants to keep the frame pointer regardless of the function attribute "frame...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool isFPReserved(const MachineFunction &MF) const
isFPReserved - Return true if the frame pointer register should be considered a reserved register on ...
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &MBB) const override
Adjust the prologue to have the function use segmented stacks.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, int SPAdj) const
void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const override
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
void setDPRCalleeSavedAreaSize(unsigned s)
bool hasStackFrame() const
bool isThumb2Function() const
unsigned getFPCXTSaveAreaSize() const
unsigned getGPRCalleeSavedArea1Size() const
unsigned getDPRCalleeSavedGapSize() const
unsigned createPICLabelUId()
void setLRIsSpilled(bool s)
void setGPRCalleeSavedArea2Size(unsigned s)
bool isThumb1OnlyFunction() const
void setHasStackFrame(bool s)
void setDPRCalleeSavedAreaOffset(unsigned o)
bool isThumbFunction() const
void setFramePtrSpillOffset(unsigned o)
unsigned getGPRCalleeSavedArea2Size() const
unsigned getNumAlignedDPRCS2Regs() const
bool shouldSignReturnAddress() const
void setGPRCalleeSavedArea1Size(unsigned s)
unsigned getArgumentStackToRestore() const
void setFPCXTSaveAreaSize(unsigned s)
bool isCmseNSEntryFunction() const
unsigned getDPRCalleeSavedAreaSize() const
unsigned getFramePtrSpillOffset() const
bool shouldRestoreSPFromFP() const
unsigned getArgRegsSaveSize() const
void setGPRCalleeSavedArea2Offset(unsigned o)
void setGPRCalleeSavedArea1Offset(unsigned o)
void setDPRCalleeSavedGapSize(unsigned s)
unsigned getArgumentStackSize() const
void setShouldRestoreSPFromFP(bool s)
unsigned getReturnRegsCount() const
bool getPreservesR0() const
const ARMBaseInstrInfo * getInstrInfo() const override
bool isTargetWindows() const
const ARMBaseRegisterInfo * getRegisterInfo() const override
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
bool splitFramePointerPush(const MachineFunction &MF) const
const ARMFrameLowering * getFrameLowering() const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
bool test(unsigned Idx) const
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
This class represents an Operation in the Expression.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool usesWindowsCFI() const
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
Context object for machine code objects.
Describe properties that are true of each instruction in the target description file.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
iterator_range< livein_iterator > liveins() const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
iterator_range< iterator > terminators()
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
MachineInstrBundleIterator< MachineInstr > iterator
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool needsSplitStackProlog() const
Return true if this function requires a split stack prolog, even if it uses no stack space.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
int getStackProtectorIndex() const
Return the index for the stack protector object.
int getOffsetAdjustment() const
Return the correction for frame offsets.
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
void setHasWinCFI(bool v)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Representation of each machine instruction.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
const std::vector< MachineJumpTableEntry > & getJumpTables() const
This class contains meta information specific to a module.
const MCContext & getContext() const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isLiveIn(Register Reg) const
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
iterator erase(const_iterator CI)
typename SuperClass::iterator iterator
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ C
The default llvm calling convention, compatible with C.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isSplitFPArea1Register(unsigned Reg, bool SplitFramePushPop)
static bool isARMArea2Register(unsigned Reg, bool SplitFramePushPop)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isSEHInstruction(const MachineInstr &MI)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
static bool isARMArea3Register(unsigned Reg, bool SplitFramePushPop)
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
static bool isARMArea1Register(unsigned Reg, bool SplitFramePushPop)
isARMArea1Register - Returns true if the register is a low register (r0-r7) or a stack/pc register th...
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static bool isSplitFPArea2Register(unsigned Reg, bool SplitFramePushPop)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.