llvm::ARMBaseInstrInfo Class Reference

#include "Target/ARM/ARMBaseInstrInfo.h"

Inheritance diagram for llvm::ARMBaseInstrInfo:

Public Member Functions
bool	hasNOP () const
virtual unsigned	getUnindexedOpcode (unsigned Opc) const =0
const ARMBaseRegisterInfo &	getRegisterInfo () const
const ARMSubtarget &	getSubtarget () const
ScheduleHazardRecognizer *	CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
ScheduleHazardRecognizer *	CreateTargetMIHazardRecognizer (const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	isPredicated (const MachineInstr &MI) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
ARMCC::CondCodes	getPredicate (const MachineInstr &MI) const
bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool	isPredicable (const MachineInstr &MI) const override
	isPredicable - Return true if the specified instruction can be predicated.
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Returns the size of the specified MachineInstr.
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
void	copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MCRegister SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void	copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MCRegister DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, unsigned SubReg=0, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool	expandPostRAPseudo (MachineInstr &MI) const override
bool	shouldSink (const MachineInstr &MI) const override
void	reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, LaneBitmask UsedLanes=LaneBitmask::getAll()) const override
MachineInstr &	duplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
const MachineInstrBuilder &	AddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, RegState State) const
bool	produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
bool	areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
	areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
bool	shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
	shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
unsigned	extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const override
unsigned	predictBranchSizeForIfCvt (MachineInstr &MI) const override
bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
	analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
	optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool	foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
	foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
unsigned	getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override
std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
std::pair< uint16_t, uint16_t >	getExecutionDomain (const MachineInstr &MI) const override
	VFP/NEON execution domains.
void	setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
unsigned	getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
void	breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
unsigned	getNumLDMAddresses (const MachineInstr &MI) const
	Get the number of addresses by LDM or VLDM or zero for unknown.
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
	ARM supports the MachineOutliner.
std::optional< std::unique_ptr< outliner::OutlinedFunction > >	getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
void	mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const override
outliner::InstrType	getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
	Enable outlining by default at -Oz.
bool	isUnspillableTerminatorImpl (const MachineInstr *MI) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
bool	isFpMLxInstruction (unsigned Opcode) const
	isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool	isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
	isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
bool	canCauseFpMLxStall (unsigned Opcode) const
	canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
bool	isSwiftFastImmShift (const MachineInstr *MI) const
	Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
unsigned	getFramePred (const MachineInstr &MI) const
	Returns predicate register associated with the given frame instruction.
std::optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override

Static Public Member Functions
static bool	isCPSRDefined (const MachineInstr &MI)

Protected Member Functions
	ARMBaseInstrInfo (const ARMSubtarget &STI, const ARMBaseRegisterInfo &TRI)
void	expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool	getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
	Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool	getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
	Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
bool	getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
	Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
	Commutes the operands in the given instruction.
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
std::optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override
	Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.

Detailed Description

Definition at line 42 of file ARMBaseInstrInfo.h.

Constructor & Destructor Documentation

ARMBaseInstrInfo()

ARMBaseInstrInfo::ARMBaseInstrInfo ( const ARMSubtarget & STI, const ARMBaseRegisterInfo & TRI )

explicitprotected

Definition at line 109 of file ARMBaseInstrInfo.cpp.

References ARM_MLxTable, llvm_unreachable, and TRI.

Referenced by llvm::ARMInstrInfo::ARMInstrInfo(), llvm::Thumb1InstrInfo::Thumb1InstrInfo(), and llvm::Thumb2InstrInfo::Thumb2InstrInfo().

Member Function Documentation

AddDReg()

const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg	(	MachineInstrBuilder &	MIB,
		unsigned	Reg,
		unsigned	SubIdx,
		RegState	State ) const

Definition at line 930 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), getRegisterInfo(), and llvm::Register::isPhysicalRegister().

Referenced by loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), storeRegToStackSlot(), and llvm::Thumb2InstrInfo::storeRegToStackSlot().

analyzeBranch()

bool ARMBaseInstrInfo::analyzeBranch ( MachineBasicBlock & MBB, MachineBasicBlock *& TBB, MachineBasicBlock *& FBB, SmallVectorImpl< MachineOperand > & Cond, bool AllowModify = false ) const

override

Definition at line 181 of file ARMBaseInstrInfo.cpp.

References assert(), Cond, llvm::MachineOperand::CreateImm(), llvm::ARMSubtarget::enableMachinePipeliner(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getOpcode(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), isPredicated(), llvm::isSpeculationBarrierEndBBOpcode(), llvm::isUncondBranchOpcode(), MBB, removeBranch(), and TBB.

analyzeCompare()

bool ARMBaseInstrInfo::analyzeCompare ( const MachineInstr & MI, Register & SrcReg, Register & SrcReg2, int64_t & CmpMask, int64_t & CmpValue ) const

override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 2612 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by shouldSink().

analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > ARMBaseInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const

override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 6744 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, llvm::MachineBasicBlock::instrs(), isCPSRDefined(), llvm::isVCTP(), and llvm::MachineBasicBlock::pred_begin().

areLoadsFromSameBasePtr()

bool ARMBaseInstrInfo::areLoadsFromSameBasePtr ( SDNode * Load1, SDNode * Load2, int64_t & Offset1, int64_t & Offset2 ) const

override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1793 of file ARMBaseInstrInfo.cpp.

References llvm::cast(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::isa(), and llvm::SDNode::isMachineOpcode().

breakPartialRegDependency()

void ARMBaseInstrInfo::breakPartialRegDependency ( MachineInstr & MI, unsigned OpNum, const TargetRegisterInfo * TRI ) const

override

Definition at line 5228 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), contains(), llvm::get(), llvm::MachineOperand::getReg(), MI, llvm::predOps(), and TRI.

buildOutlinedFrame()

void ARMBaseInstrInfo::buildOutlinedFrame ( MachineBasicBlock & MBB, MachineFunction & MF, const outliner::OutlinedFunction & OF ) const

override

Definition at line 6352 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::ARMCC::AL, llvm::any_of(), assert(), llvm::BuildMI(), Call, llvm::get(), llvm::MachineFunction::getInfo(), isThumb(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, Opc, and llvm::predOps().

canCauseFpMLxStall()

bool llvm::ARMBaseInstrInfo::canCauseFpMLxStall ( unsigned Opcode ) const

inline

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.

Definition at line 509 of file ARMBaseInstrInfo.h.

ClobbersPredicate()

bool ARMBaseInstrInfo::ClobbersPredicate ( MachineInstr & MI, std::vector< MachineOperand > & Pred, bool SkipDead ) const

override

Definition at line 487 of file ARMBaseInstrInfo.cpp.

References MI, and llvm::ARMII::ThumbArithFlagSetting.

commuteInstructionImpl()

MachineInstr * ARMBaseInstrInfo::commuteInstructionImpl ( MachineInstr & MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2 ) const

overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 2101 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), MI, and llvm::MachineOperand::setImm().

Referenced by llvm::Thumb2InstrInfo::commuteInstructionImpl().

copyFromCPSR()

void ARMBaseInstrInfo::copyFromCPSR	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		MCRegister	DestReg,
		bool	KillSrc,
		const ARMSubtarget &	Subtarget ) const

Definition at line 652 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::get(), llvm::getKillRegState(), I, llvm::Implicit, MBB, Opc, and llvm::predOps().

Referenced by copyPhysReg().

copyPhysReg()

void ARMBaseInstrInfo::copyPhysReg ( MachineBasicBlock & MBB, MachineBasicBlock::iterator I, const DebugLoc & DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false ) const

override

Definition at line 716 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::addUnpredicatedMveVpredROp(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), contains(), copyFromCPSR(), copyToCPSR(), llvm::SmallSet< T, N, C >::count(), DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, llvm::SmallSet< T, N, C >::insert(), MBB, Opc, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::copyPhysReg(), and insertOutlinedCall().

copyToCPSR()

void ARMBaseInstrInfo::copyToCPSR	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		MCRegister	SrcReg,
		bool	KillSrc,
		const ARMSubtarget &	Subtarget ) const

Definition at line 672 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::Define, llvm::get(), llvm::getKillRegState(), I, llvm::Implicit, MBB, Opc, and llvm::predOps().

Referenced by copyPhysReg().

createMIROperandComment()

std::string ARMBaseInstrInfo::createMIROperandComment ( const MachineInstr & MI, const MachineOperand & Op, unsigned OpIdx, const TargetRegisterInfo * TRI ) const

override

Definition at line 402 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCondCodeToString(), llvm::TargetInstrInfo::createMIROperandComment(), MI, and TRI.

CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI, const ScheduleDAG * DAG ) const

override

Definition at line 124 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), and II.

CreateTargetMIHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetMIHazardRecognizer ( const InstrItineraryData * II, const ScheduleDAGMI * DAG ) const

override

Definition at line 137 of file ARMBaseInstrInfo.cpp.

References llvm::MultiHazardRecognizer::AddHazardRecognizer(), llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), and II.

CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II, const ScheduleDAG * DAG ) const

override

Definition at line 159 of file ARMBaseInstrInfo.cpp.

References llvm::MultiHazardRecognizer::AddHazardRecognizer(), llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), and II.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF ) const

override

Definition at line 5357 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::MO_OPTION_MASK.

describeLoadedValue()

std::optional< ParamLoadedValue > ARMBaseInstrInfo::describeLoadedValue ( const MachineInstr & MI, Register Reg ) const

overrideprotected

Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.

Definition at line 901 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::describeLoadedValue(), isCopyInstrImpl(), and MI.

duplicate()

MachineInstr & ARMBaseInstrInfo::duplicate ( MachineBasicBlock & MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr & Orig ) const

override

Definition at line 1682 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::duplicate(), duplicateCPV(), llvm::ilist_node_impl< OptionsT >::getIterator(), I, and MBB.

expandLoadStackGuardBase()

void ARMBaseInstrInfo::expandLoadStackGuardBase ( MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc ) const

protected

Definition at line 4736 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::cast(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::get(), llvm::MachinePointerInfo::getGOT(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::Kill, MBB, MI, llvm::ARMII::MO_COFFSTUB, llvm::ARMII::MO_DLLIMPORT, llvm::ARMII::MO_GOT, llvm::ARMII::MO_NO_FLAG, llvm::ARMII::MO_NONLAZY, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::Offset, and llvm::predOps().

expandPostRAPseudo()

bool ARMBaseInstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 1531 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, contains(), llvm::dbgs(), llvm::get(), getRegisterInfo(), llvm::Implicit, LLVM_DEBUG, MI, llvm::predOps(), and TRI.

extraSizeToPredicateInstructions()

unsigned ARMBaseInstrInfo::extraSizeToPredicateInstructions ( const MachineFunction & MF, unsigned NumInsts ) const

override

Definition at line 2031 of file ARMBaseInstrInfo.cpp.

References llvm::divideCeil().

foldImmediate()

bool ARMBaseInstrInfo::foldImmediate ( MachineInstr & UseMI, MachineInstr & DefMI, Register Reg, MachineRegisterInfo * MRI ) const

override

foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.

Definition at line 3136 of file ARMBaseInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::condCodeOp(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), DefMI, llvm::get(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), llvm::predOps(), and UseMI.

getExecutionDomain()

std::pair< uint16_t, uint16_t > ARMBaseInstrInfo::getExecutionDomain ( const MachineInstr & MI ) const

override

VFP/NEON execution domains.

Definition at line 4865 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainNEONA8, llvm::ARMII::DomainVFP, ExeGeneric, ExeNEON, ExeVFP, isPredicated(), and MI.

getExtractSubregLikeInputs()

bool ARMBaseInstrInfo::getExtractSubregLikeInputs ( const MachineInstr & MI, unsigned DefIdx, RegSubRegPairAndIdx & InputReg ) const

overrideprotected

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:

• %1:sub1, sub0

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isExtractSubregLike().

Definition at line 5306 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

getFramePred()

unsigned llvm::ARMBaseInstrInfo::getFramePred ( const MachineInstr & MI ) const

inline

Returns predicate register associated with the given frame instruction.

Definition at line 518 of file ARMBaseInstrInfo.h.

References assert(), and MI.

getInsertSubregLikeInputs()

bool ARMBaseInstrInfo::getInsertSubregLikeInputs ( const MachineInstr & MI, unsigned DefIdx, RegSubRegPair & BaseReg, RegSubRegPairAndIdx & InsertedReg ) const

overrideprotected

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:

• BaseReg: %0:sub0
• InsertedReg: %1:sub1, sub3

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isInsertSubregLike().

Definition at line 5329 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

getInstSizeInBytes()

unsigned ARMBaseInstrInfo::getInstSizeInBytes ( const MachineInstr & MI ) const

override

GetInstSize - Returns the size of the specified MachineInstr.

GetInstSize - Return the size of the specified MachineInstr.

Definition at line 604 of file ARMBaseInstrInfo.cpp.

References llvm::alignTo(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, MI, and Size.

Referenced by getOutliningCandidateInfo(), and predictBranchSizeForIfCvt().

getNumLDMAddresses()

unsigned ARMBaseInstrInfo::getNumLDMAddresses

(

const MachineInstr &

MI

)

const

Get the number of addresses by LDM or VLDM or zero for unknown.

Definition at line 3533 of file ARMBaseInstrInfo.cpp.

References I, MI, and Size.

getNumMicroOps()

unsigned ARMBaseInstrInfo::getNumMicroOps ( const InstrItineraryData * ItinData, const MachineInstr & MI ) const

override

Definition at line 3587 of file ARMBaseInstrInfo.cpp.

References llvm::ARMSubtarget::DoubleIssue, llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess, llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSingleIssuePlusExtras(), getNumMicroOpsSwiftLdSt(), llvm::InstrItineraryData::isEmpty(), llvm_unreachable, MI, Opc, llvm::ARMSubtarget::SingleIssue, and llvm::ARMSubtarget::SingleIssuePlusExtras.

getOperandLatency() [1/2]

std::optional< unsigned > ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData * ItinData, const MachineInstr & DefMI, unsigned DefIdx, const MachineInstr & UseMI, unsigned UseIdx ) const

override

Definition at line 4187 of file ARMBaseInstrInfo.cpp.

References DefMI, getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isRegSequence(), and UseMI.

Referenced by getOperandLatency().

getOperandLatency() [2/2]

std::optional< unsigned > ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData * ItinData, SDNode * DefNode, unsigned DefIdx, SDNode * UseNode, unsigned UseIdx ) const

override

Definition at line 4281 of file ARMBaseInstrInfo.cpp.

References llvm::cast(), llvm::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), llvm::SDNode::isMachineOpcode(), llvm::Latency, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::Opcode.

getOutliningCandidateInfo()

std::optional< std::unique_ptr< outliner::OutlinedFunction > > ARMBaseInstrInfo::getOutliningCandidateInfo ( const MachineModuleInfo & MMI, std::vector< outliner::Candidate > & RepeatedSequenceLocs, unsigned MinRepeats ) const

override

Definition at line 5711 of file ARMBaseInstrInfo.cpp.

References llvm::any_of(), llvm::outliner::Candidate::back(), llvm::ARMFunctionInfo::branchTargetEnforcement(), C(), OutlinerCosts::CallDefault, OutlinerCosts::CallNoLRSave, OutlinerCosts::CallRegSave, OutlinerCosts::CallTailCall, OutlinerCosts::CallThunk, CanTransformInstrIntoTailCall(), llvm::drop_end(), llvm::erase_if(), OutlinerCosts::FrameDefault, OutlinerCosts::FrameNoLRSave, OutlinerCosts::FrameRegSave, OutlinerCosts::FrameTailCall, OutlinerCosts::FrameThunk, getInstSizeInBytes(), getRegisterInfo(), HasCalls, llvm::MachineInstr::isCall(), isLRAvailable(), llvm::Last, MachineOutlinerDefault, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MI, llvm::partition(), OutlinerCosts::SaveRestoreLROnStack, llvm::ARMFunctionInfo::shouldSignReturnAddress(), TRI, and UnsafeRegsDead.

getOutliningTypeImpl()

outliner::InstrType ARMBaseInstrInfo::getOutliningTypeImpl ( const MachineModuleInfo & MMI, MachineBasicBlock::iterator & MIT, unsigned Flags ) const

override

Definition at line 6116 of file ARMBaseInstrInfo.cpp.

References CanTransformInstrIntoTailCall(), llvm::ARMII::DomainMask, llvm::ARMII::DomainMVE, llvm::dyn_cast(), llvm::MachineFunction::getFrameInfo(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFrameInfo::getNumObjects(), getRegisterInfo(), llvm::MachineFrameInfo::getStackSize(), HasCalls, llvm::outliner::Illegal, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::outliner::Legal, llvm::outliner::LegalTerminator, LRUnavailableSomewhere, MI, Opc, and TRI.

getPartialRegUpdateClearance()

unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance ( const MachineInstr & MI, unsigned OpNum, const TargetRegisterInfo * TRI ) const

override

Definition at line 5167 of file ARMBaseInstrInfo.cpp.

References assert(), contains(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), MI, llvm::MachineOperand::readsReg(), and TRI.

getPredicate()

ARMCC::CondCodes llvm::ARMBaseInstrInfo::getPredicate ( const MachineInstr & MI ) const

inline

Definition at line 172 of file ARMBaseInstrInfo.h.

References llvm::ARMCC::AL, and MI.

getRegisterInfo()

const ARMBaseRegisterInfo & llvm::ARMBaseInstrInfo::getRegisterInfo ( ) const

inline

Definition at line 129 of file ARMBaseInstrInfo.h.

References llvm::TargetInstrInfo::getRegisterInfo().

Referenced by AddDReg(), copyPhysReg(), expandPostRAPseudo(), getOperandLatency(), getOutliningCandidateInfo(), getOutliningTypeImpl(), isMBBSafeToOutlineFrom(), isProfitableToIfCvt(), loadRegFromStackSlot(), optimizeCompareInstr(), predictBranchSizeForIfCvt(), setExecutionDomain(), and storeRegToStackSlot().

getRegSequenceLikeInputs()

bool ARMBaseInstrInfo::getRegSequenceLikeInputs ( const MachineInstr & MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > & InputRegs ) const

overrideprotected

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:

• %1:sub1, sub0
• %2<:0>, sub1

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isRegSequenceLike().

Definition at line 5279 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const

override

Definition at line 5375 of file ARMBaseInstrInfo.cpp.

References llvm::ArrayRef().

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 5363 of file ARMBaseInstrInfo.cpp.

References llvm::ArrayRef().

getSubtarget()

const ARMSubtarget & llvm::ARMBaseInstrInfo::getSubtarget ( ) const

inline

Definition at line 134 of file ARMBaseInstrInfo.h.

Referenced by isPredicable(), and llvm::Thumb2InstrInfo::optimizeSelect().

getUnindexedOpcode()

virtual unsigned llvm::ARMBaseInstrInfo::getUnindexedOpcode ( unsigned Opc ) const

pure virtual

Implemented in llvm::ARMInstrInfo, llvm::Thumb1InstrInfo, and llvm::Thumb2InstrInfo.

References Opc.

hasNOP()

bool ARMBaseInstrInfo::hasNOP

(

)

const

Definition at line 5261 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMInstrInfo::getNop().

insertBranch()

unsigned ARMBaseInstrInfo::insertBranch ( MachineBasicBlock & MBB, MachineBasicBlock * TBB, MachineBasicBlock * FBB, ArrayRef< MachineOperand > Cond, const DebugLoc & DL, int * BytesAdded = nullptr ) const

override

Definition at line 324 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::getImm(), isThumb(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, llvm::predOps(), and TBB.

insertOutlinedCall()

MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall ( Module & M, MachineBasicBlock & MBB, MachineBasicBlock::iterator & It, MachineFunction & MF, outliner::Candidate & C ) const

override

Definition at line 6425 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::CFIInstBuilder::buildRegister(), llvm::CFIInstBuilder::buildRestore(), C(), copyPhysReg(), llvm::dwarf_linker::DebugLoc, llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, llvm::get(), llvm::MachineFunction::getName(), llvm::ARMFunctionInfo::isLRSpilled(), isThumb(), MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, Opc, llvm::predOps(), and llvm::ARMFunctionInfo::shouldSignReturnAddress().

isAddImmediate()

std::optional< RegImmPair > ARMBaseInstrInfo::isAddImmediate ( const MachineInstr & MI, Register Reg ) const

override

Definition at line 5389 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, and llvm::Offset.

isCopyInstrImpl()

std::optional< DestSourcePair > ARMBaseInstrInfo::isCopyInstrImpl ( const MachineInstr & MI ) const

overrideprotected

If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 885 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by describeLoadedValue().

isCPSRDefined()

bool ARMBaseInstrInfo::isCPSRDefined ( const MachineInstr & MI )

static

Definition at line 511 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by analyzeLoopForPipelining(), and isEligibleForITBlock().

isFpMLxInstruction() [1/2]

bool llvm::ARMBaseInstrInfo::isFpMLxInstruction ( unsigned Opcode ) const

inline

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition at line 495 of file ARMBaseInstrInfo.h.

isFpMLxInstruction() [2/2]

bool ARMBaseInstrInfo::isFpMLxInstruction	(	unsigned	Opcode,
		unsigned &	MulOpc,
		unsigned &	AddSubOpc,
		bool &	NegAcc,
		bool &	HasLane ) const

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.

Return true for 'HasLane' for the MLX instructions with an extra lane operand.

Definition at line 4829 of file ARMBaseInstrInfo.cpp.

References ARM_MLxTable, and I.

isFunctionSafeToOutlineFrom()

bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction & MF, bool OutlineFromLinkOnceODRs ) const

override

ARM supports the MachineOutliner.

Definition at line 6044 of file ARMBaseInstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), and llvm::ARMFunctionInfo::isThumb1OnlyFunction().

isLoadFromStackSlot()

Register ARMBaseInstrInfo::isLoadFromStackSlot ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 1402 of file ARMBaseInstrInfo.cpp.

References MI.

isLoadFromStackSlotPostFE()

Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 1462 of file ARMBaseInstrInfo.cpp.

References Accesses, llvm::cast(), and MI.

isMBBSafeToOutlineFrom()

bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB, unsigned & Flags ) const

override

Definition at line 6067 of file ARMBaseInstrInfo.cpp.

References llvm::LiveRegUnits::accumulate(), llvm::LiveRegUnits::addLiveOuts(), llvm::any_of(), assert(), llvm::LiveRegUnits::available(), getRegisterInfo(), HasCalls, isLRAvailable(), LRUnavailableSomewhere, MBB, MI, llvm::reverse(), and UnsafeRegsDead.

isPredicable()

bool ARMBaseInstrInfo::isPredicable ( const MachineInstr & MI ) const

override

isPredicable - Return true if the specified instruction can be predicated.

By default, this returns true for every instruction with a PredicateOperand.

Definition at line 550 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineFunction::getInfo(), getSubtarget(), llvm::MachineFunction::getSubtarget(), isEligibleForITBlock(), llvm::isIndirectCall(), llvm::isIndirectControlFlowNotComingBack(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), and MI.

isPredicated()

bool ARMBaseInstrInfo::isPredicated ( const MachineInstr & MI ) const

override

Definition at line 386 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, I, and MI.

Referenced by analyzeBranch(), getExecutionDomain(), optimizeCompareInstr(), setExecutionDomain(), and shouldSink().

isProfitableToDupForIfCvt()

bool llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock & MBB, unsigned NumCycles, BranchProbability Probability ) const

inlineoverride

Definition at line 280 of file ARMBaseInstrInfo.h.

References MBB.

isProfitableToIfCvt() [1/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock & MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability ) const

override

Definition at line 1940 of file ARMBaseInstrInfo.cpp.

References llvm::findCMPToFoldIntoCBZ(), llvm::MachineInstr::getOpcode(), getRegisterInfo(), isProfitableToIfCvt(), MBB, and TRI.

Referenced by isProfitableToIfCvt().

isProfitableToIfCvt() [2/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock & TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock & FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability ) const

override

Definition at line 1966 of file ARMBaseInstrInfo.cpp.

References llvm::BranchProbability::getCompl(), llvm::MachineBasicBlock::pred_size(), llvm::BranchProbability::scale(), and TBB.

isProfitableToUnpredicate()

bool ARMBaseInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock & TMBB, MachineBasicBlock & FMBB ) const

override

Definition at line 2068 of file ARMBaseInstrInfo.cpp.

isSchedulingBoundary()

bool ARMBaseInstrInfo::isSchedulingBoundary ( const MachineInstr & MI, const MachineBasicBlock * MBB, const MachineFunction & MF ) const

override

Definition at line 1890 of file ARMBaseInstrInfo.cpp.

References I, llvm::isSEHInstruction(), MBB, and MI.

Referenced by llvm::Thumb2InstrInfo::isSchedulingBoundary().

isStoreToStackSlot()

Register ARMBaseInstrInfo::isStoreToStackSlot ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 1142 of file ARMBaseInstrInfo.cpp.

References MI.

isStoreToStackSlotPostFE()

Register ARMBaseInstrInfo::isStoreToStackSlotPostFE ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 1196 of file ARMBaseInstrInfo.cpp.

References Accesses, llvm::cast(), and MI.

isSwiftFastImmShift()

bool ARMBaseInstrInfo::isSwiftFastImmShift

(

const MachineInstr *

MI

)

const

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 5265 of file ARMBaseInstrInfo.cpp.

References llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and MI.

isUnspillableTerminatorImpl()

bool llvm::ARMBaseInstrInfo::isUnspillableTerminatorImpl ( const MachineInstr * MI ) const

inlineoverride

Definition at line 376 of file ARMBaseInstrInfo.h.

References MI.

loadRegFromStackSlot()

void ARMBaseInstrInfo::loadRegFromStackSlot ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass * RC, Register VReg, unsigned SubReg = 0, MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const

override

Definition at line 1209 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::DefineNoRead, DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), getRegisterInfo(), I, llvm::ImplicitDefine, llvm::Register::isPhysical(), llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().

mergeOutliningCandidateAttributes()

void ARMBaseInstrInfo::mergeOutliningCandidateAttributes ( Function & F, std::vector< outliner::Candidate > & Candidates ) const

override

Definition at line 6029 of file ARMBaseInstrInfo.cpp.

References C(), F, llvm::Function::getFnAttribute(), and llvm::Function::hasFnAttribute().

optimizeCompareInstr()

bool ARMBaseInstrInfo::optimizeCompareInstr ( MachineInstr & CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo * MRI ) const

override

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.

E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.

Definition at line 2838 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, assert(), B(), llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), Cond, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, getCmpToAddCondition(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, I, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDef(), isOptimizeCompareCandidate(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, MBB, llvm::ARMCC::MI, MI, llvm::ARMCC::NE, Opc, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T, bool >::push_back(), TRI, llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.

optimizeSelect()

MachineInstr * ARMBaseInstrInfo::optimizeSelect ( MachineInstr & MI, SmallPtrSetImpl< MachineInstr * > & SeenMIs, bool PreferFalse ) const

override

Definition at line 2165 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineInstr::clearKillInfo(), llvm::condCodeOp(), llvm::MachineRegisterInfo::constrainRegClass(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::ARMCC::getOppositeCondition(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineInstr::hasOptionalDef(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, llvm::MCInstrDesc::operands(), llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().

Referenced by llvm::Thumb2InstrInfo::optimizeSelect().

PredicateInstruction()

bool ARMBaseInstrInfo::PredicateInstruction ( MachineInstr & MI, ArrayRef< MachineOperand > Pred ) const

override

Definition at line 427 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::get(), llvm::getImm(), llvm::getMatchingCondBranchOpcode(), getReg(), llvm::isUncondBranchOpcode(), MI, Opc, llvm::MachineOperand::setImm(), and llvm::ARMII::ThumbArithFlagSetting.

predictBranchSizeForIfCvt()

unsigned ARMBaseInstrInfo::predictBranchSizeForIfCvt ( MachineInstr & MI ) const

override

Definition at line 2045 of file ARMBaseInstrInfo.cpp.

References llvm::findCMPToFoldIntoCBZ(), getInstSizeInBytes(), getRegisterInfo(), MI, and Size.

produceSameValue()

bool ARMBaseInstrInfo::produceSameValue ( const MachineInstr & MI0, const MachineInstr & MI1, const MachineRegisterInfo * MRI ) const

override

Definition at line 1706 of file ARMBaseInstrInfo.cpp.

References llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ARMConstantPoolValue::hasSameValue(), llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineInstr::isIdenticalTo(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::Register::isVirtual(), llvm::MachineConstantPoolEntry::MachineCPVal, produceSameValue(), and llvm::MachineConstantPoolEntry::Val.

Referenced by produceSameValue().

reMaterialize()

void ARMBaseInstrInfo::reMaterialize ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr & Orig, LaneBitmask UsedLanes = LaneBitmask::getAll() ) const

override

Definition at line 1654 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), duplicateCPV(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, MBB, MI, and TRI.

removeBranch()

unsigned ARMBaseInstrInfo::removeBranch ( MachineBasicBlock & MBB, int * BytesRemoved = nullptr ) const

override

Definition at line 297 of file ARMBaseInstrInfo.cpp.

References assert(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and MBB.

Referenced by analyzeBranch().

reverseBranchCondition()

bool ARMBaseInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 376 of file ARMBaseInstrInfo.cpp.

References Cond, and llvm::ARMCC::getOppositeCondition().

setExecutionDomain()

void ARMBaseInstrInfo::setExecutionDomain ( MachineInstr & MI, unsigned Domain ) const

override

Definition at line 4957 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Define, ExeNEON, llvm::get(), getCorrespondingDRegAndLane(), getImplicitSPRUseForDPRUse(), getRegisterInfo(), llvm::getUndefRegState(), llvm::Implicit, isPredicated(), llvm_unreachable, MI, llvm::predOps(), TRI, and llvm::Undef.

shouldOutlineFromFunctionByDefault()

bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const

override

Enable outlining by default at -Oz.

Definition at line 6490 of file ARMBaseInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

shouldScheduleLoadsNear()

bool ARMBaseInstrInfo::shouldScheduleLoadsNear ( SDNode * Load1, SDNode * Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads ) const

override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1860 of file ARMBaseInstrInfo.cpp.

References assert(), and llvm::SDNode::getMachineOpcode().

shouldSink()

bool ARMBaseInstrInfo::shouldSink ( const MachineInstr & MI ) const

override

Definition at line 3118 of file ARMBaseInstrInfo.cpp.

References analyzeCompare(), isPredicated(), isRedundantFlagInstr(), MI, and llvm::Next.

storeRegToStackSlot()

void ARMBaseInstrInfo::storeRegToStackSlot ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass * RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const

override

Definition at line 942 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), getRegisterInfo(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().

SubsumesPredicate()

bool ARMBaseInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2 ) const

override

Definition at line 461 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::getImm(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ArrayRef< T >::size().

---

The documentation for this class was generated from the following files:

• lib/Target/ARM/ARMBaseInstrInfo.h
• lib/Target/ARM/ARMBaseInstrInfo.cpp