llvm::Thumb1InstrInfo Class Reference

#include "Target/ARM/Thumb1InstrInfo.h"

Inheritance diagram for llvm::Thumb1InstrInfo:

Public Member Functions
	Thumb1InstrInfo (const ARMSubtarget &STI)
MCInst	getNop () const override
	Return the noop instruction to use for a noop.
unsigned	getUnindexedOpcode (unsigned Opc) const override
const ThumbRegisterInfo &	getRegisterInfo () const override
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool	canCopyGluedNodeDuringSchedule (SDNode *N) const override
Public Member Functions inherited from llvm::ARMBaseInstrInfo
bool	hasNOP () const
virtual unsigned	getUnindexedOpcode (unsigned Opc) const =0
MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
virtual const ARMBaseRegisterInfo &	getRegisterInfo () const =0
const ARMSubtarget &	getSubtarget () const
ScheduleHazardRecognizer *	CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
ScheduleHazardRecognizer *	CreateTargetMIHazardRecognizer (const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	isPredicated (const MachineInstr &MI) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
ARMCC::CondCodes	getPredicate (const MachineInstr &MI) const
bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool	isPredicable (const MachineInstr &MI) const override
	isPredicable - Return true if the specified instruction can be predicated.
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Returns the size of the specified MachineInstr.
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
void	copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MCRegister SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void	copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MCRegister DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool	expandPostRAPseudo (MachineInstr &MI) const override
bool	shouldSink (const MachineInstr &MI) const override
void	reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
MachineInstr &	duplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
const MachineInstrBuilder &	AddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
bool	produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
bool	areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
	areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
bool	shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
	shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
unsigned	extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const override
unsigned	predictBranchSizeForIfCvt (MachineInstr &MI) const override
bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
	analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
	optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
bool	analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool	foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
	foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
unsigned	getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override
std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
std::pair< uint16_t, uint16_t >	getExecutionDomain (const MachineInstr &MI) const override
	VFP/NEON execution domains.
void	setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
unsigned	getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
void	breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
unsigned	getNumLDMAddresses (const MachineInstr &MI) const
	Get the number of addresses by LDM or VLDM or zero for unknown.
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
	ARM supports the MachineOutliner.
std::optional< std::unique_ptr< outliner::OutlinedFunction > >	getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
void	mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const override
outliner::InstrType	getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
	Enable outlining by default at -Oz.
bool	isUnspillableTerminatorImpl (const MachineInstr *MI) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
bool	isFpMLxInstruction (unsigned Opcode) const
	isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool	isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
	isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
bool	canCauseFpMLxStall (unsigned Opcode) const
	canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
bool	isSwiftFastImmShift (const MachineInstr *MI) const
	Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
unsigned	getFramePred (const MachineInstr &MI) const
	Returns predicate register associated with the given frame instruction.
std::optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override

Additional Inherited Members
Static Public Member Functions inherited from llvm::ARMBaseInstrInfo
static bool	isCPSRDefined (const MachineInstr &MI)
Protected Member Functions inherited from llvm::ARMBaseInstrInfo
	ARMBaseInstrInfo (const ARMSubtarget &STI)
void	expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool	getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
	Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool	getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
	Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
bool	getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
	Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
	Commutes the operands in the given instruction.
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
std::optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override
	Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.

Detailed Description

Definition at line 22 of file Thumb1InstrInfo.h.

Constructor & Destructor Documentation

Thumb1InstrInfo()

Thumb1InstrInfo::Thumb1InstrInfo ( const ARMSubtarget &  STI )

explicit

Definition at line 26 of file Thumb1InstrInfo.cpp.

Member Function Documentation

canCopyGluedNodeDuringSchedule()

bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule ( SDNode *  N ) const

override

Definition at line 192 of file Thumb1InstrInfo.cpp.

References N.

copyPhysReg()

void Thumb1InstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  I, const DebugLoc &  DL, MCRegister  DestReg, MCRegister  SrcReg, bool  KillSrc, bool  RenamableDest = false, bool  RenamableSrc = false  ) const

override

Definition at line 42 of file Thumb1InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::LiveRegUnits::addLiveOuts(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::ARMCC::AL, assert(), llvm::LiveRegUnits::available(), llvm::BuildMI(), contains(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::TargetRegisterInfo::getAllocatableSet(), llvm::getDefRegState(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getRegClass(), llvm::ARMSubtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), I, MBB, llvm::predOps(), llvm::BitVector::set_bits(), llvm::LiveRegUnits::stepBackward(), and llvm::BitVector::test().

getNop()

MCInst Thumb1InstrInfo::getNop ( ) const

override

Return the noop instruction to use for a noop.

Definition at line 30 of file Thumb1InstrInfo.cpp.

References llvm::MCInstBuilder::addImm(), llvm::MCInstBuilder::addReg(), and llvm::ARMCC::AL.

getRegisterInfo()

const ThumbRegisterInfo & llvm::Thumb1InstrInfo::getRegisterInfo ( ) const

inlineoverridevirtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implements llvm::ARMBaseInstrInfo.

Definition at line 38 of file Thumb1InstrInfo.h.

getUnindexedOpcode()

unsigned Thumb1InstrInfo::getUnindexedOpcode ( unsigned  Opc ) const

overridevirtual

Implements llvm::ARMBaseInstrInfo.

Definition at line 38 of file Thumb1InstrInfo.cpp.

loadRegFromStackSlot()

void Thumb1InstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DestReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI, Register  VReg, MachineInstr::MIFlag  Flags = MachineInstr::NoFlags  ) const

override

Definition at line 145 of file Thumb1InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::hasSuperClassEq(), I, llvm::isARMLowRegister(), llvm::Register::isPhysical(), MBB, llvm::MachineMemOperand::MOLoad, and llvm::predOps().

storeRegToStackSlot()

void Thumb1InstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  isKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI, Register  VReg, MachineInstr::MIFlag  Flags = MachineInstr::NoFlags  ) const

override

Definition at line 115 of file Thumb1InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm::isARMLowRegister(), llvm::Register::isPhysical(), MBB, llvm::MachineMemOperand::MOStore, and llvm::predOps().

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The documentation for this class was generated from the following files:

• lib/Target/ARM/Thumb1InstrInfo.h
• lib/Target/ARM/Thumb1InstrInfo.cpp