LLVM 20.0.0git
Thumb1InstrInfo.h
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1//===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ThumbRegisterInfo.h"
18
19namespace llvm {
20 class ARMSubtarget;
21
24public:
25 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
26
27 /// Return the noop instruction to use for a noop.
28 MCInst getNop() const override;
29
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const override;
33
34 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
35 /// such, whenever a client has an instance of instruction info, it should
36 /// always be able to get register info as well (through this method).
37 ///
38 const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
39
41 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
42 bool KillSrc) const override;
45 bool isKill, int FrameIndex,
46 const TargetRegisterClass *RC,
48 Register VReg) const override;
49
52 int FrameIndex, const TargetRegisterClass *RC,
54 Register VReg) const override;
55
56 bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;
57private:
58 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
59};
60}
61
62#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
unsigned getUnindexedOpcode(unsigned Opc) const override
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N