Go to the documentation of this file.
13 #ifndef LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
42 bool KillSrc)
const override;
This is an optimization pass for GlobalISel generic memory operations.
unsigned getUnindexedOpcode(unsigned Opc) const override
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Instances of this class represent a single low-level machine instruction.
unsigned const TargetRegisterInfo * TRI
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MachineBasicBlock MachineBasicBlock::iterator MBBI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Wrapper class representing virtual and physical registers.
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
Thumb1InstrInfo(const ARMSubtarget &STI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Wrapper class representing physical registers. Should be passed by value.