LLVM  14.0.0git
Thumb1InstrInfo.h
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1 //===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ThumbRegisterInfo.h"
18 
19 namespace llvm {
20  class ARMSubtarget;
21 
24 public:
25  explicit Thumb1InstrInfo(const ARMSubtarget &STI);
26 
27  /// Return the noop instruction to use for a noop.
28  MCInst getNop() const override;
29 
30  // Return the non-pre/post incrementing version of 'Opc'. Return 0
31  // if there is not such an opcode.
32  unsigned getUnindexedOpcode(unsigned Opc) const override;
33 
34  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
35  /// such, whenever a client has an instance of instruction info, it should
36  /// always be able to get register info as well (through this method).
37  ///
38  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
39 
41  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
42  bool KillSrc) const override;
45  Register SrcReg, bool isKill, int FrameIndex,
46  const TargetRegisterClass *RC,
47  const TargetRegisterInfo *TRI) const override;
48 
51  Register DestReg, int FrameIndex,
52  const TargetRegisterClass *RC,
53  const TargetRegisterInfo *TRI) const override;
54 
55  bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;
56 private:
57  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
58 };
59 }
60 
61 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::Thumb1InstrInfo::getUnindexedOpcode
unsigned getUnindexedOpcode(unsigned Opc) const override
Definition: Thumb1InstrInfo.cpp:35
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::Thumb1InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb1InstrInfo.cpp:107
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
ThumbRegisterInfo.h
llvm::Thumb1InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: Thumb1InstrInfo.cpp:39
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
ARMBaseInstrInfo.h
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Thumb1InstrInfo::getRegisterInfo
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: Thumb1InstrInfo.h:38
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::Thumb1InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb1InstrInfo.cpp:79
llvm::Thumb1InstrInfo
Definition: Thumb1InstrInfo.h:22
llvm::Thumb1InstrInfo::canCopyGluedNodeDuringSchedule
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
Definition: Thumb1InstrInfo.cpp:148
N
#define N
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::Thumb1InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: Thumb1InstrInfo.cpp:27
llvm::Thumb1InstrInfo::Thumb1InstrInfo
Thumb1InstrInfo(const ARMSubtarget &STI)
Definition: Thumb1InstrInfo.cpp:23
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24