X86InstrInfo.cpp File Reference

#include "X86InstrInfo.h"
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86InstrFoldTables.h"
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include <optional>
#include "X86GenInstrInfo.inc"
#include "X86GenInstrMapping.inc"
#include "X86ReplaceableInstrs.def"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "x86-instr-info"
#define	GET_INSTRINFO_CTOR_DTOR
#define	VPERM_CASES(Suffix)
#define	VPERM_CASES_BROADCAST(Suffix)
#define	VPERM_CASES(Orig, New)
#define	VPERM_CASES_BROADCAST(Orig, New)
#define	CASE_ND(OP)
#define	FROM_TO_SIZE(A, B, S)
#define	FROM_TO(FROM, TO)
#define	GET_X86_NF_TRANSFORM_TABLE
#define	GET_X86_ND2NONND_TABLE
#define	GET_ND_IF_ENABLED(OPC)   (HasNDD ? OPC##_ND : OPC)
#define	GET_EGPR_IF_ENABLED(OPC)   (STI.hasEGPR() ? OPC##_EVEX : OPC)
#define	FROM_TO(A, B)
#define	FROM_TO(FROM, TO)
#define	FROM_TO(FROM, TO)
#define	FOLD_BROADCAST(SIZE)
#define	CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64)
#define	GET_INSTRINFO_HELPERS

Enumerations
enum	MachineOutlinerClass {   MachineOutlinerDefault , MachineOutlinerTailCall , MachineOutlinerNoLRSave , MachineOutlinerThunk ,   MachineOutlinerRegSave , MachineOutlinerTailCall , MachineOutlinerThunk , MachineOutlinerNoLRSave ,   MachineOutlinerRegSave , MachineOutlinerDefault , MachineOutlinerDefault , MachineOutlinerTailCall }
	Constants defining how certain sequences should be outlined. More...

Functions
static bool	isFrameLoadOpcode (int Opcode, unsigned &MemBytes)
static bool	isFrameStoreOpcode (int Opcode, unsigned &MemBytes)
static bool	regIsPICBase (Register BaseReg, const MachineRegisterInfo &MRI)
	Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
static unsigned	getTruncatedShiftCount (const MachineInstr &MI, unsigned ShiftAmtOperandIdx)
	Check whether the shift count for a machine operand is non-zero.
static bool	isTruncatedShiftCountForLEA (unsigned ShAmt)
	Check whether the given shift count is appropriate can be represented by a LEA instruction.
static bool	findRedundantFlagInstr (MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, const MachineRegisterInfo *MRI, MachineInstr **AndInstr, const TargetRegisterInfo *TRI, bool &NoSignFlag, bool &ClearsOverflowFlag)
static unsigned	getThreeSrcCommuteCase (uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
	This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.
static void	commuteVPTERNLOG (MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
static bool	isCommutableVPERMV3Instruction (unsigned Opcode)
static unsigned	getCommutedVPERMV3Opcode (unsigned Opcode)
static bool	isConvertibleLEA (MachineInstr *MI)
static unsigned	getNewOpcFromTable (ArrayRef< X86TableEntry > Table, unsigned Opc)
static X86::CondCode	getSwappedCondition (X86::CondCode CC)
	Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
static bool	isX87Reg (unsigned Reg)
	Return true if the Reg is X87 register.
static MachineBasicBlock *	getFallThroughMBB (MachineBasicBlock *MBB, MachineBasicBlock *TBB)
static int	getJumpTableIndexFromAddr (const MachineInstr &MI)
static int	getJumpTableIndexFromReg (const MachineRegisterInfo &MRI, Register Reg)
static bool	isHReg (unsigned Reg)
	Test if the given register is a physical h register.
static unsigned	CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget)
static unsigned	getLoadStoreOpcodeForFP16 (bool Load, const X86Subtarget &STI)
static unsigned	getLoadStoreRegOpcode (Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool Load)
static unsigned	getStoreRegOpcode (Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
static unsigned	getLoadRegOpcode (Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
static bool	isAMXOpcode (unsigned Opc)
static bool	isDefConvertible (const MachineInstr &MI, bool &NoSignFlag, bool &ClearsOverflowFlag)
	Check whether the definition can be converted to remove a comparison against zero.
static X86::CondCode	isUseDefConvertible (const MachineInstr &MI)
	Check whether the use can be converted to remove a comparison against zero.
static bool	canConvert2Copy (unsigned Opc)
static unsigned	convertALUrr2ALUri (unsigned Opc)
	Convert an ALUrr opcode to corresponding ALUri opcode.
static bool	Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
	Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.
static bool	Expand2AddrKreg (MachineInstrBuilder &MIB, const MCInstrDesc &Desc, Register Reg)
	Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.
static bool	expandMOV32r1 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne)
static bool	ExpandMOVImmSExti8 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget)
static void	expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool	expandXorFP (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool	expandNOVLXLoad (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx)
static bool	expandNOVLXStore (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx)
static bool	expandSHXDROT (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
static bool	hasPartialRegUpdate (unsigned Opcode, const X86Subtarget &Subtarget, bool ForLoadFold=false)
	Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.
static bool	hasUndefRegUpdate (unsigned Opcode, unsigned OpNum, bool ForLoadFold=false)
static void	addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0)
static void	updateOperandRegConstraints (MachineFunction &MF, MachineInstr &NewMI, const TargetInstrInfo &TII)
static MachineInstr *	fuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII)
static MachineInstr *	fuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0)
static MachineInstr *	makeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI)
static bool	shouldPreventUndefRegUpdateMemFold (MachineFunction &MF, MachineInstr &MI)
static void	printFailMsgforFold (const MachineInstr &MI, unsigned Idx)
static bool	isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
	Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.
static SmallVector< MachineMemOperand *, 2 >	extractLoadMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)
static SmallVector< MachineMemOperand *, 2 >	extractStoreMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)
static unsigned	getBroadcastOpcode (const X86FoldTableEntry *I, const TargetRegisterClass *RC, const X86Subtarget &STI)
static const uint16_t *	lookup (unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table)
static const uint16_t *	lookupAVX512 (unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table)
static bool	AdjustBlendMask (unsigned OldMask, unsigned OldWidth, unsigned NewWidth, unsigned *pNewMask=nullptr)
static std::optional< ParamLoadedValue >	describeMOVrrLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetRegisterInfo *TRI)
	If DescribedReg overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register.
static void	genAlternativeDpCodeSequence (MachineInstr &Root, const TargetInstrInfo &TII, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg)

Variables
static cl::opt< bool >	NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)
static cl::opt< bool >	PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)
static cl::opt< bool >	ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
static cl::opt< unsigned >	PartialRegUpdateClearance ("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)
static cl::opt< unsigned >	UndefRegClearance ("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)

Macro Definition Documentation

CASE_BCAST_TYPE_OPC

#define CASE_BCAST_TYPE_OPC	(		TYPE,
			OP16,
			OP32,
			OP64
	)

Value:

  case TYPE:                                                                   \
    switch (SpillSize) {                                                       \
    default:                                                                   \
      llvm_unreachable("Unknown spill size");                                  \
    case 16:                                                                   \
      return X86::OP16;                                                        \
    case 32:                                                                   \
      return X86::OP32;                                                        \
    case 64:                                                                   \
      return X86::OP64;                                                        \
    }                                                                          \
    break;

CASE_ND

#define CASE_ND

(

OP

)

Value:

  case X86::OP:                                                                \
  case X86::OP##_ND:

DEBUG_TYPE

#define DEBUG_TYPE   "x86-instr-info"

Definition at line 51 of file X86InstrInfo.cpp.

FOLD_BROADCAST

#define FOLD_BROADCAST

(

SIZE

)

Value:

  MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,          \
             LoadMI.operands_begin() + NumOps);                                \
  return foldMemoryBroadcast(MF, MI, Ops[0], MOs, InsertPt, /*Size=*/SIZE,     \
                             /*AllowCommute=*/true);

FROM_TO [1/4]

#define FROM_TO	(		A,
			B
	)

Value:

  CASE_ND(A) NewOpcode = X86::B;                                               \
  break;

FROM_TO [2/4]

#define FROM_TO	(		FROM,
			TO
	)

Value:

  case X86::FROM:                                                              \
    Opc = X86::TO;                                                             \
    break;

FROM_TO [3/4]

#define FROM_TO	(		FROM,
			TO
	)

Value:

  case X86::FROM:                                                              \
    return X86::TO;                                                            \
  case X86::FROM##_ND:                                                         \
    return X86::TO##_ND;

FROM_TO [4/4]

#define FROM_TO	(		FROM,
			TO
	)

Value:

  case X86::FROM:                                                              \
    return X86::TO;

FROM_TO_SIZE

#define FROM_TO_SIZE	(		A,
			B,
			S
	)

Value:

  case X86::A:                                                                 \
    Opc = X86::B;                                                              \
    Size = S;                                                                  \
    break;                                                                     \
  case X86::A##_ND:                                                            \
    Opc = X86::B##_ND;                                                         \
    Size = S;                                                                  \
    break;                                                                     \
  case X86::B:                                                                 \
    Opc = X86::A;                                                              \
    Size = S;                                                                  \
    break;                                                                     \
  case X86::B##_ND:                                                            \
    Opc = X86::A##_ND;                                                         \
    Size = S;                                                                  \
    break;

GET_EGPR_IF_ENABLED

#define GET_EGPR_IF_ENABLED

(

OPC

)

(STI.hasEGPR() ? OPC##_EVEX : OPC)

GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 53 of file X86InstrInfo.cpp.

GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 10896 of file X86InstrInfo.cpp.

GET_ND_IF_ENABLED

#define GET_ND_IF_ENABLED

(

OPC

)

(HasNDD ? OPC##_ND : OPC)

GET_X86_ND2NONND_TABLE

#define GET_X86_ND2NONND_TABLE

Definition at line 3280 of file X86InstrInfo.cpp.

GET_X86_NF_TRANSFORM_TABLE

#define GET_X86_NF_TRANSFORM_TABLE

Definition at line 3279 of file X86InstrInfo.cpp.

VPERM_CASES [1/2]

#define VPERM_CASES	(		Orig,
			New
	)

Value:

  case X86::Orig##Z128rr:                                                      \
    return X86::New##Z128rr;                                                   \
  case X86::Orig##Z128rrkz:                                                    \
    return X86::New##Z128rrkz;                                                 \
  case X86::Orig##Z128rm:                                                      \
    return X86::New##Z128rm;                                                   \
  case X86::Orig##Z128rmkz:                                                    \
    return X86::New##Z128rmkz;                                                 \
  case X86::Orig##Z256rr:                                                      \
    return X86::New##Z256rr;                                                   \
  case X86::Orig##Z256rrkz:                                                    \
    return X86::New##Z256rrkz;                                                 \
  case X86::Orig##Z256rm:                                                      \
    return X86::New##Z256rm;                                                   \
  case X86::Orig##Z256rmkz:                                                    \
    return X86::New##Z256rmkz;                                                 \
  case X86::Orig##Zrr:                                                         \
    return X86::New##Zrr;                                                      \
  case X86::Orig##Zrrkz:                                                       \
    return X86::New##Zrrkz;                                                    \
  case X86::Orig##Zrm:                                                         \
    return X86::New##Zrm;                                                      \
  case X86::Orig##Zrmkz:                                                       \
    return X86::New##Zrmkz;

VPERM_CASES [2/2]

#define VPERM_CASES

(

Suffix

)

Value:

  case X86::VPERMI2##Suffix##Z128rr:                                           \
  case X86::VPERMT2##Suffix##Z128rr:                                           \
  case X86::VPERMI2##Suffix##Z256rr:                                           \
  case X86::VPERMT2##Suffix##Z256rr:                                           \
  case X86::VPERMI2##Suffix##Zrr:                                              \
  case X86::VPERMT2##Suffix##Zrr:                                              \
  case X86::VPERMI2##Suffix##Z128rm:                                           \
  case X86::VPERMT2##Suffix##Z128rm:                                           \
  case X86::VPERMI2##Suffix##Z256rm:                                           \
  case X86::VPERMT2##Suffix##Z256rm:                                           \
  case X86::VPERMI2##Suffix##Zrm:                                              \
  case X86::VPERMT2##Suffix##Zrm:                                              \
  case X86::VPERMI2##Suffix##Z128rrkz:                                         \
  case X86::VPERMT2##Suffix##Z128rrkz:                                         \
  case X86::VPERMI2##Suffix##Z256rrkz:                                         \
  case X86::VPERMT2##Suffix##Z256rrkz:                                         \
  case X86::VPERMI2##Suffix##Zrrkz:                                            \
  case X86::VPERMT2##Suffix##Zrrkz:                                            \
  case X86::VPERMI2##Suffix##Z128rmkz:                                         \
  case X86::VPERMT2##Suffix##Z128rmkz:                                         \
  case X86::VPERMI2##Suffix##Z256rmkz:                                         \
  case X86::VPERMT2##Suffix##Z256rmkz:                                         \
  case X86::VPERMI2##Suffix##Zrmkz:                                            \
  case X86::VPERMT2##Suffix##Zrmkz:

VPERM_CASES_BROADCAST [1/2]

#define VPERM_CASES_BROADCAST	(		Orig,
			New
	)

Value:

  VPERM_CASES(Orig, New)                                                       \
  case X86::Orig##Z128rmb:                                                     \
    return X86::New##Z128rmb;                                                  \
  case X86::Orig##Z128rmbkz:                                                   \
    return X86::New##Z128rmbkz;                                                \
  case X86::Orig##Z256rmb:                                                     \
    return X86::New##Z256rmb;                                                  \
  case X86::Orig##Z256rmbkz:                                                   \
    return X86::New##Z256rmbkz;                                                \
  case X86::Orig##Zrmb:                                                        \
    return X86::New##Zrmb;                                                     \
  case X86::Orig##Zrmbkz:                                                      \
    return X86::New##Zrmbkz;

VPERM_CASES_BROADCAST [2/2]

#define VPERM_CASES_BROADCAST

(

Suffix

)

Value:

  VPERM_CASES(Suffix)                                                          \
  case X86::VPERMI2##Suffix##Z128rmb:                                          \
  case X86::VPERMT2##Suffix##Z128rmb:                                          \
  case X86::VPERMI2##Suffix##Z256rmb:                                          \
  case X86::VPERMT2##Suffix##Z256rmb:                                          \
  case X86::VPERMI2##Suffix##Zrmb:                                             \
  case X86::VPERMT2##Suffix##Zrmb:                                             \
  case X86::VPERMI2##Suffix##Z128rmbkz:                                        \
  case X86::VPERMT2##Suffix##Z128rmbkz:                                        \
  case X86::VPERMI2##Suffix##Z256rmbkz:                                        \
  case X86::VPERMT2##Suffix##Z256rmbkz:                                        \
  case X86::VPERMI2##Suffix##Zrmbkz:                                           \
  case X86::VPERMT2##Suffix##Zrmbkz:

Enumeration Type Documentation

MachineOutlinerClass

enum MachineOutlinerClass

Constants defining how certain sequences should be outlined.

MachineOutlinerDefault implies that the function is called with a call instruction, and a return must be emitted for the outlined function frame.

That is,

I1 OUTLINED_FUNCTION: I2 --> call OUTLINED_FUNCTION I1 I3 I2 I3 ret

• Call construction overhead: 1 (call instruction)
• Frame construction overhead: 1 (return instruction)

MachineOutlinerTailCall implies that the function is being tail called. A jump is emitted instead of a call, and the return is already present in the outlined sequence. That is,

I1 OUTLINED_FUNCTION: I2 --> jmp OUTLINED_FUNCTION I1 ret I2 ret

• Call construction overhead: 1 (jump instruction)
• Frame construction overhead: 0 (don't need to return)

Enumerator
MachineOutlinerDefault
MachineOutlinerTailCall	Emit a save, restore, call, and return.
MachineOutlinerNoLRSave	Only emit a branch.
MachineOutlinerThunk	Emit a call and return.
MachineOutlinerRegSave	Emit a call and tail-call. Same as default, but save to a register.
MachineOutlinerTailCall
MachineOutlinerThunk
MachineOutlinerNoLRSave
MachineOutlinerRegSave
MachineOutlinerDefault
MachineOutlinerDefault
MachineOutlinerTailCall

Definition at line 10531 of file X86InstrInfo.cpp.

Function Documentation

addOperands()

static void addOperands ( MachineInstrBuilder &  MIB, ArrayRef< MachineOperand >  MOs, int  PtrOffset = 0  )

static

Definition at line 7159 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDisp(), llvm::addOffset(), assert(), and llvm::ArrayRef< T >::size().

Referenced by fuseInst(), fuseTwoAddrInst(), and makeM0Inst().

AdjustBlendMask()

static bool AdjustBlendMask ( unsigned  OldMask, unsigned  OldWidth, unsigned  NewWidth, unsigned *  pNewMask = nullptr  )

static

Definition at line 8967 of file X86InstrInfo.cpp.

References assert().

Referenced by llvm::X86InstrInfo::getExecutionDomainCustom(), and llvm::X86InstrInfo::setExecutionDomainCustom().

canConvert2Copy()

static bool canConvert2Copy ( unsigned  Opc )

static

Returns

true if the instruction can be changed to COPY when imm is 0.

Definition at line 5685 of file X86InstrInfo.cpp.

References CASE_ND.

commuteVPTERNLOG()

static void commuteVPTERNLOG ( MachineInstr &  MI, unsigned  SrcOpIdx1, unsigned  SrcOpIdx2  )

static

Definition at line 2129 of file X86InstrInfo.cpp.

References assert(), getThreeSrcCommuteCase(), and MI.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

convertALUrr2ALUri()

static unsigned convertALUrr2ALUri ( unsigned  Opc )

static

Convert an ALUrr opcode to corresponding ALUri opcode.

Such as ADD32rr ==> ADD32ri

Definition at line 5703 of file X86InstrInfo.cpp.

References FROM_TO.

CopyToFromAsymmetricReg()

static unsigned CopyToFromAsymmetricReg ( unsigned  DestReg, unsigned  SrcReg, const X86Subtarget &  Subtarget  )

static

Definition at line 4212 of file X86InstrInfo.cpp.

References assert(), contains(), llvm::X86Subtarget::hasAVX(), and llvm::X86Subtarget::hasAVX512().

Referenced by llvm::X86InstrInfo::copyPhysReg().

describeMOVrrLoadedValue()

static std::optional< ParamLoadedValue > describeMOVrrLoadedValue ( const MachineInstr &  MI, Register  DescribedReg, const TargetRegisterInfo *  TRI  )

static

If DescribedReg overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register.

Definition at line 10040 of file X86InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), MI, and TRI.

Referenced by llvm::X86InstrInfo::describeLoadedValue().

Expand2AddrKreg()

static bool Expand2AddrKreg ( MachineInstrBuilder &  MIB, const MCInstrDesc &  Desc, Register  Reg  )

static

Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.

This is used for mapping: k4 = K_SET1 to: k4 = KXNORrr k0, k0

Definition at line 5959 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

Expand2AddrUndef()

static bool Expand2AddrUndef ( MachineInstrBuilder &  MIB, const MCInstrDesc &  Desc  )

static

Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.

This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr undef xmm4, undef xmm4

Definition at line 5939 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

expandLoadStackGuard()

static void expandLoadStackGuard ( MachineInstrBuilder &  MIB, const TargetInstrInfo &  TII  )

static

Definition at line 6045 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getGOT(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), I, llvm::RegState::Kill, MBB, llvm::MachineInstr::memoperands_begin(), llvm::X86II::MO_GOTPCREL, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::MachineInstr::setDebugLoc(), llvm::MachineInstr::setDesc(), and TII.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

expandMOV32r1()

static bool expandMOV32r1 ( MachineInstrBuilder &  MIB, const TargetInstrInfo &  TII, bool  MinusOne  )

static

Definition at line 5967 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), MBB, llvm::MachineInstr::setDesc(), TII, and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

ExpandMOVImmSExti8()

static bool ExpandMOVImmSExti8 ( MachineInstrBuilder &  MIB, const TargetInstrInfo &  TII, const X86Subtarget &  Subtarget  )

static

Definition at line 5985 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), assert(), llvm::X86FrameLowering::BuildCFI(), llvm::BuildMI(), llvm::MCCFIInstruction::createAdjustCfaOffset(), DL, llvm::MachineInstr::getDebugLoc(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstrBuilder::getInstr(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getTarget(), llvm::X86MachineFunctionInfo::getUsesRedZone(), llvm::getX86SubSuperRegister(), llvm::TargetFrameLowering::hasFP(), I, MBB, llvm::MachineFunction::needsFrameMoves(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), TII, and llvm::MCAsmInfo::usesWindowsCFI().

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

expandNOVLXLoad()

static bool expandNOVLXLoad ( MachineInstrBuilder &  MIB, const TargetRegisterInfo *  TRI, const MCInstrDesc &  LoadDesc, const MCInstrDesc &  BroadcastDesc, unsigned  SubIdx  )

static

Definition at line 6086 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and TRI.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

expandNOVLXStore()

static bool expandNOVLXStore ( MachineInstrBuilder &  MIB, const TargetRegisterInfo *  TRI, const MCInstrDesc &  StoreDesc, const MCInstrDesc &  ExtractDesc, unsigned  SubIdx  )

static

Definition at line 6108 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::X86::AddrNumOperands, llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and TRI.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

expandSHXDROT()

static bool expandSHXDROT ( MachineInstrBuilder &  MIB, const MCInstrDesc &  Desc  )

static

Definition at line 6129 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::getUndefRegState(), llvm::MachineOperand::isUndef(), llvm::MachineInstr::removeOperand(), and llvm::MachineInstr::setDesc().

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

expandXorFP()

static bool expandXorFP ( MachineInstrBuilder &  MIB, const TargetInstrInfo &  TII  )

static

Definition at line 6071 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::X86Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MBB, llvm::MachineInstr::setDesc(), TII, TRI, and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

extractLoadMMOs()

static SmallVector< MachineMemOperand *, 2 > extractLoadMMOs ( ArrayRef< MachineMemOperand * >  MMOs, MachineFunction &  MF  )

static

Definition at line 8335 of file X86InstrInfo.cpp.

References llvm::MachineFunction::getMachineMemOperand(), llvm::MachineMemOperand::MOStore, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().

extractStoreMMOs()

static SmallVector< MachineMemOperand *, 2 > extractStoreMMOs ( ArrayRef< MachineMemOperand * >  MMOs, MachineFunction &  MF  )

static

Definition at line 8356 of file X86InstrInfo.cpp.

References llvm::MachineFunction::getMachineMemOperand(), llvm::MachineMemOperand::MOLoad, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().

findRedundantFlagInstr()

static bool findRedundantFlagInstr ( MachineInstr &  CmpInstr, MachineInstr &  CmpValDefInstr, const MachineRegisterInfo *  MRI, MachineInstr **  AndInstr, const TargetRegisterInfo *  TRI, bool &  NoSignFlag, bool &  ClearsOverflowFlag  )

static

Definition at line 1040 of file X86InstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::Register::isVirtual(), llvm::make_range(), MRI, and TRI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

fuseInst()

static MachineInstr * fuseInst ( MachineFunction &  MF, unsigned  Opcode, unsigned  OpNo, ArrayRef< MachineOperand >  MOs, MachineBasicBlock::iterator  InsertPt, MachineInstr &  MI, const TargetInstrInfo &  TII, int  PtrOffset = 0  )

static

Definition at line 7238 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), addOperands(), assert(), llvm::MachineFunction::CreateMachineInstr(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isReg(), MBB, MI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), TII, and updateOperandRegConstraints().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

fuseTwoAddrInst()

static MachineInstr * fuseTwoAddrInst ( MachineFunction &  MF, unsigned  Opcode, ArrayRef< MachineOperand >  MOs, MachineBasicBlock::iterator  InsertPt, MachineInstr &  MI, const TargetInstrInfo &  TII  )

static

Definition at line 7209 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), addOperands(), llvm::MachineFunction::CreateMachineInstr(), llvm::drop_begin(), llvm::MachineBasicBlock::insert(), MBB, MI, TII, and updateOperandRegConstraints().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

genAlternativeDpCodeSequence()

static void genAlternativeDpCodeSequence ( MachineInstr &  Root, const TargetInstrInfo &  TII, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  )

static

Definition at line 10780 of file X86InstrInfo.cpp.

References llvm::Add, llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), TII, and llvm::MachineInstr::untieRegOperand().

Referenced by llvm::X86InstrInfo::genAlternativeCodeSequence().

getBroadcastOpcode()

static unsigned getBroadcastOpcode ( const X86FoldTableEntry *  I, const TargetRegisterClass *  RC, const X86Subtarget &  STI  )

static

Definition at line 8376 of file X86InstrInfo.cpp.

References assert(), CASE_BCAST_TYPE_OPC, llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX512(), I, llvm_unreachable, llvm::TB_BCAST_D, llvm::TB_BCAST_MASK, llvm::TB_BCAST_Q, llvm::TB_BCAST_SD, llvm::TB_BCAST_SH, llvm::TB_BCAST_SS, and llvm::TB_BCAST_W.

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().

getCommutedVPERMV3Opcode()

static unsigned getCommutedVPERMV3Opcode ( unsigned  Opcode )

static

Definition at line 2220 of file X86InstrInfo.cpp.

References llvm_unreachable, VPERM_CASES, and VPERM_CASES_BROADCAST.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

getFallThroughMBB()

static MachineBasicBlock * getFallThroughMBB ( MachineBasicBlock *  MBB, MachineBasicBlock *  TBB  )

static

Definition at line 3788 of file X86InstrInfo.cpp.

References MBB, llvm::MachineBasicBlock::successors(), and TBB.

Referenced by llvm::X86InstrInfo::insertBranch().

getJumpTableIndexFromAddr()

static int getJumpTableIndexFromAddr ( const MachineInstr &  MI )

static

Definition at line 3942 of file X86InstrInfo.cpp.

References llvm::X86::AddrDisp, assert(), llvm::MachineOperand::getIndex(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), llvm::MachineOperand::isJTI(), and MI.

Referenced by llvm::X86InstrInfo::getJumpTableIndex(), and getJumpTableIndexFromReg().

getJumpTableIndexFromReg()

static int getJumpTableIndexFromReg ( const MachineRegisterInfo &  MRI, Register  Reg  )

static

Definition at line 3955 of file X86InstrInfo.cpp.

References getJumpTableIndexFromAddr(), MI, and MRI.

Referenced by llvm::X86InstrInfo::getJumpTableIndex().

getLoadRegOpcode()

static unsigned getLoadRegOpcode ( Register  DestReg, const TargetRegisterClass *  RC, bool  IsStackAligned, const X86Subtarget &  STI  )

static

Definition at line 4725 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

Referenced by llvm::M68kInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

getLoadStoreOpcodeForFP16()

static unsigned getLoadStoreOpcodeForFP16 ( bool  Load, const X86Subtarget &  STI  )

static

Definition at line 4393 of file X86InstrInfo.cpp.

References llvm::X86Subtarget::hasAVX(), and llvm::X86Subtarget::hasAVX512().

Referenced by getLoadStoreRegOpcode().

getLoadStoreRegOpcode()

static unsigned getLoadStoreRegOpcode ( Register  Reg, const TargetRegisterClass *  RC, bool  IsStackAligned, const X86Subtarget &  STI, bool  Load  )

static

Definition at line 4406 of file X86InstrInfo.cpp.

References assert(), GET_EGPR_IF_ENABLED, getLoadStoreOpcodeForFP16(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), isHReg(), and llvm_unreachable.

Referenced by getLoadRegOpcode(), and getStoreRegOpcode().

getNewOpcFromTable()

static unsigned getNewOpcFromTable ( ArrayRef< X86TableEntry >  Table, unsigned  Opc  )

static

Definition at line 3283 of file X86InstrInfo.cpp.

References llvm::ArrayRef< T >::end(), I, and llvm::lower_bound().

Referenced by llvm::X86::getNFVariant(), and llvm::X86::getNonNDVariant().

getStoreRegOpcode()

static unsigned getStoreRegOpcode ( Register  SrcReg, const TargetRegisterClass *  RC, bool  IsStackAligned, const X86Subtarget &  STI  )

static

Definition at line 4718 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

Referenced by llvm::M68kInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

getSwappedCondition()

static X86::CondCode getSwappedCondition ( X86::CondCode  CC )

static

Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 3343 of file X86InstrInfo.cpp.

References CC, llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and PerformVCMPCombine().

getThreeSrcCommuteCase()

static unsigned getThreeSrcCommuteCase ( uint64_t  TSFlags, unsigned  SrcOpIdx1, unsigned  SrcOpIdx2  )

static

This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.

All prevents commuting a passthru operand. Returns -1 if the commute isn't possible. Case 0 - Possible to commute the first and second operands. Case 1 - Possible to commute the first and third operands. Case 2 - Possible to commute the second and third operands.

Definition at line 2052 of file X86InstrInfo.cpp.

References llvm::X86II::isKMasked(), llvm_unreachable, and std::swap().

Referenced by commuteVPTERNLOG(), and llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands().

getTruncatedShiftCount()

static unsigned getTruncatedShiftCount ( const MachineInstr &  MI, unsigned  ShiftAmtOperandIdx  )

inlinestatic

Check whether the shift count for a machine operand is non-zero.

Definition at line 1021 of file X86InstrInfo.cpp.

References MI, and llvm::X86II::REX_W.

Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().

hasPartialRegUpdate()

static bool hasPartialRegUpdate ( unsigned  Opcode, const X86Subtarget &  Subtarget, bool  ForLoadFold = false  )

static

Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.

This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:

movss (rdi), xmm0 cvtss2sd xmm0, xmm0

Instead of cvtss2sd (rdi), xmm0

FIXME: This should be turned into a TSFlags.

Definition at line 6403 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().

hasUndefRegUpdate()

static bool hasUndefRegUpdate ( unsigned  Opcode, unsigned  OpNum, bool  ForLoadFold = false  )

static

Definition at line 6744 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getUndefRegClearance(), and shouldPreventUndefRegUpdateMemFold().

isAMXOpcode()

static bool isAMXOpcode ( unsigned  Opc )

static

Definition at line 4731 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::storeRegToStackSlot().

isCommutableVPERMV3Instruction()

static bool isCommutableVPERMV3Instruction ( unsigned  Opcode )

static

Definition at line 2161 of file X86InstrInfo.cpp.

References B, D, VPERM_CASES, and VPERM_CASES_BROADCAST.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

isConvertibleLEA()

static bool isConvertibleLEA ( MachineInstr *  MI )

static

Definition at line 3123 of file X86InstrInfo.cpp.

References llvm::X86::AddrDisp, llvm::X86::AddrScaleAmt, llvm::X86::AddrSegmentReg, llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and MI.

Referenced by llvm::X86InstrInfo::hasCommutePreference().

isDefConvertible()

static bool isDefConvertible ( const MachineInstr &  MI, bool &  NoSignFlag, bool &  ClearsOverflowFlag  )

inlinestatic

Check whether the definition can be converted to remove a comparison against zero.

Definition at line 4980 of file X86InstrInfo.cpp.

References CASE_ND, getTruncatedShiftCount(), isTruncatedShiftCountForLEA(), MI, llvm::X86II::MO_GOTNTPOFF, llvm::X86II::MO_GOTTPOFF, and llvm::X86II::MO_INDNTPOFF.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

isFrameLoadOpcode()

static bool isFrameLoadOpcode ( int  Opcode, unsigned &  MemBytes  )

static

Definition at line 489 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().

isFrameStoreOpcode()

static bool isFrameStoreOpcode ( int  Opcode, unsigned &  MemBytes  )

static

Definition at line 591 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::isStoreToStackSlot(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().

isHReg()

static bool isHReg ( unsigned  Reg )

static

Test if the given register is a physical h register.

Definition at line 4207 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().

isNonFoldablePartialRegisterLoad()

static bool isNonFoldablePartialRegisterLoad ( const MachineInstr &  LoadMI, const MachineInstr &  UserMI, const MachineFunction &  MF  )

static

Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.

For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0

But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0

Definition at line 7628 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), RegSize, and TRI.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

isTruncatedShiftCountForLEA()

static bool isTruncatedShiftCountForLEA ( unsigned  ShAmt )

inlinestatic

Check whether the given shift count is appropriate can be represented by a LEA instruction.

Definition at line 1031 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().

isUseDefConvertible()

static X86::CondCode isUseDefConvertible ( const MachineInstr &  MI )

static

Check whether the use can be converted to remove a comparison against zero.

Definition at line 5224 of file X86InstrInfo.cpp.

References CASE_ND, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, and MI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

isX87Reg()

static bool isX87Reg ( unsigned  Reg )

static

Return true if the Reg is X87 register.

Definition at line 3586 of file X86InstrInfo.cpp.

Referenced by llvm::X86::isX87Instruction().

lookup()

static const uint16_t * lookup ( unsigned  opcode, unsigned  domain, ArrayRef< uint16_t[3]>  Table  )

static

Definition at line 8949 of file X86InstrInfo.cpp.

lookupAVX512()

static const uint16_t * lookupAVX512 ( unsigned  opcode, unsigned  domain, ArrayRef< uint16_t[4]>  Table  )

static

Definition at line 8957 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomainCustom().

makeM0Inst()

static MachineInstr * makeM0Inst ( const TargetInstrInfo &  TII, unsigned  Opcode, ArrayRef< MachineOperand >  MOs, MachineBasicBlock::iterator  InsertPt, MachineInstr &  MI  )

static

Definition at line 7270 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), addOperands(), llvm::BuildMI(), MI, and TII.

printFailMsgforFold()

static void printFailMsgforFold ( const MachineInstr &  MI, unsigned  Idx  )

static

Definition at line 7401 of file X86InstrInfo.cpp.

References llvm::dbgs(), Idx, MI, and PrintFailedFusing.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

regIsPICBase()

static bool regIsPICBase ( Register  BaseReg, const MachineRegisterInfo &  MRI  )

static

Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.

Definition at line 758 of file X86InstrInfo.cpp.

References assert(), DefMI, llvm::Register::isVirtual(), and MRI.

Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

shouldPreventUndefRegUpdateMemFold()

static bool shouldPreventUndefRegUpdateMemFold ( MachineFunction &  MF, MachineInstr &  MI  )

static

Definition at line 7361 of file X86InstrInfo.cpp.

References llvm::MachineFunction::getRegInfo(), hasUndefRegUpdate(), llvm::MachineInstr::isImplicitDef(), and MI.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

updateOperandRegConstraints()

static void updateOperandRegConstraints ( MachineFunction &  MF, MachineInstr &  NewMI, const TargetInstrInfo &  TII  )

static

Definition at line 7183 of file X86InstrInfo.cpp.

References llvm::dbgs(), llvm::MachineInstr::dump(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), Idx, llvm::MachineOperand::isReg(), LLVM_DEBUG, MRI, TII, and TRI.

Referenced by fuseInst(), and fuseTwoAddrInst().

Variable Documentation

NoFusing

cl::opt< bool > NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden) ( "disable-spill-fusing"  , cl::desc("Disable fusing of spill code into instructions")  , cl::Hidden    )

static

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

PartialRegUpdateClearance

cl::opt< unsigned > PartialRegUpdateClearance("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden) ( "partial-reg-update-clearance"  , cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update")  , cl::init(64)  , cl::Hidden    )

static

Referenced by llvm::X86InstrInfo::getPartialRegUpdateClearance().

PrintFailedFusing

cl::opt< bool > PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden) ( "print-failed-fuse-candidates"  , cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't")  , cl::Hidden    )

static

Referenced by printFailMsgforFold().

ReMatPICStubLoad

cl::opt< bool > ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) ( "remat-pic-stub-load"  , cl::desc("Re-materialize load from stub in PIC mode")  , cl::init(false)  , cl::Hidden    )

static

Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

UndefRegClearance

cl::opt< unsigned > UndefRegClearance("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden) ( "undef-reg-clearance"  , cl::desc("How many idle instructions we would like before " "certain undef register reads")  , cl::init(128)  , cl::Hidden    )

static

Referenced by llvm::X86InstrInfo::getUndefRegClearance().