#include "X86InstrInfo.h"
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86InstrFoldTables.h"
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include "X86GenInstrInfo.inc"

Include dependency graph for X86InstrInfo.cpp:

Macros
#define	DEBUG_TYPE "x86-instr-info"

#define	GET_INSTRINFO_CTOR_DTOR

#define	VPERM_CASES(Suffix)

#define	VPERM_CASES_BROADCAST(Suffix)

#define	VPERM_CASES(Orig, New)

#define	VPERM_CASES_BROADCAST(Orig, New)

#define	GET_INSTRINFO_HELPERS

Enumerations
enum	MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerNoLRSave, MachineOutlinerThunk, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerDefault, MachineOutlinerDefault, MachineOutlinerTailCall }
	Constants defining how certain sequences should be outlined. More...

Functions
static bool	isFrameLoadOpcode (int Opcode, unsigned &MemBytes)

static bool	isFrameStoreOpcode (int Opcode, unsigned &MemBytes)

static bool	regIsPICBase (Register BaseReg, const MachineRegisterInfo &MRI)
	Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. More...

static unsigned	getTruncatedShiftCount (const MachineInstr &MI, unsigned ShiftAmtOperandIdx)
	Check whether the shift count for a machine operand is non-zero. More...

static bool	isTruncatedShiftCountForLEA (unsigned ShAmt)
	Check whether the given shift count is appropriate can be represented by a LEA instruction. More...

static unsigned	getThreeSrcCommuteCase (uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
	This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands. More...

static void	commuteVPTERNLOG (MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2)

static bool	isCommutableVPERMV3Instruction (unsigned Opcode)

static unsigned	getCommutedVPERMV3Opcode (unsigned Opcode)

static X86::CondCode	getSwappedCondition (X86::CondCode CC)
	Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). More...

static MachineBasicBlock *	getFallThroughMBB (MachineBasicBlock MBB, MachineBasicBlock TBB)

static bool	isHReg (unsigned Reg)
	Test if the given register is a physical h register. More...

static unsigned	CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget)

static unsigned	getLoadStoreRegOpcode (Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool load)

static unsigned	getStoreRegOpcode (Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)

static unsigned	getLoadRegOpcode (Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)

static bool	isRedundantFlagInstr (const MachineInstr &FlagI, Register SrcReg, Register SrcReg2, int ImmMask, int ImmValue, const MachineInstr &OI)
	Check whether the first instruction, whose only purpose is to update flags, can be made redundant. More...

static bool	isDefConvertible (const MachineInstr &MI, bool &NoSignFlag)
	Check whether the definition can be converted to remove a comparison against zero. More...

static X86::CondCode	isUseDefConvertible (const MachineInstr &MI)
	Check whether the use can be converted to remove a comparison against zero. More...

static bool	Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
	Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. More...

static bool	Expand2AddrKreg (MachineInstrBuilder &MIB, const MCInstrDesc &Desc, Register Reg)
	Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads. More...

static bool	expandMOV32r1 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne)

static bool	ExpandMOVImmSExti8 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget)

static void	expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)

static bool	expandXorFP (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)

static bool	expandNOVLXLoad (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx)

static bool	expandNOVLXStore (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx)

static bool	expandSHXDROT (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)

static bool	hasPartialRegUpdate (unsigned Opcode, const X86Subtarget &Subtarget, bool ForLoadFold=false)
	Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. More...

static bool	hasUndefRegUpdate (unsigned Opcode, unsigned OpNum, bool ForLoadFold=false)

static void	addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0)

static void	updateOperandRegConstraints (MachineFunction &MF, MachineInstr &NewMI, const TargetInstrInfo &TII)

static MachineInstr *	FuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII)

static MachineInstr *	FuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0)

static MachineInstr *	MakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI)

static bool	shouldPreventUndefRegUpdateMemFold (MachineFunction &MF, MachineInstr &MI)

static bool	isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
	Check if `LoadMI` is a partial register load that we can't fold into `MI` because the latter uses contents that wouldn't be defined in the folded version. More...

static SmallVector< MachineMemOperand *, 2 >	extractLoadMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)

static SmallVector< MachineMemOperand *, 2 >	extractStoreMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)

static unsigned	getBroadcastOpcode (const X86MemoryFoldTableEntry I, const TargetRegisterClass RC, const X86Subtarget &STI)

static const uint16_t *	lookup (unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table)

static const uint16_t *	lookupAVX512 (unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table)

static bool	AdjustBlendMask (unsigned OldMask, unsigned OldWidth, unsigned NewWidth, unsigned *pNewMask=nullptr)

static Optional< ParamLoadedValue >	describeMOVrrLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetRegisterInfo *TRI)
	If `DescribedReg` overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register. More...

Variables
static cl::opt< bool >	NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)

static cl::opt< bool >	PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)

static cl::opt< bool >	ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)

static cl::opt< unsigned >	PartialRegUpdateClearance ("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)

static cl::opt< unsigned >	UndefRegClearance ("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)

static const uint16_t	ReplaceableInstrs [][3]

static const uint16_t	ReplaceableInstrsAVX2 [][3]

static const uint16_t	ReplaceableInstrsFP [][3]

static const uint16_t	ReplaceableInstrsAVX2InsertExtract [][3]

static const uint16_t	ReplaceableInstrsAVX512 [][4]

static const uint16_t	ReplaceableInstrsAVX512DQ [][4]

static const uint16_t	ReplaceableInstrsAVX512DQMasked [][4]

static const uint16_t	ReplaceableBlendInstrs [][3]

static const uint16_t	ReplaceableBlendAVX2Instrs [][3]

static const uint16_t	ReplaceableCustomAVX512LogicInstrs [][4]

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "x86-instr-info"

Definition at line 45 of file X86InstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 47 of file X86InstrInfo.cpp.

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 9060 of file X86InstrInfo.cpp.

◆ VPERM_CASES [1/2]

#define VPERM_CASES	(	Orig,
		New
	)

Value:

  case X86::Orig##128rr:    return X86::New##128rr;   \
  case X86::Orig##128rrkz:  return X86::New##128rrkz; \
  case X86::Orig##128rm:    return X86::New##128rm;   \
  case X86::Orig##128rmkz:  return X86::New##128rmkz; \
  case X86::Orig##256rr:    return X86::New##256rr;   \
  case X86::Orig##256rrkz:  return X86::New##256rrkz; \
  case X86::Orig##256rm:    return X86::New##256rm;   \
  case X86::Orig##256rmkz:  return X86::New##256rmkz; \
  case X86::Orig##rr:       return X86::New##rr;      \
  case X86::Orig##rrkz:     return X86::New##rrkz;    \
  case X86::Orig##rm:       return X86::New##rm;      \
  case X86::Orig##rmkz:     return X86::New##rmkz;

◆ VPERM_CASES [2/2]

#define VPERM_CASES ( Suffix )

Value:

  case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
  case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
  case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
  case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
  case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
  case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
  case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
  case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
  case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
  case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
  case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
  case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:

◆ VPERM_CASES_BROADCAST [1/2]

#define VPERM_CASES_BROADCAST	(	Orig,
		New
	)

Value:

  VPERM_CASES(Orig, New) \
  case X86::Orig##128rmb:   return X86::New##128rmb;   \
  case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
  case X86::Orig##256rmb:   return X86::New##256rmb;   \
  case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
  case X86::Orig##rmb:      return X86::New##rmb;      \
  case X86::Orig##rmbkz:    return X86::New##rmbkz;

◆ VPERM_CASES_BROADCAST [2/2]

#define VPERM_CASES_BROADCAST ( Suffix )

Value:

  VPERM_CASES(Suffix) \
  case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
  case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
  case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
  case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
  case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
  case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:

Enumeration Type Documentation

◆ MachineOutlinerClass

enum MachineOutlinerClass

Constants defining how certain sequences should be outlined.

MachineOutlinerDefault implies that the function is called with a call instruction, and a return must be emitted for the outlined function frame.

That is,

I1 OUTLINED_FUNCTION: I2 --> call OUTLINED_FUNCTION I1 I3 I2 I3 ret

Call construction overhead: 1 (call instruction)
Frame construction overhead: 1 (return instruction)

MachineOutlinerTailCall implies that the function is being tail called. A jump is emitted instead of a call, and the return is already present in the outlined sequence. That is,

I1 OUTLINED_FUNCTION: I2 --> jmp OUTLINED_FUNCTION I1 ret I2 ret

Call construction overhead: 1 (jump instruction)
Frame construction overhead: 0 (don't need to return)

Enumerator
MachineOutlinerDefault
MachineOutlinerTailCall	Emit a save, restore, call, and return.
MachineOutlinerNoLRSave	Only emit a branch.
MachineOutlinerThunk	Emit a call and return.
MachineOutlinerRegSave	Emit a call and tail-call. Same as default, but save to a register.
MachineOutlinerTailCall
MachineOutlinerThunk
MachineOutlinerNoLRSave
MachineOutlinerRegSave
MachineOutlinerDefault
MachineOutlinerDefault
MachineOutlinerTailCall

Definition at line 8874 of file X86InstrInfo.cpp.

Function Documentation

◆ addOperands()

static void addOperands	(	MachineInstrBuilder &	MIB,
		ArrayRef< MachineOperand >	MOs,
		int	PtrOffset = `0`
	)

static

Definition at line 5273 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDisp(), llvm::addOffset(), assert(), i, and llvm::ArrayRef< T >::size().

Referenced by FuseInst(), FuseTwoAddrInst(), and MakeM0Inst().

◆ AdjustBlendMask()

static bool AdjustBlendMask	(	unsigned	OldMask,
		unsigned	OldWidth,
		unsigned	NewWidth,
		unsigned *	pNewMask = `nullptr`
	)

static

Definition at line 7359 of file X86InstrInfo.cpp.

References assert(), and i.

Referenced by llvm::X86InstrInfo::getExecutionDomainCustom(), and llvm::X86InstrInfo::setExecutionDomainCustom().

◆ commuteVPTERNLOG()

static void commuteVPTERNLOG	(	MachineInstr &	MI,
		unsigned	SrcOpIdx1,
		unsigned	SrcOpIdx2
	)

static

Definition at line 1899 of file X86InstrInfo.cpp.

References assert(), getThreeSrcCommuteCase(), and MI.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ CopyToFromAsymmetricReg()

static unsigned CopyToFromAsymmetricReg	(	unsigned	DestReg,
		unsigned	SrcReg,
		const X86Subtarget &	Subtarget
	)

static

Definition at line 3366 of file X86InstrInfo.cpp.

References assert(), contains(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), and llvm::X86Subtarget::hasBWI().

Referenced by llvm::X86InstrInfo::copyPhysReg().

◆ describeMOVrrLoadedValue()

static Optional<ParamLoadedValue> describeMOVrrLoadedValue	(	const MachineInstr &	MI,
		Register	DescribedReg,
		const TargetRegisterInfo *	TRI
	)

static

If DescribedReg overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register.

Definition at line 8365 of file X86InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), llvm::TargetRegisterInfo::getSubReg(), llvm::MCRegisterInfo::getSubRegIndex(), llvm::MCRegisterInfo::isSuperRegister(), MI, llvm::None, and TRI.

Referenced by llvm::X86InstrInfo::describeLoadedValue().

◆ Expand2AddrKreg()

static bool Expand2AddrKreg	(	MachineInstrBuilder &	MIB,
		const MCInstrDesc &	Desc,
		Register	Reg
	)

static

Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.

This is used for mapping: k4 = K_SET1 to: k4 = KXNORrr k0, k0

Definition at line 4477 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), Reg, llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ Expand2AddrUndef()

static bool Expand2AddrUndef	(	MachineInstrBuilder &	MIB,
		const MCInstrDesc &	Desc
	)

static

Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.

This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr undef xmm4, undef xmm4

Definition at line 4456 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstrBuilder::getReg(), Reg, llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandLoadStackGuard()

static void expandLoadStackGuard	(	MachineInstrBuilder &	MIB,
		const TargetInstrInfo &	TII
	)

static

Definition at line 4561 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandMOV32r1()

static bool expandMOV32r1	(	MachineInstrBuilder &	MIB,
		const TargetInstrInfo &	TII,
		bool	MinusOne
	)

static

Definition at line 4485 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), MBB, Reg, llvm::MachineInstr::setDesc(), TII, and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ ExpandMOVImmSExti8()

static bool ExpandMOVImmSExti8	(	MachineInstrBuilder &	MIB,
		const TargetInstrInfo &	TII,
		const X86Subtarget &	Subtarget
	)

static

Definition at line 4503 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandNOVLXLoad()

static bool expandNOVLXLoad	(	MachineInstrBuilder &	MIB,
		const TargetRegisterInfo *	TRI,
		const MCInstrDesc &	LoadDesc,
		const MCInstrDesc &	BroadcastDesc,
		unsigned	SubIdx
	)

static

Definition at line 4598 of file X86InstrInfo.cpp.

References llvm::MCRegisterInfo::getEncodingValue(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and TRI.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandNOVLXStore()

static bool expandNOVLXStore	(	MachineInstrBuilder &	MIB,
		const TargetRegisterInfo *	TRI,
		const MCInstrDesc &	StoreDesc,
		const MCInstrDesc &	ExtractDesc,
		unsigned	SubIdx
	)

static

Definition at line 4621 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::X86::AddrNumOperands, llvm::MCRegisterInfo::getEncodingValue(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and TRI.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandSHXDROT()

static bool expandSHXDROT	(	MachineInstrBuilder &	MIB,
		const MCInstrDesc &	Desc
	)

static

Definition at line 4643 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::getUndefRegState(), llvm::MachineOperand::isUndef(), llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandXorFP()

static bool expandXorFP	(	MachineInstrBuilder &	MIB,
		const TargetInstrInfo &	TII
	)

static

Definition at line 4583 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::TargetRegisterInfo::getFrameRegister(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::X86Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MBB, llvm::MachineInstr::setDesc(), TII, TRI, and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ extractLoadMMOs()

static SmallVector<MachineMemOperand *, 2> extractLoadMMOs	(	ArrayRef< MachineMemOperand * >	MMOs,
		MachineFunction &	MF
	)

static

Definition at line 6153 of file X86InstrInfo.cpp.

References llvm::MachineFunction::getMachineMemOperand(), and llvm::MachineMemOperand::MOStore.

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().

◆ extractStoreMMOs()

static SmallVector<MachineMemOperand *, 2> extractStoreMMOs	(	ArrayRef< MachineMemOperand * >	MMOs,
		MachineFunction &	MF
	)

static

Definition at line 6174 of file X86InstrInfo.cpp.

References llvm::MachineFunction::getMachineMemOperand(), and llvm::MachineMemOperand::MOLoad.

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().

◆ FuseInst()

static MachineInstr* FuseInst	(	MachineFunction &	MF,
		unsigned	Opcode,
		unsigned	OpNo,
		ArrayRef< MachineOperand >	MOs,
		MachineBasicBlock::iterator	InsertPt,
		MachineInstr &	MI,
		const TargetInstrInfo &	TII,
		int	PtrOffset = `0`
	)

static

Definition at line 5354 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), addOperands(), assert(), llvm::MachineFunction::CreateMachineInstr(), llvm::numbers::e, i, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isReg(), MBB, MI, llvm::MachineInstr::setFlag(), TII, and updateOperandRegConstraints().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ FuseTwoAddrInst()

static MachineInstr* FuseTwoAddrInst	(	MachineFunction &	MF,
		unsigned	Opcode,
		ArrayRef< MachineOperand >	MOs,
		MachineBasicBlock::iterator	InsertPt,
		MachineInstr &	MI,
		const TargetInstrInfo &	TII
	)

static

Definition at line 5323 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), addOperands(), llvm::MachineFunction::CreateMachineInstr(), llvm::numbers::e, i, llvm::MachineBasicBlock::insert(), MBB, MI, TII, and updateOperandRegConstraints().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ getBroadcastOpcode()

static unsigned getBroadcastOpcode	(	const X86MemoryFoldTableEntry *	I,
		const TargetRegisterClass *	RC,
		const X86Subtarget &	STI
	)

static

Definition at line 6194 of file X86InstrInfo.cpp.

References assert(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasVLX(), I, llvm_unreachable, llvm::TB_BCAST_D, llvm::TB_BCAST_MASK, llvm::TB_BCAST_Q, llvm::TB_BCAST_SD, and llvm::TB_BCAST_SS.

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getCommutedVPERMV3Opcode()

static unsigned getCommutedVPERMV3Opcode ( unsigned Opcode )

static

Definition at line 1967 of file X86InstrInfo.cpp.

References llvm_unreachable, VPERM_CASES, and VPERM_CASES_BROADCAST.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ getFallThroughMBB()

static MachineBasicBlock* getFallThroughMBB	(	MachineBasicBlock *	MBB,
		MachineBasicBlock *	TBB
	)

static

Definition at line 2962 of file X86InstrInfo.cpp.

References MBB, SI, llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

Referenced by llvm::X86InstrInfo::insertBranch().

◆ getLoadRegOpcode()

static unsigned getLoadRegOpcode	(	Register	DestReg,
		const TargetRegisterClass *	RC,
		bool	IsStackAligned,
		const X86Subtarget &	STI
	)

static

Definition at line 3786 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

Referenced by llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getLoadStoreRegOpcode()

static unsigned getLoadStoreRegOpcode	(	Register	Reg,
		const TargetRegisterClass *	RC,
		bool	IsStackAligned,
		const X86Subtarget &	STI,
		bool	load
	)

static

Definition at line 3534 of file X86InstrInfo.cpp.

References assert(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasVLX(), llvm::X86Subtarget::is64Bit(), isHReg(), llvm_unreachable, load, and Reg.

Referenced by getLoadRegOpcode(), and getStoreRegOpcode().

◆ getStoreRegOpcode()

static unsigned getStoreRegOpcode	(	Register	SrcReg,
		const TargetRegisterClass *	RC,
		bool	IsStackAligned,
		const X86Subtarget &	STI
	)

static

Definition at line 3779 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

Referenced by llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getSwappedCondition()

static X86::CondCode getSwappedCondition ( X86::CondCode CC )

static

Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 2731 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and PerformVCMPCombine().

◆ getThreeSrcCommuteCase()

static unsigned getThreeSrcCommuteCase	(	uint64_t	TSFlags,
		unsigned	SrcOpIdx1,
		unsigned	SrcOpIdx2
	)

static

This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.

All prevents commuting a passthru operand. Returns -1 if the commute isn't possible. Case 0 - Possible to commute the first and second operands. Case 1 - Possible to commute the first and third operands. Case 2 - Possible to commute the second and third operands.

Definition at line 1820 of file X86InstrInfo.cpp.

References llvm::X86II::isKMasked(), llvm_unreachable, and std::swap().

Referenced by commuteVPTERNLOG(), and llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands().

◆ getTruncatedShiftCount()

static unsigned getTruncatedShiftCount	(	const MachineInstr &	MI,
		unsigned	ShiftAmtOperandIdx
	)

inlinestatic

Check whether the shift count for a machine operand is non-zero.

Definition at line 1170 of file X86InstrInfo.cpp.

References MI, and llvm::X86II::REX_W.

Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().

◆ hasPartialRegUpdate()

static bool hasPartialRegUpdate	(	unsigned	Opcode,
		const X86Subtarget &	Subtarget,
		bool	ForLoadFold = `false`
	)

static

Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.

This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:

movss (rdi), xmm0 cvtss2sd xmm0, xmm0

Instead of cvtss2sd (rdi), xmm0

FIXME: This should be turned into a TSFlags.

Definition at line 4849 of file X86InstrInfo.cpp.

References llvm::X86Subtarget::hasLZCNTFalseDeps(), and llvm::X86Subtarget::hasPOPCNTFalseDeps().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().

◆ hasUndefRegUpdate()

static bool hasUndefRegUpdate	(	unsigned	Opcode,
		unsigned	OpNum,
		bool	ForLoadFold = `false`
	)

static

Definition at line 4942 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getUndefRegClearance(), and shouldPreventUndefRegUpdateMemFold().

◆ isCommutableVPERMV3Instruction()

static bool isCommutableVPERMV3Instruction ( unsigned Opcode )

static

Definition at line 1927 of file X86InstrInfo.cpp.

References B, D, llvm::X86II::PD, VPERM_CASES, VPERM_CASES_BROADCAST, and llvm::RISCVFenceField::W.

Referenced by llvm::X86InstrInfo::commuteInstructionImpl().

◆ isDefConvertible()

static bool isDefConvertible	(	const MachineInstr &	MI,
		bool &	NoSignFlag
	)

inlinestatic

Check whether the definition can be converted to remove a comparison against zero.

Definition at line 3975 of file X86InstrInfo.cpp.

References getTruncatedShiftCount(), isTruncatedShiftCountForLEA(), and MI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ isFrameLoadOpcode()

static bool isFrameLoadOpcode	(	int	Opcode,
		unsigned &	MemBytes
	)

static

Definition at line 692 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().

◆ isFrameStoreOpcode()

static bool isFrameStoreOpcode	(	int	Opcode,
		unsigned &	MemBytes
	)

static

Definition at line 788 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::isStoreToStackSlot(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().

◆ isHReg()

static bool isHReg ( unsigned Reg )

static

Test if the given register is a physical h register.

Definition at line 3361 of file X86InstrInfo.cpp.

References Reg.

Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().

◆ isNonFoldablePartialRegisterLoad()

static bool isNonFoldablePartialRegisterLoad	(	const MachineInstr &	LoadMI,
		const MachineInstr &	UserMI,
		const MachineFunction &	MF
	)

static

Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.

For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0

But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0

Definition at line 5746 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineFunction::getSubtarget(), and TRI.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ isRedundantFlagInstr()

static bool isRedundantFlagInstr	(	const MachineInstr &	FlagI,
		Register	SrcReg,
		Register	SrcReg2,
		int	ImmMask,
		int	ImmValue,
		const MachineInstr &	OI
	)

inlinestatic

Check whether the first instruction, whose only purpose is to update flags, can be made redundant.

CMPrr can be made redundant by SUBrr if the operands are the same. This function can be extended later on. SrcReg, SrcRegs: register operands for FlagI. ImmValue: immediate for FlagI if it takes an immediate.

Definition at line 3941 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::X86II::ImmMask.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ isTruncatedShiftCountForLEA()

static bool isTruncatedShiftCountForLEA ( unsigned ShAmt )

inlinestatic

Check whether the given shift count is appropriate can be represented by a LEA instruction.

Definition at line 1180 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().

◆ isUseDefConvertible()

static X86::CondCode isUseDefConvertible ( const MachineInstr & MI )

static

Check whether the use can be converted to remove a comparison against zero.

Definition at line 4089 of file X86InstrInfo.cpp.

References llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, and MI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ lookup()

static const uint16_t* lookup	(	unsigned	opcode,
		unsigned	domain,
		ArrayRef< uint16_t[3]>	Table
	)

static

Definition at line 7341 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomainCustom().

◆ lookupAVX512()

static const uint16_t* lookupAVX512	(	unsigned	opcode,
		unsigned	domain,
		ArrayRef< uint16_t[4]>	Table
	)

static

Definition at line 7349 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomainCustom().

◆ MakeM0Inst()

static MachineInstr* MakeM0Inst	(	const TargetInstrInfo &	TII,
		unsigned	Opcode,
		ArrayRef< MachineOperand >	MOs,
		MachineBasicBlock::iterator	InsertPt,
		MachineInstr &	MI
	)

static

Definition at line 5386 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), addOperands(), llvm::BuildMI(), MI, and TII.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ regIsPICBase()

static bool regIsPICBase	(	Register	BaseReg,
		const MachineRegisterInfo &	MRI
	)

static

Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.

Definition at line 950 of file X86InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::def_instr_begin(), llvm::MachineRegisterInfo::def_instr_end(), DefMI, E, llvm::MachineInstr::getOpcode(), I, llvm::Register::isVirtual(), and MRI.

Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

◆ shouldPreventUndefRegUpdateMemFold()

static bool shouldPreventUndefRegUpdateMemFold	(	MachineFunction &	MF,
		MachineInstr &	MI
	)

static

Definition at line 5470 of file X86InstrInfo.cpp.

References llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), hasUndefRegUpdate(), llvm::MachineInstr::isImplicitDef(), and MI.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ updateOperandRegConstraints()

static void updateOperandRegConstraints	(	MachineFunction &	MF,
		MachineInstr &	NewMI,
		const TargetInstrInfo &	TII
	)

static

Definition at line 5297 of file X86InstrInfo.cpp.

References llvm::MachineRegisterInfo::constrainRegClass(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::MachineOperand::isReg(), LLVM_DEBUG, MRI, Reg, TII, and TRI.

Referenced by FuseInst(), and FuseTwoAddrInst().

Variable Documentation

◆ NoFusing

cl::opt<bool> NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)

static

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ PartialRegUpdateClearance

cl::opt<unsigned> PartialRegUpdateClearance("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)

static

Referenced by llvm::X86InstrInfo::getPartialRegUpdateClearance().

◆ PrintFailedFusing

cl::opt<bool> PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)

static

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ ReMatPICStubLoad

cl::opt<bool> ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)

static

Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

◆ ReplaceableBlendAVX2Instrs

const uint16_t ReplaceableBlendAVX2Instrs[][3]

static

Initial value:

= {
  
  { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
  { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
  { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
  { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
}

Definition at line 7307 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().

◆ ReplaceableBlendInstrs

const uint16_t ReplaceableBlendInstrs[][3]

static

Initial value:

= {
  
  { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
  { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
  { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
  { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
  { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
  { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
}

Definition at line 7298 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().

◆ ReplaceableCustomAVX512LogicInstrs

const uint16_t ReplaceableCustomAVX512LogicInstrs[][4]

static

Initial value:

= {
  
  
  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
  { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
  { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
  { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
  { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
  { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
  { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
  { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
  { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
}

Definition at line 7317 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().

◆ ReplaceableInstrs

const uint16_t ReplaceableInstrs[][3]

static

Definition at line 6839 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX2

const uint16_t ReplaceableInstrsAVX2[][3]

static

Definition at line 7010 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX2InsertExtract

const uint16_t ReplaceableInstrsAVX2InsertExtract[][3]

static

Initial value:

= {
  
  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
}

Definition at line 7058 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX512

const uint16_t ReplaceableInstrsAVX512[][4]

static

Initial value:

= {
  
  
  { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
  { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
  { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
  { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
  { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
  { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
  { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
  { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
  { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
  { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
  { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
  { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
  { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
  { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
  { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
}

Definition at line 7066 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX512DQ

const uint16_t ReplaceableInstrsAVX512DQ[][4]

static

Initial value:

= {
  
  
  { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
  { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
  { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
  { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
  { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
  { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
  { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
  { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
  { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
  { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
  { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
  { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
  { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
  { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
  { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
  { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
  { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
  { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
  { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
  { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
  { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
  { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
  { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
  { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
}

Definition at line 7086 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX512DQMasked

const uint16_t ReplaceableInstrsAVX512DQMasked[][4]

static

Definition at line 7115 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsFP

const uint16_t ReplaceableInstrsFP[][3]

static

Initial value:

= {
  
  { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
  { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
  { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
  { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
  { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
  { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
  { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
  { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
  { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
}

Definition at line 7045 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

◆ UndefRegClearance

cl::opt<unsigned> UndefRegClearance("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)

static

Referenced by llvm::X86InstrInfo::getUndefRegClearance().

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRINFO_HELPERS

◆ VPERM_CASES [1/2]

◆ VPERM_CASES [2/2]

◆ VPERM_CASES_BROADCAST [1/2]

◆ VPERM_CASES_BROADCAST [2/2]

Enumeration Type Documentation

◆ MachineOutlinerClass

Function Documentation

◆ addOperands()

◆ AdjustBlendMask()

◆ commuteVPTERNLOG()

◆ CopyToFromAsymmetricReg()

◆ describeMOVrrLoadedValue()

◆ Expand2AddrKreg()

◆ Expand2AddrUndef()

◆ expandLoadStackGuard()

◆ expandMOV32r1()

◆ ExpandMOVImmSExti8()

◆ expandNOVLXLoad()

◆ expandNOVLXStore()

◆ expandSHXDROT()

◆ expandXorFP()

◆ extractLoadMMOs()

◆ extractStoreMMOs()

◆ FuseInst()

◆ FuseTwoAddrInst()

◆ getBroadcastOpcode()

◆ getCommutedVPERMV3Opcode()

◆ getFallThroughMBB()

◆ getLoadRegOpcode()

◆ getLoadStoreRegOpcode()

◆ getStoreRegOpcode()

◆ getSwappedCondition()

◆ getThreeSrcCommuteCase()

◆ getTruncatedShiftCount()

◆ hasPartialRegUpdate()

◆ hasUndefRegUpdate()

◆ isCommutableVPERMV3Instruction()

◆ isDefConvertible()

◆ isFrameLoadOpcode()

◆ isFrameStoreOpcode()

◆ isHReg()

◆ isNonFoldablePartialRegisterLoad()

◆ isRedundantFlagInstr()

◆ isTruncatedShiftCountForLEA()

◆ isUseDefConvertible()

◆ lookup()

◆ lookupAVX512()

◆ MakeM0Inst()

◆ regIsPICBase()

◆ shouldPreventUndefRegUpdateMemFold()

◆ updateOperandRegConstraints()

Variable Documentation

◆ NoFusing

◆ PartialRegUpdateClearance

◆ PrintFailedFusing

◆ ReMatPICStubLoad

◆ ReplaceableBlendAVX2Instrs

◆ ReplaceableBlendInstrs

◆ ReplaceableCustomAVX512LogicInstrs

◆ ReplaceableInstrs

◆ ReplaceableInstrsAVX2

◆ ReplaceableInstrsAVX2InsertExtract

◆ ReplaceableInstrsAVX512

◆ ReplaceableInstrsAVX512DQ

◆ ReplaceableInstrsAVX512DQMasked

◆ ReplaceableInstrsFP

◆ UndefRegClearance