LLVM 17.0.0git
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#include "X86InstrInfo.h"
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86InstrFoldTables.h"
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include <optional>
#include "X86GenInstrInfo.inc"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "x86-instr-info" |
#define | GET_INSTRINFO_CTOR_DTOR |
#define | VPERM_CASES(Suffix) |
#define | VPERM_CASES_BROADCAST(Suffix) |
#define | VPERM_CASES(Orig, New) |
#define | VPERM_CASES_BROADCAST(Orig, New) |
#define | GET_INSTRINFO_HELPERS |
Enumerations | |
enum | MachineOutlinerClass { MachineOutlinerDefault , MachineOutlinerTailCall , MachineOutlinerNoLRSave , MachineOutlinerThunk , MachineOutlinerRegSave , MachineOutlinerTailCall , MachineOutlinerThunk , MachineOutlinerNoLRSave , MachineOutlinerRegSave , MachineOutlinerDefault , MachineOutlinerDefault , MachineOutlinerTailCall } |
Constants defining how certain sequences should be outlined. More... | |
Functions | |
static bool | isFrameLoadOpcode (int Opcode, unsigned &MemBytes) |
static bool | isFrameStoreOpcode (int Opcode, unsigned &MemBytes) |
static bool | regIsPICBase (Register BaseReg, const MachineRegisterInfo &MRI) |
Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. | |
static unsigned | getTruncatedShiftCount (const MachineInstr &MI, unsigned ShiftAmtOperandIdx) |
Check whether the shift count for a machine operand is non-zero. | |
static bool | isTruncatedShiftCountForLEA (unsigned ShAmt) |
Check whether the given shift count is appropriate can be represented by a LEA instruction. | |
static bool | findRedundantFlagInstr (MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, const MachineRegisterInfo *MRI, MachineInstr **AndInstr, const TargetRegisterInfo *TRI, bool &NoSignFlag, bool &ClearsOverflowFlag) |
static unsigned | getThreeSrcCommuteCase (uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2) |
This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands. | |
static void | commuteVPTERNLOG (MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) |
static bool | isCommutableVPERMV3Instruction (unsigned Opcode) |
static unsigned | getCommutedVPERMV3Opcode (unsigned Opcode) |
static bool | isConvertibleLEA (MachineInstr *MI) |
static X86::CondCode | getSwappedCondition (X86::CondCode CC) |
Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). | |
static bool | isX87Reg (unsigned Reg) |
Return true if the Reg is X87 register. | |
static MachineBasicBlock * | getFallThroughMBB (MachineBasicBlock *MBB, MachineBasicBlock *TBB) |
static bool | isHReg (unsigned Reg) |
Test if the given register is a physical h register. | |
static unsigned | CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget) |
static unsigned | getLoadStoreOpcodeForFP16 (bool Load, const X86Subtarget &STI) |
static unsigned | getLoadStoreRegOpcode (Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool Load) |
static unsigned | getStoreRegOpcode (Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI) |
static unsigned | getLoadRegOpcode (Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI) |
static bool | isAMXOpcode (unsigned Opc) |
static bool | isDefConvertible (const MachineInstr &MI, bool &NoSignFlag, bool &ClearsOverflowFlag) |
Check whether the definition can be converted to remove a comparison against zero. | |
static X86::CondCode | isUseDefConvertible (const MachineInstr &MI) |
Check whether the use can be converted to remove a comparison against zero. | |
static bool | Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc) |
Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. | |
static bool | Expand2AddrKreg (MachineInstrBuilder &MIB, const MCInstrDesc &Desc, Register Reg) |
Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads. | |
static bool | expandMOV32r1 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne) |
static bool | ExpandMOVImmSExti8 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget) |
static void | expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII) |
static bool | expandXorFP (MachineInstrBuilder &MIB, const TargetInstrInfo &TII) |
static bool | expandNOVLXLoad (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx) |
static bool | expandNOVLXStore (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx) |
static bool | expandSHXDROT (MachineInstrBuilder &MIB, const MCInstrDesc &Desc) |
static bool | hasPartialRegUpdate (unsigned Opcode, const X86Subtarget &Subtarget, bool ForLoadFold=false) |
Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. | |
static bool | hasUndefRegUpdate (unsigned Opcode, unsigned OpNum, bool ForLoadFold=false) |
static void | addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0) |
static void | updateOperandRegConstraints (MachineFunction &MF, MachineInstr &NewMI, const TargetInstrInfo &TII) |
static MachineInstr * | FuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII) |
static MachineInstr * | FuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0) |
static MachineInstr * | MakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI) |
static bool | shouldPreventUndefRegUpdateMemFold (MachineFunction &MF, MachineInstr &MI) |
static bool | isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF) |
Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version. | |
static SmallVector< MachineMemOperand *, 2 > | extractLoadMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF) |
static SmallVector< MachineMemOperand *, 2 > | extractStoreMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF) |
static unsigned | getBroadcastOpcode (const X86MemoryFoldTableEntry *I, const TargetRegisterClass *RC, const X86Subtarget &STI) |
static const uint16_t * | lookup (unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table) |
static const uint16_t * | lookupAVX512 (unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table) |
static bool | AdjustBlendMask (unsigned OldMask, unsigned OldWidth, unsigned NewWidth, unsigned *pNewMask=nullptr) |
static std::optional< ParamLoadedValue > | describeMOVrrLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetRegisterInfo *TRI) |
If DescribedReg overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register. | |
Variables | |
static cl::opt< bool > | NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden) |
static cl::opt< bool > | PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden) |
static cl::opt< bool > | ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) |
static cl::opt< unsigned > | PartialRegUpdateClearance ("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden) |
static cl::opt< unsigned > | UndefRegClearance ("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden) |
static const uint16_t | ReplaceableInstrs [][3] |
static const uint16_t | ReplaceableInstrsAVX2 [][3] |
static const uint16_t | ReplaceableInstrsFP [][3] |
static const uint16_t | ReplaceableInstrsAVX2InsertExtract [][3] |
static const uint16_t | ReplaceableInstrsAVX512 [][4] |
static const uint16_t | ReplaceableInstrsAVX512DQ [][4] |
static const uint16_t | ReplaceableInstrsAVX512DQMasked [][4] |
static const uint16_t | ReplaceableBlendInstrs [][3] |
static const uint16_t | ReplaceableBlendAVX2Instrs [][3] |
static const uint16_t | ReplaceableCustomAVX512LogicInstrs [][4] |
#define DEBUG_TYPE "x86-instr-info" |
Definition at line 50 of file X86InstrInfo.cpp.
#define GET_INSTRINFO_CTOR_DTOR |
Definition at line 52 of file X86InstrInfo.cpp.
#define GET_INSTRINFO_HELPERS |
Definition at line 9754 of file X86InstrInfo.cpp.
#define VPERM_CASES | ( | Orig, | |
New | |||
) |
#define VPERM_CASES | ( | Suffix | ) |
#define VPERM_CASES_BROADCAST | ( | Orig, | |
New | |||
) |
#define VPERM_CASES_BROADCAST | ( | Suffix | ) |
enum MachineOutlinerClass |
Constants defining how certain sequences should be outlined.
MachineOutlinerDefault
implies that the function is called with a call instruction, and a return must be emitted for the outlined function frame.
That is,
I1 OUTLINED_FUNCTION: I2 --> call OUTLINED_FUNCTION I1 I3 I2 I3 ret
MachineOutlinerTailCall
implies that the function is being tail called. A jump is emitted instead of a call, and the return is already present in the outlined sequence. That is,
I1 OUTLINED_FUNCTION: I2 --> jmp OUTLINED_FUNCTION I1 ret I2 ret
Definition at line 9597 of file X86InstrInfo.cpp.
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Definition at line 5915 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDisp(), llvm::addOffset(), assert(), and llvm::ArrayRef< T >::size().
Referenced by FuseInst(), FuseTwoAddrInst(), and MakeM0Inst().
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Definition at line 8056 of file X86InstrInfo.cpp.
References assert().
Referenced by llvm::X86InstrInfo::getExecutionDomainCustom(), and llvm::X86InstrInfo::setExecutionDomainCustom().
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Definition at line 1877 of file X86InstrInfo.cpp.
References assert(), getThreeSrcCommuteCase(), and MI.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
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Definition at line 3417 of file X86InstrInfo.cpp.
References assert(), contains(), llvm::X86Subtarget::hasAVX(), and llvm::X86Subtarget::hasAVX512().
Referenced by llvm::X86InstrInfo::copyPhysReg().
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If DescribedReg
overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register.
Definition at line 9087 of file X86InstrInfo.cpp.
References assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), MI, and TRI.
Referenced by llvm::X86InstrInfo::describeLoadedValue().
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Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.
This is used for mapping: k4 = K_SET1 to: k4 = KXNORrr k0, k0
Definition at line 4745 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.
This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr undef xmm4, undef xmm4
Definition at line 4724 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
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Definition at line 4829 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, Flags, llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getGOT(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), I, llvm::RegState::Kill, MBB, llvm::MachineInstr::memoperands_begin(), llvm::X86II::MO_GOTPCREL, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::MachineInstr::setDebugLoc(), llvm::MachineInstr::setDesc(), and TII.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4753 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), MBB, llvm::MachineInstr::setDesc(), TII, and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4771 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), assert(), llvm::X86FrameLowering::BuildCFI(), llvm::BuildMI(), llvm::MCCFIInstruction::createAdjustCfaOffset(), DL, llvm::MachineInstr::getDebugLoc(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstrBuilder::getInstr(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getTarget(), llvm::X86MachineFunctionInfo::getUsesRedZone(), llvm::getX86SubSuperRegister(), llvm::X86FrameLowering::hasFP(), I, MBB, llvm::MachineFunction::needsFrameMoves(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), TII, and llvm::MCAsmInfo::usesWindowsCFI().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4866 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and TRI.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4889 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::X86::AddrNumOperands, llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and TRI.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4911 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::getUndefRegState(), llvm::MachineOperand::isUndef(), llvm::MachineInstr::removeOperand(), and llvm::MachineInstr::setDesc().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 4851 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::X86Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MBB, llvm::MachineInstr::setDesc(), TII, TRI, and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6850 of file X86InstrInfo.cpp.
References llvm::MachineFunction::getMachineMemOperand(), llvm::MachineMemOperand::MOStore, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 6871 of file X86InstrInfo.cpp.
References llvm::MachineFunction::getMachineMemOperand(), llvm::MachineMemOperand::MOLoad, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 972 of file X86InstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::make_range(), MRI, and TRI.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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Definition at line 5994 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), addOperands(), assert(), llvm::MachineFunction::CreateMachineInstr(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isReg(), MBB, MI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), TII, and updateOperandRegConstraints().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Definition at line 5965 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), addOperands(), llvm::MachineFunction::CreateMachineInstr(), llvm::drop_begin(), llvm::MachineBasicBlock::insert(), MBB, MI, TII, and updateOperandRegConstraints().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Definition at line 6891 of file X86InstrInfo.cpp.
References assert(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX512(), I, llvm_unreachable, llvm::TB_BCAST_D, llvm::TB_BCAST_MASK, llvm::TB_BCAST_Q, llvm::TB_BCAST_SD, and llvm::TB_BCAST_SS.
Referenced by llvm::X86InstrInfo::unfoldMemoryOperand().
Definition at line 1945 of file X86InstrInfo.cpp.
References llvm_unreachable, VPERM_CASES, and VPERM_CASES_BROADCAST.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
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Definition at line 3052 of file X86InstrInfo.cpp.
References MBB, llvm::MachineBasicBlock::successors(), and TBB.
Referenced by llvm::X86InstrInfo::insertBranch().
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Definition at line 3880 of file X86InstrInfo.cpp.
References getLoadStoreRegOpcode().
Referenced by llvm::M68kInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 3585 of file X86InstrInfo.cpp.
References llvm::X86Subtarget::hasAVX(), and llvm::X86Subtarget::hasAVX512().
Referenced by getLoadStoreRegOpcode().
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Definition at line 3598 of file X86InstrInfo.cpp.
References assert(), getLoadStoreOpcodeForFP16(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), isHReg(), and llvm_unreachable.
Referenced by getLoadRegOpcode(), and getStoreRegOpcode().
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Definition at line 3873 of file X86InstrInfo.cpp.
References getLoadStoreRegOpcode().
Referenced by llvm::M68kInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
Definition at line 2796 of file X86InstrInfo.cpp.
References CC, llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and PerformVCMPCombine().
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This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.
All prevents commuting a passthru operand. Returns -1 if the commute isn't possible. Case 0 - Possible to commute the first and second operands. Case 1 - Possible to commute the first and third operands. Case 2 - Possible to commute the second and third operands.
Definition at line 1799 of file X86InstrInfo.cpp.
References llvm::X86II::isKMasked(), llvm_unreachable, std::swap(), and TSFlags.
Referenced by commuteVPTERNLOG(), and llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands().
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Check whether the shift count for a machine operand is non-zero.
Definition at line 953 of file X86InstrInfo.cpp.
References MI, and llvm::X86II::REX_W.
Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().
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Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.
This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:
movss (rdi), xmm0 cvtss2sd xmm0, xmm0
Instead of cvtss2sd (rdi), xmm0
FIXME: This should be turned into a TSFlags.
Definition at line 5158 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().
Definition at line 5500 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getUndefRegClearance(), and shouldPreventUndefRegUpdateMemFold().
Definition at line 3886 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::storeRegToStackSlot().
Definition at line 1905 of file X86InstrInfo.cpp.
References B, D, VPERM_CASES, and VPERM_CASES_BROADCAST.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
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Definition at line 2683 of file X86InstrInfo.cpp.
References llvm::X86::AddrDisp, llvm::X86::AddrScaleAmt, llvm::X86::AddrSegmentReg, llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and MI.
Referenced by llvm::X86InstrInfo::hasCommutePreference().
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Check whether the definition can be converted to remove a comparison against zero.
Definition at line 4138 of file X86InstrInfo.cpp.
References Flags, getTruncatedShiftCount(), isTruncatedShiftCountForLEA(), MI, llvm::X86II::MO_GOTNTPOFF, llvm::X86II::MO_GOTTPOFF, and llvm::X86II::MO_INDNTPOFF.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
Definition at line 469 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().
Definition at line 567 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::isStoreToStackSlot(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().
Test if the given register is a physical h register.
Definition at line 3412 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().
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Check if LoadMI
is a partial register load that we can't fold into MI
because the latter uses contents that wouldn't be defined in the folded version.
For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0
But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0
Definition at line 6391 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), RegSize, and TRI.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
Check whether the given shift count is appropriate can be represented by a LEA instruction.
Definition at line 963 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().
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Check whether the use can be converted to remove a comparison against zero.
Definition at line 4271 of file X86InstrInfo.cpp.
References llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, and MI.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
Return true if the Reg is X87 register.
Definition at line 2931 of file X86InstrInfo.cpp.
Referenced by llvm::X86::isX87Instruction().
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Definition at line 8038 of file X86InstrInfo.cpp.
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Definition at line 8046 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomainCustom().
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Definition at line 6026 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), addOperands(), llvm::BuildMI(), MI, and TII.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Definition at line 730 of file X86InstrInfo.cpp.
References assert(), DefMI, E, llvm::MachineInstr::getOpcode(), I, llvm::Register::isVirtual(), and MRI.
Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().
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Definition at line 6110 of file X86InstrInfo.cpp.
References llvm::MachineFunction::getRegInfo(), hasUndefRegUpdate(), llvm::MachineInstr::isImplicitDef(), and MI.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Definition at line 5939 of file X86InstrInfo.cpp.
References llvm::dbgs(), llvm::MachineInstr::dump(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), Idx, llvm::MachineOperand::isReg(), LLVM_DEBUG, MRI, TII, and TRI.
Referenced by FuseInst(), and FuseTwoAddrInst().
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Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Referenced by llvm::X86InstrInfo::getPartialRegUpdateClearance().
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Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().
Definition at line 8004 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().
Definition at line 7995 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().
Definition at line 8014 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().
Definition at line 7536 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 7707 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 7755 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 7763 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 7783 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 7812 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
Definition at line 7742 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
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Referenced by llvm::X86InstrInfo::getUndefRegClearance().