#include "AArch64InstrInfo.h"
#include "AArch64ExpandImm.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PointerAuth.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "MCTargetDesc/AArch64MCLFIRewriter.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AArch64GenInstrInfo.inc"

Macros
#define	GET_INSTRINFO_CTOR_DTOR
#define	DEBUG_TYPE "AArch64InstrInfo"
#define	GET_INSTRINFO_HELPERS
#define	GET_INSTRMAP_INFO

Enumerations
enum	AccessKind { AK_Write = 0x01 , AK_Read = 0x10 , AK_All = 0x11 }
enum class	FMAInstKind { Default , Indexed , Accumulator }
enum	MachineOutlinerClass { MachineOutlinerDefault , MachineOutlinerTailCall , MachineOutlinerNoLRSave , MachineOutlinerThunk , MachineOutlinerRegSave }
	Constants defining how certain sequences should be outlined. More...
enum	MachineOutlinerMBBFlags { LRUnavailableSomewhere = 0x2 , HasCalls = 0x4 , UnsafeRegsDead = 0x8 }

Functions
	STATISTIC (NumCopyInstrs, "Number of COPY instructions expanded")
	STATISTIC (NumZCRegMoveInstrsGPR, "Number of zero-cycle GPR register move " "instructions expanded from canonical COPY")
	STATISTIC (NumZCRegMoveInstrsFPR, "Number of zero-cycle FPR register move " "instructions expanded from canonical COPY")
	STATISTIC (NumZCZeroingInstrsGPR, "Number of zero-cycle GPR zeroing " "instructions expanded from canonical COPY")
static std::optional< unsigned >	getLFIInstSizeInBytes (const MachineInstr &MI)
	Return the maximum number of bytes of code the specified instruction may be after LFI rewriting.
static void	parseCondBranch (MachineInstr LastInst, MachineBasicBlock &Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned	getBranchDisplacementBits (unsigned Opc)
static unsigned	removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
static unsigned	canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewReg=nullptr)
static bool	isCheapImmediate (const MachineInstr &MI, unsigned BitSize)
static bool	isCheapCopy (const MachineInstr &MI, const AArch64RegisterInfo &RI)
static bool	UpdateOperandRegClass (MachineInstr &Instr)
static unsigned	convertToNonFlagSettingOpc (const MachineInstr &MI)
	Return the opcode that does not set flags when possible - otherwise return the original opcode.
static bool	areCFlagsAccessedBetweenInstrs (MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
	True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.
static unsigned	sForm (MachineInstr &Instr)
	Get opcode of S version of Instr.
static bool	areCFlagsAliveInSuccessors (const MachineBasicBlock *MBB)
	Check if AArch64::NZCV should be alive in successors of MBB.
static AArch64CC::CondCode	findCondCodeUsedByInstr (const MachineInstr &Instr)
	Find a condition code used by the instruction.
static UsedNZCV	getUsedNZCV (AArch64CC::CondCode CC)
static bool	isADDSRegImm (unsigned Opcode)
static bool	isSUBSRegImm (unsigned Opcode)
static bool	isANDOpcode (MachineInstr &MI)
static bool	canInstrSubstituteCmpInstr (MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI)
	Check if CmpInstr can be substituted by MI.
static bool	canCmpInstrBeRemoved (MachineInstr &MI, MachineInstr &CmpInstr, int CmpValue, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > &CCUseInstrs, bool &IsInvertCC)
static bool	isFrameLoadOpcode (int Opcode)
static bool	isFrameStoreOpcode (int Opcode)
static unsigned	regOffsetOpcode (unsigned Opcode)
unsigned	scaledOffsetOpcode (unsigned Opcode, unsigned &Scale)
unsigned	unscaledOffsetOpcode (unsigned Opcode)
static unsigned	offsetExtendOpcode (unsigned Opcode)
static bool	isPostIndexLdStOpcode (unsigned Opcode)
	Return true if the opcode is a post-index ld/st instruction, which really loads from base+0.
static const TargetRegisterClass *	getRegClass (const MachineInstr &MI, Register Reg)
static bool	scaleOffset (unsigned Opc, int64_t &Offset)
static bool	canPairLdStOpc (unsigned FirstOpc, unsigned SecondOpc)
static bool	shouldClusterFI (const MachineFrameInfo &MFI, int FI1, int64_t Offset1, unsigned Opcode1, int FI2, int64_t Offset2, unsigned Opcode2)
static const MachineInstrBuilder &	AddSubReg (const MachineInstrBuilder &MIB, MCRegister Reg, unsigned SubIdx, RegState State, const TargetRegisterInfo *TRI)
static bool	forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
static bool	isInStreamingCallSiteRegion (MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
	Returns true if the instruction at I is in a streaming call site region, within a single basic block.
static bool	mustAvoidNeonAtMBBI (const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
	Returns true if in a streaming call site region without SME-FA64.
static void	storeRegPairToStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register SrcReg, bool IsKill, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void	loadRegPairFromStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register DestReg, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void	appendConstantExpr (SmallVectorImpl< char > &Expr, int64_t Constant, dwarf::LocationAtom Operation)
static void	appendReadRegExpr (SmallVectorImpl< char > &Expr, unsigned RegNum)
static void	appendLoadRegExpr (SmallVectorImpl< char > &Expr, int64_t OffsetFromDefCFA)
static void	appendOffsetComment (int NumBytes, llvm::raw_string_ostream &Comment, StringRef RegScale={})
static MCCFIInstruction	createDefCFAExpression (const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
static void	emitFrameOffsetAdj (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int64_t Offset, unsigned Opc, const TargetInstrInfo TII, MachineInstr::MIFlag Flag, bool NeedsWinCFI, bool HasWinCFI, bool EmitCFAOffset, StackOffset CFAOffset, unsigned FrameReg)
static bool	isCombineInstrSettingFlag (unsigned Opc)
static bool	isCombineInstrCandidate32 (unsigned Opc)
static bool	isCombineInstrCandidate64 (unsigned Opc)
static bool	isCombineInstrCandidateFP (const MachineInstr &Inst)
static bool	isCombineInstrCandidate (unsigned Opc)
static bool	canCombine (MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
static bool	canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
static bool	canCombineWithFMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
static bool	getMaddPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
	Find instructions that can be turned into madd.
static bool	getFMAPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
	Floating-Point Support.
static bool	getFMULPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static bool	getFNEGPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static bool	getMiscPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
	Find other MI combine patterns.
static bool	getGatherLanePattern (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, unsigned LoadLaneOpCode, unsigned NumLanes)
	Check if the given instruction forms a gather load pattern that can be optimized for better Memory-Level Parallelism (MLP).
static bool	getLoadPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
	Search for patterns of LD instructions we can optimize.
static void	generateGatherLanePattern (MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned Pattern, unsigned NumLanes)
	Generate optimized instruction sequence for gather load patterns to improve Memory-Level Parallelism (MLP).
static MachineInstr *	genFusedMultiply (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass RC, FMAInstKind kind=FMAInstKind::Default, const Register ReplacedAddend=nullptr)
	genFusedMultiply - Generate fused multiply instructions.
static MachineInstr *	genFNegatedMAD (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs)
static MachineInstr *	genIndexedMultiply (MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxDupOp, unsigned MulOpc, const TargetRegisterClass *RC, MachineRegisterInfo &MRI)
	Fold (FMUL x (DUP y lane)) into (FMUL_indexed x y lane)
static MachineInstr *	genFusedMultiplyAcc (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
	genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.
static Register	genNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned MnegOpc, const TargetRegisterClass *RC)
	genNeg - Helper to generate an intermediate negation of the second operand of Root
static MachineInstr *	genFusedMultiplyAccNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
	genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator
static MachineInstr *	genFusedMultiplyIdx (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
	genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.
static MachineInstr *	genFusedMultiplyIdxNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
	genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator
static MachineInstr *	genMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
	genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V
static void	genSubAdd2SubSub (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo TII, MachineInstr &Root, SmallVectorImpl< MachineInstr > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, unsigned IdxOpd1, DenseMap< Register, unsigned > &InstrIdxForVirtReg)
	Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.
static bool	outliningCandidatesSigningScopeConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static bool	outliningCandidatesSigningKeyConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static bool	outliningCandidatesV8_3OpsConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static void	signOutlinedFunction (MachineFunction &MF, MachineBasicBlock &MBB, const AArch64InstrInfo *TII, bool ShouldSignReturnAddr)
static std::optional< ParamLoadedValue >	describeORRLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetInstrInfo TII, const TargetRegisterInfo TRI)
	If the given ORR instruction is a copy, and `DescribedReg` overlaps with the destination register then, if possible, describe the value in terms of the source register.
static Register	cloneInstr (const MachineInstr *MI, unsigned ReplaceOprNum, Register ReplaceReg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertTo)
	Clone an instruction from MI.
static void	extractPhiReg (const MachineInstr &Phi, const MachineBasicBlock *MBB, Register &RegMBB, Register &RegOther)
static bool	isDefinedOutside (Register Reg, const MachineBasicBlock *BB)
static bool	getIndVarInfo (Register Reg, const MachineBasicBlock LoopBB, MachineInstr &UpdateInst, unsigned &UpdateCounterOprNum, Register &InitReg, bool &IsUpdatePriorComp)
	If Reg is an induction variable, return true and set some parameters.

Variables
static cl::opt< unsigned >	CBDisplacementBits ("aarch64-cb-offset-bits", cl::Hidden, cl::init(9), cl::desc("Restrict range of CB instructions (DEBUG)"))
static cl::opt< unsigned >	TBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned >	CBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned >	BCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
static cl::opt< unsigned >	BDisplacementBits ("aarch64-b-offset-bits", cl::Hidden, cl::init(26), cl::desc("Restrict range of B instructions (DEBUG)"))
static cl::opt< unsigned >	GatherOptSearchLimit ("aarch64-search-limit", cl::Hidden, cl::init(2048), cl::desc("Restrict range of instructions to search for the " "machine-combiner gather pattern optimization"))

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "AArch64InstrInfo"

Definition at line 70 of file AArch64InstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 67 of file AArch64InstrInfo.cpp.

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 12186 of file AArch64InstrInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 12187 of file AArch64InstrInfo.cpp.

Enumeration Type Documentation

◆ AccessKind

enum AccessKind

Enumerator
AK_Write
AK_Read
AK_All

Definition at line 1807 of file AArch64InstrInfo.cpp.

◆ FMAInstKind

enum class FMAInstKind

strong

Enumerator
Default
Indexed
Accumulator

Definition at line 8685 of file AArch64InstrInfo.cpp.

◆ MachineOutlinerClass

enum MachineOutlinerClass

Constants defining how certain sequences should be outlined.

This encompasses how an outlined function should be called, and what kind of frame should be emitted for that outlined function.

MachineOutlinerDefault implies that the function should be called with a save and restore of LR to the stack.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

Call construction overhead: 3 (save + BL + restore)
Frame construction overhead: 1 (ret)
Requires stack fixups? Yes

MachineOutlinerTailCall implies that the function is being created from a sequence of instructions ending in a return.

That is,

I1 OUTLINED_FUNCTION: I2 --> B OUTLINED_FUNCTION I1 RET I2 RET

Call construction overhead: 1 (B)
Frame construction overhead: 0 (Return included in sequence)
Requires stack fixups? No

MachineOutlinerNoLRSave implies that the function should be called using a BL instruction, but doesn't require LR to be saved and restored. This happens when LR is known to be dead.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 I2 I3 RET

Call construction overhead: 1 (BL)
Frame construction overhead: 1 (RET)
Requires stack fixups? No

MachineOutlinerThunk implies that the function is being created from a sequence of instructions ending in a call. The outlined function is called with a BL instruction, and the outlined function tail-calls the original call destination.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 BL f I2 B f

Call construction overhead: 1 (BL)
Frame construction overhead: 0
Requires stack fixups? No

MachineOutlinerRegSave implies that the function should be called with a save and restore of LR to an available register. This allows us to avoid stack fixups. Note that this outlining variant is compatible with the NoLRSave case.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

Call construction overhead: 3 (save + BL + restore)
Frame construction overhead: 1 (ret)
Requires stack fixups? No

Enumerator
MachineOutlinerDefault
MachineOutlinerTailCall	Emit a save, restore, call, and return.
MachineOutlinerNoLRSave	Only emit a branch.
MachineOutlinerThunk	Emit a call and return.
MachineOutlinerRegSave	Emit a call and tail-call. Same as default, but save to a register.

Definition at line 10272 of file AArch64InstrInfo.cpp.

◆ MachineOutlinerMBBFlags

enum MachineOutlinerMBBFlags

Enumerator
LRUnavailableSomewhere
HasCalls
UnsafeRegsDead

Definition at line 10280 of file AArch64InstrInfo.cpp.

Function Documentation

◆ AddSubReg()

const MachineInstrBuilder & AddSubReg	(	const MachineInstrBuilder &	MIB,
		MCRegister	Reg,
		unsigned	SubIdx,
		RegState	State,
		const TargetRegisterInfo *	TRI )

static

Definition at line 5695 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), Reg, and TRI.

Referenced by llvm::AArch64InstrInfo::copyGPRRegTuple(), and llvm::AArch64InstrInfo::copyPhysRegTuple().

◆ appendConstantExpr()

void appendConstantExpr	(	SmallVectorImpl< char > &	Expr,
		int64_t	Constant,
		dwarf::LocationAtom	Operation )

static

Definition at line 6742 of file AArch64InstrInfo.cpp.

References llvm::appendLEB128(), Operation, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by appendLoadRegExpr(), llvm::createCFAOffset(), and createDefCFAExpression().

◆ appendLoadRegExpr()

void appendLoadRegExpr	(	SmallVectorImpl< char > &	Expr,
		int64_t	OffsetFromDefCFA )

static

Definition at line 6768 of file AArch64InstrInfo.cpp.

References appendConstantExpr(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::createCFAOffset().

◆ appendOffsetComment()

void appendOffsetComment	(	int	NumBytes,
		llvm::raw_string_ostream &	Comment,
		StringRef	RegScale = {} )

static

Definition at line 6780 of file AArch64InstrInfo.cpp.

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

◆ appendReadRegExpr()

void appendReadRegExpr	(	SmallVectorImpl< char > &	Expr,
		unsigned	RegNum )

static

Definition at line 6760 of file AArch64InstrInfo.cpp.

References llvm::appendLEB128(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

◆ areCFlagsAccessedBetweenInstrs()

bool areCFlagsAccessedBetweenInstrs	(	MachineBasicBlock::iterator	From,
		MachineBasicBlock::iterator	To,
		const TargetRegisterInfo *	TRI,
		const AccessKind	AccessToCheck = AK_All )

static

True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.

Note: If From and To are from different blocks it's assumed CC are accessed on the path.

Definition at line 1814 of file AArch64InstrInfo.cpp.

References AK_All, AK_Read, AK_Write, assert(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::instructionsWithoutDebug(), MI, and TRI.

Referenced by canCmpInstrBeRemoved(), canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().

◆ areCFlagsAliveInSuccessors()

bool areCFlagsAliveInSuccessors ( const MachineBasicBlock * MBB )

static

Check if AArch64::NZCV should be alive in successors of MBB.

Definition at line 2194 of file AArch64InstrInfo.cpp.

References MBB.

Referenced by llvm::examineCFlagsUse().

◆ canCmpInstrBeRemoved()

bool canCmpInstrBeRemoved	(	MachineInstr &	MI,
		MachineInstr &	CmpInstr,
		int	CmpValue,
		const TargetRegisterInfo &	TRI,
		SmallVectorImpl< MachineInstr * > &	CCUseInstrs,
		bool &	IsInvertCC )

static

Returns: True if CmpInstr can be removed.

IsInvertCC is true if, after removing CmpInstr, condition codes used in CCUseInstrs must be inverted.

Definition at line 2427 of file AArch64InstrInfo.cpp.

References AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::UsedNZCV::C, llvm::AArch64CC::EQ, llvm::examineCFlagsUse(), findCondCodeUsedByInstr(), llvm::MachineInstr::getOpcode(), getUsedNZCV(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), MI, llvm::UsedNZCV::N, llvm::AArch64CC::NE, llvm::AArch64CC::PL, TRI, llvm::UsedNZCV::V, and llvm::UsedNZCV::Z.

◆ canCombine()

bool canCombine	(	MachineBasicBlock &	MBB,
		MachineOperand &	MO,
		unsigned	CombineOpc,
		unsigned	ZeroReg = 0,
		bool	CheckZeroReg = false )

static

Definition at line 7533 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, and MI.

◆ canCombineWithFMUL()

bool canCombineWithFMUL	(	MachineBasicBlock &	MBB,
		MachineOperand &	MO,
		unsigned	MulOpc )

static

Definition at line 7573 of file AArch64InstrInfo.cpp.

References canCombine(), and MBB.

Referenced by getFMAPatterns().

◆ canCombineWithMUL()

bool canCombineWithMUL	(	MachineBasicBlock &	MBB,
		MachineOperand &	MO,
		unsigned	MulOpc,
		unsigned	ZeroReg )

static

Definition at line 7566 of file AArch64InstrInfo.cpp.

References canCombine(), and MBB.

Referenced by getMaddPatterns().

◆ canFoldIntoCSel()

unsigned canFoldIntoCSel	(	const MachineRegisterInfo &	MRI,
		unsigned	VReg,
		unsigned *	NewReg = nullptr )

static

Definition at line 924 of file AArch64InstrInfo.cpp.

References assert(), DefMI, llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getVRegDef(), llvm::Register::isVirtualRegister(), Opc, and removeCopies().

Referenced by llvm::AArch64InstrInfo::canInsertSelect(), and llvm::AArch64InstrInfo::insertSelect().

◆ canInstrSubstituteCmpInstr()

bool canInstrSubstituteCmpInstr	(	MachineInstr &	MI,
		MachineInstr &	CmpInstr,
		const TargetRegisterInfo &	TRI )

static

Check if CmpInstr can be substituted by MI.

CmpInstr can be substituted:

CmpInstr is either 'ADDS vreg, 0' or 'SUBS vreg, 0'
and, MI and CmpInstr are from the same MachineBB
and, condition flags are not alive in successors of the CmpInstr parent
and, if MI opcode is the S form there must be no defs of flags between MI and CmpInstr or if MI opcode is not the S form there must be neither defs of flags nor uses of flags between MI and CmpInstr.
and, C is not used after CmpInstr; CmpInstr's C is from adds/subs #0 on SrcReg and can differ from MI (e.g. carry out of ADCS/SBCS).
and, V is not used after CmpInstr unless MI is AND/BIC (V cleared) or MI has NoSWrap (overflow is poison and the fold is still safe).

Definition at line 2361 of file AArch64InstrInfo.cpp.

References AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::examineCFlagsUse(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isADDSRegImm(), isANDOpcode(), llvm::MachineOperand::isImm(), isSUBSRegImm(), MI, llvm::MachineInstr::NoSWrap, sForm(), and TRI.

◆ canPairLdStOpc()

bool canPairLdStOpc	(	unsigned	FirstOpc,
		unsigned	SecondOpc )

static

Definition at line 5552 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ cloneInstr()

Register cloneInstr	(	const MachineInstr *	MI,
		unsigned	ReplaceOprNum,
		Register	ReplaceReg,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsertTo )

static

Clone an instruction from MI.

The register of ReplaceOprNum-th operand is replaced by ReplaceReg. The output register is newly created. The other operands are unchanged from MI.

Definition at line 11796 of file AArch64InstrInfo.cpp.

References llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), I, llvm::Register::isVirtual(), MBB, MI, llvm::MachineOperand::setReg(), and TII.

◆ convertToNonFlagSettingOpc()

unsigned convertToNonFlagSettingOpc ( const MachineInstr & MI )

static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 1761 of file AArch64InstrInfo.cpp.

References MI.

Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

◆ createDefCFAExpression()

MCCFIInstruction createDefCFAExpression	(	const TargetRegisterInfo &	TRI,
		unsigned	Reg,
		const StackOffset &	Offset )

static

Definition at line 6791 of file AArch64InstrInfo.cpp.

References llvm::SmallString< InternalLen >::append(), appendConstantExpr(), llvm::appendLEB128(), appendOffsetComment(), appendReadRegExpr(), assert(), llvm::MCCFIInstruction::createEscape(), llvm::Offset, llvm::printReg(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::SmallString< InternalLen >::str(), and TRI.

Referenced by llvm::createDefCFA(), and llvm::RISCVFrameLowering::emitPrologue().

◆ describeORRLoadedValue()

std::optional< ParamLoadedValue > describeORRLoadedValue	(	const MachineInstr &	MI,
		Register	DescribedReg,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI )

static

If the given ORR instruction is a copy, and DescribedReg overlaps with the destination register then, if possible, describe the value in terms of the source register.

Definition at line 11431 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), llvm::Register::isValid(), MI, TII, and TRI.

◆ emitFrameOffsetAdj()

void emitFrameOffsetAdj	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		int64_t	Offset,
		unsigned	Opc,
		const TargetInstrInfo *	TII,
		MachineInstr::MIFlag	Flag,
		bool	NeedsWinCFI,
		bool *	HasWinCFI,
		bool	EmitCFAOffset,
		StackOffset	CFAOffset,
		unsigned	FrameReg )

static

◆ extractPhiReg()

void extractPhiReg	(	const MachineInstr &	Phi,
		const MachineBasicBlock *	MBB,
		Register &	RegMBB,
		Register &	RegOther )

static

Definition at line 11921 of file AArch64InstrInfo.cpp.

References assert(), and MBB.

Referenced by getIndVarInfo().

◆ findCondCodeUsedByInstr()

AArch64CC::CondCode findCondCodeUsedByInstr ( const MachineInstr & Instr )

static

Find a condition code used by the instruction.

Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.

Definition at line 2235 of file AArch64InstrInfo.cpp.

References llvm::getImm(), and llvm::AArch64CC::Invalid.

Referenced by canCmpInstrBeRemoved(), and llvm::examineCFlagsUse().

◆ forwardCopyWillClobberTuple()

bool forwardCopyWillClobberTuple	(	unsigned	DestReg,
		unsigned	SrcReg,
		unsigned	NumRegs )

static

Definition at line 5707 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple(), and llvm::RISCVInstrInfo::copyPhysRegVector().

◆ generateGatherLanePattern()

void generateGatherLanePattern	(	MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		SmallVectorImpl< MachineInstr * > &	DelInstrs,
		DenseMap< Register, unsigned > &	InstrIdxForVirtReg,
		unsigned	Pattern,
		unsigned	NumLanes )

static

Generate optimized instruction sequence for gather load patterns to improve Memory-Level Parallelism (MLP).

This function transforms a chain of sequential NEON lane loads into parallel vector loads that can execute concurrently.

Definition at line 8475 of file AArch64InstrInfo.cpp.

References A(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), B(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::enumerate(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm_unreachable, llvm::make_range(), llvm::MachineInstr::memoperands(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reverse(), llvm::MachineInstrBuilder::setMemRefs(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::sort(), and TII.

◆ genFNegatedMAD()

MachineInstr * genFNegatedMAD	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs )

static

Definition at line 8767 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::Register::isVirtual(), Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

◆ genFusedMultiply()

MachineInstr * genFusedMultiply	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		unsigned	IdxMulOpd,
		unsigned	MaddOpc,
		const TargetRegisterClass *	RC,
		FMAInstKind	kind = FMAInstKind::Default,
		const Register *	ReplacedAddend = nullptr )

static

genFusedMultiply - Generate fused multiply instructions.

This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C

Parameters

	MF	Containing MachineFunction
	MRI	Register information
	TII	Target information
	Root	is the F\|ADD instruction
[out]	InsInstrs	is a vector of machine instructions and will contain the generated madd instruction
	IdxMulOpd	is index of operand in Root that is the result of the F\|MUL. In the example above IdxMulOpd is 1.
	MaddOpc	the opcode fo the f\|madd instruction
	RC	Register class of operands
	kind	of fma instruction (addressing mode) to be generated
	ReplacedAddend	is the result register from the instruction replacing the non-combined operand, if any.

Definition at line 8706 of file AArch64InstrInfo.cpp.

References Accumulator, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), Default, llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), Indexed, llvm::MachineOperand::isKill(), llvm::Register::isVirtual(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by genFusedMultiplyAcc(), genFusedMultiplyAccNeg(), genFusedMultiplyIdx(), and genFusedMultiplyIdxNeg().

◆ genFusedMultiplyAcc()

MachineInstr * genFusedMultiplyAcc	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		unsigned	IdxMulOpd,
		unsigned	MaddOpc,
		const TargetRegisterClass *	RC )

static

genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.

See also: genFusedMultiply

Definition at line 8850 of file AArch64InstrInfo.cpp.

References Accumulator, genFusedMultiply(), and TII.

◆ genFusedMultiplyAccNeg()

MachineInstr * genFusedMultiplyAccNeg	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		DenseMap< Register, unsigned > &	InstrIdxForVirtReg,
		unsigned	IdxMulOpd,
		unsigned	MaddOpc,
		unsigned	MnegOpc,
		const TargetRegisterClass *	RC )

static

genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator

Definition at line 8879 of file AArch64InstrInfo.cpp.

References Accumulator, assert(), genFusedMultiply(), genNeg(), and TII.

◆ genFusedMultiplyIdx()

MachineInstr * genFusedMultiplyIdx	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		unsigned	IdxMulOpd,
		unsigned	MaddOpc,
		const TargetRegisterClass *	RC )

static

genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.

See also: genFusedMultiply

Definition at line 8896 of file AArch64InstrInfo.cpp.

References genFusedMultiply(), Indexed, and TII.

◆ genFusedMultiplyIdxNeg()

MachineInstr * genFusedMultiplyIdxNeg	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		DenseMap< Register, unsigned > &	InstrIdxForVirtReg,
		unsigned	IdxMulOpd,
		unsigned	MaddOpc,
		unsigned	MnegOpc,
		const TargetRegisterClass *	RC )

static

genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator

Definition at line 8906 of file AArch64InstrInfo.cpp.

References assert(), genFusedMultiply(), genNeg(), Indexed, and TII.

◆ genIndexedMultiply()

MachineInstr * genIndexedMultiply	(	MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		unsigned	IdxDupOp,
		unsigned	MulOpc,
		const TargetRegisterClass *	RC,
		MachineRegisterInfo &	MRI )

static

◆ genMaddR()

MachineInstr * genMaddR	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		unsigned	IdxMulOpd,
		unsigned	MaddOpc,
		unsigned	VR,
		const TargetRegisterClass *	RC )

static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters

	MF	Containing MachineFunction
	MRI	Register information
	TII	Target information
	Root	is the ADD instruction
[out]	InsInstrs	is a vector of machine instructions and will contain the generated madd instruction
	IdxMulOpd	is index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
	MaddOpc	the opcode fo the madd instruction
	VR	is a virtual register that holds the value of an ADD operand (V in the example above).
	RC	Register class of operands

Definition at line 8939 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::Register::isVirtual(), llvm::Register::isVirtualRegister(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

◆ genNeg()

Register genNeg	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		DenseMap< Register, unsigned > &	InstrIdxForVirtReg,
		unsigned	MnegOpc,
		const TargetRegisterClass *	RC )

static

genNeg - Helper to generate an intermediate negation of the second operand of Root

Definition at line 8860 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty(), llvm::MachineInstr::getOperand(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by genFusedMultiplyAccNeg(), and genFusedMultiplyIdxNeg().

◆ genSubAdd2SubSub()

void genSubAdd2SubSub	(	MachineFunction &	MF,
		MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII,
		MachineInstr &	Root,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		SmallVectorImpl< MachineInstr * > &	DelInstrs,
		unsigned	IdxOpd1,
		DenseMap< Register, unsigned > &	InstrIdxForVirtReg )

static

Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.

Definition at line 8975 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm::MachineInstr::mergeFlagsWith(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

◆ getBranchDisplacementBits()

unsigned getBranchDisplacementBits ( unsigned Opc )

static

Definition at line 379 of file AArch64InstrInfo.cpp.

References BCCDisplacementBits, BDisplacementBits, CBDisplacementBits, CBZDisplacementBits, llvm_unreachable, Opc, and TBZDisplacementBits.

Referenced by llvm::AArch64InstrInfo::isBranchOffsetInRange().

◆ getFMAPatterns()

bool getFMAPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns )

static

Floating-Point Support.

Find instructions that can be turned into madd.

Definition at line 7955 of file AArch64InstrInfo.cpp.

References assert(), canCombineWithFMUL(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidateFP(), llvm::MachineOperand::isReg(), MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getFMULPatterns()

bool getFMULPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns )

static

Definition at line 8097 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getFNEGPatterns()

bool getFNEGPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns )

static

Definition at line 8149 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::FmNsz, llvm::FNMADD, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), MBB, MI, Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getGatherLanePattern()

bool getGatherLanePattern	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns,
		unsigned	LoadLaneOpCode,
		unsigned	NumLanes )

static

Check if the given instruction forms a gather load pattern that can be optimized for better Memory-Level Parallelism (MLP).

This function identifies chains of NEON lane load instructions that load data from different memory addresses into individual lanes of a 128-bit vector register, then attempts to split the pattern into parallel loads to break the serial dependency between instructions.

Pattern Matched: Initial scalar load -> SUBREG_TO_REG (lane 0) -> LD1i* (lane 1) -> LD1i* (lane 2) -> ... -> LD1i* (lane N-1, Root)

Transformed Into: Two parallel vector loads using fewer lanes each, followed by ZIP1v2i64 to combine the results, enabling better memory-level parallelism.

Supported Element Types:

32-bit elements (LD1i32, 4 lanes total)
16-bit elements (LD1i16, 8 lanes total)
8-bit elements (LD1i8, 16 lanes total)

Definition at line 8353 of file AArch64InstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::SmallPtrSetImplBase::empty(), llvm::SmallSet< T, N, C >::empty(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::SmallSet< T, N, C >::erase(), llvm::GATHER_LANE_i16, llvm::GATHER_LANE_i32, llvm::GATHER_LANE_i8, GatherOptSearchLimit, llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::Function::hasMinSize(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MachineInstr::isLoadFoldBarrier(), llvm_unreachable, MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Range, llvm::seq(), and TRI.

Referenced by getLoadPatterns().

◆ getIndVarInfo()

bool getIndVarInfo	(	Register	Reg,
		const MachineBasicBlock *	LoopBB,
		MachineInstr *&	UpdateInst,
		unsigned &	UpdateCounterOprNum,
		Register &	InitReg,
		bool &	IsUpdatePriorComp )

static

If Reg is an induction variable, return true and set some parameters.

Definition at line 11942 of file AArch64InstrInfo.cpp.

References extractPhiReg(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), isDefinedOutside(), llvm::Register::isVirtual(), llvm::MachineBasicBlock::pred_size(), and Reg.

Referenced by llvm::AArch64InstrInfo::analyzeLoopForPipelining().

◆ getLFIInstSizeInBytes()

std::optional< unsigned > getLFIInstSizeInBytes ( const MachineInstr & MI )

static

Return the maximum number of bytes of code the specified instruction may be after LFI rewriting.

If the instruction is not rewritten, std::nullopt is returned (use default sizing).

NOTE: the size estimates here must be kept in sync with the rewrites in AArch64MCLFIRewriter.cpp. Sizes may be overestimates of the rewritten instruction sequences.

Definition at line 118 of file AArch64InstrInfo.cpp.

References llvm::isLFIPrePostMemAccess(), MI, and Size.

Referenced by llvm::AArch64InstrInfo::getInstSizeInBytes().

◆ getLoadPatterns()

bool getLoadPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns )

static

Search for patterns of LD instructions we can optimize.

Definition at line 8454 of file AArch64InstrInfo.cpp.

References getGatherLanePattern(), and llvm::MachineInstr::getOpcode().

◆ getMaddPatterns()

bool getMaddPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns )

static

Find instructions that can be turned into madd.

Definition at line 7686 of file AArch64InstrInfo.cpp.

References assert(), canCombine(), canCombineWithMUL(), convertToNonFlagSettingOpc(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), MBB, Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMiscPatterns()

bool getMiscPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns )

static

Find other MI combine patterns.

Definition at line 8300 of file AArch64InstrInfo.cpp.

References canCombine(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrSettingFlag(), MBB, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SUBADD_OP1, and llvm::SUBADD_OP2.

◆ getRegClass()

const TargetRegisterClass * getRegClass	(	const MachineInstr &	MI,
		Register	Reg )

static

Definition at line 5444 of file AArch64InstrInfo.cpp.

References llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::MachineFunction::getRegInfo(), MI, and Reg.

Referenced by llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getLargestLegalSuperClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), llvm::M68kRegisterInfo::getSpillRegisterOrder(), llvm::AArch64InstrInfo::isFpOrNEON(), llvm::AArch64InstrInfo::isHForm(), llvm::AArch64InstrInfo::isQForm(), llvm::SIRegisterInfo::isSGPRClassID(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::SIInstrInfo::reMaterialize(), selectCopy(), and llvm::AVRRegisterInfo::shouldCoalesce().

◆ getUsedNZCV()

UsedNZCV getUsedNZCV ( AArch64CC::CondCode CC )

static

◆ isADDSRegImm()

bool isADDSRegImm ( unsigned Opcode )

static

Definition at line 2320 of file AArch64InstrInfo.cpp.

Referenced by canCmpInstrBeRemoved(), and canInstrSubstituteCmpInstr().

◆ isANDOpcode()

bool isANDOpcode ( MachineInstr & MI )

static

Definition at line 2328 of file AArch64InstrInfo.cpp.

References MI, Opc, and sForm().

Referenced by canInstrSubstituteCmpInstr().

◆ isCheapCopy()

bool isCheapCopy	(	const MachineInstr &	MI,
		const AArch64RegisterInfo &	RI )

static

Definition at line 1345 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::getRegClass(), MI, and Reg.

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

◆ isCheapImmediate()

bool isCheapImmediate	(	const MachineInstr &	MI,
		unsigned	BitSize )

static

Definition at line 1332 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64_IMM::expandMOVImm(), llvm::getImm(), MI, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

◆ isCombineInstrCandidate()

bool isCombineInstrCandidate ( unsigned Opc )

static

Definition at line 7526 of file AArch64InstrInfo.cpp.

References isCombineInstrCandidate32(), isCombineInstrCandidate64(), and Opc.

Referenced by getMaddPatterns().

◆ isCombineInstrCandidate32()

bool isCombineInstrCandidate32 ( unsigned Opc )

static

Definition at line 7446 of file AArch64InstrInfo.cpp.

References Opc.

Referenced by isCombineInstrCandidate().

◆ isCombineInstrCandidate64()

bool isCombineInstrCandidate64 ( unsigned Opc )

static

Definition at line 7465 of file AArch64InstrInfo.cpp.

References Opc.

Referenced by isCombineInstrCandidate().

◆ isCombineInstrCandidateFP()

bool isCombineInstrCandidateFP ( const MachineInstr & Inst )

static

Definition at line 7496 of file AArch64InstrInfo.cpp.

References llvm::FPOpFusion::Fast, llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and Options.

Referenced by getFMAPatterns().

◆ isCombineInstrSettingFlag()

bool isCombineInstrSettingFlag ( unsigned Opc )

static

Definition at line 7427 of file AArch64InstrInfo.cpp.

References Opc.

Referenced by canCombine(), getMaddPatterns(), and getMiscPatterns().

◆ isDefinedOutside()

bool isDefinedOutside	(	Register	Reg,
		const MachineBasicBlock *	BB )

static

Definition at line 11934 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), and Reg.

Referenced by llvm::AArch64InstrInfo::analyzeLoopForPipelining(), and getIndVarInfo().

◆ isFrameLoadOpcode()

bool isFrameLoadOpcode ( int Opcode )

static

Definition at line 2826 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlotPostFE(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().

◆ isFrameStoreOpcode()

bool isFrameStoreOpcode ( int Opcode )

static

Definition at line 2855 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlotPostFE(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().

◆ isInStreamingCallSiteRegion()

bool isInStreamingCallSiteRegion	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I )

static

Returns true if the instruction at I is in a streaming call site region, within a single basic block.

A "call site streaming region" starts after smstart and ends at smstop around a call to a streaming function. This walks backward from I.

Definition at line 5770 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::hasStreamingModeChanges(), I, llvm::make_range(), MBB, MI, Opc, and llvm::reverse().

Referenced by mustAvoidNeonAtMBBI().

◆ isPostIndexLdStOpcode()

bool isPostIndexLdStOpcode ( unsigned Opcode )

static

Return true if the opcode is a post-index ld/st instruction, which really loads from base+0.

Definition at line 4397 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth().

◆ isSUBSRegImm()

bool isSUBSRegImm ( unsigned Opcode )

static

Definition at line 2324 of file AArch64InstrInfo.cpp.

Referenced by canCmpInstrBeRemoved(), and canInstrSubstituteCmpInstr().

◆ loadRegPairFromStackSlot()

void loadRegPairFromStackSlot	(	const TargetRegisterInfo &	TRI,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsertBefore,
		const MCInstrDesc &	MCID,
		Register	DestReg,
		unsigned	SubIdx0,
		unsigned	SubIdx1,
		int	FI,
		MachineMemOperand *	MMO )

static

Definition at line 6505 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::Define, llvm::getUndefRegState(), llvm::Register::isPhysical(), MBB, and TRI.

Referenced by llvm::AArch64InstrInfo::loadRegFromStackSlot().

◆ mustAvoidNeonAtMBBI()

bool mustAvoidNeonAtMBBI	(	const AArch64Subtarget &	Subtarget,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I )

static

Returns true if in a streaming call site region without SME-FA64.

Definition at line 5792 of file AArch64InstrInfo.cpp.

References I, isInStreamingCallSiteRegion(), and MBB.

Referenced by llvm::AArch64InstrInfo::copyPhysReg().

◆ offsetExtendOpcode()

unsigned offsetExtendOpcode ( unsigned Opcode )

static

Definition at line 4226 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ outliningCandidatesSigningKeyConsensus()

bool outliningCandidatesSigningKeyConsensus	(	const outliner::Candidate &	a,
		const outliner::Candidate &	b )

static

Definition at line 10317 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::outliner::Candidate::getMF(), and llvm::AArch64FunctionInfo::shouldSignWithBKey().

◆ outliningCandidatesSigningScopeConsensus()

bool outliningCandidatesSigningScopeConsensus	(	const outliner::Candidate &	a,
		const outliner::Candidate &	b )

static

Definition at line 10307 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::outliner::Candidate::getMF(), and llvm::AArch64FunctionInfo::getSignReturnAddressCondition().

◆ outliningCandidatesV8_3OpsConsensus()

bool outliningCandidatesV8_3OpsConsensus	(	const outliner::Candidate &	a,
		const outliner::Candidate &	b )

static

Definition at line 10325 of file AArch64InstrInfo.cpp.

References llvm::outliner::Candidate::getMF(), and llvm::MachineFunction::getSubtarget().

◆ parseCondBranch()

void parseCondBranch	(	MachineInstr *	LastInst,
		MachineBasicBlock *&	Target,
		SmallVectorImpl< MachineOperand > &	Cond )

static

Definition at line 325 of file AArch64InstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::analyzeBranch(), llvm::CSKYInstrInfo::analyzeBranch(), llvm::LoongArchInstrInfo::analyzeBranch(), llvm::RISCVInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), and llvm::VEInstrInfo::analyzeBranch().

◆ regOffsetOpcode()

unsigned regOffsetOpcode ( unsigned Opcode )

static

Definition at line 3971 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ removeCopies()

unsigned removeCopies	(	const MachineRegisterInfo &	MRI,
		unsigned	VReg )

static

Definition at line 911 of file AArch64InstrInfo.cpp.

References DefMI, llvm::MachineRegisterInfo::getVRegDef(), and llvm::Register::isVirtualRegister().

Referenced by canFoldIntoCSel().

◆ scaledOffsetOpcode()

unsigned scaledOffsetOpcode	(	unsigned	Opcode,
		unsigned &	Scale )

Definition at line 4045 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ scaleOffset()

bool scaleOffset	(	unsigned	Opc,
		int64_t &	Offset )

static

Definition at line 5538 of file AArch64InstrInfo.cpp.

References llvm::AArch64InstrInfo::getMemScale(), llvm::Offset, and Opc.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ sForm()

unsigned sForm ( MachineInstr & Instr )

static

Get opcode of S version of Instr.

If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.

Definition at line 2093 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr(), and isANDOpcode().

◆ shouldClusterFI()

bool shouldClusterFI	(	const MachineFrameInfo &	MFI,
		int	FI1,
		int64_t	Offset1,
		unsigned	Opcode1,
		int	FI2,
		int64_t	Offset2,
		unsigned	Opcode2 )

static

Definition at line 5597 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64InstrInfo::getMemScale(), llvm::MachineFrameInfo::getObjectOffset(), and llvm::MachineFrameInfo::isFixedObjectIndex().

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ signOutlinedFunction()

void signOutlinedFunction	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		const AArch64InstrInfo *	TII,
		bool	ShouldSignReturnAddr )

static

Definition at line 11114 of file AArch64InstrInfo.cpp.

References llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::MachineInstr::FrameSetup, MBB, llvm::MachineInstrBuilder::setMIFlag(), and TII.

◆ STATISTIC() [1/4]

STATISTIC	(	NumCopyInstrs	,
		"Number of COPY instructions expanded"	)

◆ STATISTIC() [2/4]

STATISTIC	(	NumZCRegMoveInstrsFPR	,
		"Number of zero-cycle FPR register move " "instructions expanded from canonical COPY"	)

◆ STATISTIC() [3/4]

STATISTIC	(	NumZCRegMoveInstrsGPR	,
		"Number of zero-cycle GPR register move " "instructions expanded from canonical COPY"	)

◆ STATISTIC() [4/4]

STATISTIC	(	NumZCZeroingInstrsGPR	,
		"Number of zero-cycle GPR zeroing " "instructions expanded from canonical COPY"	)

◆ storeRegPairToStackSlot()

void storeRegPairToStackSlot	(	const TargetRegisterInfo &	TRI,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsertBefore,
		const MCInstrDesc &	MCID,
		Register	SrcReg,
		bool	IsKill,
		unsigned	SubIdx0,
		unsigned	SubIdx1,
		int	FI,
		MachineMemOperand *	MMO )

static

Definition at line 6327 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::getKillRegState(), llvm::Register::isPhysical(), MBB, and TRI.

Referenced by llvm::AArch64InstrInfo::storeRegToStackSlot().

◆ unscaledOffsetOpcode()

unsigned unscaledOffsetOpcode ( unsigned Opcode )

Definition at line 4150 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ UpdateOperandRegClass()

bool UpdateOperandRegClass ( MachineInstr & Instr )

static

Variable Documentation

◆ BCCDisplacementBits

cl::opt< unsigned > BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))	(	"aarch64-bcc-offset-bits"	,
		cl::Hidden	,
		cl::init(19)	,
		cl::desc("Restrict range of Bcc instructions (DEBUG)")	)

static

Referenced by getBranchDisplacementBits().

◆ BDisplacementBits

cl::opt< unsigned > BDisplacementBits("aarch64-b-offset-bits", cl::Hidden, cl::init(26), cl::desc("Restrict range of B instructions (DEBUG)"))	(	"aarch64-b-offset-bits"	,
		cl::Hidden	,
		cl::init(26)	,
		cl::desc("Restrict range of B instructions (DEBUG)")	)

static

Referenced by getBranchDisplacementBits().

◆ CBDisplacementBits

cl::opt< unsigned > CBDisplacementBits("aarch64-cb-offset-bits", cl::Hidden, cl::init(9), cl::desc("Restrict range of CB instructions (DEBUG)"))	(	"aarch64-cb-offset-bits"	,
		cl::Hidden	,
		cl::init(9)	,
		cl::desc("Restrict range of CB instructions (DEBUG)")	)

static

Referenced by getBranchDisplacementBits().

◆ CBZDisplacementBits

cl::opt< unsigned > CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))	(	"aarch64-cbz-offset-bits"	,
		cl::Hidden	,
		cl::init(19)	,
		cl::desc("Restrict range of CB[N]Z instructions (DEBUG)")	)

static

Referenced by getBranchDisplacementBits().

◆ GatherOptSearchLimit

cl::opt< unsigned > GatherOptSearchLimit("aarch64-search-limit", cl::Hidden, cl::init(2048), cl::desc("Restrict range of instructions to search for the " "machine-combiner gather pattern optimization"))	(	"aarch64-search-limit"	,
		cl::Hidden	,
		cl::init(2048)	,
		cl::desc("Restrict range of instructions to search for the " "machine-combiner gather pattern optimization")	)

static

Referenced by getGatherLanePattern().

◆ TBZDisplacementBits

cl::opt< unsigned > TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))	(	"aarch64-tbz-offset-bits"	,
		cl::Hidden	,
		cl::init(14)	,
		cl::desc("Restrict range of TB[N]Z instructions (DEBUG)")	)

static

Referenced by getBranchDisplacementBits().

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRINFO_HELPERS

◆ GET_INSTRMAP_INFO

Enumeration Type Documentation

◆ AccessKind

◆ FMAInstKind

◆ MachineOutlinerClass

◆ MachineOutlinerMBBFlags

Function Documentation

◆ AddSubReg()

◆ appendConstantExpr()

◆ appendLoadRegExpr()

◆ appendOffsetComment()

◆ appendReadRegExpr()

◆ areCFlagsAccessedBetweenInstrs()

◆ areCFlagsAliveInSuccessors()

◆ canCmpInstrBeRemoved()

◆ canCombine()

◆ canCombineWithFMUL()

◆ canCombineWithMUL()

◆ canFoldIntoCSel()

◆ canInstrSubstituteCmpInstr()

◆ canPairLdStOpc()

◆ cloneInstr()

◆ convertToNonFlagSettingOpc()

◆ createDefCFAExpression()

◆ describeORRLoadedValue()

◆ emitFrameOffsetAdj()

◆ extractPhiReg()

◆ findCondCodeUsedByInstr()

◆ forwardCopyWillClobberTuple()

◆ generateGatherLanePattern()

◆ genFNegatedMAD()

◆ genFusedMultiply()

◆ genFusedMultiplyAcc()

◆ genFusedMultiplyAccNeg()

◆ genFusedMultiplyIdx()

◆ genFusedMultiplyIdxNeg()

◆ genIndexedMultiply()

◆ genMaddR()

◆ genNeg()

◆ genSubAdd2SubSub()

◆ getBranchDisplacementBits()

◆ getFMAPatterns()

◆ getFMULPatterns()

◆ getFNEGPatterns()

◆ getGatherLanePattern()

◆ getIndVarInfo()

◆ getLFIInstSizeInBytes()

◆ getLoadPatterns()

◆ getMaddPatterns()

◆ getMiscPatterns()

◆ getRegClass()

◆ getUsedNZCV()

◆ isADDSRegImm()

◆ isANDOpcode()

◆ isCheapCopy()

◆ isCheapImmediate()

◆ isCombineInstrCandidate()

◆ isCombineInstrCandidate32()

◆ isCombineInstrCandidate64()

◆ isCombineInstrCandidateFP()

◆ isCombineInstrSettingFlag()

◆ isDefinedOutside()

◆ isFrameLoadOpcode()

◆ isFrameStoreOpcode()

◆ isInStreamingCallSiteRegion()

◆ isPostIndexLdStOpcode()

◆ isSUBSRegImm()

◆ loadRegPairFromStackSlot()

◆ mustAvoidNeonAtMBBI()

◆ offsetExtendOpcode()

◆ outliningCandidatesSigningKeyConsensus()

◆ outliningCandidatesSigningScopeConsensus()