AArch64InstrInfo.cpp File Reference

#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AArch64GenInstrInfo.inc"

Include dependency graph for AArch64InstrInfo.cpp:

Go to the source code of this file.

Macros
#define	GET_INSTRINFO_CTOR_DTOR
#define	GET_INSTRINFO_HELPERS
#define	GET_INSTRMAP_INFO

Enumerations
enum	AccessKind { AK_Write = 0x01 , AK_Read = 0x10 , AK_All = 0x11 }
enum class	FMAInstKind { Default , Indexed , Accumulator }
enum	MachineOutlinerClass {   MachineOutlinerDefault , MachineOutlinerTailCall , MachineOutlinerNoLRSave , MachineOutlinerThunk ,   MachineOutlinerRegSave , MachineOutlinerTailCall , MachineOutlinerThunk , MachineOutlinerNoLRSave ,   MachineOutlinerRegSave , MachineOutlinerDefault , MachineOutlinerDefault , MachineOutlinerTailCall }
	Constants defining how certain sequences should be outlined. More...
enum	MachineOutlinerMBBFlags {   LRUnavailableSomewhere = 0x2 , HasCalls = 0x4 , UnsafeRegsDead = 0x8 , LRUnavailableSomewhere = 0x2 ,   HasCalls = 0x4 , UnsafeRegsDead = 0x8 }

Functions
static void	parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned	getBranchDisplacementBits (unsigned Opc)
static unsigned	removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
static unsigned	canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewVReg=nullptr)
static bool	canBeExpandedToORR (const MachineInstr &MI, unsigned BitSize)
	Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.
static bool	UpdateOperandRegClass (MachineInstr &Instr)
static unsigned	convertToNonFlagSettingOpc (const MachineInstr &MI)
	Return the opcode that does not set flags when possible - otherwise return the original opcode.
static bool	areCFlagsAccessedBetweenInstrs (MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
	True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.
static unsigned	sForm (MachineInstr &Instr)
	Get opcode of S version of Instr.
static bool	areCFlagsAliveInSuccessors (const MachineBasicBlock *MBB)
	Check if AArch64::NZCV should be alive in successors of MBB.
static int	findCondCodeUseOperandIdxForBranchOrSelect (const MachineInstr &Instr)
static AArch64CC::CondCode	findCondCodeUsedByInstr (const MachineInstr &Instr)
	Find a condition code used by the instruction.
static UsedNZCV	getUsedNZCV (AArch64CC::CondCode CC)
static bool	isADDSRegImm (unsigned Opcode)
static bool	isSUBSRegImm (unsigned Opcode)
static bool	canInstrSubstituteCmpInstr (MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI)
	Check if CmpInstr can be substituted by MI.
static bool	canCmpInstrBeRemoved (MachineInstr &MI, MachineInstr &CmpInstr, int CmpValue, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > &CCUseInstrs, bool &IsInvertCC)
static const TargetRegisterClass *	getRegClass (const MachineInstr &MI, Register Reg)
static bool	scaleOffset (unsigned Opc, int64_t &Offset)
static bool	canPairLdStOpc (unsigned FirstOpc, unsigned SecondOpc)
static bool	shouldClusterFI (const MachineFrameInfo &MFI, int FI1, int64_t Offset1, unsigned Opcode1, int FI2, int64_t Offset2, unsigned Opcode2)
static const MachineInstrBuilder &	AddSubReg (const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
static bool	forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
static void	storeRegPairToStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register SrcReg, bool IsKill, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void	loadRegPairFromStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register DestReg, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void	appendVGScaledOffsetExpr (SmallVectorImpl< char > &Expr, int NumBytes, int NumVGScaledBytes, unsigned VG, llvm::raw_string_ostream &Comment)
static MCCFIInstruction	createDefCFAExpression (const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
static void	emitFrameOffsetAdj (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int64_t Offset, unsigned Opc, const TargetInstrInfo *TII, MachineInstr::MIFlag Flag, bool NeedsWinCFI, bool *HasWinCFI, bool EmitCFAOffset, StackOffset CFAOffset, unsigned FrameReg)
static bool	isCombineInstrSettingFlag (unsigned Opc)
static bool	isCombineInstrCandidate32 (unsigned Opc)
static bool	isCombineInstrCandidate64 (unsigned Opc)
static bool	isCombineInstrCandidateFP (const MachineInstr &Inst)
static bool	isCombineInstrCandidate (unsigned Opc)
static bool	canCombine (MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
static bool	canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
static bool	canCombineWithFMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
static bool	getMaddPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
	Find instructions that can be turned into madd.
static bool	getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
	Floating-Point Support.
static bool	getFMULPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
static bool	getMiscPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
	Find other MI combine patterns.
static MachineInstr *	genFusedMultiply (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind=FMAInstKind::Default, const Register *ReplacedAddend=nullptr)
	genFusedMultiply - Generate fused multiply instructions.
static MachineInstr *	genIndexedMultiply (MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxDupOp, unsigned MulOpc, const TargetRegisterClass *RC, MachineRegisterInfo &MRI)
	Fold (FMUL x (DUP y lane)) into (FMUL_indexed x y lane)
static MachineInstr *	genFusedMultiplyAcc (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
	genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.
static Register	genNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg, unsigned MnegOpc, const TargetRegisterClass *RC)
	genNeg - Helper to generate an intermediate negation of the second operand of Root
static MachineInstr *	genFusedMultiplyAccNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
	genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator
static MachineInstr *	genFusedMultiplyIdx (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
	genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.
static MachineInstr *	genFusedMultiplyIdxNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
	genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator
static MachineInstr *	genMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
	genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V
static void	genSubAdd2SubSub (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, unsigned IdxOpd1, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg)
	Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.
static bool	outliningCandidatesSigningScopeConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static bool	outliningCandidatesSigningKeyConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static bool	outliningCandidatesV8_3OpsConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static void	signOutlinedFunction (MachineFunction &MF, MachineBasicBlock &MBB, bool ShouldSignReturnAddr, bool ShouldSignReturnAddrWithBKey)
static std::optional< ParamLoadedValue >	describeORRLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
	If the given ORR instruction is a copy, and DescribedReg overlaps with the destination register then, if possible, describe the value in terms of the source register.

Variables
static cl::opt< unsigned >	TBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned >	CBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned >	BCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))

Macro Definition Documentation

GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 57 of file AArch64InstrInfo.cpp.

GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 8330 of file AArch64InstrInfo.cpp.

GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 8331 of file AArch64InstrInfo.cpp.

Enumeration Type Documentation

AccessKind

enum AccessKind

Enumerator
AK_Write
AK_Read
AK_All

Definition at line 1261 of file AArch64InstrInfo.cpp.

FMAInstKind

enum class FMAInstKind

strong

Enumerator
Default
Indexed
Accumulator

Definition at line 5567 of file AArch64InstrInfo.cpp.

MachineOutlinerClass

enum MachineOutlinerClass

Constants defining how certain sequences should be outlined.

This encompasses how an outlined function should be called, and what kind of frame should be emitted for that outlined function.

MachineOutlinerDefault implies that the function should be called with a save and restore of LR to the stack.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

• Call construction overhead: 3 (save + BL + restore)
• Frame construction overhead: 1 (ret)
• Requires stack fixups? Yes

MachineOutlinerTailCall implies that the function is being created from a sequence of instructions ending in a return.

That is,

I1 OUTLINED_FUNCTION: I2 --> B OUTLINED_FUNCTION I1 RET I2 RET

• Call construction overhead: 1 (B)
• Frame construction overhead: 0 (Return included in sequence)
• Requires stack fixups? No

MachineOutlinerNoLRSave implies that the function should be called using a BL instruction, but doesn't require LR to be saved and restored. This happens when LR is known to be dead.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 I2 I3 RET

• Call construction overhead: 1 (BL)
• Frame construction overhead: 1 (RET)
• Requires stack fixups? No

MachineOutlinerThunk implies that the function is being created from a sequence of instructions ending in a call. The outlined function is called with a BL instruction, and the outlined function tail-calls the original call destination.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 BL f I2 B f

• Call construction overhead: 1 (BL)
• Frame construction overhead: 0
• Requires stack fixups? No

MachineOutlinerRegSave implies that the function should be called with a save and restore of LR to an available register. This allows us to avoid stack fixups. Note that this outlining variant is compatible with the NoLRSave case.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

• Call construction overhead: 3 (save + BL + restore)
• Frame construction overhead: 1 (ret)
• Requires stack fixups? No

Enumerator
MachineOutlinerDefault
MachineOutlinerTailCall	Emit a save, restore, call, and return.
MachineOutlinerNoLRSave	Only emit a branch.
MachineOutlinerThunk	Emit a call and return.
MachineOutlinerRegSave	Emit a call and tail-call. Same as default, but save to a register.
MachineOutlinerTailCall
MachineOutlinerThunk
MachineOutlinerNoLRSave
MachineOutlinerRegSave
MachineOutlinerDefault
MachineOutlinerDefault
MachineOutlinerTailCall

Definition at line 7092 of file AArch64InstrInfo.cpp.

MachineOutlinerMBBFlags

enum MachineOutlinerMBBFlags

Enumerator
LRUnavailableSomewhere
HasCalls
UnsafeRegsDead
LRUnavailableSomewhere
HasCalls
UnsafeRegsDead

Definition at line 7100 of file AArch64InstrInfo.cpp.

Function Documentation

AddSubReg()

static const MachineInstrBuilder & AddSubReg ( const MachineInstrBuilder &  MIB, unsigned  Reg, unsigned  SubIdx, unsigned  State, const TargetRegisterInfo *  TRI  )

static

Definition at line 3404 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::Register::isPhysicalRegister(), and TRI.

Referenced by llvm::AArch64InstrInfo::copyGPRRegTuple(), and llvm::AArch64InstrInfo::copyPhysRegTuple().

appendVGScaledOffsetExpr()

static void appendVGScaledOffsetExpr ( SmallVectorImpl< char > &  Expr, int  NumBytes, int  NumVGScaledBytes, unsigned  VG, llvm::raw_string_ostream &  Comment  )

static

Definition at line 4161 of file AArch64InstrInfo.cpp.

References llvm::SmallVectorImpl< T >::append(), llvm::encodeSLEB128(), llvm::encodeULEB128(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

areCFlagsAccessedBetweenInstrs()

static bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock::iterator  From, MachineBasicBlock::iterator  To, const TargetRegisterInfo *  TRI, const AccessKind  AccessToCheck = AK_All  )

static

True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.

Note: If From and To are from different blocks it's assumed CC are accessed on the path.

Definition at line 1268 of file AArch64InstrInfo.cpp.

References AK_Read, AK_Write, assert(), From, llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::instructionsWithoutDebug(), MI, and TRI.

Referenced by canCmpInstrBeRemoved(), canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().

areCFlagsAliveInSuccessors()

static bool areCFlagsAliveInSuccessors ( const MachineBasicBlock *  MBB )

static

Check if AArch64::NZCV should be alive in successors of MBB.

Definition at line 1552 of file AArch64InstrInfo.cpp.

References MBB, and llvm::MachineBasicBlock::successors().

Referenced by llvm::examineCFlagsUse().

canBeExpandedToORR()

static bool canBeExpandedToORR ( const MachineInstr &  MI, unsigned  BitSize  )

static

Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.

Definition at line 788 of file AArch64InstrInfo.cpp.

References MI, and llvm::AArch64_AM::processLogicalImmediate().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

canCmpInstrBeRemoved()

static bool canCmpInstrBeRemoved ( MachineInstr &  MI, MachineInstr &  CmpInstr, int  CmpValue, const TargetRegisterInfo &  TRI, SmallVectorImpl< MachineInstr * > &  CCUseInstrs, bool &  IsInvertCC  )

static

Returns

True if CmpInstr can be removed.

IsInvertCC is true if, after removing CmpInstr, condition codes used in CCUseInstrs must be inverted.

Definition at line 1749 of file AArch64InstrInfo.cpp.

References AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::UsedNZCV::C, llvm::AArch64CC::EQ, llvm::examineCFlagsUse(), findCondCodeUsedByInstr(), llvm::MachineInstr::getOpcode(), getUsedNZCV(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), MI, llvm::UsedNZCV::N, llvm::AArch64CC::NE, llvm::AArch64CC::PL, TRI, llvm::UsedNZCV::V, and llvm::UsedNZCV::Z.

canCombine()

static bool canCombine ( MachineBasicBlock &  MBB, MachineOperand &  MO, unsigned  CombineOpc, unsigned  ZeroReg = 0, bool  CheckZeroReg = false  )

static

Definition at line 4898 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, MI, and MRI.

Referenced by canCombineWithFMUL(), canCombineWithMUL(), getMaddPatterns(), and getMiscPatterns().

canCombineWithFMUL()

static bool canCombineWithFMUL ( MachineBasicBlock &  MBB, MachineOperand &  MO, unsigned  MulOpc  )

static

Definition at line 4938 of file AArch64InstrInfo.cpp.

References canCombine(), and MBB.

Referenced by getFMAPatterns().

canCombineWithMUL()

static bool canCombineWithMUL ( MachineBasicBlock &  MBB, MachineOperand &  MO, unsigned  MulOpc, unsigned  ZeroReg  )

static

Definition at line 4931 of file AArch64InstrInfo.cpp.

References canCombine(), and MBB.

Referenced by getMaddPatterns().

canFoldIntoCSel()

static unsigned canFoldIntoCSel ( const MachineRegisterInfo &  MRI, unsigned  VReg, unsigned *  NewVReg = nullptr  )

static

Definition at line 536 of file AArch64InstrInfo.cpp.

References assert(), DefMI, llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::Register::isVirtualRegister(), MRI, and removeCopies().

Referenced by llvm::AArch64InstrInfo::canInsertSelect(), and llvm::AArch64InstrInfo::insertSelect().

canInstrSubstituteCmpInstr()

static bool canInstrSubstituteCmpInstr ( MachineInstr &  MI, MachineInstr &  CmpInstr, const TargetRegisterInfo &  TRI  )

static

Check if CmpInstr can be substituted by MI.

CmpInstr can be substituted:

• CmpInstr is either 'ADDS vreg, 0' or 'SUBS vreg, 0'
• and, MI and CmpInstr are from the same MachineBB
• and, condition flags are not alive in successors of the CmpInstr parent
• and, if MI opcode is the S form there must be no defs of flags between MI and CmpInstr or if MI opcode is not the S form there must be neither defs of flags nor uses of flags between MI and CmpInstr.
• and C/V flags are not used after CmpInstr

Definition at line 1696 of file AArch64InstrInfo.cpp.

References AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::examineCFlagsUse(), llvm::MachineInstr::getOpcode(), isADDSRegImm(), isSUBSRegImm(), MI, sForm(), and TRI.

canPairLdStOpc()

static bool canPairLdStOpc ( unsigned  FirstOpc, unsigned  SecondOpc  )

static

Definition at line 3289 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

convertToNonFlagSettingOpc()

static unsigned convertToNonFlagSettingOpc ( const MachineInstr &  MI )

static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 1216 of file AArch64InstrInfo.cpp.

References MI.

Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

createDefCFAExpression()

static MCCFIInstruction createDefCFAExpression ( const TargetRegisterInfo &  TRI, unsigned  Reg, const StackOffset &  Offset  )

static

Definition at line 4191 of file AArch64InstrInfo.cpp.

References llvm::SmallString< InternalLen >::append(), appendVGScaledOffsetExpr(), llvm::MCCFIInstruction::createEscape(), llvm::AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets(), llvm::encodeULEB128(), llvm::Offset, llvm::printReg(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), llvm::SmallString< InternalLen >::str(), and TRI.

Referenced by llvm::createDefCFA(), and llvm::RISCVFrameLowering::emitPrologue().

describeORRLoadedValue()

static std::optional< ParamLoadedValue > describeORRLoadedValue ( const MachineInstr &  MI, Register  DescribedReg, const TargetInstrInfo *  TII, const TargetRegisterInfo *  TRI  )

static

If the given ORR instruction is a copy, and DescribedReg overlaps with the destination register then, if possible, describe the value in terms of the source register.

Definition at line 8224 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), MI, TII, and TRI.

Referenced by llvm::AArch64InstrInfo::describeLoadedValue().

emitFrameOffsetAdj()

static void emitFrameOffsetAdj ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, const DebugLoc &  DL, unsigned  DestReg, unsigned  SrcReg, int64_t  Offset, unsigned  Opc, const TargetInstrInfo *  TII, MachineInstr::MIFlag  Flag, bool  NeedsWinCFI, bool *  HasWinCFI, bool  EmitCFAOffset, StackOffset  CFAOffset, unsigned  FrameReg  )

static

Definition at line 4275 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::createDefCFA(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::StackOffset::getFixed(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::StackOffset::getScalable(), llvm::AArch64_AM::getShifterImm(), llvm::MachineFunction::getSubtarget(), llvm_unreachable, llvm::AArch64_AM::LSL, MBB, MBBI, llvm::Offset, llvm::MachineInstrBuilder::setMIFlag(), llvm::MachineInstrBuilder::setMIFlags(), TII, and TRI.

Referenced by llvm::emitFrameOffset().

findCondCodeUsedByInstr()

static AArch64CC::CondCode findCondCodeUsedByInstr ( const MachineInstr &  Instr )

static

Find a condition code used by the instruction.

Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.

Definition at line 1593 of file AArch64InstrInfo.cpp.

References findCondCodeUseOperandIdxForBranchOrSelect(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and llvm::AArch64CC::Invalid.

Referenced by canCmpInstrBeRemoved(), and llvm::examineCFlagsUse().

findCondCodeUseOperandIdxForBranchOrSelect()

static int findCondCodeUseOperandIdxForBranchOrSelect ( const MachineInstr &  Instr )

static

Returns

The condition code operand index for Instr if it is a branch or select and -1 otherwise.

Definition at line 1562 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getOpcode(), and Idx.

Referenced by findCondCodeUsedByInstr().

forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DestReg, unsigned  SrcReg, unsigned  NumRegs  )

static

Definition at line 3416 of file AArch64InstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::copyPhysReg(), and llvm::AArch64InstrInfo::copyPhysRegTuple().

genFusedMultiply()

static MachineInstr * genFusedMultiply ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, unsigned  IdxMulOpd, unsigned  MaddOpc, const TargetRegisterClass *  RC, FMAInstKind  kind = FMAInstKind::Default, const Register *  ReplacedAddend = nullptr  )

static

genFusedMultiply - Generate fused multiply instructions.

This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C

Parameters

	MF	Containing MachineFunction
	MRI	Register information
	TII	Target information
	Root	is the F|ADD instruction
[out]	InsInstrs	is a vector of machine instructions and will contain the generated madd instruction
	IdxMulOpd	is index of operand in Root that is the result of the F|MUL. In the example above IdxMulOpd is 1.
	MaddOpc	the opcode fo the f|madd instruction
	RC	Register class of operands
	kind	of fma instruction (addressing mode) to be generated
	ReplacedAddend	is the result register from the instruction replacing the non-combined operand, if any.

Definition at line 5588 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::Register::isVirtual(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genFusedMultiplyAcc(), genFusedMultiplyAccNeg(), genFusedMultiplyIdx(), and genFusedMultiplyIdxNeg().

genFusedMultiplyAcc()

static MachineInstr * genFusedMultiplyAcc ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, unsigned  IdxMulOpd, unsigned  MaddOpc, const TargetRegisterClass *  RC  )

static

genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.

See also

genFusedMultiply

Definition at line 5691 of file AArch64InstrInfo.cpp.

References genFusedMultiply(), MRI, and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genFusedMultiplyAccNeg()

static MachineInstr * genFusedMultiplyAccNeg ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg, unsigned  IdxMulOpd, unsigned  MaddOpc, unsigned  MnegOpc, const TargetRegisterClass *  RC  )

static

genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator

Definition at line 5720 of file AArch64InstrInfo.cpp.

References assert(), genFusedMultiply(), genNeg(), MRI, and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genFusedMultiplyIdx()

static MachineInstr * genFusedMultiplyIdx ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, unsigned  IdxMulOpd, unsigned  MaddOpc, const TargetRegisterClass *  RC  )

static

genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.

See also

genFusedMultiply

Definition at line 5737 of file AArch64InstrInfo.cpp.

References genFusedMultiply(), MRI, and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genFusedMultiplyIdxNeg()

static MachineInstr * genFusedMultiplyIdxNeg ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg, unsigned  IdxMulOpd, unsigned  MaddOpc, unsigned  MnegOpc, const TargetRegisterClass *  RC  )

static

genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator

Definition at line 5747 of file AArch64InstrInfo.cpp.

References assert(), genFusedMultiply(), genNeg(), MRI, and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genIndexedMultiply()

static MachineInstr * genIndexedMultiply ( MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, unsigned  IdxDupOp, unsigned  MulOpc, const TargetRegisterClass *  RC, MachineRegisterInfo &  MRI  )

static

Fold (FMUL x (DUP y lane)) into (FMUL_indexed x y lane)

Definition at line 5650 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getUniqueVRegDef(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genMaddR()

static MachineInstr * genMaddR ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, unsigned  IdxMulOpd, unsigned  MaddOpc, unsigned  VR, const TargetRegisterClass *  RC  )

static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters

	MF	Containing MachineFunction
	MRI	Register information
	TII	Target information
	Root	is the ADD instruction
[out]	InsInstrs	is a vector of machine instructions and will contain the generated madd instruction
	IdxMulOpd	is index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
	MaddOpc	the opcode fo the madd instruction
	VR	is a virtual register that holds the value of an ADD operand (V in the example above).
	RC	Register class of operands

Definition at line 5780 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::Register::isVirtual(), llvm::Register::isVirtualRegister(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genNeg()

static Register genNeg ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg, unsigned  MnegOpc, const TargetRegisterClass *  RC  )

static

genNeg - Helper to generate an intermediate negation of the second operand of Root

Definition at line 5701 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty(), llvm::MachineInstr::getOperand(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by genFusedMultiplyAccNeg(), and genFusedMultiplyIdxNeg().

genSubAdd2SubSub()

static void genSubAdd2SubSub ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, unsigned  IdxOpd1, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  )

static

Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.

Definition at line 5817 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

getBranchDisplacementBits()

static unsigned getBranchDisplacementBits ( unsigned  Opc )

static

Definition at line 182 of file AArch64InstrInfo.cpp.

References BCCDisplacementBits, CBZDisplacementBits, llvm_unreachable, and TBZDisplacementBits.

Referenced by llvm::AArch64InstrInfo::isBranchOffsetInRange().

getFMAPatterns()

static bool getFMAPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  )

static

Floating-Point Support.

Find instructions that can be turned into madd.

Definition at line 5193 of file AArch64InstrInfo.cpp.

References assert(), canCombineWithFMUL(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidateFP(), llvm::MachineOperand::isReg(), llvm::Match, MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().

getFMULPatterns()

static bool getFMULPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  )

static

Definition at line 5336 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::Match, MBB, MI, MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().

getMaddPatterns()

static bool getMaddPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  )

static

Find instructions that can be turned into madd.

Definition at line 5052 of file AArch64InstrInfo.cpp.

References assert(), canCombine(), canCombineWithMUL(), convertToNonFlagSettingOpc(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().

getMiscPatterns()

static bool getMiscPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  )

static

Find other MI combine patterns.

Definition at line 5508 of file AArch64InstrInfo.cpp.

References canCombine(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrSettingFlag(), MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SUBADD_OP1, and llvm::SUBADD_OP2.

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().

getRegClass()

static const TargetRegisterClass * getRegClass ( const MachineInstr &  MI, Register  Reg  )

static

Definition at line 3228 of file AArch64InstrInfo.cpp.

References llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::MachineFunction::getRegInfo(), and MI.

Referenced by llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::M68kRegisterInfo::getSpillRegisterOrder(), llvm::AArch64InstrInfo::isFpOrNEON(), llvm::AArch64InstrInfo::isQForm(), selectCopy(), llvm::AVRRegisterInfo::shouldCoalesce(), and llvm::X86InstrInfo::unfoldMemoryOperand().

getUsedNZCV()

static UsedNZCV getUsedNZCV ( AArch64CC::CondCode  CC )

static

Definition at line 1600 of file AArch64InstrInfo.cpp.

References assert(), llvm::UsedNZCV::C, CC, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::UsedNZCV::N, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::UsedNZCV::V, llvm::AArch64CC::VC, llvm::AArch64CC::VS, and llvm::UsedNZCV::Z.

Referenced by canCmpInstrBeRemoved(), and llvm::examineCFlagsUse().

isADDSRegImm()

static bool isADDSRegImm ( unsigned  Opcode )

static

Definition at line 1677 of file AArch64InstrInfo.cpp.

Referenced by canCmpInstrBeRemoved(), and canInstrSubstituteCmpInstr().

isCombineInstrCandidate()

static bool isCombineInstrCandidate ( unsigned  Opc )

static

Definition at line 4891 of file AArch64InstrInfo.cpp.

References isCombineInstrCandidate32(), and isCombineInstrCandidate64().

Referenced by getMaddPatterns().

isCombineInstrCandidate32()

static bool isCombineInstrCandidate32 ( unsigned  Opc )

static

Definition at line 4809 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

isCombineInstrCandidate64()

static bool isCombineInstrCandidate64 ( unsigned  Opc )

static

Definition at line 4828 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

isCombineInstrCandidateFP()

static bool isCombineInstrCandidateFP ( const MachineInstr &  Inst )

static

Definition at line 4859 of file AArch64InstrInfo.cpp.

References llvm::FPOpFusion::Fast, llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and Options.

Referenced by getFMAPatterns().

isCombineInstrSettingFlag()

static bool isCombineInstrSettingFlag ( unsigned  Opc )

static

Definition at line 4790 of file AArch64InstrInfo.cpp.

Referenced by canCombine(), getMaddPatterns(), and getMiscPatterns().

isSUBSRegImm()

static bool isSUBSRegImm ( unsigned  Opcode )

static

Definition at line 1681 of file AArch64InstrInfo.cpp.

Referenced by canCmpInstrBeRemoved(), and canInstrSubstituteCmpInstr().

loadRegPairFromStackSlot()

static void loadRegPairFromStackSlot ( const TargetRegisterInfo &  TRI, MachineBasicBlock &  MBB, MachineBasicBlock::iterator  InsertBefore, const MCInstrDesc &  MCID, Register  DestReg, unsigned  SubIdx0, unsigned  SubIdx1, int  FI, MachineMemOperand *  MMO  )

static

Definition at line 3951 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::getUndefRegState(), llvm::Register::isPhysical(), MBB, and TRI.

Referenced by llvm::AArch64InstrInfo::loadRegFromStackSlot().

outliningCandidatesSigningKeyConsensus()

static bool outliningCandidatesSigningKeyConsensus ( const outliner::Candidate &  a, const outliner::Candidate &  b  )

static

Definition at line 7137 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::outliner::Candidate::getMF(), and llvm::AArch64FunctionInfo::shouldSignWithBKey().

outliningCandidatesSigningScopeConsensus()

static bool outliningCandidatesSigningScopeConsensus ( const outliner::Candidate &  a, const outliner::Candidate &  b  )

static

Definition at line 7127 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::outliner::Candidate::getMF(), and llvm::AArch64FunctionInfo::shouldSignReturnAddress().

outliningCandidatesV8_3OpsConsensus()

static bool outliningCandidatesV8_3OpsConsensus ( const outliner::Candidate &  a, const outliner::Candidate &  b  )

static

Definition at line 7145 of file AArch64InstrInfo.cpp.

References llvm::outliner::Candidate::getMF(), and llvm::MachineFunction::getSubtarget().

parseCondBranch()

static void parseCondBranch ( MachineInstr *  LastInst, MachineBasicBlock *&  Target, SmallVectorImpl< MachineOperand > &  Cond  )

static

Definition at line 151 of file AArch64InstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm_unreachable.

Referenced by llvm::LoongArchInstrInfo::analyzeBranch(), llvm::RISCVInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::CSKYInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), and llvm::VEInstrInfo::analyzeBranch().

removeCopies()

static unsigned removeCopies ( const MachineRegisterInfo &  MRI, unsigned  VReg  )

static

Definition at line 523 of file AArch64InstrInfo.cpp.

References DefMI, llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isFullCopy(), llvm::Register::isVirtualRegister(), and MRI.

Referenced by canFoldIntoCSel().

scaleOffset()

static bool scaleOffset ( unsigned  Opc, int64_t &  Offset  )

static

Definition at line 3275 of file AArch64InstrInfo.cpp.

References llvm::AArch64InstrInfo::getMemScale(), and llvm::Offset.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

sForm()

static unsigned sForm ( MachineInstr &  Instr )

static

Get opcode of S version of Instr.

If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.

Definition at line 1505 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by canInstrSubstituteCmpInstr().

shouldClusterFI()

static bool shouldClusterFI ( const MachineFrameInfo &  MFI, int  FI1, int64_t  Offset1, unsigned  Opcode1, int  FI2, int64_t  Offset2, unsigned  Opcode2  )

static

Definition at line 3307 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64InstrInfo::getMemScale(), llvm::MachineFrameInfo::getObjectOffset(), and llvm::MachineFrameInfo::isFixedObjectIndex().

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

signOutlinedFunction()

static void signOutlinedFunction ( MachineFunction &  MF, MachineBasicBlock &  MBB, bool  ShouldSignReturnAddr, bool  ShouldSignReturnAddrWithBKey  )

static

Definition at line 7883 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::MCCFIInstruction::createNegateRAState(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getInfo(), llvm::AArch64Subtarget::getInstrInfo(), llvm::MachineFunction::getSubtarget(), MBB, llvm::AArch64FunctionInfo::needsDwarfUnwindInfo(), llvm::MachineInstrBuilder::setMIFlag(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by llvm::AArch64InstrInfo::buildOutlinedFrame().

storeRegPairToStackSlot()

static void storeRegPairToStackSlot ( const TargetRegisterInfo &  TRI, MachineBasicBlock &  MBB, MachineBasicBlock::iterator  InsertBefore, const MCInstrDesc &  MCID, Register  SrcReg, bool  IsKill, unsigned  SubIdx0, unsigned  SubIdx1, int  FI, MachineMemOperand *  MMO  )

static

Definition at line 3797 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::Register::isPhysical(), MBB, and TRI.

Referenced by llvm::AArch64InstrInfo::storeRegToStackSlot().

UpdateOperandRegClass()

static bool UpdateOperandRegClass ( MachineInstr &  Instr )

static

Definition at line 1175 of file AArch64InstrInfo.cpp.

References assert(), llvm::TargetRegisterClass::contains(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::TargetRegisterClass::hasSubClassEq(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isReg(), MBB, MRI, TII, and TRI.

Referenced by llvm::AArch64InstrInfo::optimizeCompareInstr().

Variable Documentation

BCCDisplacementBits

cl::opt< unsigned > BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)")) ( "aarch64-bcc-offset-bits"  , cl::Hidden  , cl::init(19)  , cl::desc("Restrict range of Bcc instructions (DEBUG)")    )

static

Referenced by getBranchDisplacementBits().

CBZDisplacementBits

cl::opt< unsigned > CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)")) ( "aarch64-cbz-offset-bits"  , cl::Hidden  , cl::init(19)  , cl::desc("Restrict range of CB[N]Z instructions (DEBUG)")    )

static

Referenced by getBranchDisplacementBits().

TBZDisplacementBits

cl::opt< unsigned > TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)")) ( "aarch64-tbz-offset-bits"  , cl::Hidden  , cl::init(14)  , cl::desc("Restrict range of TB[N]Z instructions (DEBUG)")    )

static

Referenced by getBranchDisplacementBits().