46 #define DEBUG_TYPE "reginfo" 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 51 STATISTIC(InflateGPRC,
"Number of gprc inputs for getLargestLegalClass");
52 STATISTIC(InflateGP8RC,
"Number of g8rc inputs for getLargestLegalClass");
56 cl::desc(
"Enable use of a base pointer for complex stack frames"));
60 cl::desc(
"Force the use of a base pointer in every function"));
64 cl::desc(
"Enable spills from gpr to vsr rather than stack"));
68 cl::desc(
"Consider R1 caller preserved so stack saves of " 69 "caller preserved registers can be LICM candidates"),
74 cl::desc(
"Maximum search distance for definition of CR bit " 83 TM.isPPC64() ? 0 : 1),
85 ImmToIdxMap[
PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
86 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
87 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
88 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
89 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
90 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
91 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
92 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
93 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
96 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
97 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
98 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
99 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
100 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
103 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
104 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
105 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
106 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
107 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
108 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
109 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
110 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
111 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
112 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
113 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
114 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
117 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
118 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
119 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
120 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
132 return &PPC::G8RC_NOX0RegClass;
133 return &PPC::GPRC_NOR0RegClass;
137 return &PPC::G8RCRegClass;
138 return &PPC::GPRCRegClass;
146 return CSR_64_AllRegs_VSX_SaveList;
148 return CSR_64_AllRegs_Altivec_SaveList;
149 return CSR_64_AllRegs_SaveList;
154 ? (Subtarget.
hasAltivec() ? CSR_Darwin64_Altivec_SaveList
155 : CSR_Darwin64_SaveList)
156 : (Subtarget.
hasAltivec() ? CSR_Darwin32_Altivec_SaveList
157 : CSR_Darwin32_SaveList);
160 return CSR_SRV464_TLS_PE_SaveList;
169 return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
170 : CSR_SVR64_ColdCC_Altivec_SaveList;
171 return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
172 : CSR_SVR64_ColdCC_SaveList;
176 return CSR_SVR32_ColdCC_Altivec_SaveList;
177 else if (Subtarget.
hasSPE())
178 return CSR_SVR32_ColdCC_SPE_SaveList;
179 return CSR_SVR32_ColdCC_SaveList;
184 return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
185 : CSR_SVR464_Altivec_SaveList;
186 return SaveR2 ? CSR_SVR464_R2_SaveList
187 : CSR_SVR464_SaveList;
191 return CSR_SVR432_Altivec_SaveList;
192 else if (Subtarget.
hasSPE())
193 return CSR_SVR432_SPE_SaveList;
194 return CSR_SVR432_SaveList;
199 assert(MF &&
"Invalid MachineFunction pointer.");
214 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
215 : CSR_SVR464_Altivec_ViaCopy_SaveList;
218 ? CSR_SVR464_R2_ViaCopy_SaveList
219 : CSR_SVR464_ViaCopy_SaveList;
228 return CSR_64_AllRegs_VSX_RegMask;
230 return CSR_64_AllRegs_Altivec_RegMask;
231 return CSR_64_AllRegs_RegMask;
236 : CSR_Darwin64_RegMask)
237 : (Subtarget.
hasAltivec() ? CSR_Darwin32_Altivec_RegMask
238 : CSR_Darwin32_RegMask);
240 assert(!Subtarget.
hasAltivec() &&
"Altivec is not implemented on AIX yet.");
241 return TM.
isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask;
246 : CSR_SVR64_ColdCC_RegMask)
247 : (Subtarget.
hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
249 ? CSR_SVR32_ColdCC_SPE_RegMask
250 : CSR_SVR32_ColdCC_RegMask));
254 : CSR_SVR464_RegMask)
255 : (Subtarget.
hasAltivec() ? CSR_SVR432_Altivec_RegMask
257 ? CSR_SVR432_SPE_RegMask
258 : CSR_SVR432_RegMask));
263 return CSR_NoRegs_RegMask;
267 for (
unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8,
PPC::RM})
268 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
278 markSuperRegs(Reserved, PPC::ZERO);
282 markSuperRegs(Reserved,
PPC::FP);
286 markSuperRegs(Reserved, PPC::BP);
290 markSuperRegs(Reserved, PPC::CTR);
291 markSuperRegs(Reserved, PPC::CTR8);
293 markSuperRegs(Reserved, PPC::R1);
294 markSuperRegs(Reserved, PPC::LR);
295 markSuperRegs(Reserved, PPC::LR8);
296 markSuperRegs(Reserved,
PPC::RM);
299 markSuperRegs(Reserved, PPC::VRSAVE);
310 markSuperRegs(Reserved,
PPC::R2);
311 markSuperRegs(Reserved, PPC::R13);
317 markSuperRegs(Reserved,
PPC::R2);
321 markSuperRegs(Reserved, PPC::R13);
323 if (TFI->needsFP(MF))
324 markSuperRegs(Reserved, PPC::R31);
329 markSuperRegs(Reserved, PPC::R29);
331 markSuperRegs(Reserved, PPC::R30);
335 markSuperRegs(Reserved, PPC::R30);
340 IE = PPC::VRRCRegClass.end();
I !=
IE; ++
I)
341 markSuperRegs(Reserved, *
I);
343 assert(checkAllSuperRegsMarked(Reserved));
362 if (FrameSize & ~0x7FFF)
368 for (
unsigned i = 0; i < Info.size(); i++) {
369 int FrIdx = Info[i].getFrameIdx();
370 unsigned Reg = Info[i].getReg();
372 unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(Reg);
386 if (InstrInfo->isXFormMemOp(Opcode))
402 if (PhysReg == PPC::X2)
408 if (
StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
409 && !MFI.hasOpaqueSPAdjustment())
420 const unsigned DefaultSafety = 1;
422 switch (RC->
getID()) {
425 case PPC::G8RC_NOX0RegClassID:
426 case PPC::GPRC_NOR0RegClassID:
427 case PPC::SPERCRegClassID:
428 case PPC::G8RCRegClassID:
429 case PPC::GPRCRegClassID: {
430 unsigned FP = TFI->
hasFP(MF) ? 1 : 0;
431 return 32 - FP - DefaultSafety;
433 case PPC::F8RCRegClassID:
434 case PPC::F4RCRegClassID:
435 case PPC::QFRCRegClassID:
436 case PPC::QSRCRegClassID:
437 case PPC::QBRCRegClassID:
438 case PPC::VRRCRegClassID:
439 case PPC::VFRCRegClassID:
440 case PPC::VSLRCRegClassID:
441 return 32 - DefaultSafety;
442 case PPC::VSRCRegClassID:
443 case PPC::VSFRCRegClassID:
444 case PPC::VSSRCRegClassID:
445 return 64 - DefaultSafety;
446 case PPC::CRRCRegClassID:
447 return 8 - DefaultSafety;
464 RC == &PPC::G8RCRegClass) {
466 return &PPC::SPILLTOVSRRCRegClass;
471 if (RC == &PPC::F8RCRegClass)
472 return &PPC::VSFRCRegClass;
473 else if (RC == &PPC::VRRCRegClass)
474 return &PPC::VSRCRegClass;
475 else if (RC == &PPC::F4RCRegClass && Subtarget.
hasP8Vector())
476 return &PPC::VSSRCRegClass;
518 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
519 "Maximum call-frame size not sufficiently aligned");
531 if (MaxAlign < TargetAlign &&
isInt<16>(FrameSize)) {
556 if (MaxAlign > TargetAlign) {
557 unsigned UnalNegSizeReg = NegSizeReg;
562 BuildMI(MBB, II, dl, TII.
get(PPC::LI8), NegSizeReg)
563 .addImm(~(MaxAlign-1));
565 unsigned NegSizeReg1 = NegSizeReg;
567 BuildMI(MBB, II, dl, TII.
get(PPC::AND8), NegSizeReg)
570 KillNegSizeReg =
true;
573 BuildMI(MBB, II, dl, TII.
get(PPC::STDUX), PPC::X1)
579 .
addImm(maxCallFrameSize);
581 if (MaxAlign > TargetAlign) {
582 unsigned UnalNegSizeReg = NegSizeReg;
587 BuildMI(MBB, II, dl, TII.
get(PPC::LI), NegSizeReg)
588 .addImm(~(MaxAlign-1));
590 unsigned NegSizeReg1 = NegSizeReg;
595 KillNegSizeReg =
true;
598 BuildMI(MBB, II, dl, TII.
get(PPC::STWUX), PPC::R1)
604 .
addImm(maxCallFrameSize);
628 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::LI8 : PPC::LI),
630 .addImm(maxCallFrameSize);
667 if (SrcReg != PPC::CR0) {
672 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
674 .
addImm(getEncodingValue(SrcReg) * 4)
705 "RESTORE_CR does not define its destination");
712 if (DestReg != PPC::CR0) {
716 unsigned ShiftBits = getEncodingValue(DestReg)*4;
718 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
723 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
751 unsigned CRBitSpillDistance = 0;
752 for (Ins = MI; Ins != MBB.
rend(); Ins++) {
754 if (Ins->modifiesRegister(SrcReg, TRI))
762 if (!Ins->isDebugInstr())
763 CRBitSpillDistance++;
767 if (Ins == MBB.
rend())
771 switch (Ins->getOpcode()) {
773 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::LI8 : PPC::LI),
Reg)
777 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::LIS8 : PPC::LIS),
Reg)
797 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
799 .
addImm(getEncodingValue(SrcReg))
828 "RESTORE_CRBIT does not define its destination");
833 BuildMI(MBB, II, dl, TII.
get(TargetOpcode::IMPLICIT_DEF), DestReg);
839 unsigned ShiftBits = getEncodingValue(DestReg);
841 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
844 .
addImm(ShiftBits ? 32 - ShiftBits : 0)
848 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
901 "RESTORE_VRSAVE does not define its destination");
906 BuildMI(MBB, II, dl, TII.
get(PPC::MTVRSAVEv), DestReg)
914 unsigned Reg,
int &FrameIdx)
const {
921 if (Subtarget.
isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
946 case PPC::DFSTOREf32:
947 case PPC::DFSTOREf64:
970 unsigned FIOperandNum) {
972 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
974 OffsetOperandNo = FIOperandNum - 1;
975 else if (MI.
getOpcode() == TargetOpcode::STACKMAP ||
976 MI.
getOpcode() == TargetOpcode::PATCHPOINT)
977 OffsetOperandNo = FIOperandNum + 1;
979 return OffsetOperandNo;
984 int SPAdj,
unsigned FIOperandNum,
986 assert(SPAdj == 0 &&
"Unexpected");
1019 if (FPSI && FrameIndex == FPSI &&
1026 if (OpC == PPC::SPILL_CR) {
1029 }
else if (OpC == PPC::RESTORE_CR) {
1032 }
else if (OpC == PPC::SPILL_CRBIT) {
1035 }
else if (OpC == PPC::RESTORE_CRBIT) {
1038 }
else if (OpC == PPC::SPILL_VRSAVE) {
1041 }
else if (OpC == PPC::RESTORE_VRSAVE) {
1052 bool noImmForm = !MI.
isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1053 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.
count(OpC);
1076 assert(OpC != PPC::DBG_VALUE &&
1077 "This should be handled in a target-independent way");
1078 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1081 if (!noImmForm && ((OffsetFitsMnemonic &&
1083 OpC == TargetOpcode::STACKMAP ||
1084 OpC == TargetOpcode::PATCHPOINT)) {
1101 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1104 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1105 .addImm(Offset >> 16);
1106 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1115 unsigned OperandBase;
1122 "No indexed form of load or store available!");
1123 unsigned NewOpcode = ImmToIdxMap.
find(OpC)->second;
1124 MI.
setDesc(TII.get(NewOpcode));
1127 OperandBase = OffsetOperandNo;
1139 return TFI->
hasFP(MF) ? PPC::R31 : PPC::R1;
1141 return TFI->
hasFP(MF) ? PPC::X31 : PPC::X1;
1167 return needsStackRealignment(MF);
1176 assert(Offset < 0 &&
"Local offset must be negative");
1188 if (!ImmToIdxMap.
count(OpC))
1192 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1221 unsigned BaseReg,
int FrameIdx,
1223 unsigned ADDriOpc = TM.
isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1227 if (Ins != MBB->
end())
1228 DL = Ins->getDebugLoc();
1237 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1243 unsigned FIOperandNum = 0;
1247 "Instr doesn't have FrameIndex operand!");
1262 TII.getRegClass(MCID, FIOperandNum,
this, MF));
1268 unsigned FIOperandNum = 0;
1271 assert(FIOperandNum < MI->getNumOperands() &&
1272 "Instr doesn't have FrameIndex operand!");
1278 return MI->
getOpcode() == PPC::DBG_VALUE ||
1279 MI->
getOpcode() == TargetOpcode::STACKMAP ||
1280 MI->
getOpcode() == TargetOpcode::PATCHPOINT ||
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
DILocation * get() const
Get the underlying DILocation.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
int getFramePointerSaveIndex() const
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
This class represents lattice values for constants.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Describe properties that are true of each instruction in the target description file.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
unsigned determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
bool test(unsigned Idx) const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
constexpr bool isInt< 16 >(int64_t x)
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
static unsigned offsetMinAlignForOpcode(unsigned OpC)
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
int getCRSpillFrameIndex() const
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override
unsigned getID() const
Return the register class ID number.
INLINEASM - Represents an inline asm block.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
bool hasBasePointer(const MachineFunction &MF) const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Analysis containing CSE Info
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
iterator find(const_arg_type_t< KeyT > Val)
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
This file declares the machine register scavenger class.
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
constexpr bool isUInt< 8 >(uint64_t x)
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool is64Bit(const char *name)
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
static unsigned offsetMinAlign(const MachineInstr &MI)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
static cl::opt< unsigned > MaxCRBitSpillDist("ppc-max-crbit-spill-dist", cl::desc("Maximum search distance for definition of CR bit " "spill on ppc"), cl::Hidden, cl::init(100))
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Common code between 32-bit and 64-bit PowerPC targets.
const MachineInstrBuilder & addFrameIndex(int Idx) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const uint32_t * getNoPreservedMask() const override
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const PPCRegisterInfo * getRegisterInfo() const override
static cl::opt< bool > EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), cl::desc("Enable spills from gpr to vsr rather than stack"))
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const PPCInstrInfo * getInstrInfo() const override
bool is32BitELFABI() const
Register getBaseRegister(const MachineFunction &MF) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Register getFrameRegister(const MachineFunction &MF) const override
const MCPhysReg * iterator
const MachineBasicBlock * getParent() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool usesTOCBasePtr() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
static cl::opt< bool > StackPtrConst("ppc-stack-ptr-caller-preserved", cl::desc("Consider R1 caller preserved so stack saves of " "caller preserved registers can be LICM candidates"), cl::init(true), cl::Hidden)
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override