LLVM  15.0.0git
PPCRegisterInfo.cpp
Go to the documentation of this file.
1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCRegisterInfo.h"
15 #include "PPCFrameLowering.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Type.h"
37 #include "llvm/Support/Debug.h"
43 #include <cstdlib>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "reginfo"
48 
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
51 
52 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
53 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
54 
55 static cl::opt<bool>
56 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
57  cl::desc("Enable use of a base pointer for complex stack frames"));
58 
59 static cl::opt<bool>
60 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
61  cl::desc("Force the use of a base pointer in every function"));
62 
63 static cl::opt<bool>
64 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
65  cl::desc("Enable spills from gpr to vsr rather than stack"));
66 
67 static cl::opt<bool>
68 StackPtrConst("ppc-stack-ptr-caller-preserved",
69  cl::desc("Consider R1 caller preserved so stack saves of "
70  "caller preserved registers can be LICM candidates"),
71  cl::init(true), cl::Hidden);
72 
73 static cl::opt<unsigned>
74 MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
75  cl::desc("Maximum search distance for definition of CR bit "
76  "spill on ppc"),
77  cl::Hidden, cl::init(100));
78 
79 // Copies/moves of physical accumulators are expensive operations
80 // that should be avoided whenever possible. MMA instructions are
81 // meant to be used in performance-sensitive computational kernels.
82 // This option is provided, at least for the time being, to give the
83 // user a tool to detect this expensive operation and either rework
84 // their code or report a compiler bug if that turns out to be the
85 // cause.
86 #ifndef NDEBUG
87 static cl::opt<bool>
88 ReportAccMoves("ppc-report-acc-moves",
89  cl::desc("Emit information about accumulator register spills "
90  "and copies"),
91  cl::Hidden, cl::init(false));
92 #endif
93 
95 
96 static unsigned offsetMinAlignForOpcode(unsigned OpC);
97 
99  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
100  TM.isPPC64() ? 0 : 1,
101  TM.isPPC64() ? 0 : 1),
102  TM(TM) {
103  ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
104  ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
105  ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
106  ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
107  ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
108  ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
109  ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
110  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
111  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
112 
113  // 64-bit
114  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
115  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
116  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
117  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
118  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
119  ImmToIdxMap[PPC::LQ] = PPC::LQX_PSEUDO;
120  ImmToIdxMap[PPC::STQ] = PPC::STQX_PSEUDO;
121 
122  // VSX
123  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
124  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
125  ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
126  ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
127  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
128  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
129  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
130  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
131  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
132  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
133  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
134  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
135 
136  // SPE
137  ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
138  ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
139  ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
140  ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
141 
142  // Power10
143  ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8;
144  ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8;
145  ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8;
146  ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8;
147  ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX;
148  ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX;
149 
150  ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8;
151  ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8;
152  ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8;
153 
154  ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX;
155  ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX;
156  ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX;
157  ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX;
158  ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX;
159 
160  ImmToIdxMap[PPC::LXVP] = PPC::LXVPX;
161  ImmToIdxMap[PPC::STXVP] = PPC::STXVPX;
162  ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX;
163  ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX;
164 }
165 
166 /// getPointerRegClass - Return the register class to use to hold pointers.
167 /// This is used for addressing modes.
168 const TargetRegisterClass *
170  const {
171  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
172  // when it checks for ZERO folding.
173  if (Kind == 1) {
174  if (TM.isPPC64())
175  return &PPC::G8RC_NOX0RegClass;
176  return &PPC::GPRC_NOR0RegClass;
177  }
178 
179  if (TM.isPPC64())
180  return &PPC::G8RCRegClass;
181  return &PPC::GPRCRegClass;
182 }
183 
184 const MCPhysReg*
186  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
188  if (!TM.isPPC64() && Subtarget.isAIXABI())
189  report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
190  if (Subtarget.hasVSX()) {
191  if (Subtarget.pairedVectorMemops())
192  return CSR_64_AllRegs_VSRP_SaveList;
193  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
194  return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
195  return CSR_64_AllRegs_VSX_SaveList;
196  }
197  if (Subtarget.hasAltivec()) {
198  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
199  return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList;
200  return CSR_64_AllRegs_Altivec_SaveList;
201  }
202  return CSR_64_AllRegs_SaveList;
203  }
204 
205  // On PPC64, we might need to save r2 (but only if it is not reserved).
206  // We do not need to treat R2 as callee-saved when using PC-Relative calls
207  // because any direct uses of R2 will cause it to be reserved. If the function
208  // is a leaf or the only uses of R2 are implicit uses for calls, the calls
209  // will use the @notoc relocation which will cause this function to set the
210  // st_other bit to 1, thereby communicating to its caller that it arbitrarily
211  // clobbers the TOC.
212  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) &&
213  !Subtarget.isUsingPCRelativeCalls();
214 
215  // Cold calling convention CSRs.
217  if (Subtarget.isAIXABI())
218  report_fatal_error("Cold calling unimplemented on AIX.");
219  if (TM.isPPC64()) {
220  if (Subtarget.pairedVectorMemops())
221  return SaveR2 ? CSR_SVR64_ColdCC_R2_VSRP_SaveList
222  : CSR_SVR64_ColdCC_VSRP_SaveList;
223  if (Subtarget.hasAltivec())
224  return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
225  : CSR_SVR64_ColdCC_Altivec_SaveList;
226  return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
227  : CSR_SVR64_ColdCC_SaveList;
228  }
229  // 32-bit targets.
230  if (Subtarget.pairedVectorMemops())
231  return CSR_SVR32_ColdCC_VSRP_SaveList;
232  else if (Subtarget.hasAltivec())
233  return CSR_SVR32_ColdCC_Altivec_SaveList;
234  else if (Subtarget.hasSPE())
235  return CSR_SVR32_ColdCC_SPE_SaveList;
236  return CSR_SVR32_ColdCC_SaveList;
237  }
238  // Standard calling convention CSRs.
239  if (TM.isPPC64()) {
240  if (Subtarget.pairedVectorMemops())
241  return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
242  if (Subtarget.hasAltivec() &&
243  (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
244  return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
245  : CSR_PPC64_Altivec_SaveList;
246  }
247  return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
248  }
249  // 32-bit targets.
250  if (Subtarget.isAIXABI()) {
251  if (Subtarget.hasAltivec())
252  return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
253  : CSR_AIX32_SaveList;
254  return CSR_AIX32_SaveList;
255  }
256  if (Subtarget.pairedVectorMemops())
257  return CSR_SVR432_VSRP_SaveList;
258  if (Subtarget.hasAltivec())
259  return CSR_SVR432_Altivec_SaveList;
260  else if (Subtarget.hasSPE())
261  return CSR_SVR432_SPE_SaveList;
262  return CSR_SVR432_SaveList;
263 }
264 
265 const uint32_t *
267  CallingConv::ID CC) const {
268  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
269  if (CC == CallingConv::AnyReg) {
270  if (Subtarget.hasVSX()) {
271  if (Subtarget.pairedVectorMemops())
272  return CSR_64_AllRegs_VSRP_RegMask;
273  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
274  return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
275  return CSR_64_AllRegs_VSX_RegMask;
276  }
277  if (Subtarget.hasAltivec()) {
278  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
279  return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
280  return CSR_64_AllRegs_Altivec_RegMask;
281  }
282  return CSR_64_AllRegs_RegMask;
283  }
284 
285  if (Subtarget.isAIXABI()) {
286  return TM.isPPC64()
287  ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
288  ? CSR_PPC64_Altivec_RegMask
289  : CSR_PPC64_RegMask)
290  : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
291  ? CSR_AIX32_Altivec_RegMask
292  : CSR_AIX32_RegMask);
293  }
294 
295  if (CC == CallingConv::Cold) {
296  if (TM.isPPC64())
297  return Subtarget.pairedVectorMemops()
298  ? CSR_SVR64_ColdCC_VSRP_RegMask
299  : (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
300  : CSR_SVR64_ColdCC_RegMask);
301  else
302  return Subtarget.pairedVectorMemops()
303  ? CSR_SVR32_ColdCC_VSRP_RegMask
304  : (Subtarget.hasAltivec()
305  ? CSR_SVR32_ColdCC_Altivec_RegMask
306  : (Subtarget.hasSPE() ? CSR_SVR32_ColdCC_SPE_RegMask
307  : CSR_SVR32_ColdCC_RegMask));
308  }
309 
310  if (TM.isPPC64())
311  return Subtarget.pairedVectorMemops()
312  ? CSR_SVR464_VSRP_RegMask
313  : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
314  : CSR_PPC64_RegMask);
315  else
316  return Subtarget.pairedVectorMemops()
317  ? CSR_SVR432_VSRP_RegMask
318  : (Subtarget.hasAltivec()
319  ? CSR_SVR432_Altivec_RegMask
320  : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
321  : CSR_SVR432_RegMask));
322 }
323 
324 const uint32_t*
326  return CSR_NoRegs_RegMask;
327 }
328 
330  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
331  Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
332 }
333 
335  BitVector Reserved(getNumRegs());
336  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
337  const PPCFrameLowering *TFI = getFrameLowering(MF);
338 
339  // The ZERO register is not really a register, but the representation of r0
340  // when used in instructions that treat r0 as the constant 0.
341  markSuperRegs(Reserved, PPC::ZERO);
342 
343  // The FP register is also not really a register, but is the representation
344  // of the frame pointer register used by ISD::FRAMEADDR.
345  markSuperRegs(Reserved, PPC::FP);
346 
347  // The BP register is also not really a register, but is the representation
348  // of the base pointer register used by setjmp.
349  markSuperRegs(Reserved, PPC::BP);
350 
351  // The counter registers must be reserved so that counter-based loops can
352  // be correctly formed (and the mtctr instructions are not DCE'd).
353  markSuperRegs(Reserved, PPC::CTR);
354  markSuperRegs(Reserved, PPC::CTR8);
355 
356  markSuperRegs(Reserved, PPC::R1);
357  markSuperRegs(Reserved, PPC::LR);
358  markSuperRegs(Reserved, PPC::LR8);
359  markSuperRegs(Reserved, PPC::RM);
360 
361  markSuperRegs(Reserved, PPC::VRSAVE);
362 
363  // The SVR4 ABI reserves r2 and r13
364  if (Subtarget.isSVR4ABI()) {
365  // We only reserve r2 if we need to use the TOC pointer. If we have no
366  // explicit uses of the TOC pointer (meaning we're a leaf function with
367  // no constant-pool loads, etc.) and we have no potential uses inside an
368  // inline asm block, then we can treat r2 has an ordinary callee-saved
369  // register.
370  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
371  if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
372  markSuperRegs(Reserved, PPC::R2); // System-reserved register
373  markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
374  }
375 
376  // Always reserve r2 on AIX for now.
377  // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
378  if (Subtarget.isAIXABI())
379  markSuperRegs(Reserved, PPC::R2); // System-reserved register
380 
381  // On PPC64, r13 is the thread pointer. Never allocate this register.
382  if (TM.isPPC64())
383  markSuperRegs(Reserved, PPC::R13);
384 
385  if (TFI->needsFP(MF))
386  markSuperRegs(Reserved, PPC::R31);
387 
388  bool IsPositionIndependent = TM.isPositionIndependent();
389  if (hasBasePointer(MF)) {
390  if (Subtarget.is32BitELFABI() && IsPositionIndependent)
391  markSuperRegs(Reserved, PPC::R29);
392  else
393  markSuperRegs(Reserved, PPC::R30);
394  }
395 
396  if (Subtarget.is32BitELFABI() && IsPositionIndependent)
397  markSuperRegs(Reserved, PPC::R30);
398 
399  // Reserve Altivec registers when Altivec is unavailable.
400  if (!Subtarget.hasAltivec())
401  for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
402  IE = PPC::VRRCRegClass.end(); I != IE; ++I)
403  markSuperRegs(Reserved, *I);
404 
405  if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
406  !TM.getAIXExtendedAltivecABI()) {
407  // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved
408  // and cannot be used.
409  for (auto Reg : CSR_Altivec_SaveList) {
410  if (Reg == 0)
411  break;
412  markSuperRegs(Reserved, Reg);
413  for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) {
414  Reserved.set(*AS);
415  }
416  }
417  }
418 
419  assert(checkAllSuperRegsMarked(Reserved));
420  return Reserved;
421 }
422 
424  MCRegister PhysReg) const {
425  // We cannot use getReservedRegs() to find the registers that are not asm
426  // clobberable because there are some reserved registers which can be
427  // clobbered by inline asm. For example, when LR is clobbered, the register is
428  // saved and restored. We will hardcode the registers that are not asm
429  // cloberable in this function.
430 
431  // The stack pointer (R1/X1) is not clobberable by inline asm
432  return PhysReg != PPC::R1 && PhysReg != PPC::X1;
433 }
434 
436  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
437  const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo();
438  const MachineFrameInfo &MFI = MF.getFrameInfo();
439  const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
440 
441  LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
442  << ".\n");
443  // If the callee saved info is invalid we have to default to true for safety.
444  if (!MFI.isCalleeSavedInfoValid()) {
445  LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n");
446  return true;
447  }
448 
449  // We will require the use of X-Forms because the frame is larger than what
450  // can be represented in signed 16 bits that fit in the immediate of a D-Form.
451  // If we need an X-Form then we need a register to store the address offset.
452  unsigned FrameSize = MFI.getStackSize();
453  // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
454  if (FrameSize & ~0x7FFF) {
455  LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n");
456  return true;
457  }
458 
459  // The callee saved info is valid so it can be traversed.
460  // Checking for registers that need saving that do not have load or store
461  // forms where the address offset is an immediate.
462  for (unsigned i = 0; i < Info.size(); i++) {
463  // If the spill is to a register no scavenging is required.
464  if (Info[i].isSpilledToReg())
465  continue;
466 
467  int FrIdx = Info[i].getFrameIdx();
468  Register Reg = Info[i].getReg();
469 
470  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
471  unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);
472  if (!MFI.isFixedObjectIndex(FrIdx)) {
473  // This is not a fixed object. If it requires alignment then we may still
474  // need to use the XForm.
475  if (offsetMinAlignForOpcode(Opcode) > 1) {
476  LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
477  << " for register " << printReg(Reg, this) << ".\n");
478  LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires "
479  << "alignment.\n");
480  return true;
481  }
482  }
483 
484  // This is eiher:
485  // 1) A fixed frame index object which we know are aligned so
486  // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
487  // need to consider the alignment here.
488  // 2) A not fixed object but in that case we now know that the min required
489  // alignment is no more than 1 based on the previous check.
490  if (InstrInfo->isXFormMemOp(Opcode)) {
491  LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
492  << " for register " << printReg(Reg, this) << ".\n");
493  LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n");
494  return true;
495  }
496 
497  // This is a spill/restore of a quadword.
498  if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) {
499  LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
500  << " for register " << printReg(Reg, this) << ".\n");
501  LLVM_DEBUG(dbgs() << "TRUE - Memory operand is a quadword.\n");
502  return true;
503  }
504  }
505  LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n");
506  return false;
507 }
508 
510  const MachineFunction &MF) const {
511  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
512  // Do not use virtual base registers when ROP protection is turned on.
513  // Virtual base registers break the layout of the local variable space and may
514  // push the ROP Hash location past the 512 byte range of the ROP store
515  // instruction.
516  return !Subtarget.hasROPProtect();
517 }
518 
520  const MachineFunction &MF) const {
522  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
523  const MachineFrameInfo &MFI = MF.getFrameInfo();
524 
525  if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
526  return false;
527  if (PhysReg == Subtarget.getTOCPointerRegister())
528  // X2/R2 is guaranteed to be preserved within a function if it is reserved.
529  // The reason it's reserved is that it's the TOC pointer (and the function
530  // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
531  // with no TOC access), we can't claim that it is preserved.
532  return (getReservedRegs(MF).test(PhysReg));
533  if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
534  !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
535  // The value of the stack pointer does not change within a function after
536  // the prologue and before the epilogue if there are no dynamic allocations
537  // and no inline asm which clobbers X1/R1.
538  return true;
539  return false;
540 }
541 
543  ArrayRef<MCPhysReg> Order,
545  const MachineFunction &MF,
546  const VirtRegMap *VRM,
547  const LiveRegMatrix *Matrix) const {
548  const MachineRegisterInfo *MRI = &MF.getRegInfo();
549 
550  // Call the base implementation first to set any hints based on the usual
551  // heuristics and decide what the return value should be. We want to return
552  // the same value returned by the base implementation. If the base
553  // implementation decides to return true and force the allocation then we
554  // will leave it as such. On the other hand if the base implementation
555  // decides to return false the following code will not force the allocation
556  // as we are just looking to provide a hint.
557  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
558  VirtReg, Order, Hints, MF, VRM, Matrix);
559  // We are interested in instructions that copy values to ACC/UACC.
560  // The copy into UACC will be simply a COPY to a subreg so we
561  // want to allocate the corresponding physical subreg for the source.
562  // The copy into ACC will be a BUILD_UACC so we want to allocate
563  // the same number UACC for the source.
564  for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
565  const MachineOperand *ResultOp = nullptr;
566  Register ResultReg;
567  switch (Use.getOpcode()) {
568  case TargetOpcode::COPY: {
569  ResultOp = &Use.getOperand(0);
570  ResultReg = ResultOp->getReg();
571  if (Register::isVirtualRegister(ResultReg) &&
572  MRI->getRegClass(ResultReg)->contains(PPC::UACC0) &&
573  VRM->hasPhys(ResultReg)) {
574  Register UACCPhys = VRM->getPhys(ResultReg);
575  Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
576  // Ensure that the hint is a VSRp register.
577  if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
578  Hints.push_back(HintReg);
579  }
580  break;
581  }
582  case PPC::BUILD_UACC: {
583  ResultOp = &Use.getOperand(0);
584  ResultReg = ResultOp->getReg();
585  if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) &&
586  VRM->hasPhys(ResultReg)) {
587  Register ACCPhys = VRM->getPhys(ResultReg);
588  assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
589  "Expecting an ACC register for BUILD_UACC.");
590  Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
591  Hints.push_back(HintReg);
592  }
593  break;
594  }
595  }
596  }
597  return BaseImplRetVal;
598 }
599 
601  MachineFunction &MF) const {
602  const PPCFrameLowering *TFI = getFrameLowering(MF);
603  const unsigned DefaultSafety = 1;
604 
605  switch (RC->getID()) {
606  default:
607  return 0;
608  case PPC::G8RC_NOX0RegClassID:
609  case PPC::GPRC_NOR0RegClassID:
610  case PPC::SPERCRegClassID:
611  case PPC::G8RCRegClassID:
612  case PPC::GPRCRegClassID: {
613  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
614  return 32 - FP - DefaultSafety;
615  }
616  case PPC::F4RCRegClassID:
617  case PPC::F8RCRegClassID:
618  case PPC::VSLRCRegClassID:
619  return 32 - DefaultSafety;
620  case PPC::VFRCRegClassID:
621  case PPC::VRRCRegClassID: {
622  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
623  // Vector registers VR20-VR31 are reserved and cannot be used in the default
624  // Altivec ABI on AIX.
625  if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
626  return 20 - DefaultSafety;
627  }
628  return 32 - DefaultSafety;
629  case PPC::VSFRCRegClassID:
630  case PPC::VSSRCRegClassID:
631  case PPC::VSRCRegClassID: {
632  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
633  if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
634  // Vector registers VR20-VR31 are reserved and cannot be used in the
635  // default Altivec ABI on AIX.
636  return 52 - DefaultSafety;
637  }
638  return 64 - DefaultSafety;
639  case PPC::CRRCRegClassID:
640  return 8 - DefaultSafety;
641  }
642 }
643 
644 const TargetRegisterClass *
646  const MachineFunction &MF) const {
647  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
648  const auto *DefaultSuperclass =
650  if (Subtarget.hasVSX()) {
651  // With VSX, we can inflate various sub-register classes to the full VSX
652  // register set.
653 
654  // For Power9 we allow the user to enable GPR to vector spills.
655  // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
656  // support to spill GPRC.
657  if (TM.isELFv2ABI() || Subtarget.isAIXABI()) {
658  if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
659  RC == &PPC::G8RCRegClass) {
660  InflateGP8RC++;
661  return &PPC::SPILLTOVSRRCRegClass;
662  }
663  if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
664  InflateGPRC++;
665  }
666 
667  for (const auto *I = RC->getSuperClasses(); *I; ++I) {
668  if (getRegSizeInBits(**I) != getRegSizeInBits(*RC))
669  continue;
670 
671  switch ((*I)->getID()) {
672  case PPC::VSSRCRegClassID:
673  return Subtarget.hasP8Vector() ? *I : DefaultSuperclass;
674  case PPC::VSFRCRegClassID:
675  case PPC::VSRCRegClassID:
676  return *I;
677  case PPC::VSRpRCRegClassID:
678  return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass;
679  case PPC::ACCRCRegClassID:
680  case PPC::UACCRCRegClassID:
681  return Subtarget.hasMMA() ? *I : DefaultSuperclass;
682  }
683  }
684  }
685 
686  return DefaultSuperclass;
687 }
688 
689 //===----------------------------------------------------------------------===//
690 // Stack Frame Processing methods
691 //===----------------------------------------------------------------------===//
692 
693 /// lowerDynamicAlloc - Generate the code for allocating an object in the
694 /// current frame. The sequence of code will be in the general form
695 ///
696 /// addi R0, SP, \#frameSize ; get the address of the previous frame
697 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
698 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
699 ///
701  // Get the instruction.
702  MachineInstr &MI = *II;
703  // Get the instruction's basic block.
704  MachineBasicBlock &MBB = *MI.getParent();
705  // Get the basic block's function.
706  MachineFunction &MF = *MBB.getParent();
707  // Get the frame info.
708  MachineFrameInfo &MFI = MF.getFrameInfo();
709  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
710  // Get the instruction info.
711  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
712  // Determine whether 64-bit pointers are used.
713  bool LP64 = TM.isPPC64();
714  DebugLoc dl = MI.getDebugLoc();
715 
716  // Get the maximum call stack size.
717  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
718  Align MaxAlign = MFI.getMaxAlign();
719  assert(isAligned(MaxAlign, maxCallFrameSize) &&
720  "Maximum call-frame size not sufficiently aligned");
721  (void)MaxAlign;
722 
723  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
724  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
725  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
726  bool KillNegSizeReg = MI.getOperand(1).isKill();
727  Register NegSizeReg = MI.getOperand(1).getReg();
728 
729  prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, Reg);
730  // Grow the stack and update the stack pointer link, then determine the
731  // address of new allocated space.
732  if (LP64) {
733  BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
735  .addReg(PPC::X1)
736  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
737  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
738  .addReg(PPC::X1)
739  .addImm(maxCallFrameSize);
740  } else {
741  BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
743  .addReg(PPC::R1)
744  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
745  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
746  .addReg(PPC::R1)
747  .addImm(maxCallFrameSize);
748  }
749 
750  // Discard the DYNALLOC instruction.
751  MBB.erase(II);
752 }
753 
754 /// To accomplish dynamic stack allocation, we have to calculate exact size
755 /// subtracted from the stack pointer according alignment information and get
756 /// previous frame pointer.
758  Register &NegSizeReg,
759  bool &KillNegSizeReg,
760  Register &FramePointer) const {
761  // Get the instruction.
762  MachineInstr &MI = *II;
763  // Get the instruction's basic block.
764  MachineBasicBlock &MBB = *MI.getParent();
765  // Get the basic block's function.
766  MachineFunction &MF = *MBB.getParent();
767  // Get the frame info.
768  MachineFrameInfo &MFI = MF.getFrameInfo();
769  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
770  // Get the instruction info.
771  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
772  // Determine whether 64-bit pointers are used.
773  bool LP64 = TM.isPPC64();
774  DebugLoc dl = MI.getDebugLoc();
775  // Get the total frame size.
776  unsigned FrameSize = MFI.getStackSize();
777 
778  // Get stack alignments.
779  const PPCFrameLowering *TFI = getFrameLowering(MF);
780  Align TargetAlign = TFI->getStackAlign();
781  Align MaxAlign = MFI.getMaxAlign();
782 
783  // Determine the previous frame's address. If FrameSize can't be
784  // represented as 16 bits or we need special alignment, then we load the
785  // previous frame's address from 0(SP). Why not do an addis of the hi?
786  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
787  // Constructing the constant and adding would take 3 instructions.
788  // Fortunately, a frame greater than 32K is rare.
789  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
790  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
791 
792  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
793  if (LP64)
794  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer)
795  .addReg(PPC::X31)
796  .addImm(FrameSize);
797  else
798  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer)
799  .addReg(PPC::R31)
800  .addImm(FrameSize);
801  } else if (LP64) {
802  BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer)
803  .addImm(0)
804  .addReg(PPC::X1);
805  } else {
806  BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer)
807  .addImm(0)
808  .addReg(PPC::R1);
809  }
810  // Determine the actual NegSizeReg according to alignment info.
811  if (LP64) {
812  if (MaxAlign > TargetAlign) {
813  unsigned UnalNegSizeReg = NegSizeReg;
814  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
815 
816  // Unfortunately, there is no andi, only andi., and we can't insert that
817  // here because we might clobber cr0 while it is live.
818  BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
819  .addImm(~(MaxAlign.value() - 1));
820 
821  unsigned NegSizeReg1 = NegSizeReg;
822  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
823  BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
824  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
825  .addReg(NegSizeReg1, RegState::Kill);
826  KillNegSizeReg = true;
827  }
828  } else {
829  if (MaxAlign > TargetAlign) {
830  unsigned UnalNegSizeReg = NegSizeReg;
831  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
832 
833  // Unfortunately, there is no andi, only andi., and we can't insert that
834  // here because we might clobber cr0 while it is live.
835  BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
836  .addImm(~(MaxAlign.value() - 1));
837 
838  unsigned NegSizeReg1 = NegSizeReg;
839  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
840  BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
841  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
842  .addReg(NegSizeReg1, RegState::Kill);
843  KillNegSizeReg = true;
844  }
845  }
846 }
847 
849  MachineBasicBlock::iterator II) const {
850  MachineInstr &MI = *II;
851  // Get the instruction's basic block.
852  MachineBasicBlock &MBB = *MI.getParent();
853  // Get the basic block's function.
854  MachineFunction &MF = *MBB.getParent();
855  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
856  // Get the instruction info.
857  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
858  // Determine whether 64-bit pointers are used.
859  bool LP64 = TM.isPPC64();
860  DebugLoc dl = MI.getDebugLoc();
861  Register FramePointer = MI.getOperand(0).getReg();
862  const Register ActualNegSizeReg = MI.getOperand(1).getReg();
863  bool KillNegSizeReg = MI.getOperand(2).isKill();
864  Register NegSizeReg = MI.getOperand(2).getReg();
865  const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR);
866  // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
867  if (FramePointer == NegSizeReg) {
868  assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
869  "NegSizeReg should be killed");
870  // FramePointer is clobbered earlier than the use of NegSizeReg in
871  // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
872  // misuse.
873  BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
874  .addReg(NegSizeReg)
875  .addReg(NegSizeReg);
876  NegSizeReg = ActualNegSizeReg;
877  KillNegSizeReg = false;
878  }
879  prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
880  // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
881  // TargetAlign.
882  if (NegSizeReg != ActualNegSizeReg)
883  BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
884  .addReg(NegSizeReg)
885  .addReg(NegSizeReg);
886  MBB.erase(II);
887 }
888 
890  MachineBasicBlock::iterator II) const {
891  // Get the instruction.
892  MachineInstr &MI = *II;
893  // Get the instruction's basic block.
894  MachineBasicBlock &MBB = *MI.getParent();
895  // Get the basic block's function.
896  MachineFunction &MF = *MBB.getParent();
897  // Get the frame info.
898  MachineFrameInfo &MFI = MF.getFrameInfo();
899  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
900  // Get the instruction info.
901  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
902 
903  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
904  bool is64Bit = TM.isPPC64();
905  DebugLoc dl = MI.getDebugLoc();
906  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
907  MI.getOperand(0).getReg())
908  .addImm(maxCallFrameSize);
909  MBB.erase(II);
910 }
911 
912 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
913 /// reserving a whole register (R0), we scrounge for one here. This generates
914 /// code like this:
915 ///
916 /// mfcr rA ; Move the conditional register into GPR rA.
917 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
918 /// stw rA, FI ; Store rA to the frame.
919 ///
921  unsigned FrameIndex) const {
922  // Get the instruction.
923  MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
924  // Get the instruction's basic block.
925  MachineBasicBlock &MBB = *MI.getParent();
926  MachineFunction &MF = *MBB.getParent();
927  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
928  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
929  DebugLoc dl = MI.getDebugLoc();
930 
931  bool LP64 = TM.isPPC64();
932  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
933  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
934 
935  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
936  Register SrcReg = MI.getOperand(0).getReg();
937 
938  // We need to store the CR in the low 4-bits of the saved value. First, issue
939  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
940  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
941  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
942 
943  // If the saved register wasn't CR0, shift the bits left so that they are in
944  // CR0's slot.
945  if (SrcReg != PPC::CR0) {
946  Register Reg1 = Reg;
947  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
948 
949  // rlwinm rA, rA, ShiftBits, 0, 31.
950  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
951  .addReg(Reg1, RegState::Kill)
952  .addImm(getEncodingValue(SrcReg) * 4)
953  .addImm(0)
954  .addImm(31);
955  }
956 
957  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
959  FrameIndex);
960 
961  // Discard the pseudo instruction.
962  MBB.erase(II);
963 }
964 
966  unsigned FrameIndex) const {
967  // Get the instruction.
968  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
969  // Get the instruction's basic block.
970  MachineBasicBlock &MBB = *MI.getParent();
971  MachineFunction &MF = *MBB.getParent();
972  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
973  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
974  DebugLoc dl = MI.getDebugLoc();
975 
976  bool LP64 = TM.isPPC64();
977  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
978  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
979 
980  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
981  Register DestReg = MI.getOperand(0).getReg();
982  assert(MI.definesRegister(DestReg) &&
983  "RESTORE_CR does not define its destination");
984 
985  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
986  Reg), FrameIndex);
987 
988  // If the reloaded register isn't CR0, shift the bits right so that they are
989  // in the right CR's slot.
990  if (DestReg != PPC::CR0) {
991  Register Reg1 = Reg;
992  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
993 
994  unsigned ShiftBits = getEncodingValue(DestReg)*4;
995  // rlwinm r11, r11, 32-ShiftBits, 0, 31.
996  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
997  .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
998  .addImm(31);
999  }
1000 
1001  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
1003 
1004  // Discard the pseudo instruction.
1005  MBB.erase(II);
1006 }
1007 
1009  unsigned FrameIndex) const {
1010  // Get the instruction.
1011  MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
1012  // Get the instruction's basic block.
1013  MachineBasicBlock &MBB = *MI.getParent();
1014  MachineFunction &MF = *MBB.getParent();
1015  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1016  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1017  const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
1018  DebugLoc dl = MI.getDebugLoc();
1019 
1020  bool LP64 = TM.isPPC64();
1021  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1022  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1023 
1024  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1025  Register SrcReg = MI.getOperand(0).getReg();
1026 
1027  // Search up the BB to find the definition of the CR bit.
1030  ++Ins;
1031  unsigned CRBitSpillDistance = 0;
1032  bool SeenUse = false;
1033  for (; Ins != Rend; ++Ins) {
1034  // Definition found.
1035  if (Ins->modifiesRegister(SrcReg, TRI))
1036  break;
1037  // Use found.
1038  if (Ins->readsRegister(SrcReg, TRI))
1039  SeenUse = true;
1040  // Unable to find CR bit definition within maximum search distance.
1041  if (CRBitSpillDistance == MaxCRBitSpillDist) {
1042  Ins = MI;
1043  break;
1044  }
1045  // Skip debug instructions when counting CR bit spill distance.
1046  if (!Ins->isDebugInstr())
1047  CRBitSpillDistance++;
1048  }
1049 
1050  // Unable to find the definition of the CR bit in the MBB.
1051  if (Ins == MBB.rend())
1052  Ins = MI;
1053 
1054  bool SpillsKnownBit = false;
1055  // There is no need to extract the CR bit if its value is already known.
1056  switch (Ins->getOpcode()) {
1057  case PPC::CRUNSET:
1058  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
1059  .addImm(0);
1060  SpillsKnownBit = true;
1061  break;
1062  case PPC::CRSET:
1063  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
1064  .addImm(-32768);
1065  SpillsKnownBit = true;
1066  break;
1067  default:
1068  // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
1069  // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
1070  // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
1071  // register), and SETNBC will set this.
1072  if (Subtarget.isISA3_1()) {
1073  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg)
1074  .addReg(SrcReg, RegState::Undef);
1075  break;
1076  }
1077 
1078  // On Power9, we can use SETB to extract the LT bit. This only works for
1079  // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
1080  // of the bit we care about (32-bit sign bit) will be set to the value of
1081  // the LT bit (regardless of the other bits in the CR field).
1082  if (Subtarget.isISA3_0()) {
1083  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
1084  SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
1085  SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
1086  SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
1087  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
1089  break;
1090  }
1091  }
1092 
1093  // We need to move the CR field that contains the CR bit we are spilling.
1094  // The super register may not be explicitly defined (i.e. it can be defined
1095  // by a CR-logical that only defines the subreg) so we state that the CR
1096  // field is undef. Also, in order to preserve the kill flag on the CR bit,
1097  // we add it as an implicit use.
1098  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
1100  .addReg(SrcReg,
1101  RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
1102 
1103  // If the saved register wasn't CR0LT, shift the bits left so that the bit
1104  // to store is the first one. Mask all but that bit.
1105  Register Reg1 = Reg;
1106  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1107 
1108  // rlwinm rA, rA, ShiftBits, 0, 0.
1109  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
1110  .addReg(Reg1, RegState::Kill)
1111  .addImm(getEncodingValue(SrcReg))
1112  .addImm(0).addImm(0);
1113  }
1114  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
1116  FrameIndex);
1117 
1118  bool KillsCRBit = MI.killsRegister(SrcReg, TRI);
1119  // Discard the pseudo instruction.
1120  MBB.erase(II);
1121  if (SpillsKnownBit && KillsCRBit && !SeenUse) {
1122  Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
1123  Ins->removeOperand(0);
1124  }
1125 }
1126 
1128  unsigned FrameIndex) const {
1129  // Get the instruction.
1130  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
1131  // Get the instruction's basic block.
1132  MachineBasicBlock &MBB = *MI.getParent();
1133  MachineFunction &MF = *MBB.getParent();
1134  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1135  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1136  DebugLoc dl = MI.getDebugLoc();
1137 
1138  bool LP64 = TM.isPPC64();
1139  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1140  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1141 
1142  Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1143  Register DestReg = MI.getOperand(0).getReg();
1144  assert(MI.definesRegister(DestReg) &&
1145  "RESTORE_CRBIT does not define its destination");
1146 
1147  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
1148  Reg), FrameIndex);
1149 
1150  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
1151 
1152  Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1153  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
1154  .addReg(getCRFromCRBit(DestReg));
1155 
1156  unsigned ShiftBits = getEncodingValue(DestReg);
1157  // rlwimi r11, r10, 32-ShiftBits, ..., ...
1158  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
1159  .addReg(RegO, RegState::Kill)
1161  .addImm(ShiftBits ? 32 - ShiftBits : 0)
1162  .addImm(ShiftBits)
1163  .addImm(ShiftBits);
1164 
1165  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
1166  getCRFromCRBit(DestReg))
1167  .addReg(RegO, RegState::Kill)
1168  // Make sure we have a use dependency all the way through this
1169  // sequence of instructions. We can't have the other bits in the CR
1170  // modified in between the mfocrf and the mtocrf.
1172 
1173  // Discard the pseudo instruction.
1174  MBB.erase(II);
1175 }
1176 
1178  MCRegister DestReg, MCRegister SrcReg) {
1179 #ifdef NDEBUG
1180  return;
1181 #else
1182  if (ReportAccMoves) {
1183  std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc";
1184  std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc";
1185  dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n";
1186  MBB.dump();
1187  }
1188 #endif
1189 }
1190 
1191 static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
1192  bool IsRestore) {
1193 #ifdef NDEBUG
1194  return;
1195 #else
1196  if (ReportAccMoves) {
1197  dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register "
1198  << (IsRestore ? "restore" : "spill") << ":\n";
1199  MBB.dump();
1200  }
1201 #endif
1202 }
1203 
1206  const TargetInstrInfo &TII, Register SrcReg,
1207  unsigned FrameIndex, bool IsLittleEndian,
1208  bool IsKilled, bool TwoPairs) {
1209  unsigned Offset = 0;
1210  if (TwoPairs)
1211  Offset = IsLittleEndian ? 48 : 0;
1212  else
1213  Offset = IsLittleEndian ? 16 : 0;
1214  Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2
1215  : PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1216  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1217  .addReg(Reg, getKillRegState(IsKilled)),
1218  FrameIndex, Offset);
1219  Offset += IsLittleEndian ? -16 : 16;
1220  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1221  .addReg(Reg + 1, getKillRegState(IsKilled)),
1222  FrameIndex, Offset);
1223  if (TwoPairs) {
1224  Offset += IsLittleEndian ? -16 : 16;
1225  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1226  .addReg(Reg + 2, getKillRegState(IsKilled)),
1227  FrameIndex, Offset);
1228  Offset += IsLittleEndian ? -16 : 16;
1229  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1230  .addReg(Reg + 3, getKillRegState(IsKilled)),
1231  FrameIndex, Offset);
1232  }
1233 }
1234 
1235 /// Remove any STXVP[X] instructions and split them out into a pair of
1236 /// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
1237 /// the command line.
1239  unsigned FrameIndex) const {
1241  "Expecting to do this only if paired vector stores are disabled.");
1242  MachineInstr &MI = *II; // STXVP <SrcReg>, <offset>
1243  MachineBasicBlock &MBB = *MI.getParent();
1244  MachineFunction &MF = *MBB.getParent();
1245  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1246  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1247  DebugLoc DL = MI.getDebugLoc();
1248  Register SrcReg = MI.getOperand(0).getReg();
1249  bool IsLittleEndian = Subtarget.isLittleEndian();
1250  bool IsKilled = MI.getOperand(0).isKill();
1251  spillRegPairs(MBB, II, DL, TII, SrcReg, FrameIndex, IsLittleEndian, IsKilled,
1252  /* TwoPairs */ false);
1253  // Discard the original instruction.
1254  MBB.erase(II);
1255 }
1256 
1257 /// lowerACCSpilling - Generate the code for spilling the accumulator register.
1258 /// Similarly to other spills/reloads that use pseudo-ops, we do not actually
1259 /// eliminate the FrameIndex here nor compute the stack offset. We simply
1260 /// create a real instruction with an FI and rely on eliminateFrameIndex to
1261 /// handle the FI elimination.
1263  unsigned FrameIndex) const {
1264  MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset>
1265  MachineBasicBlock &MBB = *MI.getParent();
1266  MachineFunction &MF = *MBB.getParent();
1267  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1268  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1269  DebugLoc DL = MI.getDebugLoc();
1270  Register SrcReg = MI.getOperand(0).getReg();
1271  bool IsKilled = MI.getOperand(0).isKill();
1272 
1273  bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1274  Register Reg =
1275  PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1276  bool IsLittleEndian = Subtarget.isLittleEndian();
1277 
1278  emitAccSpillRestoreInfo(MBB, IsPrimed, false);
1279 
1280  // De-prime the register being spilled, create two stores for the pair
1281  // subregisters accounting for endianness and then re-prime the register if
1282  // it isn't killed. This uses the Offset parameter to addFrameReference() to
1283  // adjust the offset of the store that is within the 64-byte stack slot.
1284  if (IsPrimed)
1285  BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1287  spillRegPairs(MBB, II, DL, TII, Reg, FrameIndex, IsLittleEndian, IsKilled,
1288  /* TwoPairs */ true);
1289  else {
1290  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1291  .addReg(Reg, getKillRegState(IsKilled)),
1292  FrameIndex, IsLittleEndian ? 32 : 0);
1293  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1294  .addReg(Reg + 1, getKillRegState(IsKilled)),
1295  FrameIndex, IsLittleEndian ? 0 : 32);
1296  }
1297  if (IsPrimed && !IsKilled)
1298  BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
1299 
1300  // Discard the pseudo instruction.
1301  MBB.erase(II);
1302 }
1303 
1304 /// lowerACCRestore - Generate the code to restore the accumulator register.
1306  unsigned FrameIndex) const {
1307  MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset>
1308  MachineBasicBlock &MBB = *MI.getParent();
1309  MachineFunction &MF = *MBB.getParent();
1310  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1311  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1312  DebugLoc DL = MI.getDebugLoc();
1313 
1314  Register DestReg = MI.getOperand(0).getReg();
1315  assert(MI.definesRegister(DestReg) &&
1316  "RESTORE_ACC does not define its destination");
1317 
1318  bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg);
1319  Register Reg =
1320  PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1321  bool IsLittleEndian = Subtarget.isLittleEndian();
1322 
1323  emitAccSpillRestoreInfo(MBB, IsPrimed, true);
1324 
1325  // Create two loads for the pair subregisters accounting for endianness and
1326  // then prime the accumulator register being restored.
1327  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg),
1328  FrameIndex, IsLittleEndian ? 32 : 0);
1329  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1),
1330  FrameIndex, IsLittleEndian ? 0 : 32);
1331  if (IsPrimed)
1332  BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg);
1333 
1334  // Discard the pseudo instruction.
1335  MBB.erase(II);
1336 }
1337 
1338 /// lowerQuadwordSpilling - Generate code to spill paired general register.
1340  unsigned FrameIndex) const {
1341  MachineInstr &MI = *II;
1342  MachineBasicBlock &MBB = *MI.getParent();
1343  MachineFunction &MF = *MBB.getParent();
1344  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1345  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1346  DebugLoc DL = MI.getDebugLoc();
1347 
1348  Register SrcReg = MI.getOperand(0).getReg();
1349  bool IsKilled = MI.getOperand(0).isKill();
1350 
1351  Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2;
1352  bool IsLittleEndian = Subtarget.isLittleEndian();
1353 
1354  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1355  .addReg(Reg, getKillRegState(IsKilled)),
1356  FrameIndex, IsLittleEndian ? 8 : 0);
1357  addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1358  .addReg(Reg + 1, getKillRegState(IsKilled)),
1359  FrameIndex, IsLittleEndian ? 0 : 8);
1360 
1361  // Discard the pseudo instruction.
1362  MBB.erase(II);
1363 }
1364 
1365 /// lowerQuadwordRestore - Generate code to restore paired general register.
1367  unsigned FrameIndex) const {
1368  MachineInstr &MI = *II;
1369  MachineBasicBlock &MBB = *MI.getParent();
1370  MachineFunction &MF = *MBB.getParent();
1371  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1372  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1373  DebugLoc DL = MI.getDebugLoc();
1374 
1375  Register DestReg = MI.getOperand(0).getReg();
1376  assert(MI.definesRegister(DestReg) &&
1377  "RESTORE_QUADWORD does not define its destination");
1378 
1379  Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2;
1380  bool IsLittleEndian = Subtarget.isLittleEndian();
1381 
1383  IsLittleEndian ? 8 : 0);
1385  IsLittleEndian ? 0 : 8);
1386 
1387  // Discard the pseudo instruction.
1388  MBB.erase(II);
1389 }
1390 
1392  Register Reg, int &FrameIdx) const {
1393  // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
1394  // prevent allocating an additional frame slot.
1395  // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
1396  // for 32-bit AIX the CR save area is in the linkage area at SP+4.
1397  // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
1398  // valid.
1399  // For 32-bit ELF, we have previously created the stack slot if needed, so
1400  // return its FrameIdx.
1401  if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
1402  FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
1403  return true;
1404  }
1405  return false;
1406 }
1407 
1408 // If the offset must be a multiple of some value, return what that value is.
1409 static unsigned offsetMinAlignForOpcode(unsigned OpC) {
1410  switch (OpC) {
1411  default:
1412  return 1;
1413  case PPC::LWA:
1414  case PPC::LWA_32:
1415  case PPC::LD:
1416  case PPC::LDU:
1417  case PPC::STD:
1418  case PPC::STDU:
1419  case PPC::DFLOADf32:
1420  case PPC::DFLOADf64:
1421  case PPC::DFSTOREf32:
1422  case PPC::DFSTOREf64:
1423  case PPC::LXSD:
1424  case PPC::LXSSP:
1425  case PPC::STXSD:
1426  case PPC::STXSSP:
1427  case PPC::STQ:
1428  return 4;
1429  case PPC::EVLDD:
1430  case PPC::EVSTDD:
1431  return 8;
1432  case PPC::LXV:
1433  case PPC::STXV:
1434  case PPC::LQ:
1435  case PPC::LXVP:
1436  case PPC::STXVP:
1437  return 16;
1438  }
1439 }
1440 
1441 // If the offset must be a multiple of some value, return what that value is.
1442 static unsigned offsetMinAlign(const MachineInstr &MI) {
1443  unsigned OpC = MI.getOpcode();
1444  return offsetMinAlignForOpcode(OpC);
1445 }
1446 
1447 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
1448 static unsigned getOffsetONFromFION(const MachineInstr &MI,
1449  unsigned FIOperandNum) {
1450  // Take into account whether it's an add or mem instruction
1451  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
1452  if (MI.isInlineAsm())
1453  OffsetOperandNo = FIOperandNum - 1;
1454  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
1455  MI.getOpcode() == TargetOpcode::PATCHPOINT)
1456  OffsetOperandNo = FIOperandNum + 1;
1457 
1458  return OffsetOperandNo;
1459 }
1460 
1461 void
1463  int SPAdj, unsigned FIOperandNum,
1464  RegScavenger *RS) const {
1465  assert(SPAdj == 0 && "Unexpected");
1466 
1467  // Get the instruction.
1468  MachineInstr &MI = *II;
1469  // Get the instruction's basic block.
1470  MachineBasicBlock &MBB = *MI.getParent();
1471  // Get the basic block's function.
1472  MachineFunction &MF = *MBB.getParent();
1473  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1474  // Get the instruction info.
1475  const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1476  // Get the frame info.
1477  MachineFrameInfo &MFI = MF.getFrameInfo();
1478  DebugLoc dl = MI.getDebugLoc();
1479 
1480  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1481 
1482  // Get the frame index.
1483  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1484 
1485  // Get the frame pointer save index. Users of this index are primarily
1486  // DYNALLOC instructions.
1488  int FPSI = FI->getFramePointerSaveIndex();
1489  // Get the instruction opcode.
1490  unsigned OpC = MI.getOpcode();
1491 
1492  if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
1494  return;
1495  }
1496 
1497  // Special case for dynamic alloca.
1498  if (FPSI && FrameIndex == FPSI &&
1499  (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
1500  lowerDynamicAlloc(II);
1501  return;
1502  }
1503 
1504  if (FPSI && FrameIndex == FPSI &&
1505  (OpC == PPC::PREPARE_PROBED_ALLOCA_64 ||
1506  OpC == PPC::PREPARE_PROBED_ALLOCA_32 ||
1507  OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 ||
1508  OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) {
1510  return;
1511  }
1512 
1513  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1514  if (OpC == PPC::SPILL_CR) {
1516  return;
1517  } else if (OpC == PPC::RESTORE_CR) {
1519  return;
1520  } else if (OpC == PPC::SPILL_CRBIT) {
1522  return;
1523  } else if (OpC == PPC::RESTORE_CRBIT) {
1525  return;
1526  } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) {
1528  return;
1529  } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) {
1531  return;
1532  } else if (OpC == PPC::STXVP && DisableAutoPairedVecSt) {
1534  return;
1535  } else if (OpC == PPC::SPILL_QUADWORD) {
1537  return;
1538  } else if (OpC == PPC::RESTORE_QUADWORD) {
1540  return;
1541  }
1542 
1543  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1544  MI.getOperand(FIOperandNum).ChangeToRegister(
1545  FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
1546 
1547  // If the instruction is not present in ImmToIdxMap, then it has no immediate
1548  // form (and must be r+r).
1549  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1550  OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
1551 
1552  // Now add the frame object offset to the offset from r1.
1553  int64_t Offset = MFI.getObjectOffset(FrameIndex);
1554  Offset += MI.getOperand(OffsetOperandNo).getImm();
1555 
1556  // If we're not using a Frame Pointer that has been set to the value of the
1557  // SP before having the stack size subtracted from it, then add the stack size
1558  // to Offset to get the correct offset.
1559  // Naked functions have stack size 0, although getStackSize may not reflect
1560  // that because we didn't call all the pieces that compute it for naked
1561  // functions.
1562  if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1563  if (!(hasBasePointer(MF) && FrameIndex < 0))
1564  Offset += MFI.getStackSize();
1565  }
1566 
1567  // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can
1568  // transform it to the prefixed version so we don't have to use the XForm.
1569  if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
1570  (!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1571  Subtarget.hasPrefixInstrs()) {
1572  unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
1573  MI.setDesc(TII.get(NewOpc));
1574  OpC = NewOpc;
1575  }
1576 
1577  // If we can, encode the offset directly into the instruction. If this is a
1578  // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
1579  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1580  // clear can be encoded. This is extremely uncommon, because normally you
1581  // only "std" to a stack slot that is at least 4-byte aligned, but it can
1582  // happen in invalid code.
1583  assert(OpC != PPC::DBG_VALUE &&
1584  "This should be handled in a target-independent way");
1585  // FIXME: This should be factored out to a separate function as prefixed
1586  // instructions add a number of opcodes for which we can use 34-bit imm.
1587  bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1588  isUInt<8>(Offset) :
1589  isInt<16>(Offset);
1590  if (TII.isPrefixed(MI.getOpcode()))
1591  OffsetFitsMnemonic = isInt<34>(Offset);
1592  if (!noImmForm && ((OffsetFitsMnemonic &&
1593  ((Offset % offsetMinAlign(MI)) == 0)) ||
1594  OpC == TargetOpcode::STACKMAP ||
1595  OpC == TargetOpcode::PATCHPOINT)) {
1596  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1597  return;
1598  }
1599 
1600  // The offset doesn't fit into a single register, scavenge one to build the
1601  // offset in.
1602 
1603  bool is64Bit = TM.isPPC64();
1604  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1605  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1606  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1607  Register SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1608  SReg = MF.getRegInfo().createVirtualRegister(RC);
1609  unsigned NewOpcode = 0u;
1610 
1611  // Insert a set of rA with the full offset value before the ld, st, or add
1612  if (isInt<16>(Offset))
1613  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1614  .addImm(Offset);
1615  else if (isInt<32>(Offset)) {
1616  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1617  .addImm(Offset >> 16);
1618  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1619  .addReg(SRegHi, RegState::Kill)
1620  .addImm(Offset);
1621  } else {
1622  assert(is64Bit && "Huge stack is only supported on PPC64");
1623  TII.materializeImmPostRA(MBB, II, dl, SReg, Offset);
1624  }
1625 
1626  // Convert into indexed form of the instruction:
1627  //
1628  // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1629  // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1630  unsigned OperandBase;
1631 
1632  if (noImmForm)
1633  OperandBase = 1;
1634  else if (OpC != TargetOpcode::INLINEASM &&
1635  OpC != TargetOpcode::INLINEASM_BR) {
1636  assert(ImmToIdxMap.count(OpC) &&
1637  "No indexed form of load or store available!");
1638  NewOpcode = ImmToIdxMap.find(OpC)->second;
1639  MI.setDesc(TII.get(NewOpcode));
1640  OperandBase = 1;
1641  } else {
1642  OperandBase = OffsetOperandNo;
1643  }
1644 
1645  Register StackReg = MI.getOperand(FIOperandNum).getReg();
1646  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1647  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1648 
1649  // Since these are not real X-Form instructions, we must
1650  // add the registers and access 0(NewReg) rather than
1651  // emitting the X-Form pseudo.
1652  if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) {
1653  assert(is64Bit && "Quadword loads/stores only supported in 64-bit mode");
1654  Register NewReg = MF.getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
1655  BuildMI(MBB, II, dl, TII.get(PPC::ADD8), NewReg)
1656  .addReg(SReg, RegState::Kill)
1657  .addReg(StackReg);
1658  MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ));
1659  MI.getOperand(OperandBase + 1).ChangeToRegister(NewReg, false);
1660  MI.getOperand(OperandBase).ChangeToImmediate(0);
1661  }
1662 }
1663 
1665  const PPCFrameLowering *TFI = getFrameLowering(MF);
1666 
1667  if (!TM.isPPC64())
1668  return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1669  else
1670  return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1671 }
1672 
1674  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1675  if (!hasBasePointer(MF))
1676  return getFrameRegister(MF);
1677 
1678  if (TM.isPPC64())
1679  return PPC::X30;
1680 
1681  if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1682  return PPC::R29;
1683 
1684  return PPC::R30;
1685 }
1686 
1688  if (!EnableBasePointer)
1689  return false;
1690  if (AlwaysBasePointer)
1691  return true;
1692 
1693  // If we need to realign the stack, then the stack pointer can no longer
1694  // serve as an offset into the caller's stack space. As a result, we need a
1695  // base pointer.
1696  return hasStackRealignment(MF);
1697 }
1698 
1699 /// Returns true if the instruction's frame index
1700 /// reference would be better served by a base register other than FP
1701 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1702 /// references it should create new base registers for.
1703 bool PPCRegisterInfo::
1704 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1705  assert(Offset < 0 && "Local offset must be negative");
1706 
1707  // It's the load/store FI references that cause issues, as it can be difficult
1708  // to materialize the offset if it won't fit in the literal field. Estimate
1709  // based on the size of the local frame and some conservative assumptions
1710  // about the rest of the stack frame (note, this is pre-regalloc, so
1711  // we don't know everything for certain yet) whether this offset is likely
1712  // to be out of range of the immediate. Return true if so.
1713 
1714  // We only generate virtual base registers for loads and stores that have
1715  // an r+i form. Return false for everything else.
1716  unsigned OpC = MI->getOpcode();
1717  if (!ImmToIdxMap.count(OpC))
1718  return false;
1719 
1720  // Don't generate a new virtual base register just to add zero to it.
1721  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1722  MI->getOperand(2).getImm() == 0)
1723  return false;
1724 
1725  MachineBasicBlock &MBB = *MI->getParent();
1726  MachineFunction &MF = *MBB.getParent();
1727  const PPCFrameLowering *TFI = getFrameLowering(MF);
1728  unsigned StackEst = TFI->determineFrameLayout(MF, true);
1729 
1730  // If we likely don't need a stack frame, then we probably don't need a
1731  // virtual base register either.
1732  if (!StackEst)
1733  return false;
1734 
1735  // Estimate an offset from the stack pointer.
1736  // The incoming offset is relating to the SP at the start of the function,
1737  // but when we access the local it'll be relative to the SP after local
1738  // allocation, so adjust our SP-relative offset by that allocation size.
1739  Offset += StackEst;
1740 
1741  // The frame pointer will point to the end of the stack, so estimate the
1742  // offset as the difference between the object offset and the FP location.
1743  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1744 }
1745 
1746 /// Insert defining instruction(s) for BaseReg to
1747 /// be a pointer to FrameIdx at the beginning of the basic block.
1749  int FrameIdx,
1750  int64_t Offset) const {
1751  unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1752 
1754  DebugLoc DL; // Defaults to "unknown"
1755  if (Ins != MBB->end())
1756  DL = Ins->getDebugLoc();
1757 
1758  const MachineFunction &MF = *MBB->getParent();
1759  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1760  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1761  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1763  const TargetRegisterClass *RC = getPointerRegClass(MF);
1764  Register BaseReg = MRI.createVirtualRegister(RC);
1765  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1766 
1767  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1768  .addFrameIndex(FrameIdx).addImm(Offset);
1769 
1770  return BaseReg;
1771 }
1772 
1774  int64_t Offset) const {
1775  unsigned FIOperandNum = 0;
1776  while (!MI.getOperand(FIOperandNum).isFI()) {
1777  ++FIOperandNum;
1778  assert(FIOperandNum < MI.getNumOperands() &&
1779  "Instr doesn't have FrameIndex operand!");
1780  }
1781 
1782  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1783  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1784  Offset += MI.getOperand(OffsetOperandNo).getImm();
1785  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1786 
1787  MachineBasicBlock &MBB = *MI.getParent();
1788  MachineFunction &MF = *MBB.getParent();
1789  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1790  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1791  const MCInstrDesc &MCID = MI.getDesc();
1793  MRI.constrainRegClass(BaseReg,
1794  TII.getRegClass(MCID, FIOperandNum, this, MF));
1795 }
1796 
1798  Register BaseReg,
1799  int64_t Offset) const {
1800  unsigned FIOperandNum = 0;
1801  while (!MI->getOperand(FIOperandNum).isFI()) {
1802  ++FIOperandNum;
1803  assert(FIOperandNum < MI->getNumOperands() &&
1804  "Instr doesn't have FrameIndex operand!");
1805  }
1806 
1807  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1808  Offset += MI->getOperand(OffsetOperandNo).getImm();
1809 
1810  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1811  MI->getOpcode() == TargetOpcode::STACKMAP ||
1812  MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1813  (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1814 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:788
llvm::MachineFunction::hasInlineAsm
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
Definition: MachineFunction.h:729
llvm::PPCRegisterInfo::lowerDynamicAlloc
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
Definition: PPCRegisterInfo.cpp:700
CmpMode::FP
@ FP
llvm::PPCRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
Definition: PPCRegisterInfo.cpp:169
llvm::getCRFromCRBit
static unsigned getCRFromCRBit(unsigned SrcReg)
Definition: PPCRegisterInfo.h:26
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:146
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::PPCSubtarget::getRegisterInfo
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:224
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::PPCRegisterInfo::lowerQuadwordRestore
void lowerQuadwordRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordRestore - Generate code to restore paired general register.
Definition: PPCRegisterInfo.cpp:1366
llvm::PPCFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: PPCFrameLowering.cpp:359
llvm::PPCRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:435
TargetFrameLowering.h
PPCRegisterInfo.h
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::PPCSubtarget::hasPrefixInstrs
bool hasPrefixInstrs() const
Definition: PPCSubtarget.h:288
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::PPCSubtarget::hasMMA
bool hasMMA() const
Definition: PPCSubtarget.h:290
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1018
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
PPCInstrBuilder.h
Statistic.h
llvm::PPCSubtarget::hasP8Vector
bool hasP8Vector() const
Definition: PPCSubtarget.h:282
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::PPCSubtarget::isLittleEndian
bool isLittleEndian() const
Definition: PPCSubtarget.h:262
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::PPCSubtarget::hasROPProtect
bool hasROPProtect() const
Definition: PPCSubtarget.h:291
llvm::PPCRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:645
llvm::PPCSubtarget::hasVSX
bool hasVSX() const
Definition: PPCSubtarget.h:280
llvm::PPCRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:1664
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::PPCSubtarget::hasP9Vector
bool hasP9Vector() const
Definition: PPCSubtarget.h:285
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::PPCFunctionInfo
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
Definition: PPCMachineFunctionInfo.h:24
llvm::PPCISD::DYNALLOC
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
Definition: PPCISelLowering.h:144
getOffsetONFromFION
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
Definition: PPCRegisterInfo.cpp:1448
llvm::PPCRegisterInfo::lowerOctWordSpilling
void lowerOctWordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Remove any STXVP[X] instructions and split them out into a pair of STXV[X] instructions if –disable-a...
Definition: PPCRegisterInfo.cpp:1238
STLExtras.h
llvm::PPCSubtarget::getStackPointerRegister
MCRegister getStackPointerRegister() const
Definition: PPCSubtarget.h:430
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::PPCSubtarget::is64BitELFABI
bool is64BitELFABI() const
Definition: PPCSubtarget.h:371
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MaxCRBitSpillDist
static cl::opt< unsigned > MaxCRBitSpillDist("ppc-max-crbit-spill-dist", cl::desc("Maximum search distance for definition of CR bit " "spill on ppc"), cl::Hidden, cl::init(100))
MachineRegisterInfo.h
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::MachineBasicBlock::dump
void dump() const
Definition: MachineBasicBlock.cpp:291
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::PPCRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Definition: PPCRegisterInfo.cpp:1748
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
PPCSubtarget.h
CommandLine.h
llvm::MachineRegisterInfo::reg_nodbg_instructions
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:362
R2
#define R2(n)
llvm::PPCRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: PPCRegisterInfo.cpp:1773
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
StackPtrConst
static cl::opt< bool > StackPtrConst("ppc-stack-ptr-caller-preserved", cl::desc("Consider R1 caller preserved so stack saves of " "caller preserved registers can be LICM candidates"), cl::init(true), cl::Hidden)
Constants.h
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCSubtarget::getTOCPointerRegister
MCRegister getTOCPointerRegister() const
Definition: PPCSubtarget.h:424
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::PPCFrameLowering
Definition: PPCFrameLowering.h:22
AlwaysBasePointer
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::PPCSubtarget::isISA3_1
bool isISA3_1() const
Definition: PPCSubtarget.h:339
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::PPCSubtarget::isISA3_0
bool isISA3_0() const
Definition: PPCSubtarget.h:338
llvm::PPCRegisterInfo::lowerQuadwordSpilling
void lowerQuadwordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordSpilling - Generate code to spill paired general register.
Definition: PPCRegisterInfo.cpp:1339
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
PPCFrameLowering.h
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:288
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:577
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::BitVector
Definition: BitVector.h:75
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::PPCRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: PPCRegisterInfo.cpp:325
llvm::PPCSubtarget::getInstrInfo
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:217
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::PPCRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: PPCRegisterInfo.cpp:542
llvm::MachineFrameInfo::isCalleeSavedInfoValid
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
Definition: MachineFrameInfo.h:792
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::PPCISD::XXMFACC
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
Definition: PPCISelLowering.h:488
llvm::VirtRegMap::hasPhys
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:99
ReportAccMoves
static cl::opt< bool > ReportAccMoves("ppc-report-acc-moves", cl::desc("Emit information about accumulator register spills " "and copies"), cl::Hidden, cl::init(false))
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::PPCSubtarget::isAIXABI
bool isAIXABI() const
Definition: PPCSubtarget.h:367
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::PPCSubtarget::isSVR4ABI
bool isSVR4ABI() const
Definition: PPCSubtarget.h:368
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::cl::opt< bool >
llvm::TargetMachine::getAIXExtendedAltivecABI
bool getAIXExtendedAltivecABI() const
Definition: TargetMachine.h:265
llvm::PPCRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: PPCRegisterInfo.cpp:1704
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
VirtRegMap.h
llvm::PPCRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: PPCRegisterInfo.cpp:185
llvm::PPCSubtarget::is32BitELFABI
bool is32BitELFABI() const
Definition: PPCSubtarget.h:372
llvm::PPCRegisterInfo::lowerDynamicAreaOffset
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
Definition: PPCRegisterInfo.cpp:889
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:422
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:943
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:565
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::PPCRegisterInfo::lowerCRBitRestore
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:1127
llvm::PPCRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: PPCRegisterInfo.cpp:423
llvm::PPCRegisterInfo::getBaseRegister
Register getBaseRegister(const MachineFunction &MF) const
Definition: PPCRegisterInfo.cpp:1673
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::PPCRegisterInfo::lowerCRBitSpilling
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:1008
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::PPCISD::DYNAREAOFFSET
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
Definition: PPCISelLowering.h:149
EnableBasePointer
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::PPCRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:600
llvm::PPCRegisterInfo::adjustStackMapLiveOutMask
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
Definition: PPCRegisterInfo.cpp:329
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:779
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:471
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::PPCRegisterInfo::hasReservedSpillSlot
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Definition: PPCRegisterInfo.cpp:1391
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
emitAccSpillRestoreInfo
static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed, bool IsRestore)
Definition: PPCRegisterInfo.cpp:1191
offsetMinAlignForOpcode
static unsigned offsetMinAlignForOpcode(unsigned OpC)
Definition: PPCRegisterInfo.cpp:1409
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCTargetMachine::isPPC64
bool isPPC64() const
Definition: PPCTargetMachine.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:593
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::PPCRegisterInfo::emitAccCopyInfo
static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg, MCRegister SrcReg)
Definition: PPCRegisterInfo.cpp:1177
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::PPCRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: PPCRegisterInfo.cpp:1687
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::PPCRegisterInfo::PPCRegisterInfo
PPCRegisterInfo(const PPCTargetMachine &TM)
Definition: PPCRegisterInfo.cpp:98
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
uint16_t
llvm::PPCFrameLowering::determineFrameLayout
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
Definition: PPCFrameLowering.cpp:297
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:177
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::PPCRegisterInfo::lowerACCRestore
void lowerACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCRestore - Generate the code to restore the accumulator register.
Definition: PPCRegisterInfo.cpp:1305
offsetMinAlign
static unsigned offsetMinAlign(const MachineInstr &MI)
Definition: PPCRegisterInfo.cpp:1442
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::PPCRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: PPCRegisterInfo.cpp:266
Function.h
PPCGenRegisterInfo
llvm::PPCSubtarget::hasSPE
bool hasSPE() const
Definition: PPCSubtarget.h:277
llvm::PPCRegisterInfo::lowerCRSpilling
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
Definition: PPCRegisterInfo.cpp:920
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::PPCISD::MFOCRF
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
Definition: PPCISelLowering.h:217
llvm::PPCRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:334
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::PPCRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: PPCRegisterInfo.cpp:1797
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:257
spillRegPairs
static void spillRegPairs(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, const TargetInstrInfo &TII, Register SrcReg, unsigned FrameIndex, bool IsLittleEndian, bool IsKilled, bool TwoPairs)
Definition: PPCRegisterInfo.cpp:1204
llvm::PPCSubtarget::hasAltivec
bool hasAltivec() const
Definition: PPCSubtarget.h:276
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
MachineInstrBuilder.h
llvm::PPCRegisterInfo::lowerPrepareProbedAlloca
void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const
Definition: PPCRegisterInfo.cpp:848
llvm::PPCTargetMachine::isELFv2ABI
bool isELFv2ABI() const
Definition: PPCTargetMachine.h:59
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
PPCMachineFunctionInfo.h
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::PPCFunctionInfo::getFramePointerSaveIndex
int getFramePointerSaveIndex() const
Definition: PPCMachineFunctionInfo.h:161
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl< MCPhysReg >
llvm::PPCRegisterInfo::isCallerPreservedPhysReg
bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:519
llvm::PPCRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:509
EnableGPRToVecSpills
static cl::opt< bool > EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), cl::desc("Enable spills from gpr to vsr rather than stack"))
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::PPCRegisterInfo::lowerCRRestore
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:965
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
RegisterScavenging.h
llvm::PPCFunctionInfo::usesTOCBasePtr
bool usesTOCBasePtr() const
Definition: PPCMachineFunctionInfo.h:219
raw_ostream.h
llvm::PPCRegisterInfo::lowerACCSpilling
void lowerACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCSpilling - Generate the code for spilling the accumulator register.
Definition: PPCRegisterInfo.cpp:1262
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::PPCRegisterInfo::prepareDynamicAlloca
void prepareDynamicAlloca(MachineBasicBlock::iterator II, Register &NegSizeReg, bool &KillNegSizeReg, Register &FramePointer) const
To accomplish dynamic stack allocation, we have to calculate exact size subtracted from the stack poi...
Definition: PPCRegisterInfo.cpp:757
llvm::PPCRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: PPCRegisterInfo.cpp:1462
Debug.h
DisableAutoPairedVecSt
cl::opt< bool > DisableAutoPairedVecSt
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
PPCTargetMachine.h
llvm::PPCSubtarget::pairedVectorMemops
bool pairedVectorMemops() const
Definition: PPCSubtarget.h:293
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52