LLVM 19.0.0git
PPCRegisterInfo.h
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1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16
18#include "llvm/ADT/DenseMap.h"
19
20#define GET_REGINFO_HEADER
21#include "PPCGenRegisterInfo.inc"
22
23namespace llvm {
24class PPCTargetMachine;
25
26inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27 unsigned Reg = 0;
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30 Reg = PPC::CR0;
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33 Reg = PPC::CR1;
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36 Reg = PPC::CR2;
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39 Reg = PPC::CR3;
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42 Reg = PPC::CR4;
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45 Reg = PPC::CR5;
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48 Reg = PPC::CR6;
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51 Reg = PPC::CR7;
52
53 assert(Reg != 0 && "Invalid CR bit register");
54 return Reg;
55}
56
59 const PPCTargetMachine &TM;
60
61public:
63
64 /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65 /// for a given imm form load/store opcode \p ImmFormOpcode.
66 /// FIXME: move this to PPCInstrInfo class.
67 unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68 if (!ImmToIdxMap.count(ImmOpcode))
69 return PPC::INSTRUCTION_LIST_END;
70 return ImmToIdxMap.find(ImmOpcode)->second;
71 }
72
73 /// getPointerRegClass - Return the register class to use to hold pointers.
74 /// This is used for addressing modes.
76 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
77
79 MachineFunction &MF) const override;
80
83 const MachineFunction &MF) const override;
84
85 /// Code Generation virtual methods...
86 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
88 CallingConv::ID CC) const override;
89 const uint32_t *getNoPreservedMask() const override;
90
91 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
92
93 BitVector getReservedRegs(const MachineFunction &MF) const override;
94 bool isAsmClobberable(const MachineFunction &MF,
95 MCRegister PhysReg) const override;
97 const MachineFunction &MF) const override;
98
99 // Provide hints to the register allocator for allocating subregisters
100 // of primed and unprimed accumulators. For example, if accumulator
101 // ACC5 is assigned, we also want to assign UACC5 to the input.
102 // Similarly if UACC5 is assigned, we want to assign VSRp10, VSRp11
103 // to its inputs.
106 const MachineFunction &MF, const VirtRegMap *VRM,
107 const LiveRegMatrix *Matrix) const override;
108
109 /// We require the register scavenger.
110 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
111 return true;
112 }
113
114 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
115
116 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
117
121 Register &NegSizeReg, bool &KillNegSizeReg,
122 Register &FramePointer) const;
125 unsigned FrameIndex) const;
127 unsigned FrameIndex) const;
129 unsigned FrameIndex) const;
131 unsigned FrameIndex) const;
132
134 unsigned FrameIndex) const;
136 unsigned FrameIndex) const;
138 unsigned FrameIndex) const;
139
141 unsigned FrameIndex) const;
143 unsigned FrameIndex) const;
144
146 unsigned FrameIndex) const;
148 unsigned FrameIndex) const;
149
150 static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
151 MCRegister SrcReg);
152
154 int &FrameIdx) const override;
156 unsigned FIOperandNum,
157 RegScavenger *RS = nullptr) const override;
158
159 // Support for virtual base registers.
160 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
162 int64_t Offset) const override;
164 int64_t Offset) const override;
165 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
166 int64_t Offset) const override;
167
168 // Debug information queries.
169 Register getFrameRegister(const MachineFunction &MF) const override;
170
171 // Base pointer (stack realignment) support.
173 bool hasBasePointer(const MachineFunction &MF) const;
174
176 return Reg == PPC::LR || Reg == PPC::LR8;
177 }
178};
179
180} // end namespace llvm
181
182#endif
MachineBasicBlock & MBB
This file defines the DenseMap class.
IRTranslator LLVM IR MI
Live Register Matrix
unsigned Reg
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:151
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:68
bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Register getFrameRegister(const MachineFunction &MF) const override
bool hasBasePointer(const MachineFunction &MF) const
Register getBaseRegister(const MachineFunction &MF) const
void prepareDynamicAlloca(MachineBasicBlock::iterator II, Register &NegSizeReg, bool &KillNegSizeReg, Register &FramePointer) const
To accomplish dynamic stack allocation, we have to calculate exact size subtracted from the stack poi...
unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const
getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode for a given imm form load/s...
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCSpilling - Generate the code for spilling the accumulator register.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
const uint32_t * getNoPreservedMask() const override
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
void lowerQuadwordRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordRestore - Generate code to restore paired general register.
static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg, MCRegister SrcReg)
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
void lowerWACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerWACCRestore - Generate the code to restore the wide accumulator register.
void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const
void lowerQuadwordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordSpilling - Generate code to spill paired general register.
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void lowerWACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerWACCSpilling - Generate the code for spilling the wide accumulator register.
void lowerOctWordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Remove any STXVP[X] instructions and split them out into a pair of STXV[X] instructions if –disable-a...
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
void lowerACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCRestore - Generate the code to restore the accumulator register.
Common code between 32-bit and 64-bit PowerPC targets.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
static unsigned getCRFromCRBit(unsigned SrcReg)