LLVM  17.0.0git
PPCRegisterInfo.h
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1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 
18 #include "llvm/ADT/DenseMap.h"
19 
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
22 
23 namespace llvm {
24 class PPCTargetMachine;
25 
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27  unsigned Reg = 0;
28  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29  SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30  Reg = PPC::CR0;
31  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32  SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33  Reg = PPC::CR1;
34  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35  SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36  Reg = PPC::CR2;
37  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38  SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39  Reg = PPC::CR3;
40  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41  SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42  Reg = PPC::CR4;
43  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44  SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45  Reg = PPC::CR5;
46  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47  SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48  Reg = PPC::CR6;
49  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50  SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51  Reg = PPC::CR7;
52 
53  assert(Reg != 0 && "Invalid CR bit register");
54  return Reg;
55 }
56 
58  DenseMap<unsigned, unsigned> ImmToIdxMap;
59  const PPCTargetMachine &TM;
60 
61 public:
63 
64  /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65  /// for a given imm form load/store opcode \p ImmFormOpcode.
66  /// FIXME: move this to PPCInstrInfo class.
67  unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68  if (!ImmToIdxMap.count(ImmOpcode))
69  return PPC::INSTRUCTION_LIST_END;
70  return ImmToIdxMap.find(ImmOpcode)->second;
71  }
72 
73  /// getPointerRegClass - Return the register class to use to hold pointers.
74  /// This is used for addressing modes.
75  const TargetRegisterClass *
76  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
77 
78  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
79  MachineFunction &MF) const override;
80 
81  const TargetRegisterClass *
83  const MachineFunction &MF) const override;
84 
85  /// Code Generation virtual methods...
86  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
88  CallingConv::ID CC) const override;
89  const uint32_t *getNoPreservedMask() const override;
90 
91  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
92 
93  BitVector getReservedRegs(const MachineFunction &MF) const override;
94  bool isAsmClobberable(const MachineFunction &MF,
95  MCRegister PhysReg) const override;
97  const MachineFunction &MF) const override;
98 
99  // Provide hints to the register allocator for allocating subregisters
100  // of primed and unprimed accumulators. For example, if accumulator
101  // ACC5 is assigned, we also want to assign UACC5 to the input.
102  // Similarly if UACC5 is assigned, we want to assign VSRp10, VSRp11
103  // to its inputs.
106  const MachineFunction &MF, const VirtRegMap *VRM,
107  const LiveRegMatrix *Matrix) const override;
108 
109  /// We require the register scavenger.
110  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
111  return true;
112  }
113 
114  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
115 
116  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
117 
121  Register &NegSizeReg, bool &KillNegSizeReg,
122  Register &FramePointer) const;
125  unsigned FrameIndex) const;
127  unsigned FrameIndex) const;
129  unsigned FrameIndex) const;
131  unsigned FrameIndex) const;
132 
134  unsigned FrameIndex) const;
136  unsigned FrameIndex) const;
138  unsigned FrameIndex) const;
139 
141  unsigned FrameIndex) const;
143  unsigned FrameIndex) const;
144 
146  unsigned FrameIndex) const;
148  unsigned FrameIndex) const;
149 
150  static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
151  MCRegister SrcReg);
152 
154  int &FrameIdx) const override;
156  unsigned FIOperandNum,
157  RegScavenger *RS = nullptr) const override;
158 
159  // Support for virtual base registers.
160  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
162  int64_t Offset) const override;
163  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
164  int64_t Offset) const override;
165  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
166  int64_t Offset) const override;
167 
168  // Debug information queries.
169  Register getFrameRegister(const MachineFunction &MF) const override;
170 
171  // Base pointer (stack realignment) support.
172  Register getBaseRegister(const MachineFunction &MF) const;
173  bool hasBasePointer(const MachineFunction &MF) const;
174 
175  /// stripRegisterPrefix - This method strips the character prefix from a
176  /// register name so that only the number is left. Used by for linux asm.
177  static const char *stripRegisterPrefix(const char *RegName) {
178  switch (RegName[0]) {
179  case 'a':
180  if (RegName[1] == 'c' && RegName[2] == 'c')
181  return RegName + 3;
182  break;
183  case 'r':
184  case 'f':
185  case 'v':
186  if (RegName[1] == 's') {
187  if (RegName[2] == 'p')
188  return RegName + 3;
189  return RegName + 2;
190  }
191  return RegName + 1;
192  case 'c':
193  if (RegName[1] == 'r')
194  return RegName + 2;
195  break;
196  case 'w':
197  // For wacc and wacc_hi
198  if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
199  if (RegName[4] == '_')
200  return RegName + 7;
201  else
202  return RegName + 4;
203  }
204  break;
205  case 'd':
206  // For dmr, dmrp, dmrrow, dmrrowp
207  if (RegName[1] == 'm' && RegName[2] == 'r') {
208  if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
209  RegName[6] == 'p')
210  return RegName + 7;
211  else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
212  return RegName + 6;
213  else if (RegName[3] == 'p')
214  return RegName + 4;
215  else
216  return RegName + 3;
217  }
218  break;
219  }
220 
221  return RegName;
222  }
223 
225  return Reg == PPC::LR || Reg == PPC::LR8;
226  }
227 };
228 
229 } // end namespace llvm
230 
231 #endif
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
llvm::PPCRegisterInfo::lowerDynamicAlloc
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
Definition: PPCRegisterInfo.cpp:734
llvm::PPCRegisterInfo::lowerWACCSpilling
void lowerWACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerWACCSpilling - Generate the code for spilling the wide accumulator register.
Definition: PPCRegisterInfo.cpp:1391
llvm::PPCRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
Definition: PPCRegisterInfo.cpp:169
llvm::getCRFromCRBit
static unsigned getCRFromCRBit(unsigned SrcReg)
Definition: PPCRegisterInfo.h:26
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::PPCRegisterInfo::lowerQuadwordRestore
void lowerQuadwordRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordRestore - Generate code to restore paired general register.
Definition: PPCRegisterInfo.cpp:1484
llvm::PPCRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:454
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::PPCRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:679
llvm::PPCRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:1815
DenseMap.h
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::PPCRegisterInfo::lowerOctWordSpilling
void lowerOctWordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Remove any STXVP[X] instructions and split them out into a pair of STXV[X] instructions if –disable-a...
Definition: PPCRegisterInfo.cpp:1277
PPCMCTargetDesc.h
llvm::PPCRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Definition: PPCRegisterInfo.cpp:1899
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: PPCRegisterInfo.cpp:1924
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::PPCRegisterInfo::lowerQuadwordSpilling
void lowerQuadwordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordSpilling - Generate code to spill paired general register.
Definition: PPCRegisterInfo.cpp:1457
llvm::BitVector
Definition: BitVector.h:75
llvm::PPCRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: PPCRegisterInfo.cpp:345
llvm::PPCRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: PPCRegisterInfo.cpp:561
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::PPCRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: PPCRegisterInfo.cpp:1855
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::PPCRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: PPCRegisterInfo.cpp:185
llvm::PPCRegisterInfo::getMappedIdxOpcForImmOpc
unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const
getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode for a given imm form load/s...
Definition: PPCRegisterInfo.h:67
llvm::PPCRegisterInfo::lowerDynamicAreaOffset
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
Definition: PPCRegisterInfo.cpp:923
llvm::DenseMap< unsigned, unsigned >
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::PPCRegisterInfo::lowerCRBitRestore
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:1161
llvm::PPCRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: PPCRegisterInfo.cpp:442
llvm::PPCRegisterInfo::getBaseRegister
Register getBaseRegister(const MachineFunction &MF) const
Definition: PPCRegisterInfo.cpp:1824
llvm::PPCRegisterInfo::lowerCRBitSpilling
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:1042
llvm::PPCRegisterInfo::stripRegisterPrefix
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
Definition: PPCRegisterInfo.h:177
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::PPCRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:634
llvm::PPCRegisterInfo::adjustStackMapLiveOutMask
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
Definition: PPCRegisterInfo.cpp:349
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::PPCRegisterInfo::hasReservedSpillSlot
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Definition: PPCRegisterInfo.cpp:1509
llvm::Offset
@ Offset
Definition: DWP.cpp:406
uint32_t
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::PPCRegisterInfo::isNonallocatableRegisterCalleeSave
bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override
Definition: PPCRegisterInfo.h:224
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCRegisterInfo::emitAccCopyInfo
static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg, MCRegister SrcReg)
Definition: PPCRegisterInfo.cpp:1211
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PPCRegisterInfo::lowerWACCRestore
void lowerWACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerWACCRestore - Generate the code to restore the wide accumulator register.
Definition: PPCRegisterInfo.cpp:1425
llvm::PPCRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: PPCRegisterInfo.cpp:1838
llvm::PPCRegisterInfo::PPCRegisterInfo
PPCRegisterInfo(const PPCTargetMachine &TM)
Definition: PPCRegisterInfo.cpp:98
uint16_t
llvm::PPCRegisterInfo::lowerACCRestore
void lowerACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCRestore - Generate the code to restore the accumulator register.
Definition: PPCRegisterInfo.cpp:1356
llvm::PPCRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: PPCRegisterInfo.cpp:278
PPCGenRegisterInfo
llvm::PPCRegisterInfo::lowerCRSpilling
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
Definition: PPCRegisterInfo.cpp:954
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:26
llvm::PPCRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:354
llvm::PPCRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: PPCRegisterInfo.cpp:1948
llvm::PPCRegisterInfo::lowerPrepareProbedAlloca
void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const
Definition: PPCRegisterInfo.cpp:882
llvm::PPCRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
Definition: PPCRegisterInfo.h:110
llvm::SmallVectorImpl< MCPhysReg >
llvm::PPCRegisterInfo::isCallerPreservedPhysReg
bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:538
llvm::PPCRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: PPCRegisterInfo.cpp:528
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::PPCRegisterInfo::lowerCRRestore
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Definition: PPCRegisterInfo.cpp:999
llvm::PPCRegisterInfo::lowerACCSpilling
void lowerACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCSpilling - Generate the code for spilling the accumulator register.
Definition: PPCRegisterInfo.cpp:1313
llvm::PPCRegisterInfo::eliminateFrameIndex
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: PPCRegisterInfo.cpp:1580
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::PPCRegisterInfo::prepareDynamicAlloca
void prepareDynamicAlloca(MachineBasicBlock::iterator II, Register &NegSizeReg, bool &KillNegSizeReg, Register &FramePointer) const
To accomplish dynamic stack allocation, we have to calculate exact size subtracted from the stack poi...
Definition: PPCRegisterInfo.cpp:791
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40