LLVM  12.0.0git
PPCRegisterInfo.h
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1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 
18 #include "llvm/ADT/DenseMap.h"
19 
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
22 
23 namespace llvm {
24 class PPCTargetMachine;
25 
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27  unsigned Reg = 0;
28  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29  SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30  Reg = PPC::CR0;
31  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32  SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33  Reg = PPC::CR1;
34  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35  SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36  Reg = PPC::CR2;
37  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38  SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39  Reg = PPC::CR3;
40  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41  SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42  Reg = PPC::CR4;
43  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44  SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45  Reg = PPC::CR5;
46  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47  SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48  Reg = PPC::CR6;
49  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50  SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51  Reg = PPC::CR7;
52 
53  assert(Reg != 0 && "Invalid CR bit register");
54  return Reg;
55 }
56 
58  DenseMap<unsigned, unsigned> ImmToIdxMap;
59  const PPCTargetMachine &TM;
60 
61 public:
63 
64  /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65  /// for a given imm form load/store opcode \p ImmFormOpcode.
66  /// FIXME: move this to PPCInstrInfo class.
67  unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68  if (!ImmToIdxMap.count(ImmOpcode))
69  return PPC::INSTRUCTION_LIST_END;
70  return ImmToIdxMap.find(ImmOpcode)->second;
71  }
72 
73  /// getPointerRegClass - Return the register class to use to hold pointers.
74  /// This is used for addressing modes.
75  const TargetRegisterClass *
76  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
77 
78  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
79  MachineFunction &MF) const override;
80 
81  const TargetRegisterClass *
83  const MachineFunction &MF) const override;
84 
85  /// Code Generation virtual methods...
86  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
88  CallingConv::ID CC) const override;
89  const uint32_t *getNoPreservedMask() const override;
90 
91  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
92 
93  BitVector getReservedRegs(const MachineFunction &MF) const override;
95  const MachineFunction &MF) const override;
96 
97  /// We require the register scavenger.
98  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
99  return true;
100  }
101 
102  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
103 
104  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
105  return true;
106  }
107 
111  Register &NegSizeReg, bool &KillNegSizeReg,
112  Register &FramePointer) const;
115  unsigned FrameIndex) const;
117  unsigned FrameIndex) const;
119  unsigned FrameIndex) const;
121  unsigned FrameIndex) const;
123  unsigned FrameIndex) const;
125  unsigned FrameIndex) const;
126 
128  int &FrameIdx) const override;
130  unsigned FIOperandNum,
131  RegScavenger *RS = nullptr) const override;
132 
133  // Support for virtual base registers.
134  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
136  int FrameIdx,
137  int64_t Offset) const override;
138  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
139  int64_t Offset) const override;
140  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
141  int64_t Offset) const override;
142 
143  // Debug information queries.
144  Register getFrameRegister(const MachineFunction &MF) const override;
145 
146  // Base pointer (stack realignment) support.
147  Register getBaseRegister(const MachineFunction &MF) const;
148  bool hasBasePointer(const MachineFunction &MF) const;
149 
150  /// stripRegisterPrefix - This method strips the character prefix from a
151  /// register name so that only the number is left. Used by for linux asm.
152  static const char *stripRegisterPrefix(const char *RegName) {
153  switch (RegName[0]) {
154  case 'r':
155  case 'f':
156  case 'q': // for QPX
157  case 'v':
158  if (RegName[1] == 's')
159  return RegName + 2;
160  return RegName + 1;
161  case 'c': if (RegName[1] == 'r') return RegName + 2;
162  }
163 
164  return RegName;
165  }
166 };
167 
168 } // end namespace llvm
169 
170 #endif
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
unsigned Reg
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
MachineBasicBlock & MBB
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const override
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const
bool hasBasePointer(const MachineFunction &MF) const
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Common code between 32-bit and 64-bit PowerPC targets.
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
const uint32_t * getNoPreservedMask() const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register getBaseRegister(const MachineFunction &MF) const
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Register getFrameRegister(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Representation of each machine instruction.
Definition: MachineInstr.h:62
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const
getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode for a given imm form load/s...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
IRTranslator LLVM IR MI
void prepareDynamicAlloca(MachineBasicBlock::iterator II, Register &NegSizeReg, bool &KillNegSizeReg, Register &FramePointer) const
To accomplish dynamic stack allocation, we have to calculate exact size subtracted from the stack poi...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19