33#define DEBUG_TYPE "framelowering"
34STATISTIC(NumPESpillVSR,
"Number of spills to vector in prologue");
35STATISTIC(NumPEReloadVSR,
"Number of reloads from vector in epilogue");
36STATISTIC(NumPrologProbed,
"Number of prologues probed");
40 cl::desc(
"Enable spills in prologue to vector registers."),
58 return STI.
isPPC64() ? -8U : -4U;
75 return STI.
isPPC64() ? -16U : -8U;
84 STI.getPlatformStackAlignment(), 0),
94 unsigned &NumEntries)
const {
97#define CALLEE_SAVED_FPRS \
119#define CALLEE_SAVED_GPRS32 \
140#define CALLEE_SAVED_GPRS64 \
161#define CALLEE_SAVED_VRS \
178 static const SpillSlot ELFOffsets32[] = {
213 static const SpillSlot ELFOffsets64[] = {
228 static const SpillSlot AIXOffsets64[] = {
232 NumEntries = std::size(ELFOffsets64);
237 NumEntries = std::size(ELFOffsets32);
244 NumEntries = std::size(AIXOffsets64);
248 NumEntries = std::size(AIXOffsets32);
285 bool UseEstimate)
const {
286 unsigned NewMaxCallFrameSize = 0;
288 &NewMaxCallFrameSize);
299 unsigned *NewMaxCallFrameSize)
const {
310 Align Alignment = std::max(TargetAlign, MaxAlign);
314 unsigned LR = RegInfo->getRARegister();
327 if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
337 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
342 maxCallFrameSize =
alignTo(maxCallFrameSize, Alignment);
345 if (NewMaxCallFrameSize)
346 *NewMaxCallFrameSize = maxCallFrameSize;
349 FrameSize += maxCallFrameSize;
352 FrameSize =
alignTo(FrameSize, Alignment);
387 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
388 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
393 unsigned BP8Reg = HasBP ? (
unsigned) PPC::X30 : FP8Reg;
398 for (
unsigned I = 0,
E =
MBBI->getNumOperands();
I !=
E; ++
I) {
441 bool TwoUniqueRegsRequired,
453 assert (SR1 &&
"Asking for the second scratch register but not the first?");
496 for (
int i = 0; CSRegs[i]; ++i)
502 *SR1 = FirstScratchReg == -1 ? (
unsigned)PPC::NoRegister : FirstScratchReg;
509 int SecondScratchReg = BV.
find_next(*SR1);
510 if (SecondScratchReg != -1)
511 *SR2 = SecondScratchReg;
513 *SR2 = TwoUniqueRegsRequired ?
Register() : *SR1;
518 if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
535 bool HasBP =
RegInfo->hasBasePointer(MF);
537 int NegFrameSize = -FrameSize;
538 bool IsLargeFrame = !isInt<16>(NegFrameSize);
544 return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||
551 return findScratchRegister(TmpMBB,
false,
552 twoUniqueScratchRegsRequired(TmpMBB));
558 return findScratchRegister(TmpMBB,
true);
561bool PPCFrameLowering::stackUpdateCanBeMoved(
MachineFunction &MF)
const {
619 const bool HasFastMFLR = Subtarget.hasFastMFLR();
622 bool isPPC64 = Subtarget.
isPPC64();
626 assert((isSVR4ABI || Subtarget.
isAIXABI()) &&
"Unsupported PPC ABI.");
630 int64_t NegFrameSize = -FrameSize;
631 if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
642 bool MustSaveCR = !MustSaveCRs.
empty();
644 bool HasFP =
hasFP(MF);
646 bool HasRedZone = isPPC64 || !isSVR4ABI;
647 bool HasROPProtect = Subtarget.hasROPProtect();
648 bool HasPrivileged = Subtarget.hasPrivileged();
650 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
652 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
653 Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
654 Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
656 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
664 const MCInstrDesc& StoreUpdtIdxInst =
TII.get(isPPC64 ? PPC::STDUX
668 const MCInstrDesc& SubtractCarryingInst =
TII.get(isPPC64 ? PPC::SUBFC8
670 const MCInstrDesc& SubtractImmCarryingInst =
TII.get(isPPC64 ? PPC::SUBFIC8
672 const MCInstrDesc &MoveFromCondRegInst =
TII.get(isPPC64 ? PPC::MFCR8
674 const MCInstrDesc &StoreWordInst =
TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
676 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)
677 : (HasPrivileged ? PPC::HASHSTP : PPC::HASHST));
684 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
687 bool SingleScratchReg = findScratchRegister(
688 &
MBB,
false, twoUniqueScratchRegsRequired(&
MBB), &ScratchReg, &TempReg);
689 assert(SingleScratchReg &&
690 "Required number of registers not available in this block");
692 SingleScratchReg = ScratchReg == TempReg;
696 int64_t FPOffset = 0;
700 assert(FPIndex &&
"No Frame Pointer Save Slot!");
704 int64_t BPOffset = 0;
708 assert(BPIndex &&
"No Base Pointer Save Slot!");
712 int64_t PBPOffset = 0;
716 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
722 if (HasBP && MaxAlign > 1)
723 assert(
Log2(MaxAlign) < 16 &&
"Invalid alignment!");
727 bool isLargeFrame = !isInt<16>(NegFrameSize);
733 bool MovingStackUpdateDown =
false;
736 if (stackUpdateCanBeMoved(MF)) {
749 if (CSI.isSpilledToReg()) {
750 StackUpdateLoc =
MBBI;
751 MovingStackUpdateDown =
false;
755 int FrIdx = CSI.getFrameIdx();
764 MovingStackUpdateDown =
true;
768 StackUpdateLoc =
MBBI;
769 MovingStackUpdateDown =
false;
775 if (MovingStackUpdateDown) {
777 int FrIdx = CSI.getFrameIdx();
787 auto BuildMoveFromCR = [&]() {
788 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
793 assert(isPPC64 &&
"V2 ABI is 64-bit only.");
800 for (
unsigned CRfield : MustSaveCRs)
807 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
818 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR))
842 auto SaveLR = [&](int64_t
Offset) {
858 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
859 "ROP hash save offset out of range.");
860 assert(((ImmOffset & 0x7) == 0) &&
861 "ROP hash save offset must be 8 byte aligned.");
874 assert(HasRedZone &&
"A red zone is always available on PPC64");
891 if (HasBP && HasRedZone) {
902 (HasBP && MaxAlign > 1) || isLargeFrame;
910 (HasSTUX || !isInt<16>(FrameSize + LROffset)))
920 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
921 : PPC::PROBED_STACKALLOC_32))
935 if (HasBP && MaxAlign > 1) {
952 assert(!SingleScratchReg &&
"Only a single scratch reg available");
953 TII.materializeImmPostRA(
MBB,
MBBI, dl, TempReg, NegFrameSize);
963 }
else if (!isLargeFrame) {
964 BuildMI(
MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
969 TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, NegFrameSize);
980 assert(isELFv2ABI &&
"TOC saves in the prologue only supported on ELFv2");
988 assert(!isPPC64 &&
"A red zone is always available on PPC64");
1004 if (ScratchReg == PPC::R0) {
1013 .
addImm(FPOffset-LastOffset);
1014 LastOffset = FPOffset;
1025 .
addImm(PBPOffset-LastOffset);
1026 LastOffset = PBPOffset;
1036 .
addImm(BPOffset-LastOffset);
1037 LastOffset = BPOffset;
1081 .
addImm(FrameSize + FPOffset)
1086 .
addImm(FrameSize + PBPOffset)
1091 .
addImm(FrameSize + BPOffset)
1101 if (!HasSTUX &&
MustSaveLR && !HasFastMFLR && isInt<16>(FrameSize + LROffset))
1102 SaveLR(LROffset + FrameSize);
1112 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1126 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1135 unsigned Reg =
MRI->getDwarfRegNum(PPC::R30,
true);
1144 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1153 unsigned Reg =
MRI->getDwarfRegNum(LRReg,
true);
1167 if (!HasBP && needsCFI) {
1170 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1185 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM)
continue;
1189 if (PPC::CRBITRCRegClass.
contains(Reg))
1192 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
1197 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1203 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1207 Register CRReg = isELFv2ABI? Reg : PPC::CR2;
1209 nullptr,
MRI->getDwarfRegNum(CRReg,
true), CRSaveOffset));
1215 if (
I.isSpilledToReg()) {
1216 unsigned SpilledReg =
I.getDstReg();
1218 nullptr,
MRI->getDwarfRegNum(Reg,
true),
1219 MRI->getDwarfRegNum(SpilledReg,
true)));
1227 if (MovingStackUpdateDown)
1231 nullptr,
MRI->getDwarfRegNum(Reg,
true),
Offset));
1241 bool isPPC64 = Subtarget.
isPPC64();
1250 int Opc =
MI.getOpcode();
1251 return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;
1253 if (StackAllocMIPos == PrologMBB.
end())
1259 int64_t NegFrameSize =
MI.getOperand(2).getImm();
1261 int64_t NegProbeSize = -(int64_t)ProbeSize;
1262 assert(isInt<32>(NegProbeSize) &&
"Unhandled probe size");
1263 int64_t NumBlocks = NegFrameSize / NegProbeSize;
1264 int64_t NegResidualSize = NegFrameSize % NegProbeSize;
1265 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1266 Register ScratchReg =
MI.getOperand(0).getReg();
1273 const MCInstrDesc &CopyInst =
TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
1277 unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1286 unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1293 auto CanUseDForm = [](int64_t Imm) {
return isInt<16>(Imm) && Imm % 4 == 0; };
1298 assert(isInt<32>(Imm) &&
"Unhandled imm");
1313 Register NegSizeReg,
bool UseDForm,
1355 assert(HasBP &&
"The function is supposed to have base pointer when its "
1356 "stack is realigned.");
1364 "Probe size should be larger or equal to the size of red-zone so "
1365 "that red-zone is not clobbered by probing.");
1371 NegProbeSize = std::max(NegProbeSize, -((int64_t)1 << 15));
1372 assert(isInt<16>(NegProbeSize) &&
1373 "NegProbeSize should be materializable by DForm");
1390 MF.
insert(MBBInsertPoint, ProbeLoopBodyMBB);
1392 MF.
insert(MBBInsertPoint, ProbeExitMBB);
1395 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1396 allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->
end(), 0, ScratchReg,
false,
1401 BuildMI(*ProbeExitMBB, ProbeExitMBB->
end(),
DL, CopyInst, TempReg)
1409 BuildMI(&
MBB,
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), ScratchReg)
1426 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1427 allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->
end(), NegProbeSize,
1428 0,
true , BackChainPointer);
1429 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),
1433 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),
1440 .
addMBB(ProbeLoopBodyMBB);
1447 return ProbeExitMBB;
1452 if (HasBP && MaxAlign > 1) {
1465 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),
1469 MaterializeImm(*CurrentMBB, {
MI}, NegFrameSize, ScratchReg);
1470 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
1474 CurrentMBB = probeRealignedStack(*CurrentMBB, {
MI}, ScratchReg, FPReg);
1482 buildDefCFA(*CurrentMBB, {
MI}, FPReg, 0);
1484 if (NegResidualSize) {
1485 bool ResidualUseDForm = CanUseDForm(NegResidualSize);
1486 if (!ResidualUseDForm)
1487 MaterializeImm(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg);
1488 allocateAndProbe(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg,
1489 ResidualUseDForm, FPReg);
1491 bool UseDForm = CanUseDForm(NegProbeSize);
1493 if (NumBlocks < 3) {
1495 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1496 for (
int i = 0; i < NumBlocks; ++i)
1497 allocateAndProbe(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg, UseDForm,
1508 MaterializeImm(*CurrentMBB, {
MI}, NumBlocks, ScratchReg);
1509 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
1512 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1517 MF.
insert(MBBInsertPoint, LoopMBB);
1519 MF.
insert(MBBInsertPoint, ExitMBB);
1521 allocateAndProbe(*LoopMBB, LoopMBB->
end(), NegProbeSize, ScratchReg,
1523 BuildMI(LoopMBB,
DL,
TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
1528 ExitMBB->
splice(ExitMBB->
end(), CurrentMBB,
1543 MI.eraseFromParent();
1552 dl =
MBBI->getDebugLoc();
1564 bool isPPC64 = Subtarget.
isPPC64();
1570 bool MustSaveCR = !MustSaveCRs.
empty();
1572 bool HasFP =
hasFP(MF);
1575 bool HasROPProtect = Subtarget.hasROPProtect();
1576 bool HasPrivileged = Subtarget.hasPrivileged();
1578 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1580 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1582 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
1587 const MCInstrDesc& LoadImmShiftedInst =
TII.get( isPPC64 ? PPC::LIS8
1599 const MCInstrDesc& MoveToCRInst =
TII.get( isPPC64 ? PPC::MTOCRF8
1602 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)
1603 : (HasPrivileged ? PPC::HASHCHKP : PPC::HASHCHK));
1606 int64_t FPOffset = 0;
1609 bool SingleScratchReg = findScratchRegister(&
MBB,
true,
false, &ScratchReg,
1611 assert(SingleScratchReg &&
1612 "Could not find an available scratch register");
1614 SingleScratchReg = ScratchReg == TempReg;
1618 assert(FPIndex &&
"No Frame Pointer Save Slot!");
1622 int64_t BPOffset = 0;
1625 assert(BPIndex &&
"No Base Pointer Save Slot!");
1629 int64_t PBPOffset = 0;
1632 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1638 if (IsReturnBlock) {
1639 unsigned RetOpcode =
MBBI->getOpcode();
1640 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1641 RetOpcode == PPC::TCRETURNdi ||
1642 RetOpcode == PPC::TCRETURNai ||
1643 RetOpcode == PPC::TCRETURNri8 ||
1644 RetOpcode == PPC::TCRETURNdi8 ||
1645 RetOpcode == PPC::TCRETURNai8;
1650 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1652 int StackAdj = StackAdjust.
getImm();
1653 int Delta = StackAdj - MaxTCRetDelta;
1654 assert((Delta >= 0) &&
"Delta must be positive");
1655 if (MaxTCRetDelta>0)
1656 FrameSize += (StackAdj +Delta);
1658 FrameSize += StackAdj;
1664 bool isLargeFrame = !isInt<16>(FrameSize);
1678 unsigned RBReg = SPReg;
1686 if (stackUpdateCanBeMoved(MF)) {
1691 if (CSI.isSpilledToReg()) {
1692 StackUpdateLoc =
MBBI;
1695 int FrIdx = CSI.getFrameIdx();
1707 StackUpdateLoc =
MBBI;
1720 if (HasRedZone && HasBP) {
1730 assert(HasFP &&
"Expecting a valid frame pointer.");
1733 if (!isLargeFrame) {
1737 TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, FrameSize);
1745 BuildMI(
MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1751 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1752 "Local offsets should be negative");
1754 FPOffset += FrameSize;
1755 BPOffset += FrameSize;
1756 PBPOffset += FrameSize;
1774 assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1781 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
1784 assert(HasRedZone &&
"Expecting red zone");
1788 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1797 bool LoadedLR =
false;
1798 if (
MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1805 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR)) {
1806 assert(RBReg == SPReg &&
"Should be using SP as a base register");
1815 if (HasRedZone || RBReg == SPReg)
1837 if (RBReg != SPReg || SPAdd != 0) {
1838 assert(!HasRedZone &&
"This should not happen with red zone");
1849 assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1864 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1871 if (HasROPProtect) {
1874 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
1875 "ROP hash check location offset out of range.");
1876 assert(((ImmOffset & 0x7) == 0) &&
1877 "ROP hash check location offset must be 8 byte aligned.");
1888 if (IsReturnBlock) {
1889 unsigned RetOpcode =
MBBI->getOpcode();
1891 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1896 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1901 .
addImm(CallerAllocatedAmt >> 16);
1904 .
addImm(CallerAllocatedAmt & 0xFFFF);
1911 createTailCallBranchInstr(
MBB);
1932 unsigned RetOpcode =
MBBI->getOpcode();
1933 if (RetOpcode == PPC::TCRETURNdi) {
1944 }
else if (RetOpcode == PPC::TCRETURNri) {
1946 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1948 }
else if (RetOpcode == PPC::TCRETURNai) {
1952 }
else if (RetOpcode == PPC::TCRETURNdi8) {
1963 }
else if (RetOpcode == PPC::TCRETURNri8) {
1965 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1967 }
else if (RetOpcode == PPC::TCRETURNai8) {
1983 SavedRegs.
reset(PPC::VSRp26);
1984 SavedRegs.
reset(PPC::VSRp27);
1985 SavedRegs.
reset(PPC::VSRp28);
1986 SavedRegs.
reset(PPC::VSRp29);
1987 SavedRegs.
reset(PPC::VSRp30);
1988 SavedRegs.
reset(PPC::VSRp31);
1992 unsigned LR = RegInfo->getRARegister();
1994 SavedRegs.
reset(LR);
1998 const bool isPPC64 = Subtarget.
isPPC64();
2032 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
2036 SavedRegs.
reset(PPC::R30);
2051 if ((SavedRegs.
test(PPC::CR2) || SavedRegs.
test(PPC::CR3) ||
2052 SavedRegs.
test(PPC::CR4))) {
2054 const int64_t SpillOffset =
2077 createTailCallBranchInstr(
MBB);
2082 if (CSI.empty() && !
needsFP(MF)) {
2087 unsigned MinGPR = PPC::R31;
2088 unsigned MinG8R = PPC::X31;
2089 unsigned MinFPR = PPC::F31;
2090 unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
2092 bool HasGPSaveArea =
false;
2093 bool HasG8SaveArea =
false;
2094 bool HasFPSaveArea =
false;
2095 bool HasVRSaveArea =
false;
2105 (Reg != PPC::X2 && Reg != PPC::R2)) &&
2106 "Not expecting to try to spill R2 in a function that must save TOC");
2107 if (PPC::GPRCRegClass.
contains(Reg)) {
2108 HasGPSaveArea =
true;
2115 }
else if (PPC::G8RCRegClass.
contains(Reg)) {
2116 HasG8SaveArea =
true;
2123 }
else if (PPC::F8RCRegClass.
contains(Reg)) {
2124 HasFPSaveArea =
true;
2131 }
else if (PPC::CRBITRCRegClass.
contains(Reg) ||
2134 }
else if (PPC::VRRCRegClass.
contains(Reg) ||
2135 PPC::SPERCRegClass.
contains(Reg)) {
2138 HasVRSaveArea =
true;
2153 int64_t LowerBound = 0;
2159 LowerBound = TCSPDelta;
2164 if (HasFPSaveArea) {
2165 for (
unsigned i = 0, e = FPRegs.
size(); i != e; ++i) {
2166 int FI = FPRegs[i].getFrameIdx();
2171 LowerBound -= (31 -
TRI->getEncodingValue(MinFPR) + 1) * 8;
2178 assert(FI &&
"No Frame Pointer Save Slot!");
2181 HasGPSaveArea =
true;
2186 assert(FI &&
"No PIC Base Pointer Save Slot!");
2189 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
2190 HasGPSaveArea =
true;
2196 assert(FI &&
"No Base Pointer Save Slot!");
2200 if (PPC::G8RCRegClass.
contains(BP)) {
2201 MinG8R = std::min<unsigned>(MinG8R, BP);
2202 HasG8SaveArea =
true;
2203 }
else if (PPC::GPRCRegClass.
contains(BP)) {
2204 MinGPR = std::min<unsigned>(MinGPR, BP);
2205 HasGPSaveArea =
true;
2211 if (HasGPSaveArea || HasG8SaveArea) {
2214 for (
unsigned i = 0, e = GPRegs.
size(); i != e; ++i) {
2215 if (!GPRegs[i].isSpilledToReg()) {
2216 int FI = GPRegs[i].getFrameIdx();
2223 for (
unsigned i = 0, e = G8Regs.
size(); i != e; ++i) {
2224 if (!G8Regs[i].isSpilledToReg()) {
2225 int FI = G8Regs[i].getFrameIdx();
2231 std::min<unsigned>(
TRI->getEncodingValue(MinGPR),
2232 TRI->getEncodingValue(MinG8R));
2234 const unsigned GPRegSize = Subtarget.
isPPC64() ? 8 : 4;
2235 LowerBound -= (31 - MinReg + 1) * GPRegSize;
2245 for (
const auto &CSInfo : CSI) {
2246 if (CSInfo.getReg() == PPC::CR2) {
2247 int FI = CSInfo.getFrameIdx();
2258 if (HasVRSaveArea) {
2264 assert(LowerBound <= 0 &&
"Expect LowerBound have a non-positive value!");
2265 LowerBound &= ~(15);
2267 for (
unsigned i = 0, e = VRegs.
size(); i != e; ++i) {
2268 int FI = VRegs[i].getFrameIdx();
2296 (
hasSpills(MF) && !isInt<16>(StackSize))) {
2301 unsigned Size =
TRI.getSpillSize(RC);
2302 Align Alignment =
TRI.getSpillAlign(RC);
2323 std::vector<CalleeSavedInfo> &CSI)
const {
2338 for (
unsigned i = 0; CSRegs[i]; ++i)
2339 BVCalleeSaved.
set(CSRegs[i]);
2341 for (
unsigned Reg : BVAllocatable.
set_bits()) {
2344 if (BVCalleeSaved[Reg] || !PPC::VSRCRegClass.
contains(Reg) ||
2346 BVAllocatable.
reset(Reg);
2349 bool AllSpilledToReg =
true;
2350 unsigned LastVSRUsedForSpill = 0;
2351 for (
auto &CS : CSI) {
2352 if (BVAllocatable.
none())
2357 if (!PPC::G8RCRegClass.
contains(Reg)) {
2358 AllSpilledToReg =
false;
2364 if (LastVSRUsedForSpill != 0) {
2365 CS.setDstReg(LastVSRUsedForSpill);
2366 BVAllocatable.
reset(LastVSRUsedForSpill);
2367 LastVSRUsedForSpill = 0;
2371 unsigned VolatileVFReg = BVAllocatable.
find_first();
2372 if (VolatileVFReg < BVAllocatable.
size()) {
2373 CS.setDstReg(VolatileVFReg);
2374 LastVSRUsedForSpill = VolatileVFReg;
2376 AllSpilledToReg =
false;
2379 return AllSpilledToReg;
2391 bool CRSpilled =
false;
2395 VSRContainingGPRs.clear();
2400 if (
Info.isSpilledToReg()) {
2402 VSRContainingGPRs.FindAndConstruct(
Info.getDstReg()).second;
2403 assert(SpilledVSR.second == 0 &&
2404 "Can't spill more than two GPRs into VSR!");
2405 if (SpilledVSR.first == 0)
2406 SpilledVSR.first =
Info.getReg();
2408 SpilledVSR.second =
Info.getReg();
2416 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
2424 bool IsLiveIn =
MRI.isLiveIn(Reg);
2428 if (CRSpilled && IsCRField) {
2434 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2459 if (
I.isSpilledToReg()) {
2460 unsigned Dst =
I.getDstReg();
2465 if (VSRContainingGPRs[Dst].second != 0) {
2466 assert(Subtarget.hasP9Vector() &&
2467 "mtvsrdd is unavailable on pre-P9 targets.");
2473 }
else if (VSRContainingGPRs[Dst].second == 0) {
2474 assert(Subtarget.hasP8Vector() &&
2475 "Can't move GPR to VSR on pre-P8 targets.");
2479 TRI->getSubReg(Dst, PPC::sub_64))
2494 TII.storeRegToStackSlotNoUpd(
MBB,
MI, Reg, !IsLiveIn,
2495 I.getFrameIdx(), RC,
TRI);
2505static void restoreCRs(
bool is31,
bool CR2Spilled,
bool CR3Spilled,
2513 unsigned MoveReg = PPC::R12;
2518 CSI[CSIIndex].getFrameIdx()));
2520 unsigned RestoreOp = PPC::MTOCRF;
2539 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2541 if (
int CalleeAmt =
I->getOperand(1).getImm()) {
2544 unsigned StackReg =
is64Bit ? PPC::X1 : PPC::R1;
2545 unsigned TmpReg =
is64Bit ? PPC::X0 : PPC::R0;
2546 unsigned ADDIInstr =
is64Bit ? PPC::ADDI8 : PPC::ADDI;
2547 unsigned ADDInstr =
is64Bit ? PPC::ADD8 : PPC::ADD4;
2548 unsigned LISInstr =
is64Bit ? PPC::LIS8 : PPC::LIS;
2549 unsigned ORIInstr =
is64Bit ? PPC::ORI8 : PPC::ORI;
2552 if (isInt<16>(CalleeAmt)) {
2559 .
addImm(CalleeAmt >> 16);
2562 .
addImm(CalleeAmt & 0xFFFF);
2574 return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4;
2584 bool CR2Spilled =
false;
2585 bool CR3Spilled =
false;
2586 bool CR4Spilled =
false;
2587 unsigned CSIIndex = 0;
2598 for (
unsigned i = 0, e = CSI.
size(); i != e; ++i) {
2601 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2609 if (Reg == PPC::CR2) {
2615 }
else if (Reg == PPC::CR3) {
2618 }
else if (Reg == PPC::CR4) {
2624 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2626 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI,
2628 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2631 if (CSI[i].isSpilledToReg()) {
2633 unsigned Dst = CSI[i].getDstReg();
2638 if (VSRContainingGPRs[Dst].second != 0) {
2639 assert(Subtarget.hasP9Vector());
2640 NumPEReloadVSR += 2;
2642 VSRContainingGPRs[Dst].second)
2645 VSRContainingGPRs[Dst].first)
2647 }
else if (VSRContainingGPRs[Dst].second == 0) {
2648 assert(Subtarget.hasP8Vector());
2651 VSRContainingGPRs[Dst].first)
2667 TII.loadRegFromStackSlotNoUpd(
MBB,
I, Reg, CSI[i].getFrameIdx(), RC,
2674 "loadRegFromStackSlot didn't insert any code!");
2688 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2690 "Only set CR[2|3|4]Spilled on 32-bit SVR4.");
2692 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI, CSIIndex);
2699 return TOCSaveOffset;
2703 return FramePointerSaveOffset;
2707 return BasePointerSaveOffset;
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
typename CallsiteContextGraph< DerivedCCG, FuncTy, CallTy >::FuncInfo FuncInfo
static bool hasSpills(const MachineFunction &MF)
static unsigned computeCRSaveOffset(const PPCSubtarget &STI)
static void restoreCRs(bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, unsigned CSIIndex)
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
#define CALLEE_SAVED_FPRS
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
#define CALLEE_SAVED_GPRS32
#define CALLEE_SAVED_GPRS64
static unsigned computeLinkageSize(const PPCSubtarget &STI)
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
static bool isCalleeSavedCR(unsigned Reg)
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static bool hasNonRISpills(const MachineFunction &MF)
static bool spillsCR(const MachineFunction &MF)
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static void buildDefCFAReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg, const SystemZInstrInfo *ZII)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool test(unsigned Idx) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
size_type count() const
count - Returns the number of bits which are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
bool none() const
none - Returns true if none of the bits are set.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
An instruction for reading from memory.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
const MCRegisterInfo * getRegisterInfo() const
Describe properties that are true of each instruction in the target description file.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
MachineBasicBlock * getRestorePoint() const
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool hasTailCall() const
Returns true if the function contains a tail call.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
void setMaxCallFrameSize(unsigned S)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineBasicBlock * getSavePoint() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
This class contains meta information specific to a module.
const MCContext & getContext() const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
int64_t getOffset() const
Return the offset from the symbol in this operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
def_iterator def_begin(Register RegNo) const
static def_iterator def_end()
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
uint64_t getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
bool needsFP(const MachineFunction &MF) const
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
uint64_t getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void replaceFPWithRealFP(MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
PPCFrameLowering(const PPCSubtarget &STI)
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
uint64_t determineFrameLayoutAndUpdate(MachineFunction &MF, bool UseEstimate=false) const
Determine the frame layout and update the machine function.
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
uint64_t getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
uint64_t getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
int getTailCallSPDelta() const
const SmallVectorImpl< Register > & getMustSaveCRs() const
int getPICBasePointerSaveIndex() const
bool shrinkWrapDisabled() const
int getFramePointerSaveIndex() const
void addMustSaveCR(Register Reg)
void setBasePointerSaveIndex(int Idx)
bool hasNonRISpills() const
bool isLRStoreRequired() const
void setPICBasePointerSaveIndex(int Idx)
int getROPProtectionHashSaveIndex() const
unsigned getMinReservedArea() const
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function.
void setCRSpillFrameIndex(int idx)
int getBasePointerSaveIndex() const
void setFramePointerSaveIndex(int Idx)
bool hasBasePointer(const MachineFunction &MF) const
Register getBaseRegister(const MachineFunction &MF) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool is32BitELFABI() const
bool needsSwapsForVSXMemOps() const
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
const PPCTargetLowering * getTargetLowering() const override
const PPCInstrInfo * getInstrInfo() const override
unsigned getRedZoneSize() const
bool is64BitELFABI() const
const PPCTargetMachine & getTargetMachine() const
const PPCRegisterInfo * getRegisterInfo() const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
void forward()
Move the internal MBB iterator and update register states.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
bool isPositionIndependent() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
This struct is a compact representation of a valid (non-zero power of two) alignment.