33#define DEBUG_TYPE "framelowering"
34STATISTIC(NumPESpillVSR,
"Number of spills to vector in prologue");
35STATISTIC(NumPEReloadVSR,
"Number of reloads from vector in epilogue");
36STATISTIC(NumPrologProbed,
"Number of prologues probed");
40 cl::desc(
"Enable spills in prologue to vector registers."),
58 return STI.
isPPC64() ? -8U : -4U;
75 return STI.
isPPC64() ? -16U : -8U;
84 STI.getPlatformStackAlignment(), 0),
94 unsigned &NumEntries)
const {
97#define CALLEE_SAVED_FPRS \
119#define CALLEE_SAVED_GPRS32 \
140#define CALLEE_SAVED_GPRS64 \
161#define CALLEE_SAVED_VRS \
178 static const SpillSlot ELFOffsets32[] = {
213 static const SpillSlot ELFOffsets64[] = {
228 static const SpillSlot AIXOffsets64[] = {
232 NumEntries = std::size(ELFOffsets64);
237 NumEntries = std::size(ELFOffsets32);
244 NumEntries = std::size(AIXOffsets64);
248 NumEntries = std::size(AIXOffsets32);
285 bool UseEstimate)
const {
286 unsigned NewMaxCallFrameSize = 0;
288 &NewMaxCallFrameSize);
299 unsigned *NewMaxCallFrameSize)
const {
310 Align Alignment = std::max(TargetAlign, MaxAlign);
314 unsigned LR = RegInfo->getRARegister();
327 if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
337 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
342 maxCallFrameSize =
alignTo(maxCallFrameSize, Alignment);
345 if (NewMaxCallFrameSize)
346 *NewMaxCallFrameSize = maxCallFrameSize;
349 FrameSize += maxCallFrameSize;
352 FrameSize =
alignTo(FrameSize, Alignment);
387 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
388 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
393 unsigned BP8Reg = HasBP ? (
unsigned) PPC::X30 : FP8Reg;
402 switch (MO.getReg()) {
440 bool TwoUniqueRegsRequired,
452 assert (SR1 &&
"Asking for the second scratch register but not the first?");
495 for (
int i = 0; CSRegs[i]; ++i)
501 *SR1 = FirstScratchReg == -1 ? (
unsigned)PPC::NoRegister : FirstScratchReg;
508 int SecondScratchReg = BV.
find_next(*SR1);
509 if (SecondScratchReg != -1)
510 *SR2 = SecondScratchReg;
512 *SR2 = TwoUniqueRegsRequired ?
Register() : *SR1;
517 if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
534 bool HasBP =
RegInfo->hasBasePointer(MF);
536 int NegFrameSize = -FrameSize;
537 bool IsLargeFrame = !isInt<16>(NegFrameSize);
543 return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||
550 return findScratchRegister(TmpMBB,
false,
551 twoUniqueScratchRegsRequired(TmpMBB));
557 return findScratchRegister(TmpMBB,
true);
560bool PPCFrameLowering::stackUpdateCanBeMoved(
MachineFunction &MF)
const {
618 const bool HasFastMFLR = Subtarget.hasFastMFLR();
621 bool isPPC64 = Subtarget.
isPPC64();
625 assert((isSVR4ABI || Subtarget.
isAIXABI()) &&
"Unsupported PPC ABI.");
629 int64_t NegFrameSize = -FrameSize;
630 if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
641 bool MustSaveCR = !MustSaveCRs.
empty();
643 bool HasFP =
hasFP(MF);
645 bool HasRedZone = isPPC64 || !isSVR4ABI;
646 bool HasROPProtect = Subtarget.hasROPProtect();
647 bool HasPrivileged = Subtarget.hasPrivileged();
649 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
651 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
652 Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
653 Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
655 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
663 const MCInstrDesc& StoreUpdtIdxInst =
TII.get(isPPC64 ? PPC::STDUX
667 const MCInstrDesc& SubtractCarryingInst =
TII.get(isPPC64 ? PPC::SUBFC8
669 const MCInstrDesc& SubtractImmCarryingInst =
TII.get(isPPC64 ? PPC::SUBFIC8
671 const MCInstrDesc &MoveFromCondRegInst =
TII.get(isPPC64 ? PPC::MFCR8
673 const MCInstrDesc &StoreWordInst =
TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
675 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)
676 : (HasPrivileged ? PPC::HASHSTP : PPC::HASHST));
683 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
686 bool SingleScratchReg = findScratchRegister(
687 &
MBB,
false, twoUniqueScratchRegsRequired(&
MBB), &ScratchReg, &TempReg);
688 assert(SingleScratchReg &&
689 "Required number of registers not available in this block");
691 SingleScratchReg = ScratchReg == TempReg;
695 int64_t FPOffset = 0;
699 assert(FPIndex &&
"No Frame Pointer Save Slot!");
703 int64_t BPOffset = 0;
707 assert(BPIndex &&
"No Base Pointer Save Slot!");
711 int64_t PBPOffset = 0;
715 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
721 if (HasBP && MaxAlign > 1)
722 assert(
Log2(MaxAlign) < 16 &&
"Invalid alignment!");
726 bool isLargeFrame = !isInt<16>(NegFrameSize);
732 bool MovingStackUpdateDown =
false;
735 if (stackUpdateCanBeMoved(MF)) {
748 if (CSI.isSpilledToReg()) {
749 StackUpdateLoc =
MBBI;
750 MovingStackUpdateDown =
false;
754 int FrIdx = CSI.getFrameIdx();
763 MovingStackUpdateDown =
true;
767 StackUpdateLoc =
MBBI;
768 MovingStackUpdateDown =
false;
774 if (MovingStackUpdateDown) {
776 int FrIdx = CSI.getFrameIdx();
786 auto BuildMoveFromCR = [&]() {
787 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
792 assert(isPPC64 &&
"V2 ABI is 64-bit only.");
799 for (
unsigned CRfield : MustSaveCRs)
806 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
817 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR))
841 auto SaveLR = [&](int64_t
Offset) {
857 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
858 "ROP hash save offset out of range.");
859 assert(((ImmOffset & 0x7) == 0) &&
860 "ROP hash save offset must be 8 byte aligned.");
873 assert(HasRedZone &&
"A red zone is always available on PPC64");
890 if (HasBP && HasRedZone) {
901 (HasBP && MaxAlign > 1) || isLargeFrame;
909 (HasSTUX || !isInt<16>(FrameSize + LROffset)))
919 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
920 : PPC::PROBED_STACKALLOC_32))
934 if (HasBP && MaxAlign > 1) {
951 assert(!SingleScratchReg &&
"Only a single scratch reg available");
952 TII.materializeImmPostRA(
MBB,
MBBI, dl, TempReg, NegFrameSize);
962 }
else if (!isLargeFrame) {
963 BuildMI(
MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
968 TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, NegFrameSize);
979 assert(isELFv2ABI &&
"TOC saves in the prologue only supported on ELFv2");
987 assert(!isPPC64 &&
"A red zone is always available on PPC64");
1003 if (ScratchReg == PPC::R0) {
1012 .
addImm(FPOffset-LastOffset);
1013 LastOffset = FPOffset;
1024 .
addImm(PBPOffset-LastOffset);
1025 LastOffset = PBPOffset;
1035 .
addImm(BPOffset-LastOffset);
1036 LastOffset = BPOffset;
1080 .
addImm(FrameSize + FPOffset)
1085 .
addImm(FrameSize + PBPOffset)
1090 .
addImm(FrameSize + BPOffset)
1100 if (!HasSTUX &&
MustSaveLR && !HasFastMFLR && isInt<16>(FrameSize + LROffset))
1101 SaveLR(LROffset + FrameSize);
1111 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1125 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1134 unsigned Reg =
MRI->getDwarfRegNum(PPC::R30,
true);
1143 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1152 unsigned Reg =
MRI->getDwarfRegNum(LRReg,
true);
1166 if (!HasBP && needsCFI) {
1169 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1184 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM)
continue;
1188 if (PPC::CRBITRCRegClass.
contains(Reg))
1191 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
1196 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1202 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1206 Register CRReg = isELFv2ABI? Reg : PPC::CR2;
1208 nullptr,
MRI->getDwarfRegNum(CRReg,
true), CRSaveOffset));
1214 if (
I.isSpilledToReg()) {
1215 unsigned SpilledReg =
I.getDstReg();
1217 nullptr,
MRI->getDwarfRegNum(Reg,
true),
1218 MRI->getDwarfRegNum(SpilledReg,
true)));
1226 if (MovingStackUpdateDown)
1230 nullptr,
MRI->getDwarfRegNum(Reg,
true),
Offset));
1240 bool isPPC64 = Subtarget.
isPPC64();
1249 int Opc =
MI.getOpcode();
1250 return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;
1252 if (StackAllocMIPos == PrologMBB.
end())
1258 int64_t NegFrameSize =
MI.getOperand(2).getImm();
1260 int64_t NegProbeSize = -(int64_t)ProbeSize;
1261 assert(isInt<32>(NegProbeSize) &&
"Unhandled probe size");
1262 int64_t NumBlocks = NegFrameSize / NegProbeSize;
1263 int64_t NegResidualSize = NegFrameSize % NegProbeSize;
1264 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1265 Register ScratchReg =
MI.getOperand(0).getReg();
1272 const MCInstrDesc &CopyInst =
TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
1276 unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1285 unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1292 auto CanUseDForm = [](int64_t Imm) {
return isInt<16>(Imm) && Imm % 4 == 0; };
1297 assert(isInt<32>(Imm) &&
"Unhandled imm");
1312 Register NegSizeReg,
bool UseDForm,
1354 assert(HasBP &&
"The function is supposed to have base pointer when its "
1355 "stack is realigned.");
1363 "Probe size should be larger or equal to the size of red-zone so "
1364 "that red-zone is not clobbered by probing.");
1370 NegProbeSize = std::max(NegProbeSize, -((int64_t)1 << 15));
1371 assert(isInt<16>(NegProbeSize) &&
1372 "NegProbeSize should be materializable by DForm");
1389 MF.
insert(MBBInsertPoint, ProbeLoopBodyMBB);
1391 MF.
insert(MBBInsertPoint, ProbeExitMBB);
1394 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1395 allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->
end(), 0, ScratchReg,
false,
1400 BuildMI(*ProbeExitMBB, ProbeExitMBB->
end(),
DL, CopyInst, TempReg)
1408 BuildMI(&
MBB,
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), ScratchReg)
1425 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1426 allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->
end(), NegProbeSize,
1427 0,
true , BackChainPointer);
1428 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),
1432 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),
1439 .
addMBB(ProbeLoopBodyMBB);
1446 return ProbeExitMBB;
1451 if (HasBP && MaxAlign > 1) {
1464 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),
1468 MaterializeImm(*CurrentMBB, {
MI}, NegFrameSize, ScratchReg);
1469 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
1473 CurrentMBB = probeRealignedStack(*CurrentMBB, {
MI}, ScratchReg, FPReg);
1481 buildDefCFA(*CurrentMBB, {
MI}, FPReg, 0);
1483 if (NegResidualSize) {
1484 bool ResidualUseDForm = CanUseDForm(NegResidualSize);
1485 if (!ResidualUseDForm)
1486 MaterializeImm(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg);
1487 allocateAndProbe(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg,
1488 ResidualUseDForm, FPReg);
1490 bool UseDForm = CanUseDForm(NegProbeSize);
1492 if (NumBlocks < 3) {
1494 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1495 for (
int i = 0; i < NumBlocks; ++i)
1496 allocateAndProbe(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg, UseDForm,
1507 MaterializeImm(*CurrentMBB, {
MI}, NumBlocks, ScratchReg);
1508 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
1511 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1516 MF.
insert(MBBInsertPoint, LoopMBB);
1518 MF.
insert(MBBInsertPoint, ExitMBB);
1520 allocateAndProbe(*LoopMBB, LoopMBB->
end(), NegProbeSize, ScratchReg,
1522 BuildMI(LoopMBB,
DL,
TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
1527 ExitMBB->
splice(ExitMBB->
end(), CurrentMBB,
1542 MI.eraseFromParent();
1551 dl =
MBBI->getDebugLoc();
1563 bool isPPC64 = Subtarget.
isPPC64();
1569 bool MustSaveCR = !MustSaveCRs.
empty();
1571 bool HasFP =
hasFP(MF);
1574 bool HasROPProtect = Subtarget.hasROPProtect();
1575 bool HasPrivileged = Subtarget.hasPrivileged();
1577 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1579 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1581 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
1586 const MCInstrDesc& LoadImmShiftedInst =
TII.get( isPPC64 ? PPC::LIS8
1598 const MCInstrDesc& MoveToCRInst =
TII.get( isPPC64 ? PPC::MTOCRF8
1601 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)
1602 : (HasPrivileged ? PPC::HASHCHKP : PPC::HASHCHK));
1605 int64_t FPOffset = 0;
1608 bool SingleScratchReg = findScratchRegister(&
MBB,
true,
false, &ScratchReg,
1610 assert(SingleScratchReg &&
1611 "Could not find an available scratch register");
1613 SingleScratchReg = ScratchReg == TempReg;
1617 assert(FPIndex &&
"No Frame Pointer Save Slot!");
1621 int64_t BPOffset = 0;
1624 assert(BPIndex &&
"No Base Pointer Save Slot!");
1628 int64_t PBPOffset = 0;
1631 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1637 if (IsReturnBlock) {
1638 unsigned RetOpcode =
MBBI->getOpcode();
1639 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1640 RetOpcode == PPC::TCRETURNdi ||
1641 RetOpcode == PPC::TCRETURNai ||
1642 RetOpcode == PPC::TCRETURNri8 ||
1643 RetOpcode == PPC::TCRETURNdi8 ||
1644 RetOpcode == PPC::TCRETURNai8;
1649 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1651 int StackAdj = StackAdjust.
getImm();
1652 int Delta = StackAdj - MaxTCRetDelta;
1653 assert((Delta >= 0) &&
"Delta must be positive");
1654 if (MaxTCRetDelta>0)
1655 FrameSize += (StackAdj +Delta);
1657 FrameSize += StackAdj;
1663 bool isLargeFrame = !isInt<16>(FrameSize);
1677 unsigned RBReg = SPReg;
1685 if (stackUpdateCanBeMoved(MF)) {
1690 if (CSI.isSpilledToReg()) {
1691 StackUpdateLoc =
MBBI;
1694 int FrIdx = CSI.getFrameIdx();
1706 StackUpdateLoc =
MBBI;
1719 if (HasRedZone && HasBP) {
1729 assert(HasFP &&
"Expecting a valid frame pointer.");
1732 if (!isLargeFrame) {
1736 TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, FrameSize);
1744 BuildMI(
MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1750 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1751 "Local offsets should be negative");
1753 FPOffset += FrameSize;
1754 BPOffset += FrameSize;
1755 PBPOffset += FrameSize;
1773 assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1780 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
1783 assert(HasRedZone &&
"Expecting red zone");
1787 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1796 bool LoadedLR =
false;
1797 if (
MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1804 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR)) {
1805 assert(RBReg == SPReg &&
"Should be using SP as a base register");
1814 if (HasRedZone || RBReg == SPReg)
1836 if (RBReg != SPReg || SPAdd != 0) {
1837 assert(!HasRedZone &&
"This should not happen with red zone");
1848 assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1863 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1870 if (HasROPProtect) {
1873 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
1874 "ROP hash check location offset out of range.");
1875 assert(((ImmOffset & 0x7) == 0) &&
1876 "ROP hash check location offset must be 8 byte aligned.");
1887 if (IsReturnBlock) {
1888 unsigned RetOpcode =
MBBI->getOpcode();
1890 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1895 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1900 .
addImm(CallerAllocatedAmt >> 16);
1903 .
addImm(CallerAllocatedAmt & 0xFFFF);
1910 createTailCallBranchInstr(
MBB);
1931 unsigned RetOpcode =
MBBI->getOpcode();
1932 if (RetOpcode == PPC::TCRETURNdi) {
1943 }
else if (RetOpcode == PPC::TCRETURNri) {
1945 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1947 }
else if (RetOpcode == PPC::TCRETURNai) {
1951 }
else if (RetOpcode == PPC::TCRETURNdi8) {
1962 }
else if (RetOpcode == PPC::TCRETURNri8) {
1964 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1966 }
else if (RetOpcode == PPC::TCRETURNai8) {
1982 SavedRegs.
reset(PPC::VSRp26);
1983 SavedRegs.
reset(PPC::VSRp27);
1984 SavedRegs.
reset(PPC::VSRp28);
1985 SavedRegs.
reset(PPC::VSRp29);
1986 SavedRegs.
reset(PPC::VSRp30);
1987 SavedRegs.
reset(PPC::VSRp31);
1991 unsigned LR = RegInfo->getRARegister();
1993 SavedRegs.
reset(LR);
1997 const bool isPPC64 = Subtarget.
isPPC64();
2031 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
2035 SavedRegs.
reset(PPC::R30);
2050 if ((SavedRegs.
test(PPC::CR2) || SavedRegs.
test(PPC::CR3) ||
2051 SavedRegs.
test(PPC::CR4))) {
2053 const int64_t SpillOffset =
2076 createTailCallBranchInstr(
MBB);
2081 if (CSI.empty() && !
needsFP(MF)) {
2086 unsigned MinGPR = PPC::R31;
2087 unsigned MinG8R = PPC::X31;
2088 unsigned MinFPR = PPC::F31;
2089 unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
2091 bool HasGPSaveArea =
false;
2092 bool HasG8SaveArea =
false;
2093 bool HasFPSaveArea =
false;
2094 bool HasVRSaveArea =
false;
2104 (Reg != PPC::X2 && Reg != PPC::R2)) &&
2105 "Not expecting to try to spill R2 in a function that must save TOC");
2106 if (PPC::GPRCRegClass.
contains(Reg)) {
2107 HasGPSaveArea =
true;
2114 }
else if (PPC::G8RCRegClass.
contains(Reg)) {
2115 HasG8SaveArea =
true;
2122 }
else if (PPC::F8RCRegClass.
contains(Reg)) {
2123 HasFPSaveArea =
true;
2130 }
else if (PPC::CRBITRCRegClass.
contains(Reg) ||
2133 }
else if (PPC::VRRCRegClass.
contains(Reg) ||
2134 PPC::SPERCRegClass.
contains(Reg)) {
2137 HasVRSaveArea =
true;
2152 int64_t LowerBound = 0;
2158 LowerBound = TCSPDelta;
2163 if (HasFPSaveArea) {
2164 for (
unsigned i = 0, e = FPRegs.
size(); i != e; ++i) {
2165 int FI = FPRegs[i].getFrameIdx();
2170 LowerBound -= (31 -
TRI->getEncodingValue(MinFPR) + 1) * 8;
2177 assert(FI &&
"No Frame Pointer Save Slot!");
2180 HasGPSaveArea =
true;
2185 assert(FI &&
"No PIC Base Pointer Save Slot!");
2188 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
2189 HasGPSaveArea =
true;
2195 assert(FI &&
"No Base Pointer Save Slot!");
2199 if (PPC::G8RCRegClass.
contains(BP)) {
2200 MinG8R = std::min<unsigned>(MinG8R, BP);
2201 HasG8SaveArea =
true;
2202 }
else if (PPC::GPRCRegClass.
contains(BP)) {
2203 MinGPR = std::min<unsigned>(MinGPR, BP);
2204 HasGPSaveArea =
true;
2210 if (HasGPSaveArea || HasG8SaveArea) {
2213 for (
unsigned i = 0, e = GPRegs.
size(); i != e; ++i) {
2214 if (!GPRegs[i].isSpilledToReg()) {
2215 int FI = GPRegs[i].getFrameIdx();
2222 for (
unsigned i = 0, e = G8Regs.
size(); i != e; ++i) {
2223 if (!G8Regs[i].isSpilledToReg()) {
2224 int FI = G8Regs[i].getFrameIdx();
2230 std::min<unsigned>(
TRI->getEncodingValue(MinGPR),
2231 TRI->getEncodingValue(MinG8R));
2233 const unsigned GPRegSize = Subtarget.
isPPC64() ? 8 : 4;
2234 LowerBound -= (31 - MinReg + 1) * GPRegSize;
2244 for (
const auto &CSInfo : CSI) {
2245 if (CSInfo.getReg() == PPC::CR2) {
2246 int FI = CSInfo.getFrameIdx();
2257 if (HasVRSaveArea) {
2263 assert(LowerBound <= 0 &&
"Expect LowerBound have a non-positive value!");
2264 LowerBound &= ~(15);
2266 for (
unsigned i = 0, e = VRegs.
size(); i != e; ++i) {
2267 int FI = VRegs[i].getFrameIdx();
2294 bool NeedSpills = Subtarget.hasSPE() ? !isInt<8>(StackSize) : !isInt<16>(StackSize);
2302 unsigned Size =
TRI.getSpillSize(RC);
2303 Align Alignment =
TRI.getSpillAlign(RC);
2324 std::vector<CalleeSavedInfo> &CSI)
const {
2333 if (Subtarget.hasSPE()) {
2338 for (
auto &CalleeSaveReg : CSI) {
2339 const MCPhysReg &Reg = CalleeSaveReg.getReg();
2341 const MCPhysReg &Higher = RegInfo->getSubReg(Reg, 2);
2345 if (
MRI.isPhysRegModified(Higher)) {
2350 CSI.erase(CSI.begin() +
Idx);
2366 for (
unsigned i = 0; CSRegs[i]; ++i)
2367 BVCalleeSaved.
set(CSRegs[i]);
2369 for (
unsigned Reg : BVAllocatable.
set_bits()) {
2372 if (BVCalleeSaved[Reg] || !PPC::VSRCRegClass.
contains(Reg) ||
2373 MRI.isPhysRegUsed(Reg))
2374 BVAllocatable.
reset(Reg);
2377 bool AllSpilledToReg =
true;
2378 unsigned LastVSRUsedForSpill = 0;
2379 for (
auto &CS : CSI) {
2380 if (BVAllocatable.
none())
2385 if (!PPC::G8RCRegClass.
contains(Reg)) {
2386 AllSpilledToReg =
false;
2392 if (LastVSRUsedForSpill != 0) {
2393 CS.setDstReg(LastVSRUsedForSpill);
2394 BVAllocatable.
reset(LastVSRUsedForSpill);
2395 LastVSRUsedForSpill = 0;
2399 unsigned VolatileVFReg = BVAllocatable.
find_first();
2400 if (VolatileVFReg < BVAllocatable.
size()) {
2401 CS.setDstReg(VolatileVFReg);
2402 LastVSRUsedForSpill = VolatileVFReg;
2404 AllSpilledToReg =
false;
2407 return AllSpilledToReg;
2419 bool CRSpilled =
false;
2423 VSRContainingGPRs.clear();
2428 if (
Info.isSpilledToReg()) {
2430 VSRContainingGPRs.FindAndConstruct(
Info.getDstReg()).second;
2431 assert(SpilledVSR.second == 0 &&
2432 "Can't spill more than two GPRs into VSR!");
2433 if (SpilledVSR.first == 0)
2434 SpilledVSR.first =
Info.getReg();
2436 SpilledVSR.second =
Info.getReg();
2444 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
2452 bool IsLiveIn =
MRI.isLiveIn(Reg);
2456 if (CRSpilled && IsCRField) {
2462 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2487 if (
I.isSpilledToReg()) {
2488 unsigned Dst =
I.getDstReg();
2493 if (VSRContainingGPRs[Dst].second != 0) {
2494 assert(Subtarget.hasP9Vector() &&
2495 "mtvsrdd is unavailable on pre-P9 targets.");
2501 }
else if (VSRContainingGPRs[Dst].second == 0) {
2502 assert(Subtarget.hasP8Vector() &&
2503 "Can't move GPR to VSR on pre-P8 targets.");
2507 TRI->getSubReg(Dst, PPC::sub_64))
2522 TII.storeRegToStackSlotNoUpd(
MBB,
MI, Reg, !IsLiveIn,
2523 I.getFrameIdx(), RC,
TRI);
2533static void restoreCRs(
bool is31,
bool CR2Spilled,
bool CR3Spilled,
2541 unsigned MoveReg = PPC::R12;
2546 CSI[CSIIndex].getFrameIdx()));
2548 unsigned RestoreOp = PPC::MTOCRF;
2567 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2569 if (
int CalleeAmt =
I->getOperand(1).getImm()) {
2572 unsigned StackReg =
is64Bit ? PPC::X1 : PPC::R1;
2573 unsigned TmpReg =
is64Bit ? PPC::X0 : PPC::R0;
2574 unsigned ADDIInstr =
is64Bit ? PPC::ADDI8 : PPC::ADDI;
2575 unsigned ADDInstr =
is64Bit ? PPC::ADD8 : PPC::ADD4;
2576 unsigned LISInstr =
is64Bit ? PPC::LIS8 : PPC::LIS;
2577 unsigned ORIInstr =
is64Bit ? PPC::ORI8 : PPC::ORI;
2580 if (isInt<16>(CalleeAmt)) {
2587 .
addImm(CalleeAmt >> 16);
2590 .
addImm(CalleeAmt & 0xFFFF);
2602 return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4;
2612 bool CR2Spilled =
false;
2613 bool CR3Spilled =
false;
2614 bool CR4Spilled =
false;
2615 unsigned CSIIndex = 0;
2626 for (
unsigned i = 0, e = CSI.
size(); i != e; ++i) {
2629 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2637 if (Reg == PPC::CR2) {
2643 }
else if (Reg == PPC::CR3) {
2646 }
else if (Reg == PPC::CR4) {
2652 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2654 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI,
2656 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2659 if (CSI[i].isSpilledToReg()) {
2661 unsigned Dst = CSI[i].getDstReg();
2666 if (VSRContainingGPRs[Dst].second != 0) {
2667 assert(Subtarget.hasP9Vector());
2668 NumPEReloadVSR += 2;
2670 VSRContainingGPRs[Dst].second)
2673 VSRContainingGPRs[Dst].first)
2675 }
else if (VSRContainingGPRs[Dst].second == 0) {
2676 assert(Subtarget.hasP8Vector());
2679 VSRContainingGPRs[Dst].first)
2695 TII.loadRegFromStackSlotNoUpd(
MBB,
I, Reg, CSI[i].getFrameIdx(), RC,
2702 "loadRegFromStackSlot didn't insert any code!");
2716 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2718 "Only set CR[2|3|4]Spilled on 32-bit SVR4.");
2720 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI, CSIIndex);
2727 return TOCSaveOffset;
2731 return FramePointerSaveOffset;
2735 return BasePointerSaveOffset;
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
static bool hasSpills(const MachineFunction &MF)
static unsigned computeCRSaveOffset(const PPCSubtarget &STI)
static void restoreCRs(bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, unsigned CSIIndex)
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
#define CALLEE_SAVED_FPRS
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
#define CALLEE_SAVED_GPRS32
#define CALLEE_SAVED_GPRS64
static unsigned computeLinkageSize(const PPCSubtarget &STI)
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
static bool isCalleeSavedCR(unsigned Reg)
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static bool hasNonRISpills(const MachineFunction &MF)
static bool spillsCR(const MachineFunction &MF)
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static void buildDefCFAReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg, const SystemZInstrInfo *ZII)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool test(unsigned Idx) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
size_type count() const
count - Returns the number of bits which are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
bool none() const
none - Returns true if none of the bits are set.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
An instruction for reading from memory.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
const MCRegisterInfo * getRegisterInfo() const
Describe properties that are true of each instruction in the target description file.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
MachineBasicBlock * getRestorePoint() const
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool hasTailCall() const
Returns true if the function contains a tail call.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
void setMaxCallFrameSize(unsigned S)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineBasicBlock * getSavePoint() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
This class contains meta information specific to a module.
const MCContext & getContext() const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
int64_t getOffset() const
Return the offset from the symbol in this operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
def_iterator def_begin(Register RegNo) const
static def_iterator def_end()
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
uint64_t getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
bool needsFP(const MachineFunction &MF) const
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
uint64_t getStackThreshold() const override
getStackThreshold - Return the maximum stack size
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
uint64_t getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void replaceFPWithRealFP(MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
PPCFrameLowering(const PPCSubtarget &STI)
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
uint64_t determineFrameLayoutAndUpdate(MachineFunction &MF, bool UseEstimate=false) const
Determine the frame layout and update the machine function.
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
uint64_t getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
uint64_t getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
int getTailCallSPDelta() const
const SmallVectorImpl< Register > & getMustSaveCRs() const
int getPICBasePointerSaveIndex() const
bool shrinkWrapDisabled() const
int getFramePointerSaveIndex() const
void addMustSaveCR(Register Reg)
void setBasePointerSaveIndex(int Idx)
bool hasNonRISpills() const
bool isLRStoreRequired() const
void setPICBasePointerSaveIndex(int Idx)
int getROPProtectionHashSaveIndex() const
unsigned getMinReservedArea() const
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function.
void setCRSpillFrameIndex(int idx)
int getBasePointerSaveIndex() const
void setFramePointerSaveIndex(int Idx)
bool hasBasePointer(const MachineFunction &MF) const
Register getBaseRegister(const MachineFunction &MF) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool is32BitELFABI() const
bool needsSwapsForVSXMemOps() const
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
const PPCTargetLowering * getTargetLowering() const override
const PPCInstrInfo * getInstrInfo() const override
unsigned getRedZoneSize() const
bool is64BitELFABI() const
const PPCTargetMachine & getTargetMachine() const
const PPCRegisterInfo * getRegisterInfo() const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void backward()
Update internal register state and move MBB iterator backwards.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual uint64_t getStackThreshold() const
getStackThreshold - Return the maximum stack size
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
bool isPositionIndependent() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
This struct is a compact representation of a valid (non-zero power of two) alignment.