33#define DEBUG_TYPE "framelowering"
34STATISTIC(NumPESpillVSR,
"Number of spills to vector in prologue");
35STATISTIC(NumPEReloadVSR,
"Number of reloads from vector in epilogue");
36STATISTIC(NumPrologProbed,
"Number of prologues probed");
40 cl::desc(
"Enable spills in prologue to vector registers."),
58 return STI.
isPPC64() ? -8U : -4U;
75 return STI.
isPPC64() ? -16U : -8U;
84 STI.getPlatformStackAlignment(), 0),
94 unsigned &NumEntries)
const {
97#define CALLEE_SAVED_FPRS \
119#define CALLEE_SAVED_GPRS32 \
140#define CALLEE_SAVED_GPRS64 \
161#define CALLEE_SAVED_VRS \
178 static const SpillSlot ELFOffsets32[] = {
213 static const SpillSlot ELFOffsets64[] = {
228 static const SpillSlot AIXOffsets64[] = {
232 NumEntries = std::size(ELFOffsets64);
237 NumEntries = std::size(ELFOffsets32);
244 NumEntries = std::size(AIXOffsets64);
248 NumEntries = std::size(AIXOffsets32);
285 bool UseEstimate)
const {
286 unsigned NewMaxCallFrameSize = 0;
288 &NewMaxCallFrameSize);
299 unsigned *NewMaxCallFrameSize)
const {
310 Align Alignment = std::max(TargetAlign, MaxAlign);
314 unsigned LR = RegInfo->getRARegister();
328 if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
338 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
343 maxCallFrameSize =
alignTo(maxCallFrameSize, Alignment);
346 if (NewMaxCallFrameSize)
347 *NewMaxCallFrameSize = maxCallFrameSize;
350 FrameSize += maxCallFrameSize;
353 FrameSize =
alignTo(FrameSize, Alignment);
391 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
392 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
397 unsigned BP8Reg = HasBP ? (
unsigned) PPC::X30 : FP8Reg;
406 switch (MO.getReg()) {
444 bool TwoUniqueRegsRequired,
456 assert (SR1 &&
"Asking for the second scratch register but not the first?");
499 for (
int i = 0; CSRegs[i]; ++i)
505 *SR1 = FirstScratchReg == -1 ? (
unsigned)PPC::NoRegister : FirstScratchReg;
512 int SecondScratchReg = BV.
find_next(*SR1);
513 if (SecondScratchReg != -1)
514 *SR2 = SecondScratchReg;
516 *SR2 = TwoUniqueRegsRequired ?
Register() : *SR1;
521 if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
538 bool HasBP =
RegInfo->hasBasePointer(MF);
540 int NegFrameSize = -FrameSize;
541 bool IsLargeFrame = !isInt<16>(NegFrameSize);
547 return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||
554 return findScratchRegister(TmpMBB,
false,
555 twoUniqueScratchRegsRequired(TmpMBB));
561 return findScratchRegister(TmpMBB,
true);
564bool PPCFrameLowering::stackUpdateCanBeMoved(
MachineFunction &MF)
const {
622 const bool HasFastMFLR = Subtarget.hasFastMFLR();
625 bool isPPC64 = Subtarget.
isPPC64();
629 assert((isSVR4ABI || Subtarget.
isAIXABI()) &&
"Unsupported PPC ABI.");
633 int64_t NegFrameSize = -FrameSize;
634 if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
645 bool MustSaveCR = !MustSaveCRs.
empty();
647 bool HasFP =
hasFP(MF);
649 bool HasRedZone = isPPC64 || !isSVR4ABI;
650 bool HasROPProtect = Subtarget.hasROPProtect();
651 bool HasPrivileged = Subtarget.hasPrivileged();
653 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
655 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
656 Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
657 Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
659 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
667 const MCInstrDesc& StoreUpdtIdxInst =
TII.get(isPPC64 ? PPC::STDUX
671 const MCInstrDesc& SubtractCarryingInst =
TII.get(isPPC64 ? PPC::SUBFC8
673 const MCInstrDesc& SubtractImmCarryingInst =
TII.get(isPPC64 ? PPC::SUBFIC8
675 const MCInstrDesc &MoveFromCondRegInst =
TII.get(isPPC64 ? PPC::MFCR8
677 const MCInstrDesc &StoreWordInst =
TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
679 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)
680 : (HasPrivileged ? PPC::HASHSTP : PPC::HASHST));
687 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
690 bool SingleScratchReg = findScratchRegister(
691 &
MBB,
false, twoUniqueScratchRegsRequired(&
MBB), &ScratchReg, &TempReg);
692 assert(SingleScratchReg &&
693 "Required number of registers not available in this block");
695 SingleScratchReg = ScratchReg == TempReg;
699 int64_t FPOffset = 0;
703 assert(FPIndex &&
"No Frame Pointer Save Slot!");
707 int64_t BPOffset = 0;
711 assert(BPIndex &&
"No Base Pointer Save Slot!");
715 int64_t PBPOffset = 0;
719 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
725 if (HasBP && MaxAlign > 1)
726 assert(
Log2(MaxAlign) < 16 &&
"Invalid alignment!");
730 bool isLargeFrame = !isInt<16>(NegFrameSize);
736 bool MovingStackUpdateDown =
false;
739 if (stackUpdateCanBeMoved(MF)) {
752 if (CSI.isSpilledToReg()) {
753 StackUpdateLoc =
MBBI;
754 MovingStackUpdateDown =
false;
758 int FrIdx = CSI.getFrameIdx();
767 MovingStackUpdateDown =
true;
771 StackUpdateLoc =
MBBI;
772 MovingStackUpdateDown =
false;
778 if (MovingStackUpdateDown) {
780 int FrIdx = CSI.getFrameIdx();
790 auto BuildMoveFromCR = [&]() {
791 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
796 assert(isPPC64 &&
"V2 ABI is 64-bit only.");
803 for (
unsigned CRfield : MustSaveCRs)
810 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
821 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR))
845 auto SaveLR = [&](int64_t
Offset) {
861 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
862 "ROP hash save offset out of range.");
863 assert(((ImmOffset & 0x7) == 0) &&
864 "ROP hash save offset must be 8 byte aligned.");
877 assert(HasRedZone &&
"A red zone is always available on PPC64");
894 if (HasBP && HasRedZone) {
905 (HasBP && MaxAlign > 1) || isLargeFrame;
913 (HasSTUX || !isInt<16>(FrameSize + LROffset)))
923 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
924 : PPC::PROBED_STACKALLOC_32))
938 if (HasBP && MaxAlign > 1) {
955 assert(!SingleScratchReg &&
"Only a single scratch reg available");
956 TII.materializeImmPostRA(
MBB,
MBBI, dl, TempReg, NegFrameSize);
966 }
else if (!isLargeFrame) {
967 BuildMI(
MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
972 TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, NegFrameSize);
983 assert(isELFv2ABI &&
"TOC saves in the prologue only supported on ELFv2");
991 assert(!isPPC64 &&
"A red zone is always available on PPC64");
1007 if (ScratchReg == PPC::R0) {
1016 .
addImm(FPOffset-LastOffset);
1017 LastOffset = FPOffset;
1028 .
addImm(PBPOffset-LastOffset);
1029 LastOffset = PBPOffset;
1039 .
addImm(BPOffset-LastOffset);
1040 LastOffset = BPOffset;
1084 .
addImm(FrameSize + FPOffset)
1089 .
addImm(FrameSize + PBPOffset)
1094 .
addImm(FrameSize + BPOffset)
1104 if (!HasSTUX &&
MustSaveLR && !HasFastMFLR && isInt<16>(FrameSize + LROffset))
1105 SaveLR(LROffset + FrameSize);
1115 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1129 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1138 unsigned Reg =
MRI->getDwarfRegNum(PPC::R30,
true);
1147 unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1156 unsigned Reg =
MRI->getDwarfRegNum(LRReg,
true);
1170 if (!HasBP && needsCFI) {
1173 unsigned Reg =
MRI->getDwarfRegNum(FPReg,
true);
1188 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM)
continue;
1192 if (PPC::CRBITRCRegClass.
contains(Reg))
1195 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
1200 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1204 Register CRReg = isELFv2ABI? Reg : PPC::CR2;
1206 nullptr,
MRI->getDwarfRegNum(CRReg,
true), CRSaveOffset));
1212 if (
I.isSpilledToReg()) {
1213 unsigned SpilledReg =
I.getDstReg();
1215 nullptr,
MRI->getDwarfRegNum(Reg,
true),
1216 MRI->getDwarfRegNum(SpilledReg,
true)));
1224 if (MovingStackUpdateDown)
1228 nullptr,
MRI->getDwarfRegNum(Reg,
true),
Offset));
1238 bool isPPC64 = Subtarget.
isPPC64();
1247 int Opc =
MI.getOpcode();
1248 return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;
1250 if (StackAllocMIPos == PrologMBB.
end())
1256 int64_t NegFrameSize =
MI.getOperand(2).getImm();
1258 int64_t NegProbeSize = -(int64_t)ProbeSize;
1259 assert(isInt<32>(NegProbeSize) &&
"Unhandled probe size");
1260 int64_t NumBlocks = NegFrameSize / NegProbeSize;
1261 int64_t NegResidualSize = NegFrameSize % NegProbeSize;
1262 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1263 Register ScratchReg =
MI.getOperand(0).getReg();
1270 const MCInstrDesc &CopyInst =
TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
1274 unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1283 unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1290 auto CanUseDForm = [](int64_t Imm) {
return isInt<16>(Imm) && Imm % 4 == 0; };
1295 assert(isInt<32>(Imm) &&
"Unhandled imm");
1310 Register NegSizeReg,
bool UseDForm,
1352 assert(HasBP &&
"The function is supposed to have base pointer when its "
1353 "stack is realigned.");
1361 "Probe size should be larger or equal to the size of red-zone so "
1362 "that red-zone is not clobbered by probing.");
1368 NegProbeSize = std::max(NegProbeSize, -((int64_t)1 << 15));
1369 assert(isInt<16>(NegProbeSize) &&
1370 "NegProbeSize should be materializable by DForm");
1387 MF.
insert(MBBInsertPoint, ProbeLoopBodyMBB);
1389 MF.
insert(MBBInsertPoint, ProbeExitMBB);
1392 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1393 allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->
end(), 0, ScratchReg,
false,
1398 BuildMI(*ProbeExitMBB, ProbeExitMBB->
end(),
DL, CopyInst, TempReg)
1406 BuildMI(&
MBB,
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), ScratchReg)
1423 Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1424 allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->
end(), NegProbeSize,
1425 0,
true , BackChainPointer);
1426 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),
1430 BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),
1437 .
addMBB(ProbeLoopBodyMBB);
1443 return ProbeExitMBB;
1448 if (HasBP && MaxAlign > 1) {
1461 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),
1465 MaterializeImm(*CurrentMBB, {
MI}, NegFrameSize, ScratchReg);
1466 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
1470 CurrentMBB = probeRealignedStack(*CurrentMBB, {
MI}, ScratchReg, FPReg);
1478 buildDefCFA(*CurrentMBB, {
MI}, FPReg, 0);
1480 if (NegResidualSize) {
1481 bool ResidualUseDForm = CanUseDForm(NegResidualSize);
1482 if (!ResidualUseDForm)
1483 MaterializeImm(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg);
1484 allocateAndProbe(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg,
1485 ResidualUseDForm, FPReg);
1487 bool UseDForm = CanUseDForm(NegProbeSize);
1489 if (NumBlocks < 3) {
1491 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1492 for (
int i = 0; i < NumBlocks; ++i)
1493 allocateAndProbe(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg, UseDForm,
1504 MaterializeImm(*CurrentMBB, {
MI}, NumBlocks, ScratchReg);
1505 BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
1508 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1513 MF.
insert(MBBInsertPoint, LoopMBB);
1515 MF.
insert(MBBInsertPoint, ExitMBB);
1517 allocateAndProbe(*LoopMBB, LoopMBB->
end(), NegProbeSize, ScratchReg,
1519 BuildMI(LoopMBB,
DL,
TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
1524 ExitMBB->
splice(ExitMBB->
end(), CurrentMBB,
1538 MI.eraseFromParent();
1547 dl =
MBBI->getDebugLoc();
1559 bool isPPC64 = Subtarget.
isPPC64();
1565 bool MustSaveCR = !MustSaveCRs.
empty();
1567 bool HasFP =
hasFP(MF);
1570 bool HasROPProtect = Subtarget.hasROPProtect();
1571 bool HasPrivileged = Subtarget.hasPrivileged();
1573 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1575 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1577 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
1582 const MCInstrDesc& LoadImmShiftedInst =
TII.get( isPPC64 ? PPC::LIS8
1594 const MCInstrDesc& MoveToCRInst =
TII.get( isPPC64 ? PPC::MTOCRF8
1597 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)
1598 : (HasPrivileged ? PPC::HASHCHKP : PPC::HASHCHK));
1601 int64_t FPOffset = 0;
1604 bool SingleScratchReg = findScratchRegister(&
MBB,
true,
false, &ScratchReg,
1606 assert(SingleScratchReg &&
1607 "Could not find an available scratch register");
1609 SingleScratchReg = ScratchReg == TempReg;
1613 assert(FPIndex &&
"No Frame Pointer Save Slot!");
1617 int64_t BPOffset = 0;
1620 assert(BPIndex &&
"No Base Pointer Save Slot!");
1624 int64_t PBPOffset = 0;
1627 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1633 if (IsReturnBlock) {
1634 unsigned RetOpcode =
MBBI->getOpcode();
1635 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1636 RetOpcode == PPC::TCRETURNdi ||
1637 RetOpcode == PPC::TCRETURNai ||
1638 RetOpcode == PPC::TCRETURNri8 ||
1639 RetOpcode == PPC::TCRETURNdi8 ||
1640 RetOpcode == PPC::TCRETURNai8;
1645 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1647 int StackAdj = StackAdjust.
getImm();
1648 int Delta = StackAdj - MaxTCRetDelta;
1649 assert((Delta >= 0) &&
"Delta must be positive");
1650 if (MaxTCRetDelta>0)
1651 FrameSize += (StackAdj +Delta);
1653 FrameSize += StackAdj;
1659 bool isLargeFrame = !isInt<16>(FrameSize);
1673 unsigned RBReg = SPReg;
1681 if (stackUpdateCanBeMoved(MF)) {
1686 if (CSI.isSpilledToReg()) {
1687 StackUpdateLoc =
MBBI;
1690 int FrIdx = CSI.getFrameIdx();
1702 StackUpdateLoc =
MBBI;
1715 if (HasRedZone && HasBP) {
1725 assert(HasFP &&
"Expecting a valid frame pointer.");
1728 if (!isLargeFrame) {
1732 TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, FrameSize);
1740 BuildMI(
MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1746 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1747 "Local offsets should be negative");
1749 FPOffset += FrameSize;
1750 BPOffset += FrameSize;
1751 PBPOffset += FrameSize;
1769 assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1776 if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
1779 assert(HasRedZone &&
"Expecting red zone");
1783 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1792 bool LoadedLR =
false;
1793 if (
MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1800 if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR)) {
1801 assert(RBReg == SPReg &&
"Should be using SP as a base register");
1810 if (HasRedZone || RBReg == SPReg)
1832 if (RBReg != SPReg || SPAdd != 0) {
1833 assert(!HasRedZone &&
"This should not happen with red zone");
1844 assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1859 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1866 if (HasROPProtect) {
1869 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
1870 "ROP hash check location offset out of range.");
1871 assert(((ImmOffset & 0x7) == 0) &&
1872 "ROP hash check location offset must be 8 byte aligned.");
1883 if (IsReturnBlock) {
1884 unsigned RetOpcode =
MBBI->getOpcode();
1886 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1891 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1896 .
addImm(CallerAllocatedAmt >> 16);
1899 .
addImm(CallerAllocatedAmt & 0xFFFF);
1906 createTailCallBranchInstr(
MBB);
1927 unsigned RetOpcode =
MBBI->getOpcode();
1928 if (RetOpcode == PPC::TCRETURNdi) {
1939 }
else if (RetOpcode == PPC::TCRETURNri) {
1941 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1943 }
else if (RetOpcode == PPC::TCRETURNai) {
1947 }
else if (RetOpcode == PPC::TCRETURNdi8) {
1958 }
else if (RetOpcode == PPC::TCRETURNri8) {
1960 assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1962 }
else if (RetOpcode == PPC::TCRETURNai8) {
1980 SavedRegs.
reset(PPC::VSRp26);
1981 SavedRegs.
reset(PPC::VSRp27);
1982 SavedRegs.
reset(PPC::VSRp28);
1983 SavedRegs.
reset(PPC::VSRp29);
1984 SavedRegs.
reset(PPC::VSRp30);
1985 SavedRegs.
reset(PPC::VSRp31);
1989 unsigned LR = RegInfo->getRARegister();
1991 SavedRegs.
reset(LR);
1995 const bool isPPC64 = Subtarget.
isPPC64();
2029 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
2033 SavedRegs.
reset(PPC::R30);
2048 if ((SavedRegs.
test(PPC::CR2) || SavedRegs.
test(PPC::CR3) ||
2049 SavedRegs.
test(PPC::CR4))) {
2051 const int64_t SpillOffset =
2074 createTailCallBranchInstr(
MBB);
2079 if (CSI.empty() && !
needsFP(MF)) {
2084 unsigned MinGPR = PPC::R31;
2085 unsigned MinG8R = PPC::X31;
2086 unsigned MinFPR = PPC::F31;
2087 unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
2089 bool HasGPSaveArea =
false;
2090 bool HasG8SaveArea =
false;
2091 bool HasFPSaveArea =
false;
2092 bool HasVRSaveArea =
false;
2102 (Reg != PPC::X2 && Reg != PPC::R2)) &&
2103 "Not expecting to try to spill R2 in a function that must save TOC");
2104 if (PPC::GPRCRegClass.
contains(Reg)) {
2105 HasGPSaveArea =
true;
2112 }
else if (PPC::G8RCRegClass.
contains(Reg)) {
2113 HasG8SaveArea =
true;
2120 }
else if (PPC::F8RCRegClass.
contains(Reg)) {
2121 HasFPSaveArea =
true;
2128 }
else if (PPC::CRBITRCRegClass.
contains(Reg) ||
2131 }
else if (PPC::VRRCRegClass.
contains(Reg) ||
2132 PPC::SPERCRegClass.
contains(Reg)) {
2135 HasVRSaveArea =
true;
2150 int64_t LowerBound = 0;
2156 LowerBound = TCSPDelta;
2161 if (HasFPSaveArea) {
2162 for (
unsigned i = 0, e = FPRegs.
size(); i != e; ++i) {
2163 int FI = FPRegs[i].getFrameIdx();
2168 LowerBound -= (31 -
TRI->getEncodingValue(MinFPR) + 1) * 8;
2175 assert(FI &&
"No Frame Pointer Save Slot!");
2178 HasGPSaveArea =
true;
2183 assert(FI &&
"No PIC Base Pointer Save Slot!");
2186 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
2187 HasGPSaveArea =
true;
2193 assert(FI &&
"No Base Pointer Save Slot!");
2197 if (PPC::G8RCRegClass.
contains(BP)) {
2198 MinG8R = std::min<unsigned>(MinG8R, BP);
2199 HasG8SaveArea =
true;
2200 }
else if (PPC::GPRCRegClass.
contains(BP)) {
2201 MinGPR = std::min<unsigned>(MinGPR, BP);
2202 HasGPSaveArea =
true;
2208 if (HasGPSaveArea || HasG8SaveArea) {
2211 for (
unsigned i = 0, e = GPRegs.
size(); i != e; ++i) {
2212 if (!GPRegs[i].isSpilledToReg()) {
2213 int FI = GPRegs[i].getFrameIdx();
2220 for (
unsigned i = 0, e = G8Regs.
size(); i != e; ++i) {
2221 if (!G8Regs[i].isSpilledToReg()) {
2222 int FI = G8Regs[i].getFrameIdx();
2228 std::min<unsigned>(
TRI->getEncodingValue(MinGPR),
2229 TRI->getEncodingValue(MinG8R));
2231 const unsigned GPRegSize = Subtarget.
isPPC64() ? 8 : 4;
2232 LowerBound -= (31 - MinReg + 1) * GPRegSize;
2242 for (
const auto &CSInfo : CSI) {
2243 if (CSInfo.getReg() == PPC::CR2) {
2244 int FI = CSInfo.getFrameIdx();
2255 if (HasVRSaveArea) {
2261 assert(LowerBound <= 0 &&
"Expect LowerBound have a non-positive value!");
2262 LowerBound &= ~(15);
2264 for (
unsigned i = 0, e = VRegs.
size(); i != e; ++i) {
2265 int FI = VRegs[i].getFrameIdx();
2292 bool NeedSpills = Subtarget.hasSPE() ? !isInt<8>(StackSize) : !isInt<16>(StackSize);
2300 unsigned Size =
TRI.getSpillSize(RC);
2301 Align Alignment =
TRI.getSpillAlign(RC);
2322 std::vector<CalleeSavedInfo> &CSI)
const {
2331 if (Subtarget.hasSPE()) {
2335 for (
auto &CalleeSaveReg : CSI) {
2338 MCPhysReg Higher = RegInfo->getSubReg(Reg, 2);
2343 !
MRI.isPhysRegModified(Higher))
2356 for (
unsigned i = 0; CSRegs[i]; ++i)
2357 BVCalleeSaved.
set(CSRegs[i]);
2359 for (
unsigned Reg : BVAllocatable.
set_bits()) {
2362 if (BVCalleeSaved[Reg] || !PPC::VSRCRegClass.
contains(Reg) ||
2363 MRI.isPhysRegUsed(Reg))
2364 BVAllocatable.
reset(Reg);
2367 bool AllSpilledToReg =
true;
2368 unsigned LastVSRUsedForSpill = 0;
2369 for (
auto &CS : CSI) {
2370 if (BVAllocatable.
none())
2375 if (!PPC::G8RCRegClass.
contains(Reg)) {
2376 AllSpilledToReg =
false;
2382 if (LastVSRUsedForSpill != 0) {
2383 CS.setDstReg(LastVSRUsedForSpill);
2384 BVAllocatable.
reset(LastVSRUsedForSpill);
2385 LastVSRUsedForSpill = 0;
2389 unsigned VolatileVFReg = BVAllocatable.
find_first();
2390 if (VolatileVFReg < BVAllocatable.
size()) {
2391 CS.setDstReg(VolatileVFReg);
2392 LastVSRUsedForSpill = VolatileVFReg;
2394 AllSpilledToReg =
false;
2397 return AllSpilledToReg;
2409 bool CRSpilled =
false;
2413 VSRContainingGPRs.clear();
2418 if (
Info.isSpilledToReg()) {
2420 VSRContainingGPRs.FindAndConstruct(
Info.getDstReg()).second;
2421 assert(SpilledVSR.second == 0 &&
2422 "Can't spill more than two GPRs into VSR!");
2423 if (SpilledVSR.first == 0)
2424 SpilledVSR.first =
Info.getReg();
2426 SpilledVSR.second =
Info.getReg();
2434 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
2442 bool IsLiveIn =
MRI.isLiveIn(Reg);
2446 if (CRSpilled && IsCRField) {
2452 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2477 if (
I.isSpilledToReg()) {
2478 unsigned Dst =
I.getDstReg();
2483 if (VSRContainingGPRs[Dst].second != 0) {
2484 assert(Subtarget.hasP9Vector() &&
2485 "mtvsrdd is unavailable on pre-P9 targets.");
2491 }
else if (VSRContainingGPRs[Dst].second == 0) {
2492 assert(Subtarget.hasP8Vector() &&
2493 "Can't move GPR to VSR on pre-P8 targets.");
2497 TRI->getSubReg(Dst, PPC::sub_64))
2512 TII.storeRegToStackSlotNoUpd(
MBB,
MI, Reg, !IsLiveIn,
2513 I.getFrameIdx(), RC,
TRI);
2523static void restoreCRs(
bool is31,
bool CR2Spilled,
bool CR3Spilled,
2531 unsigned MoveReg = PPC::R12;
2536 CSI[CSIIndex].getFrameIdx()));
2538 unsigned RestoreOp = PPC::MTOCRF;
2557 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2559 if (
int CalleeAmt =
I->getOperand(1).getImm()) {
2562 unsigned StackReg =
is64Bit ? PPC::X1 : PPC::R1;
2563 unsigned TmpReg =
is64Bit ? PPC::X0 : PPC::R0;
2564 unsigned ADDIInstr =
is64Bit ? PPC::ADDI8 : PPC::ADDI;
2565 unsigned ADDInstr =
is64Bit ? PPC::ADD8 : PPC::ADD4;
2566 unsigned LISInstr =
is64Bit ? PPC::LIS8 : PPC::LIS;
2567 unsigned ORIInstr =
is64Bit ? PPC::ORI8 : PPC::ORI;
2570 if (isInt<16>(CalleeAmt)) {
2577 .
addImm(CalleeAmt >> 16);
2580 .
addImm(CalleeAmt & 0xFFFF);
2592 return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4;
2602 bool CR2Spilled =
false;
2603 bool CR3Spilled =
false;
2604 bool CR4Spilled =
false;
2605 unsigned CSIIndex = 0;
2616 for (
unsigned i = 0, e = CSI.
size(); i != e; ++i) {
2619 if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2627 if (Reg == PPC::CR2) {
2633 }
else if (Reg == PPC::CR3) {
2636 }
else if (Reg == PPC::CR4) {
2642 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2644 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI,
2646 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2649 if (CSI[i].isSpilledToReg()) {
2651 unsigned Dst = CSI[i].getDstReg();
2656 if (VSRContainingGPRs[Dst].second != 0) {
2657 assert(Subtarget.hasP9Vector());
2658 NumPEReloadVSR += 2;
2660 VSRContainingGPRs[Dst].second)
2663 VSRContainingGPRs[Dst].first)
2665 }
else if (VSRContainingGPRs[Dst].second == 0) {
2666 assert(Subtarget.hasP8Vector());
2669 VSRContainingGPRs[Dst].first)
2685 TII.loadRegFromStackSlotNoUpd(
MBB,
I, Reg, CSI[i].getFrameIdx(), RC,
2692 "loadRegFromStackSlot didn't insert any code!");
2706 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2708 "Only set CR[2|3|4]Spilled on 32-bit SVR4.");
2710 restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI, CSIIndex);
2717 return TOCSaveOffset;
2721 return FramePointerSaveOffset;
2725 return BasePointerSaveOffset;
2744 "Function updateCalleeSaves should only be called for AIX.");
2747 if (SavedRegs.
none())
2761 for (
int i = 0; CSRegs[i]; i++) {
2765 if (!SavedRegs.
test(Cand))
2767 if (PPC::GPRCRegClass.
contains(Cand) && Cand < LowestGPR)
2769 else if (PPC::G8RCRegClass.
contains(Cand) && Cand < LowestG8R)
2771 else if ((PPC::F4RCRegClass.
contains(Cand) ||
2772 PPC::F8RCRegClass.
contains(Cand)) &&
2775 else if (PPC::VRRCRegClass.
contains(Cand) && Cand < LowestVR)
2779 for (
int i = 0; CSRegs[i]; i++) {
2781 if ((PPC::GPRCRegClass.
contains(Cand) && Cand > LowestGPR) ||
2782 (PPC::G8RCRegClass.
contains(Cand) && Cand > LowestG8R) ||
2783 ((PPC::F4RCRegClass.
contains(Cand) ||
2784 PPC::F8RCRegClass.
contains(Cand)) &&
2785 Cand > LowestFPR) ||
2786 (PPC::VRRCRegClass.
contains(Cand) && Cand > LowestVR))
2787 SavedRegs.
set(Cand);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
static bool hasSpills(const MachineFunction &MF)
static unsigned computeCRSaveOffset(const PPCSubtarget &STI)
static void restoreCRs(bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, unsigned CSIIndex)
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
#define CALLEE_SAVED_FPRS
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
#define CALLEE_SAVED_GPRS32
#define CALLEE_SAVED_GPRS64
static unsigned computeLinkageSize(const PPCSubtarget &STI)
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
static bool isCalleeSavedCR(unsigned Reg)
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static bool hasNonRISpills(const MachineFunction &MF)
static bool spillsCR(const MachineFunction &MF)
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static void buildDefCFAReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg, const SystemZInstrInfo *ZII)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool test(unsigned Idx) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
size_type count() const
count - Returns the number of bits which are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
bool none() const
none - Returns true if none of the bits are set.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
An instruction for reading from memory.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
const MCRegisterInfo * getRegisterInfo() const
Describe properties that are true of each instruction in the target description file.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
MachineBasicBlock * getRestorePoint() const
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool hasTailCall() const
Returns true if the function contains a tail call.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
void setMaxCallFrameSize(unsigned S)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineBasicBlock * getSavePoint() const
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
This class contains meta information specific to a module.
const MCContext & getContext() const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
int64_t getOffset() const
Return the offset from the symbol in this operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
def_iterator def_begin(Register RegNo) const
static def_iterator def_end()
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
uint64_t getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
bool needsFP(const MachineFunction &MF) const
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
uint64_t getStackThreshold() const override
getStackThreshold - Return the maximum stack size
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
uint64_t getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void replaceFPWithRealFP(MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
PPCFrameLowering(const PPCSubtarget &STI)
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
uint64_t determineFrameLayoutAndUpdate(MachineFunction &MF, bool UseEstimate=false) const
Determine the frame layout and update the machine function.
void updateCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
uint64_t getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
uint64_t getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
int getTailCallSPDelta() const
const SmallVectorImpl< Register > & getMustSaveCRs() const
int getPICBasePointerSaveIndex() const
bool shrinkWrapDisabled() const
int getFramePointerSaveIndex() const
void addMustSaveCR(Register Reg)
void setBasePointerSaveIndex(int Idx)
bool hasNonRISpills() const
bool isLRStoreRequired() const
void setPICBasePointerSaveIndex(int Idx)
int getROPProtectionHashSaveIndex() const
unsigned getMinReservedArea() const
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function.
void setCRSpillFrameIndex(int idx)
int getBasePointerSaveIndex() const
void setFramePointerSaveIndex(int Idx)
bool hasBasePointer(const MachineFunction &MF) const
Register getBaseRegister(const MachineFunction &MF) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool is32BitELFABI() const
bool needsSwapsForVSXMemOps() const
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
const PPCTargetLowering * getTargetLowering() const override
const PPCInstrInfo * getInstrInfo() const override
unsigned getRedZoneSize() const
bool is64BitELFABI() const
const PPCTargetMachine & getTargetMachine() const
const PPCRegisterInfo * getRegisterInfo() const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void backward()
Update internal register state and move MBB iterator backwards.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual uint64_t getStackThreshold() const
getStackThreshold - Return the maximum stack size
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
bool isPositionIndependent() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void fullyRecomputeLiveIns(ArrayRef< MachineBasicBlock * > MBBs)
Convenience function for recomputing live-in's for a set of MBBs until the computation converges.
This struct is a compact representation of a valid (non-zero power of two) alignment.