LLVM 20.0.0git
TargetFrameLoweringImpl.cpp
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1//===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the layout of a stack frame on the target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
19#include "llvm/IR/Attributes.h"
20#include "llvm/IR/Function.h"
21#include "llvm/IR/InstrTypes.h"
22#include "llvm/MC/MCAsmInfo.h"
27
28using namespace llvm;
29
31
33 assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
34 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
35 !MF.getFunction().hasFnAttribute(Attribute::UWTable));
36 return false;
37}
38
40 return MF.needsFrameMoves() &&
42}
43
44/// Returns the displacement from the frame register to the stack
45/// frame of the specified index, along with the frame register used
46/// (in output arg FrameReg). This is the default implementation which
47/// is overridden for some targets.
50 Register &FrameReg) const {
51 const MachineFrameInfo &MFI = MF.getFrameInfo();
53
54 // By default, assume all frame indices are referenced via whatever
55 // getFrameRegister() says. The target can override this if it's doing
56 // something different.
57 FrameReg = RI->getFrameRegister(MF);
58
62}
63
64/// Returns the offset from the stack pointer to the slot of the specified
65/// index. This function serves to provide a comparable offset from a single
66/// reference point (the value of the stack-pointer at function entry) that can
67/// be used for analysis. This is the default implementation using
68/// MachineFrameInfo offsets.
71 int FI) const {
72 // To display the true offset from SP, we need to subtract the offset to the
73 // local area from MFI's ObjectOffset.
76}
77
79 const MachineFunction &MF) const {
80 return MF.getFrameInfo().hasStackObjects();
81}
82
84 BitVector &CalleeSaves) const {
86 CalleeSaves.resize(TRI.getNumRegs());
87
88 const MachineFrameInfo &MFI = MF.getFrameInfo();
89 if (!MFI.isCalleeSavedInfoValid())
90 return;
91
92 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
93 CalleeSaves.set(Info.getReg());
94}
95
97 BitVector &SavedRegs,
98 RegScavenger *RS) const {
100
101 // Resize before the early returns. Some backends expect that
102 // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
103 // saved registers.
104 SavedRegs.resize(TRI.getNumRegs());
105
106 // When interprocedural register allocation is enabled caller saved registers
107 // are preferred over callee saved registers.
108 if (MF.getTarget().Options.EnableIPRA &&
111 return;
112
113 // Get the callee saved register list...
114 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
115
116 // Early exit if there are no callee saved registers.
117 if (!CSRegs || CSRegs[0] == 0)
118 return;
119
120 // In Naked functions we aren't going to save any registers.
121 if (MF.getFunction().hasFnAttribute(Attribute::Naked))
122 return;
123
124 // Noreturn+nounwind functions never restore CSR, so no saves are needed.
125 // Purely noreturn functions may still return through throws, so those must
126 // save CSR for caller exception handlers.
127 //
128 // If the function uses longjmp to break out of its current path of
129 // execution we do not need the CSR spills either: setjmp stores all CSRs
130 // it was called with into the jmp_buf, which longjmp then restores.
131 if (MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
132 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
133 !MF.getFunction().hasFnAttribute(Attribute::UWTable) &&
135 return;
136
137 // Functions which call __builtin_unwind_init get all their registers saved.
138 bool CallsUnwindInit = MF.callsUnwindInit();
139 const MachineRegisterInfo &MRI = MF.getRegInfo();
140 for (unsigned i = 0; CSRegs[i]; ++i) {
141 unsigned Reg = CSRegs[i];
142 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
143 SavedRegs.set(Reg);
144 }
145}
146
148 const MachineFunction &MF) const {
149 if (!hasFP(MF))
150 return false;
151
152 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
153 return RegInfo->useFPForScavengingIndex(MF) &&
154 !RegInfo->hasStackRealignment(MF);
155}
156
158 if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
159 !F.hasFnAttribute(Attribute::NoRecurse))
160 return false;
161 // Function should not be optimized as tail call.
162 for (const User *U : F.users())
163 if (auto *CB = dyn_cast<CallBase>(U))
164 if (CB->isTailCall())
165 return false;
166 return true;
167}
168
170 llvm_unreachable("getInitialCFAOffset() not implemented!");
171}
172
175 llvm_unreachable("getInitialCFARegister() not implemented!");
176}
177
182}
unsigned const MachineRegisterInfo * MRI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
BitVector & set()
Definition: BitVector.h:351
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:743
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:793
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getOffsetAdjustment() const
Return the correction for frame offsets.
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool hasStackObjects() const
Return true if there are any stack objects in this function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool callsUnwindInit() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
virtual bool allocateScavengingFrameIndexesNearIncomingSP(const MachineFunction &MF) const
Control the placement of special register scavenging spill slots when allocating a stack frame.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual bool enableCalleeSaveSkip(const MachineFunction &MF) const
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
virtual Register getInitialCFARegister(const MachineFunction &MF) const
Return initial CFA register value i.e.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
virtual DwarfFrameBase getDwarfFrameBase(const MachineFunction &MF) const
Return the frame base information to be encoded in the DWARF subprogram debug info.
virtual bool needsFrameIndexResolution(const MachineFunction &MF) const
virtual bool isProfitableForNoCSROpt(const Function &F) const
Check if the no-CSR optimisation is profitable for the given function.
static bool isSafeForNoCSROpt(const Function &F)
Check if given function is safe for not having callee saved registers.
virtual bool enableCFIFixup(MachineFunction &MF) const
Returns true if we may need to fix the unwind information for the function.
virtual StackOffset getFrameIndexReferenceFromSP(const MachineFunction &MF, int FI) const
getFrameIndexReferenceFromSP - This method returns the offset from the stack pointer to the slot of t...
virtual int getInitialCFAOffset(const MachineFunction &MF) const
Return initial CFA offset value i.e.
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
TargetOptions Options
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18