LLVM 19.0.0git
TargetFrameLoweringImpl.cpp
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1//===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the layout of a stack frame on the target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
19#include "llvm/IR/Attributes.h"
20#include "llvm/IR/Function.h"
21#include "llvm/IR/InstrTypes.h"
22#include "llvm/MC/MCAsmInfo.h"
27
28using namespace llvm;
29
31
33 assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
34 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
35 !MF.getFunction().hasFnAttribute(Attribute::UWTable));
36 return false;
37}
38
40 return MF.needsFrameMoves() &&
42}
43
44/// Returns the displacement from the frame register to the stack
45/// frame of the specified index, along with the frame register used
46/// (in output arg FrameReg). This is the default implementation which
47/// is overridden for some targets.
50 Register &FrameReg) const {
51 const MachineFrameInfo &MFI = MF.getFrameInfo();
53
54 // By default, assume all frame indices are referenced via whatever
55 // getFrameRegister() says. The target can override this if it's doing
56 // something different.
57 FrameReg = RI->getFrameRegister(MF);
58
62}
63
65 const MachineFunction &MF) const {
66 return MF.getFrameInfo().hasStackObjects();
67}
68
70 BitVector &CalleeSaves) const {
72 CalleeSaves.resize(TRI.getNumRegs());
73
74 const MachineFrameInfo &MFI = MF.getFrameInfo();
75 if (!MFI.isCalleeSavedInfoValid())
76 return;
77
78 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
79 CalleeSaves.set(Info.getReg());
80}
81
83 BitVector &SavedRegs,
84 RegScavenger *RS) const {
86
87 // Resize before the early returns. Some backends expect that
88 // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
89 // saved registers.
90 SavedRegs.resize(TRI.getNumRegs());
91
92 // When interprocedural register allocation is enabled caller saved registers
93 // are preferred over callee saved registers.
94 if (MF.getTarget().Options.EnableIPRA &&
97 return;
98
99 // Get the callee saved register list...
100 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
101
102 // Early exit if there are no callee saved registers.
103 if (!CSRegs || CSRegs[0] == 0)
104 return;
105
106 // In Naked functions we aren't going to save any registers.
107 if (MF.getFunction().hasFnAttribute(Attribute::Naked))
108 return;
109
110 // Noreturn+nounwind functions never restore CSR, so no saves are needed.
111 // Purely noreturn functions may still return through throws, so those must
112 // save CSR for caller exception handlers.
113 //
114 // If the function uses longjmp to break out of its current path of
115 // execution we do not need the CSR spills either: setjmp stores all CSRs
116 // it was called with into the jmp_buf, which longjmp then restores.
117 if (MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
118 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
119 !MF.getFunction().hasFnAttribute(Attribute::UWTable) &&
121 return;
122
123 // Functions which call __builtin_unwind_init get all their registers saved.
124 bool CallsUnwindInit = MF.callsUnwindInit();
125 const MachineRegisterInfo &MRI = MF.getRegInfo();
126 for (unsigned i = 0; CSRegs[i]; ++i) {
127 unsigned Reg = CSRegs[i];
128 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
129 SavedRegs.set(Reg);
130 }
131}
132
134 const MachineFunction &MF) const {
135 if (!hasFP(MF))
136 return false;
137
138 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
139 return RegInfo->useFPForScavengingIndex(MF) &&
140 !RegInfo->hasStackRealignment(MF);
141}
142
144 if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
145 !F.hasFnAttribute(Attribute::NoRecurse))
146 return false;
147 // Function should not be optimized as tail call.
148 for (const User *U : F.users())
149 if (auto *CB = dyn_cast<CallBase>(U))
150 if (CB->isTailCall())
151 return false;
152 return true;
153}
154
156 llvm_unreachable("getInitialCFAOffset() not implemented!");
157}
158
161 llvm_unreachable("getInitialCFARegister() not implemented!");
162}
163
168}
unsigned const MachineRegisterInfo * MRI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
BitVector & set()
Definition: BitVector.h:351
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:680
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:799
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int getOffsetAdjustment() const
Return the correction for frame offsets.
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool hasStackObjects() const
Return true if there are any stack objects in this function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool callsUnwindInit() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
virtual bool allocateScavengingFrameIndexesNearIncomingSP(const MachineFunction &MF) const
Control the placement of special register scavenging spill slots when allocating a stack frame.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual bool enableCalleeSaveSkip(const MachineFunction &MF) const
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
virtual Register getInitialCFARegister(const MachineFunction &MF) const
Return initial CFA register value i.e.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
virtual DwarfFrameBase getDwarfFrameBase(const MachineFunction &MF) const
Return the frame base information to be encoded in the DWARF subprogram debug info.
virtual bool needsFrameIndexResolution(const MachineFunction &MF) const
virtual bool isProfitableForNoCSROpt(const Function &F) const
Check if the no-CSR optimisation is profitable for the given function.
static bool isSafeForNoCSROpt(const Function &F)
Check if given function is safe for not having callee saved registers.
virtual bool enableCFIFixup(MachineFunction &MF) const
Returns true if we may need to fix the unwind information for the function.
virtual int getInitialCFAOffset(const MachineFunction &MF) const
Return initial CFA offset value i.e.
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
TargetOptions Options
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18