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PPCISelLowering.h
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1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that PPC uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15#define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16
17#include "PPCInstrInfo.h"
25#include "llvm/IR/Attributes.h"
26#include "llvm/IR/CallingConv.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/Metadata.h"
30#include "llvm/IR/Type.h"
32#include <optional>
33#include <utility>
34
35namespace llvm {
36
37 namespace PPCISD {
38
39 // When adding a NEW PPCISD node please add it to the correct position in
40 // the enum. The order of elements in this enum matters!
41 // Values that are added after this entry:
42 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
43 // are considered memory opcodes and are treated differently than entries
44 // that come before it. For example, ADD or MUL should be placed before
45 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
46 // after it.
47 enum NodeType : unsigned {
48 // Start the numbering where the builtin ops and target ops leave off.
50
51 /// FSEL - Traditional three-operand fsel node.
52 ///
54
55 /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
58
59 /// FCFID - The FCFID instruction, taking an f64 operand and producing
60 /// and f64 value containing the FP representation of the integer that
61 /// was temporarily in the f64 operand.
63
64 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
65 /// unsigned integers and single-precision outputs.
69
70 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
71 /// operand, producing an f64 value containing the integer representation
72 /// of that FP value.
75
76 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
77 /// unsigned integers with round toward zero.
80
81 /// Floating-point-to-integer conversion instructions
84
85 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
86 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
88
89 /// Reciprocal estimate instructions (unary FP ops).
92
93 /// Test instruction for software square root.
95
96 /// Square root instruction.
98
99 /// VPERM - The PPC VPERM Instruction.
100 ///
102
103 /// XXSPLT - The PPC VSX splat instructions
104 ///
106
107 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
108 /// converting immediate single precision numbers to double precision
109 /// vector or scalar.
111
112 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
113 ///
115
116 /// VECINSERT - The PPC vector insert instruction
117 ///
119
120 /// VECSHL - The PPC vector shift left instruction
121 ///
123
124 /// XXPERMDI - The PPC XXPERMDI instruction
125 ///
128
129 /// The CMPB instruction (takes two operands of i32 or i64).
131
132 /// Hi/Lo - These represent the high and low 16-bit parts of a global
133 /// address respectively. These nodes have two operands, the first of
134 /// which must be a TargetGlobalAddress, and the second of which must be a
135 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
136 /// though these are usually folded into other nodes.
139
140 /// The following two target-specific nodes are used for calls through
141 /// function pointers in the 64-bit SVR4 ABI.
142
143 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
144 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
145 /// compute an allocation on the stack.
147
148 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
149 /// compute an offset from native SP to the address of the most recent
150 /// dynamic alloca.
152
153 /// To avoid stack clash, allocation is performed by block and each block is
154 /// probed.
156
157 /// The result of the mflr at function entry, used for PIC code.
159
160 /// These nodes represent PPC shifts.
161 ///
162 /// For scalar types, only the last `n + 1` bits of the shift amounts
163 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
164 /// for exact behaviors.
165 ///
166 /// For vector types, only the last n bits are used. See vsld.
170
171 /// FNMSUB - Negated multiply-subtract instruction.
173
174 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
175 /// word and shift left immediate.
177
178 /// The combination of sra[wd]i and addze used to implemented signed
179 /// integer division by a power of 2. The first operand is the dividend,
180 /// and the second is the constant shift amount (representing the
181 /// divisor).
183
184 /// CALL - A direct function call.
185 /// CALL_NOP is a call with the special NOP which follows 64-bit
186 /// CALL_NOTOC the caller does not use the TOC.
187 /// SVR4 calls and 32-bit/64-bit AIX calls.
191
192 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
193 /// MTCTR instruction.
195
196 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
197 /// BCTRL instruction.
199
200 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
201 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
202 /// and 64-bit AIX.
204
205 /// The variants that implicitly define rounding mode for calls with
206 /// strictfp semantics.
212
213 /// Return with a flag operand, matched by 'blr'
215
216 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
217 /// This copies the bits corresponding to the specified CRREG into the
218 /// resultant GPR. Bits corresponding to other CR regs are undefined.
220
221 /// Direct move from a VSX register to a GPR
223
224 /// Direct move from a GPR to a VSX register (algebraic)
226
227 /// Direct move from a GPR to a VSX register (zero)
229
230 /// Direct move of 2 consecutive GPR to a VSX register.
232
233 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
234 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
235 /// unsupported for this target.
236 /// Merge 2 GPRs to a single SPE register.
238
239 /// Extract SPE register component, second argument is high or low.
241
242 /// Extract a subvector from signed integer vector and convert to FP.
243 /// It is primarily used to convert a (widened) illegal integer vector
244 /// type to a legal floating point vector type.
245 /// For example v2i32 -> widened to v4i32 -> v2f64
247
248 /// Extract a subvector from unsigned integer vector and convert to FP.
249 /// As with SINT_VEC_TO_FP, used for converting illegal types.
251
252 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to
253 /// place the value into the least significant element of the most
254 /// significant doubleword in the vector. This is not element zero for
255 /// anything smaller than a doubleword on either endianness. This node has
256 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in
257 /// the aforementioned location in the vector register.
259
260 // FIXME: Remove these once the ANDI glue bug is fixed:
261 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
262 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
263 /// implement truncation of i32 or i64 to i1.
266
267 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
268 // target (returns (Lo, Hi)). It takes a chain operand.
270
271 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
273
274 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
276
277 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
278 /// instructions. For lack of better number, we use the opcode number
279 /// encoding for the OPC field to identify the compare. For example, 838
280 /// is VCMPGTSH.
282
283 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
284 /// altivec VCMP*_rec instructions. For lack of better number, we use the
285 /// opcode number encoding for the OPC field to identify the compare. For
286 /// example, 838 is VCMPGTSH.
288
289 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
290 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
291 /// condition register to branch on, OPC is the branch opcode to use (e.g.
292 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
293 /// an optional input flag argument.
295
296 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
297 /// loops.
300
301 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
302 /// towards zero. Used only as part of the long double-to-int
303 /// conversion sequence.
305
306 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
308
309 /// TC_RETURN - A tail call return.
310 /// operand #0 chain
311 /// operand #1 callee (register or absolute)
312 /// operand #2 stack adjustment
313 /// operand #3 optional in flag
315
316 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
319
320 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
321 /// for non-position independent code on PPC32.
323
324 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
325 /// local dynamic TLS and position indendepent code on PPC32.
327
328 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
329 /// TLS model, produces an ADDIS8 instruction that adds the GOT
330 /// base to sym\@got\@tprel\@ha.
332
333 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
334 /// TLS model, produces a LD instruction with base register G8RReg
335 /// and offset sym\@got\@tprel\@l. This completes the addition that
336 /// finds the offset of "sym" relative to the thread pointer.
338
339 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
340 /// model, produces an ADD instruction that adds the contents of
341 /// G8RReg to the thread pointer. Symbol contains a relocation
342 /// sym\@tls which is to be replaced by the thread pointer and
343 /// identifies to the linker that the instruction is part of a
344 /// TLS sequence.
346
347 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
348 /// model, produces an ADDIS8 instruction that adds the GOT base
349 /// register to sym\@got\@tlsgd\@ha.
351
352 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
353 /// model, produces an ADDI8 instruction that adds G8RReg to
354 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
355 /// ADDIS_TLSGD_L_ADDR until after register assignment.
357
358 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
359 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
360 /// ADDIS_TLSGD_L_ADDR until after register assignment.
362
363 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
364 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
365 /// register assignment.
367
368 /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
369 /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
370 /// Op that combines two register copies of TOC entries
371 /// (region handle into R3 and variable offset into R4) followed by a
372 /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr.
373 /// This node is used in 64-bit mode as well (in which case the result is
374 /// G8RC and inputs are X3/X4).
376
377 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
378 /// model, produces an ADDIS8 instruction that adds the GOT base
379 /// register to sym\@got\@tlsld\@ha.
381
382 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
383 /// model, produces an ADDI8 instruction that adds G8RReg to
384 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
385 /// ADDIS_TLSLD_L_ADDR until after register assignment.
387
388 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
389 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
390 /// ADDIS_TLSLD_L_ADDR until after register assignment.
392
393 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
394 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
395 /// following register assignment.
397
398 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
399 /// model, produces an ADDIS8 instruction that adds X3 to
400 /// sym\@dtprel\@ha.
402
403 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
404 /// model, produces an ADDI8 instruction that adds G8RReg to
405 /// sym\@got\@dtprel\@l.
407
408 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
409 /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.
411
412 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
413 /// during instruction selection to optimize a BUILD_VECTOR into
414 /// operations on splats. This is necessary to avoid losing these
415 /// optimizations due to constant folding.
417
418 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
419 /// operand identifies the operating system entry point.
421
422 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
424
425 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
426 /// history rolling buffer entry.
428
429 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
431
432 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
433 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
434 /// or stxvd2x instruction. The chain is necessary because the
435 /// sequence replaces a load and needs to provide the same number
436 /// of outputs.
438
439 /// An SDNode for swaps that are not associated with any loads/stores
440 /// and thereby have no chain.
442
443 /// An SDNode for Power9 vector absolute value difference.
444 /// operand #0 vector
445 /// operand #1 vector
446 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
447 /// the most significant bit for signed i32
448 ///
449 /// Power9 VABSD* instructions are designed to support unsigned integer
450 /// vectors (byte/halfword/word), if we want to make use of them for signed
451 /// integer vectors, we have to flip their sign bits first. To flip sign bit
452 /// for byte/halfword integer vector would become inefficient, but for word
453 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
454 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
455 /// => VABSDUW((XVNEGSP a), (XVNEGSP b))
457
458 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
459 /// lower (IDX=1) half of v4f32 to v2f64.
461
462 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
463 /// either through an add like PADDI or through a PC Relative load like
464 /// PLD.
466
467 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for
468 /// TLS global address when using dynamic access models. This can be done
469 /// through an add like PADDI.
471
472 /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address
473 /// when using local exec access models, and when prefixed instructions are
474 /// available. This is used with ADD_TLS to produce an add like PADDI.
476
477 /// ACC_BUILD = Build an accumulator register from 4 VSX registers.
479
480 /// PAIR_BUILD = Build a vector pair register from 2 VSX registers.
482
483 /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of
484 /// an accumulator or pair register. This node is needed because
485 /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same
486 /// element type.
488
489 /// XXMFACC = This corresponds to the xxmfacc instruction.
491
492 // Constrained conversion from floating point to int
497
498 /// Constrained integer-to-floating-point conversion instructions.
503
504 /// Constrained floating point add in round-to-zero mode.
506
507 // NOTE: The nodes below may require PC-Rel specific patterns if the
508 // address could be PC-Relative. When adding new nodes below, consider
509 // whether or not the address can be PC-Relative and add the corresponding
510 // PC-relative patterns and tests.
511
512 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
513 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
514 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
515 /// i32.
517
518 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
519 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
520 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
521 /// or i32.
523
524 /// STFIWX - The STFIWX instruction. The first operand is an input token
525 /// chain, then an f64 value to store, then an address to store it to.
527
528 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
529 /// load which sign-extends from a 32-bit integer value into the
530 /// destination 64-bit register.
532
533 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
534 /// load which zero-extends from a 32-bit integer value into the
535 /// destination 64-bit register.
537
538 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
539 /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
540 /// This can be used for converting loaded integers to floating point.
542
543 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
544 /// chain, then an f64 value to store, then an address to store it to,
545 /// followed by a byte-width for the store.
547
548 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
549 /// Maps directly to an lxvd2x instruction that will be followed by
550 /// an xxswapd.
552
553 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend
554 /// This node represents v1i128 BUILD_VECTOR of a zero extending load
555 /// instruction from <byte, halfword, word, or doubleword> to i128.
556 /// Allows utilization of the Load VSX Vector Rightmost Instructions.
558
559 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
560 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
561 /// the vector type to load vector in big-endian element order.
563
564 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
565 /// v2f32 value into the lower half of a VSR register.
567
568 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
569 /// instructions such as LXVDSX, LXVWSX.
571
572 /// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
573 /// that zero-extends.
575
576 /// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
577 /// that sign-extends.
579
580 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
581 /// Maps directly to an stxvd2x instruction that will be preceded by
582 /// an xxswapd.
584
585 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
586 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
587 /// the vector type to store vector in big-endian element order.
589
590 /// Store scalar integers from VSR.
592
593 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
594 /// except they ensure that the compare input is zero-extended for
595 /// sub-word versions because the atomic loads zero-extend.
598
599 /// CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr
600 /// The store conditional instruction ST[BHWD]ARX that produces a glue
601 /// result to attach it to a conditional branch.
603
604 /// GPRC = TOC_ENTRY GA, TOC
605 /// Loads the entry for GA from the TOC, where the TOC base is given by
606 /// the last operand.
608 };
609
610 } // end namespace PPCISD
611
612 /// Define some predicates that are used for node matching.
613 namespace PPC {
614
615 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
616 /// VPKUHUM instruction.
617 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
618 SelectionDAG &DAG);
619
620 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
621 /// VPKUWUM instruction.
622 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
623 SelectionDAG &DAG);
624
625 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
626 /// VPKUDUM instruction.
627 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
628 SelectionDAG &DAG);
629
630 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
631 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
632 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
633 unsigned ShuffleKind, SelectionDAG &DAG);
634
635 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
636 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
637 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
638 unsigned ShuffleKind, SelectionDAG &DAG);
639
640 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
641 /// a VMRGEW or VMRGOW instruction
642 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
643 unsigned ShuffleKind, SelectionDAG &DAG);
644 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
645 /// for a XXSLDWI instruction.
646 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
647 bool &Swap, bool IsLE);
648
649 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
650 /// for a XXBRH instruction.
651 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
652
653 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
654 /// for a XXBRW instruction.
655 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
656
657 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
658 /// for a XXBRD instruction.
659 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
660
661 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
662 /// for a XXBRQ instruction.
663 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
664
665 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
666 /// for a XXPERMDI instruction.
667 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
668 bool &Swap, bool IsLE);
669
670 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
671 /// shift amount, otherwise return -1.
672 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
673 SelectionDAG &DAG);
674
675 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
676 /// specifies a splat of a single element that is suitable for input to
677 /// VSPLTB/VSPLTH/VSPLTW.
678 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
679
680 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
681 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
682 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
683 /// vector into the other. This function will also set a couple of
684 /// output parameters for how much the source vector needs to be shifted and
685 /// what byte number needs to be specified for the instruction to put the
686 /// element in the desired location of the target vector.
687 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
688 unsigned &InsertAtByte, bool &Swap, bool IsLE);
689
690 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
691 /// appropriate for PPC mnemonics (which have a big endian bias - namely
692 /// elements are counted from the left of the vector register).
693 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
694 SelectionDAG &DAG);
695
696 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
697 /// formed by using a vspltis[bhw] instruction of the specified element
698 /// size, return the constant being splatted. The ByteSize field indicates
699 /// the number of bytes of each element [124] -> [bhw].
700 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
701
702 // Flags for computing the optimal addressing mode for loads and stores.
705
706 // Extension mode for integer loads.
708 MOF_ZExt = 1 << 1,
709 MOF_NoExt = 1 << 2,
710
711 // Address computation flags.
712 MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar.
713 MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant.
714 MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation
715 MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4.
716 MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16.
717 MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant.
718 MOF_RPlusR = 1 << 11, // Sum of two variables.
719 MOF_PCRel = 1 << 12, // PC-Relative relocation.
720 MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant.
721
722 // The in-memory type.
723 MOF_SubWordInt = 1 << 15,
724 MOF_WordInt = 1 << 16,
726 MOF_ScalarFloat = 1 << 18, // Scalar single or double precision.
727 MOF_Vector = 1 << 19, // Vector types and quad precision scalars.
728 MOF_Vector256 = 1 << 20,
729
730 // Subtarget features.
734 MOF_SubtargetSPE = 1 << 25
735 };
736
737 // The addressing modes for loads and stores.
738 enum AddrMode {
746 };
747 } // end namespace PPC
748
750 const PPCSubtarget &Subtarget;
751
752 public:
753 explicit PPCTargetLowering(const PPCTargetMachine &TM,
754 const PPCSubtarget &STI);
755
756 /// getTargetNodeName() - This method returns the name of a target specific
757 /// DAG node.
758 const char *getTargetNodeName(unsigned Opcode) const override;
759
760 bool isSelectSupported(SelectSupportKind Kind) const override {
761 // PowerPC does not support scalar condition selects on vectors.
763 }
764
765 /// getPreferredVectorAction - The code we generate when vector types are
766 /// legalized by promoting the integer element type is often much worse
767 /// than code we generate if we widen the type for applicable vector types.
768 /// The issue with promoting is that the vector is scalaraized, individual
769 /// elements promoted and then the vector is rebuilt. So say we load a pair
770 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
771 /// loads, moves back into VSR's (or memory ops if we don't have moves) and
772 /// then the VPERM for the shuffle. All in all a very slow sequence.
774 const override {
775 // Default handling for scalable and single-element vectors.
776 if (VT.isScalableVector() || VT.getVectorNumElements() == 1)
778
779 // Split and promote vNi1 vectors so we don't produce v256i1/v512i1
780 // types as those are only for MMA instructions.
781 if (VT.getScalarSizeInBits() == 1 && VT.getSizeInBits() > 16)
782 return TypeSplitVector;
783 if (VT.getScalarSizeInBits() == 1)
784 return TypePromoteInteger;
785
786 // Widen vectors that have reasonably sized elements.
787 if (VT.getScalarSizeInBits() % 8 == 0)
788 return TypeWidenVector;
790 }
791
792 bool useSoftFloat() const override;
793
794 bool hasSPE() const;
795
796 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
797 return MVT::i32;
798 }
799
800 bool isCheapToSpeculateCttz(Type *Ty) const override {
801 return true;
802 }
803
804 bool isCheapToSpeculateCtlz(Type *Ty) const override {
805 return true;
806 }
807
808 bool isCtlzFast() const override {
809 return true;
810 }
811
812 bool isEqualityCmpFoldedWithSignedCmp() const override {
813 return false;
814 }
815
816 bool hasAndNotCompare(SDValue) const override {
817 return true;
818 }
819
820 bool preferIncOfAddToSubOfNot(EVT VT) const override;
821
822 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
823 return VT.isScalarInteger();
824 }
825
826 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
827 bool OptForSize, NegatibleCost &Cost,
828 unsigned Depth = 0) const override;
829
830 /// getSetCCResultType - Return the ISD::SETCC ValueType
832 EVT VT) const override;
833
834 /// Return true if target always benefits from combining into FMA for a
835 /// given value type. This must typically return false on targets where FMA
836 /// takes more cycles to execute than FADD.
837 bool enableAggressiveFMAFusion(EVT VT) const override;
838
839 /// getPreIndexedAddressParts - returns true by value, base pointer and
840 /// offset pointer and addressing mode by reference if the node's address
841 /// can be legally represented as pre-indexed load / store address.
845 SelectionDAG &DAG) const override;
846
847 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
848 /// it can be more efficiently represented as [r+imm].
850 SelectionDAG &DAG) const;
851
852 /// SelectAddressRegReg - Given the specified addressed, check to see if it
853 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
854 /// is non-zero, only accept displacement which is not suitable for [r+imm].
855 /// Returns false if it can be represented by [r+imm], which are preferred.
857 SelectionDAG &DAG,
858 MaybeAlign EncodingAlignment = std::nullopt) const;
859
860 /// SelectAddressRegImm - Returns true if the address N can be represented
861 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
862 /// is not better represented as reg+reg. If \p EncodingAlignment is
863 /// non-zero, only accept displacements suitable for instruction encoding
864 /// requirement, i.e. multiples of 4 for DS form.
866 SelectionDAG &DAG,
867 MaybeAlign EncodingAlignment) const;
869 SelectionDAG &DAG) const;
870
871 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
872 /// represented as an indexed [r+r] operation.
874 SelectionDAG &DAG) const;
875
876 /// SelectAddressPCRel - Represent the specified address as pc relative to
877 /// be represented as [pc+imm]
879
881
882 /// LowerOperation - Provide custom lowering hooks for some operations.
883 ///
884 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
885
886 /// ReplaceNodeResults - Replace the results of node with an illegal result
887 /// type with new values built out of custom code.
888 ///
890 SelectionDAG &DAG) const override;
891
892 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
893 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
894
895 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
896
897 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
898 SmallVectorImpl<SDNode *> &Created) const override;
899
900 Register getRegisterByName(const char* RegName, LLT VT,
901 const MachineFunction &MF) const override;
902
904 KnownBits &Known,
905 const APInt &DemandedElts,
906 const SelectionDAG &DAG,
907 unsigned Depth = 0) const override;
908
909 Align getPrefLoopAlignment(MachineLoop *ML) const override;
910
911 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
912 return true;
913 }
914
916 AtomicOrdering Ord) const override;
918 AtomicOrdering Ord) const override;
919
920 bool shouldInlineQuadwordAtomics() const;
921
923 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
924
927
929 AtomicRMWInst *AI, Value *AlignedAddr,
930 Value *Incr, Value *Mask,
931 Value *ShiftAmt,
932 AtomicOrdering Ord) const override;
935 Value *AlignedAddr, Value *CmpVal,
936 Value *NewVal, Value *Mask,
937 AtomicOrdering Ord) const override;
938
941 MachineBasicBlock *MBB) const override;
944 unsigned AtomicSize,
945 unsigned BinOpcode,
946 unsigned CmpOpcode = 0,
947 unsigned CmpPred = 0) const;
950 bool is8bit,
951 unsigned Opcode,
952 unsigned CmpOpcode = 0,
953 unsigned CmpPred = 0) const;
954
956 MachineBasicBlock *MBB) const;
957
959 MachineBasicBlock *MBB) const;
960
962 MachineBasicBlock *MBB) const;
963
964 bool hasInlineStackProbe(const MachineFunction &MF) const override;
965
966 unsigned getStackProbeSize(const MachineFunction &MF) const;
967
968 ConstraintType getConstraintType(StringRef Constraint) const override;
969
970 /// Examine constraint string and operand type and determine a weight value.
971 /// The operand object must already have been set up with the operand type.
973 AsmOperandInfo &info, const char *constraint) const override;
974
975 std::pair<unsigned, const TargetRegisterClass *>
977 StringRef Constraint, MVT VT) const override;
978
979 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
980 /// function arguments in the caller parameter area. This is the actual
981 /// alignment, not its logarithm.
983 const DataLayout &DL) const override;
984
985 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
986 /// vector. If it is invalid, don't add anything to Ops.
988 std::string &Constraint,
989 std::vector<SDValue> &Ops,
990 SelectionDAG &DAG) const override;
991
992 unsigned
993 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
994 if (ConstraintCode == "es")
996 else if (ConstraintCode == "Q")
998 else if (ConstraintCode == "Z")
1000 else if (ConstraintCode == "Zy")
1002 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1003 }
1004
1007 SelectionDAG &DAG) const override;
1008
1009 /// isLegalAddressingMode - Return true if the addressing mode represented
1010 /// by AM is legal for this target, for a load/store of the specified type.
1011 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1012 Type *Ty, unsigned AS,
1013 Instruction *I = nullptr) const override;
1014
1015 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1016 /// icmp immediate, that is the target has icmp instructions which can
1017 /// compare a register against the immediate without having to materialize
1018 /// the immediate into a register.
1019 bool isLegalICmpImmediate(int64_t Imm) const override;
1020
1021 /// isLegalAddImmediate - Return true if the specified immediate is legal
1022 /// add immediate, that is the target has add instructions which can
1023 /// add a register and the immediate without having to materialize
1024 /// the immediate into a register.
1025 bool isLegalAddImmediate(int64_t Imm) const override;
1026
1027 /// isTruncateFree - Return true if it's free to truncate a value of
1028 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
1029 /// register X1 to i32 by referencing its sub-register R1.
1030 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1031 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1032
1033 bool isZExtFree(SDValue Val, EVT VT2) const override;
1034
1035 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
1036
1037 /// Returns true if it is beneficial to convert a load of a constant
1038 /// to just the constant itself.
1040 Type *Ty) const override;
1041
1042 bool convertSelectOfConstantsToMath(EVT VT) const override {
1043 return true;
1044 }
1045
1046 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
1047 SDValue C) const override;
1048
1050 EVT VT) const override {
1051 // Only handle float load/store pair because float(fpr) load/store
1052 // instruction has more cycles than integer(gpr) load/store in PPC.
1053 if (Opc != ISD::LOAD && Opc != ISD::STORE)
1054 return false;
1055 if (VT != MVT::f32 && VT != MVT::f64)
1056 return false;
1057
1058 return true;
1059 }
1060
1061 // Returns true if the address of the global is stored in TOC entry.
1062 bool isAccessedAsGotIndirect(SDValue N) const;
1063
1064 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
1065
1066 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
1067 const CallInst &I,
1068 MachineFunction &MF,
1069 unsigned Intrinsic) const override;
1070
1071 /// It returns EVT::Other if the type should be determined using generic
1072 /// target-independent logic.
1073 EVT getOptimalMemOpType(const MemOp &Op,
1074 const AttributeList &FuncAttributes) const override;
1075
1076 /// Is unaligned memory access allowed for the given type, and is it fast
1077 /// relative to software emulation.
1079 EVT VT, unsigned AddrSpace, Align Alignment = Align(1),
1081 unsigned *Fast = nullptr) const override;
1082
1083 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
1084 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
1085 /// expanded to FMAs when this method returns true, otherwise fmuladd is
1086 /// expanded to fmul + fadd.
1088 EVT VT) const override;
1089
1090 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
1091
1092 /// isProfitableToHoist - Check if it is profitable to hoist instruction
1093 /// \p I to its dominator block.
1094 /// For example, it is not profitable if \p I and it's only user can form a
1095 /// FMA instruction, because Powerpc prefers FMADD.
1096 bool isProfitableToHoist(Instruction *I) const override;
1097
1098 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1099
1100 // Should we expand the build vector with shuffles?
1101 bool
1103 unsigned DefinedValues) const override;
1104
1105 // Keep the zero-extensions for arguments to libcalls.
1106 bool shouldKeepZExtForFP16Conv() const override { return true; }
1107
1108 /// createFastISel - This method returns a target-specific FastISel object,
1109 /// or null if the target does not support "fast" instruction selection.
1111 const TargetLibraryInfo *LibInfo) const override;
1112
1113 /// Returns true if an argument of type Ty needs to be passed in a
1114 /// contiguous block of registers in calling convention CallConv.
1116 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
1117 const DataLayout &DL) const override {
1118 // We support any array type as "consecutive" block in the parameter
1119 // save area. The element type defines the alignment requirement and
1120 // whether the argument should go in GPRs, FPRs, or VRs if available.
1121 //
1122 // Note that clang uses this capability both to implement the ELFv2
1123 // homogeneous float/vector aggregate ABI, and to avoid having to use
1124 // "byval" when passing aggregates that might fully fit in registers.
1125 return Ty->isArrayTy();
1126 }
1127
1128 /// If a physical register, this returns the register that receives the
1129 /// exception address on entry to an EH pad.
1130 Register
1131 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1132
1133 /// If a physical register, this returns the register that receives the
1134 /// exception typeid on entry to a landing pad.
1135 Register
1136 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1137
1138 /// Override to support customized stack guard loading.
1139 bool useLoadStackGuardNode() const override;
1140 void insertSSPDeclarations(Module &M) const override;
1141 Value *getSDagStackGuard(const Module &M) const override;
1142
1143 bool isFPImmLegal(const APFloat &Imm, EVT VT,
1144 bool ForCodeSize) const override;
1145
1146 unsigned getJumpTableEncoding() const override;
1147 bool isJumpTableRelative() const override;
1149 SelectionDAG &DAG) const override;
1151 unsigned JTI,
1152 MCContext &Ctx) const override;
1153
1154 /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode),
1155 /// compute the address flags of the node, get the optimal address mode
1156 /// based on the flags, and set the Base and Disp based on the address mode.
1158 SDValue &Disp, SDValue &Base,
1159 SelectionDAG &DAG,
1160 MaybeAlign Align) const;
1161 /// SelectForceXFormMode - Given the specified address, force it to be
1162 /// represented as an indexed [r+r] operation (an XForm instruction).
1164 SelectionDAG &DAG) const;
1165
1167 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
1168 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
1169 const override;
1170 /// Structure that collects some common arguments that get passed around
1171 /// between the functions for call lowering.
1172 struct CallFlags {
1174 const bool IsTailCall : 1;
1175 const bool IsVarArg : 1;
1176 const bool IsPatchPoint : 1;
1177 const bool IsIndirect : 1;
1178 const bool HasNest : 1;
1179 const bool NoMerge : 1;
1180
1182 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
1186 };
1187
1189 bool IsVarArg) const;
1190
1191 private:
1192 struct ReuseLoadInfo {
1193 SDValue Ptr;
1194 SDValue Chain;
1195 SDValue ResChain;
1197 bool IsDereferenceable = false;
1198 bool IsInvariant = false;
1199 Align Alignment;
1200 AAMDNodes AAInfo;
1201 const MDNode *Ranges = nullptr;
1202
1203 ReuseLoadInfo() = default;
1204
1205 MachineMemOperand::Flags MMOFlags() const {
1207 if (IsDereferenceable)
1209 if (IsInvariant)
1211 return F;
1212 }
1213 };
1214
1215 // Map that relates a set of common address flags to PPC addressing modes.
1216 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap;
1217 void initializeAddrModeMap();
1218
1219 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
1220 SelectionDAG &DAG,
1222 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
1223 SelectionDAG &DAG) const;
1224
1225 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
1226 SelectionDAG &DAG, const SDLoc &dl) const;
1227 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
1228 const SDLoc &dl) const;
1229
1230 bool directMoveIsProfitable(const SDValue &Op) const;
1231 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
1232 const SDLoc &dl) const;
1233
1234 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
1235 const SDLoc &dl) const;
1236
1237 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
1238
1239 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
1240 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
1241
1242 bool
1243 IsEligibleForTailCallOptimization(SDValue Callee,
1244 CallingConv::ID CalleeCC,
1245 bool isVarArg,
1246 const SmallVectorImpl<ISD::InputArg> &Ins,
1247 SelectionDAG& DAG) const;
1248
1249 bool IsEligibleForTailCallOptimization_64SVR4(
1250 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB,
1251 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
1252 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1253
1254 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
1255 SDValue Chain, SDValue &LROpOut,
1256 SDValue &FPOpOut,
1257 const SDLoc &dl) const;
1258
1259 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1260
1261 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1262 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1263 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1264 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1265 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1266 SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const;
1267 SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
1268 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1269 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1270 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1271 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1272 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1273 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
1274 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1275 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1276 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1277 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1278 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1279 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1280 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1281 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1282 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1283 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1284 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1285 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1286 const SDLoc &dl) const;
1287 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1288 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1289 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1290 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1291 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1292 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
1293 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1294 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1295 SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef<int> PermMask,
1296 EVT VT, SDValue V1, SDValue V2) const;
1297 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1298 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1299 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1300 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1301 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1302 SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
1303 SelectionDAG &DAG) const;
1304 SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,
1305 const char *LibCallDoubleName, SDValue Op,
1306 SelectionDAG &DAG) const;
1307 bool isLowringToMASSFiniteSafe(SDValue Op) const;
1308 bool isLowringToMASSSafe(SDValue Op) const;
1309 bool isScalarMASSConversionEnabled() const;
1310 SDValue lowerLibCallBase(const char *LibCallDoubleName,
1311 const char *LibCallFloatName,
1312 const char *LibCallDoubleNameFinite,
1313 const char *LibCallFloatNameFinite, SDValue Op,
1314 SelectionDAG &DAG) const;
1315 SDValue lowerPow(SDValue Op, SelectionDAG &DAG) const;
1316 SDValue lowerSin(SDValue Op, SelectionDAG &DAG) const;
1317 SDValue lowerCos(SDValue Op, SelectionDAG &DAG) const;
1318 SDValue lowerLog(SDValue Op, SelectionDAG &DAG) const;
1319 SDValue lowerLog10(SDValue Op, SelectionDAG &DAG) const;
1320 SDValue lowerExp(SDValue Op, SelectionDAG &DAG) const;
1321 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;
1322 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1323 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1324 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1325 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1326 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
1327
1328 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1329 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1330
1331 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1332 CallingConv::ID CallConv, bool isVarArg,
1333 const SmallVectorImpl<ISD::InputArg> &Ins,
1334 const SDLoc &dl, SelectionDAG &DAG,
1335 SmallVectorImpl<SDValue> &InVals) const;
1336
1337 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
1338 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1339 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1340 SDValue &Callee, int SPDiff, unsigned NumBytes,
1341 const SmallVectorImpl<ISD::InputArg> &Ins,
1342 SmallVectorImpl<SDValue> &InVals,
1343 const CallBase *CB) const;
1344
1345 SDValue
1346 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1347 const SmallVectorImpl<ISD::InputArg> &Ins,
1348 const SDLoc &dl, SelectionDAG &DAG,
1349 SmallVectorImpl<SDValue> &InVals) const override;
1350
1351 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1352 SmallVectorImpl<SDValue> &InVals) const override;
1353
1354 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1355 bool isVarArg,
1356 const SmallVectorImpl<ISD::OutputArg> &Outs,
1357 LLVMContext &Context) const override;
1358
1359 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1360 const SmallVectorImpl<ISD::OutputArg> &Outs,
1361 const SmallVectorImpl<SDValue> &OutVals,
1362 const SDLoc &dl, SelectionDAG &DAG) const override;
1363
1364 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1365 SelectionDAG &DAG, SDValue ArgVal,
1366 const SDLoc &dl) const;
1367
1368 SDValue LowerFormalArguments_AIX(
1369 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1370 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1371 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1372 SDValue LowerFormalArguments_64SVR4(
1373 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1374 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1375 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1376 SDValue LowerFormalArguments_32SVR4(
1377 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1378 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1379 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1380
1381 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1382 SDValue CallSeqStart,
1383 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1384 const SDLoc &dl) const;
1385
1386 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1387 const SmallVectorImpl<ISD::OutputArg> &Outs,
1388 const SmallVectorImpl<SDValue> &OutVals,
1389 const SmallVectorImpl<ISD::InputArg> &Ins,
1390 const SDLoc &dl, SelectionDAG &DAG,
1391 SmallVectorImpl<SDValue> &InVals,
1392 const CallBase *CB) const;
1393 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1394 const SmallVectorImpl<ISD::OutputArg> &Outs,
1395 const SmallVectorImpl<SDValue> &OutVals,
1396 const SmallVectorImpl<ISD::InputArg> &Ins,
1397 const SDLoc &dl, SelectionDAG &DAG,
1398 SmallVectorImpl<SDValue> &InVals,
1399 const CallBase *CB) const;
1400 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags,
1401 const SmallVectorImpl<ISD::OutputArg> &Outs,
1402 const SmallVectorImpl<SDValue> &OutVals,
1403 const SmallVectorImpl<ISD::InputArg> &Ins,
1404 const SDLoc &dl, SelectionDAG &DAG,
1405 SmallVectorImpl<SDValue> &InVals,
1406 const CallBase *CB) const;
1407
1408 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1409 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1410 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1411
1412 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1413 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1414 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1415 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1416 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1417 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1418 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1419 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1420 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1421 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1422 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
1423 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1424 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1425 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1426 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1427 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
1428 SelectionDAG &DAG) const;
1429 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1430 DAGCombinerInfo &DCI) const;
1431
1432 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1433 /// SETCC with integer subtraction when (1) there is a legal way of doing it
1434 /// (2) keeping the result of comparison in GPR has performance benefit.
1435 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1436
1437 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1438 int &RefinementSteps, bool &UseOneConstNR,
1439 bool Reciprocal) const override;
1440 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1441 int &RefinementSteps) const override;
1442 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1443 const DenormalMode &Mode) const override;
1444 SDValue getSqrtResultForDenormInput(SDValue Operand,
1445 SelectionDAG &DAG) const override;
1446 unsigned combineRepeatedFPDivisors() const override;
1447
1448 SDValue
1449 combineElementTruncationToVectorTruncation(SDNode *N,
1450 DAGCombinerInfo &DCI) const;
1451
1452 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1453 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1454 /// essentially any shuffle of v8i16 vectors that just inserts one element
1455 /// from one vector into the other.
1456 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1457
1458 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1459 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1460 /// essentially v16i8 vector version of VINSERTH.
1461 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1462
1463 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
1464 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1.
1465 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1466
1467 // Return whether the call instruction can potentially be optimized to a
1468 // tail call. This will cause the optimizers to attempt to move, or
1469 // duplicate return instructions to help enable tail call optimizations.
1470 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1471 bool hasBitPreservingFPLogic(EVT VT) const override;
1472 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1473
1474 /// getAddrModeForFlags - Based on the set of address flags, select the most
1475 /// optimal instruction format to match by.
1476 PPC::AddrMode getAddrModeForFlags(unsigned Flags) const;
1477
1478 /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute
1479 /// the address flags of the load/store instruction that is to be matched.
1480 /// The address flags are stored in a map, which is then searched
1481 /// through to determine the optimal load/store instruction format.
1482 unsigned computeMOFlags(const SDNode *Parent, SDValue N,
1483 SelectionDAG &DAG) const;
1484 }; // end class PPCTargetLowering
1485
1486 namespace PPC {
1487
1488 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1489 const TargetLibraryInfo *LibInfo);
1490
1491 } // end namespace PPC
1492
1493 bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1494 bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1495 bool isIntS34Immediate(SDNode *N, int64_t &Imm);
1496 bool isIntS34Immediate(SDValue Op, int64_t &Imm);
1497
1498 bool convertToNonDenormSingle(APInt &ArgAPInt);
1499 bool convertToNonDenormSingle(APFloat &ArgAPFloat);
1500 bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat);
1501
1502} // end namespace llvm
1503
1504#endif // LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Function Alias Analysis Results
This file contains the simple types necessary to represent the attributes associated with functions a...
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file contains the declarations for metadata subclasses.
const char LLVMTargetMachineRef TM
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:75
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Metadata node.
Definition: Metadata.h:943
Machine Value Type.
uint64_t getScalarSizeInBits() const
unsigned getVectorNumElements() const
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOInvariant
The memory access always returns the same value (or traps).
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isSelectSupported(SelectSupportKind Kind) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=std::nullopt) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
bool useSoftFloat() const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
bool isEqualityCmpFoldedWithSignedCmp() const override
Return true if instruction generated for equality comparison is folded with instruction generated for...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const override
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
unsigned getStackProbeSize(const MachineFunction &MF) const
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldKeepZExtForFP16Conv() const override
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool isJumpTableRelative() const override
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const
SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool isAccessedAsGotIndirect(SDValue N) const
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
bool shouldInlineQuadwordAtomics() const
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Common code between 32-bit and 64-bit PowerPC targets.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Provides information about what library functions are available for the current target.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
NegatibleCost
Enum that specifies when a float negation is beneficial.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:246
LLVM Value Representation.
Definition: Value.h:74
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:965
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1323
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1377
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1317
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1408
@ SEXT_LD_SPLAT
VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that sign-extends.
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
@ FSQRT
Square root instruction.
@ STRICT_FCFID
Constrained integer-to-floating-point conversion instructions.
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
@ VABSD
An SDNode for Power9 vector absolute value difference.
@ CALL_RM
The variants that implicitly define rounding mode for calls with strictfp semantics.
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
@ SRL
These nodes represent PPC shifts.
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
@ RFEBB
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
@ FP_TO_UINT_IN_VSR
Floating-point-to-integer conversion instructions.
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
@ FRE
Reciprocal estimate instructions (unary FP ops).
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
@ CLRBHRB
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
@ STORE_COND
CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr The store conditional instruction ST[BHWD]ARX that produces a...
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
@ EXTRACT_VSX_REG
EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
@ ACC_BUILD
ACC_BUILD = Build an accumulator register from 4 VSX registers.
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
@ XSMAXC
XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
@ CALL
CALL - A direct function call.
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
@ TC_RETURN
TC_RETURN - A tail call return.
@ STFIWX
STFIWX - The STFIWX instruction.
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
@ VCMP_rec
RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
@ PADDI_DTPREL
G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 inst...
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
@ TLS_LOCAL_EXEC_MAT_ADDR
TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access ...
@ VPERM
VPERM - The PPC VPERM Instruction.
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
@ PAIR_BUILD
PAIR_BUILD = Build a vector pair register from 2 VSX registers.
@ STRICT_FADDRTZ
Constrained floating point add in round-to-zero mode.
@ FTSQRT
Test instruction for software square root.
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
@ RET_FLAG
Return with a flag operand, matched by 'blr'.
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
@ VECSHL
VECSHL - The PPC vector shift left instruction.
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
@ ZEXT_LD_SPLAT
VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that zero-extends.
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
@ TLSGD_AIX
GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two re...
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
@ LXVRZX
LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero...
@ MFBHRBE
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
@ FSEL
FSEL - Traditional three-operand fsel node.
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
@ STBRX
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
@ MFVSR
Direct move from a VSX register to a GPR.
@ TLS_DYNAMIC_MAT_PCREL_ADDR
TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dyna...
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
bool convertToNonDenormSingle(APInt &ArgAPInt)
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool isIntS34Immediate(SDNode *N, int64_t &Imm)
isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
#define N
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
This class contains a discriminated union of information about pointers in memory operands,...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Structure that collects some common arguments that get passed around between the functions for call l...
CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)