Go to the documentation of this file.
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
626 unsigned ShuffleKind, SelectionDAG &DAG);
631 unsigned ShuffleKind, SelectionDAG &DAG);
636 unsigned ShuffleKind, SelectionDAG &DAG);
640 bool &Swap,
bool IsLE);
661 bool &Swap,
bool IsLE);
681 unsigned &InsertAtByte,
bool &Swap,
bool IsLE);
693 SDValue
get_VSPLTI_elt(SDNode *
N,
unsigned ByteSize, SelectionDAG &DAG);
755 return (
Kind != SelectSupportKind::ScalarCondVectorVal);
821 unsigned Depth = 0)
const override;
825 EVT VT)
const override;
898 const APInt &DemandedElts,
900 unsigned Depth = 0)
const override;
939 unsigned CmpOpcode = 0,
940 unsigned CmpPred = 0)
const;
945 unsigned CmpOpcode = 0,
946 unsigned CmpPred = 0)
const;
966 AsmOperandInfo &
info,
const char *constraint)
const override;
968 std::pair<unsigned, const TargetRegisterClass *>
981 std::string &Constraint,
982 std::vector<SDValue> &Ops,
987 if (ConstraintCode ==
"es")
989 else if (ConstraintCode ==
"Q")
991 else if (ConstraintCode ==
"Z")
993 else if (ConstraintCode ==
"Zy")
1001 Type *Ty,
unsigned AS,
1029 Type *Ty)
const override;
1039 EVT VT)
const override {
1058 unsigned Intrinsic)
const override;
1070 bool *Fast =
nullptr)
const override;
1077 EVT VT)
const override;
1092 unsigned DefinedValues)
const override;
1133 bool ForCodeSize)
const override;
1157 SDValue *Parts,
unsigned NumParts,
MVT PartVT,
1178 bool IsVarArg)
const;
1181 struct ReuseLoadInfo {
1186 bool IsDereferenceable =
false;
1187 bool IsInvariant =
false;
1190 const MDNode *Ranges =
nullptr;
1192 ReuseLoadInfo() =
default;
1196 if (IsDereferenceable)
1205 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap;
1206 void initializeAddrModeMap();
1208 bool canReuseLoadAddress(SDValue
Op, EVT MemVT, ReuseLoadInfo &RLI,
1211 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
1212 SelectionDAG &DAG)
const;
1214 void LowerFP_TO_INTForReuse(SDValue
Op, ReuseLoadInfo &RLI,
1215 SelectionDAG &DAG,
const SDLoc &dl)
const;
1216 SDValue LowerFP_TO_INTDirectMove(SDValue
Op, SelectionDAG &DAG,
1217 const SDLoc &dl)
const;
1219 bool directMoveIsProfitable(
const SDValue &
Op)
const;
1220 SDValue LowerINT_TO_FPDirectMove(SDValue
Op, SelectionDAG &DAG,
1221 const SDLoc &dl)
const;
1223 SDValue LowerINT_TO_FPVector(SDValue
Op, SelectionDAG &DAG,
1224 const SDLoc &dl)
const;
1226 SDValue LowerTRUNCATEVector(SDValue
Op, SelectionDAG &DAG)
const;
1228 SDValue getFramePointerFrameIndex(SelectionDAG & DAG)
const;
1229 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG)
const;
1232 IsEligibleForTailCallOptimization(SDValue Callee,
1235 const SmallVectorImpl<ISD::InputArg> &
Ins,
1236 SelectionDAG& DAG)
const;
1238 bool IsEligibleForTailCallOptimization_64SVR4(
1240 bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
1241 const SmallVectorImpl<ISD::InputArg> &
Ins, SelectionDAG &DAG)
const;
1243 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG,
int SPDiff,
1244 SDValue Chain, SDValue &LROpOut,
1246 const SDLoc &dl)
const;
1248 SDValue getTOCEntry(SelectionDAG &DAG,
const SDLoc &dl, SDValue GA)
const;
1250 SDValue LowerRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1251 SDValue LowerFRAMEADDR(SDValue
Op, SelectionDAG &DAG)
const;
1252 SDValue LowerConstantPool(SDValue
Op, SelectionDAG &DAG)
const;
1253 SDValue LowerBlockAddress(SDValue
Op, SelectionDAG &DAG)
const;
1254 SDValue LowerGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1255 SDValue LowerGlobalTLSAddressAIX(SDValue
Op, SelectionDAG &DAG)
const;
1256 SDValue LowerGlobalTLSAddressLinux(SDValue
Op, SelectionDAG &DAG)
const;
1257 SDValue LowerGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
1258 SDValue LowerJumpTable(SDValue
Op, SelectionDAG &DAG)
const;
1259 SDValue LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const;
1260 SDValue LowerINIT_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1261 SDValue LowerADJUST_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1262 SDValue LowerINLINEASM(SDValue
Op, SelectionDAG &DAG)
const;
1263 SDValue LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const;
1264 SDValue LowerVAARG(SDValue
Op, SelectionDAG &DAG)
const;
1265 SDValue LowerVACOPY(SDValue
Op, SelectionDAG &DAG)
const;
1266 SDValue LowerSTACKRESTORE(SDValue
Op, SelectionDAG &DAG)
const;
1267 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue
Op, SelectionDAG &DAG)
const;
1268 SDValue LowerDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1269 SDValue LowerEH_DWARF_CFA(SDValue
Op, SelectionDAG &DAG)
const;
1270 SDValue LowerLOAD(SDValue
Op, SelectionDAG &DAG)
const;
1271 SDValue LowerSTORE(SDValue
Op, SelectionDAG &DAG)
const;
1272 SDValue LowerTRUNCATE(SDValue
Op, SelectionDAG &DAG)
const;
1273 SDValue LowerSELECT_CC(SDValue
Op, SelectionDAG &DAG)
const;
1274 SDValue LowerFP_TO_INT(SDValue
Op, SelectionDAG &DAG,
1275 const SDLoc &dl)
const;
1276 SDValue LowerINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1277 SDValue LowerFLT_ROUNDS_(SDValue
Op, SelectionDAG &DAG)
const;
1278 SDValue LowerSHL_PARTS(SDValue
Op, SelectionDAG &DAG)
const;
1279 SDValue LowerSRL_PARTS(SDValue
Op, SelectionDAG &DAG)
const;
1280 SDValue LowerSRA_PARTS(SDValue
Op, SelectionDAG &DAG)
const;
1281 SDValue LowerFunnelShift(SDValue
Op, SelectionDAG &DAG)
const;
1282 SDValue LowerBUILD_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1283 SDValue LowerVECTOR_SHUFFLE(SDValue
Op, SelectionDAG &DAG)
const;
1284 SDValue LowerINSERT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1285 SDValue LowerINTRINSIC_WO_CHAIN(SDValue
Op, SelectionDAG &DAG)
const;
1286 SDValue LowerINTRINSIC_VOID(SDValue
Op, SelectionDAG &DAG)
const;
1287 SDValue LowerBSWAP(SDValue
Op, SelectionDAG &DAG)
const;
1288 SDValue LowerATOMIC_CMP_SWAP(SDValue
Op, SelectionDAG &DAG)
const;
1289 SDValue lowerToLibCall(
const char *LibCallName, SDValue
Op,
1290 SelectionDAG &DAG)
const;
1291 SDValue lowerLibCallBasedOnType(
const char *LibCallFloatName,
1292 const char *LibCallDoubleName, SDValue
Op,
1293 SelectionDAG &DAG)
const;
1294 bool isLowringToMASSFiniteSafe(SDValue
Op)
const;
1295 bool isLowringToMASSSafe(SDValue
Op)
const;
1296 SDValue lowerLibCallBase(
const char *LibCallDoubleName,
1297 const char *LibCallFloatName,
1298 const char *LibCallDoubleNameFinite,
1299 const char *LibCallFloatNameFinite, SDValue
Op,
1300 SelectionDAG &DAG)
const;
1301 SDValue lowerPow(SDValue
Op, SelectionDAG &DAG)
const;
1302 SDValue lowerSin(SDValue
Op, SelectionDAG &DAG)
const;
1303 SDValue lowerCos(SDValue
Op, SelectionDAG &DAG)
const;
1304 SDValue lowerLog(SDValue
Op, SelectionDAG &DAG)
const;
1305 SDValue lowerLog10(SDValue
Op, SelectionDAG &DAG)
const;
1306 SDValue lowerExp(SDValue
Op, SelectionDAG &DAG)
const;
1307 SDValue LowerATOMIC_LOAD_STORE(SDValue
Op, SelectionDAG &DAG)
const;
1308 SDValue LowerSCALAR_TO_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1309 SDValue LowerMUL(SDValue
Op, SelectionDAG &DAG)
const;
1310 SDValue LowerFP_EXTEND(SDValue
Op, SelectionDAG &DAG)
const;
1311 SDValue LowerFP_ROUND(SDValue
Op, SelectionDAG &DAG)
const;
1312 SDValue LowerROTL(SDValue
Op, SelectionDAG &DAG)
const;
1314 SDValue LowerVectorLoad(SDValue
Op, SelectionDAG &DAG)
const;
1315 SDValue LowerVectorStore(SDValue
Op, SelectionDAG &DAG)
const;
1317 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1319 const SmallVectorImpl<ISD::InputArg> &
Ins,
1320 const SDLoc &dl, SelectionDAG &DAG,
1321 SmallVectorImpl<SDValue> &InVals)
const;
1323 SDValue FinishCall(CallFlags CFlags,
const SDLoc &dl, SelectionDAG &DAG,
1324 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1325 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1326 SDValue &Callee,
int SPDiff,
unsigned NumBytes,
1327 const SmallVectorImpl<ISD::InputArg> &
Ins,
1328 SmallVectorImpl<SDValue> &InVals,
1329 const CallBase *CB)
const;
1332 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1333 const SmallVectorImpl<ISD::InputArg> &
Ins,
1334 const SDLoc &dl, SelectionDAG &DAG,
1335 SmallVectorImpl<SDValue> &InVals)
const override;
1337 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1338 SmallVectorImpl<SDValue> &InVals)
const override;
1342 const SmallVectorImpl<ISD::OutputArg> &Outs,
1343 LLVMContext &
Context)
const override;
1345 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1346 const SmallVectorImpl<ISD::OutputArg> &Outs,
1347 const SmallVectorImpl<SDValue> &OutVals,
1348 const SDLoc &dl, SelectionDAG &DAG)
const override;
1350 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1351 SelectionDAG &DAG, SDValue ArgVal,
1352 const SDLoc &dl)
const;
1354 SDValue LowerFormalArguments_AIX(
1356 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
1357 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const;
1358 SDValue LowerFormalArguments_64SVR4(
1360 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
1361 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const;
1362 SDValue LowerFormalArguments_32SVR4(
1364 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
1365 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const;
1367 SDValue createMemcpyOutsideCallSeq(SDValue
Arg, SDValue PtrOff,
1368 SDValue CallSeqStart,
1369 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1370 const SDLoc &dl)
const;
1372 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1373 const SmallVectorImpl<ISD::OutputArg> &Outs,
1374 const SmallVectorImpl<SDValue> &OutVals,
1375 const SmallVectorImpl<ISD::InputArg> &
Ins,
1376 const SDLoc &dl, SelectionDAG &DAG,
1377 SmallVectorImpl<SDValue> &InVals,
1378 const CallBase *CB)
const;
1379 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1380 const SmallVectorImpl<ISD::OutputArg> &Outs,
1381 const SmallVectorImpl<SDValue> &OutVals,
1382 const SmallVectorImpl<ISD::InputArg> &
Ins,
1383 const SDLoc &dl, SelectionDAG &DAG,
1384 SmallVectorImpl<SDValue> &InVals,
1385 const CallBase *CB)
const;
1386 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags,
1387 const SmallVectorImpl<ISD::OutputArg> &Outs,
1388 const SmallVectorImpl<SDValue> &OutVals,
1389 const SmallVectorImpl<ISD::InputArg> &
Ins,
1390 const SDLoc &dl, SelectionDAG &DAG,
1391 SmallVectorImpl<SDValue> &InVals,
1392 const CallBase *CB)
const;
1394 SDValue lowerEH_SJLJ_SETJMP(SDValue
Op, SelectionDAG &DAG)
const;
1395 SDValue lowerEH_SJLJ_LONGJMP(SDValue
Op, SelectionDAG &DAG)
const;
1396 SDValue LowerBITCAST(SDValue
Op, SelectionDAG &DAG)
const;
1398 SDValue DAGCombineExtBoolTrunc(SDNode *
N, DAGCombinerInfo &DCI)
const;
1399 SDValue DAGCombineBuildVector(SDNode *
N, DAGCombinerInfo &DCI)
const;
1400 SDValue DAGCombineTruncBoolExt(SDNode *
N, DAGCombinerInfo &DCI)
const;
1401 SDValue combineStoreFPToInt(SDNode *
N, DAGCombinerInfo &DCI)
const;
1402 SDValue combineFPToIntToFP(SDNode *
N, DAGCombinerInfo &DCI)
const;
1403 SDValue combineSHL(SDNode *
N, DAGCombinerInfo &DCI)
const;
1404 SDValue combineSRA(SDNode *
N, DAGCombinerInfo &DCI)
const;
1405 SDValue combineSRL(SDNode *
N, DAGCombinerInfo &DCI)
const;
1406 SDValue combineMUL(SDNode *
N, DAGCombinerInfo &DCI)
const;
1407 SDValue combineADD(SDNode *
N, DAGCombinerInfo &DCI)
const;
1408 SDValue combineFMALike(SDNode *
N, DAGCombinerInfo &DCI)
const;
1409 SDValue combineTRUNCATE(SDNode *
N, DAGCombinerInfo &DCI)
const;
1410 SDValue combineSetCC(SDNode *
N, DAGCombinerInfo &DCI)
const;
1411 SDValue combineABS(SDNode *
N, DAGCombinerInfo &DCI)
const;
1412 SDValue combineVSelect(SDNode *
N, DAGCombinerInfo &DCI)
const;
1413 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
1414 SelectionDAG &DAG)
const;
1415 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1416 DAGCombinerInfo &DCI)
const;
1421 SDValue ConvertSETCCToSubtract(SDNode *
N, DAGCombinerInfo &DCI)
const;
1423 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
1424 int &RefinementSteps,
bool &UseOneConstNR,
1425 bool Reciprocal)
const override;
1426 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
1427 int &RefinementSteps)
const override;
1428 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1429 const DenormalMode &
Mode)
const override;
1430 SDValue getSqrtResultForDenormInput(SDValue Operand,
1431 SelectionDAG &DAG)
const override;
1432 unsigned combineRepeatedFPDivisors()
const override;
1435 combineElementTruncationToVectorTruncation(SDNode *
N,
1436 DAGCombinerInfo &DCI)
const;
1442 SDValue lowerToVINSERTH(ShuffleVectorSDNode *
N, SelectionDAG &DAG)
const;
1447 SDValue lowerToVINSERTB(ShuffleVectorSDNode *
N, SelectionDAG &DAG)
const;
1451 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *
N, SelectionDAG &DAG)
const;
1456 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
1457 bool hasBitPreservingFPLogic(EVT VT)
const override;
1458 bool isMaskAndCmp0FoldingBeneficial(
const Instruction &AndI)
const override;
1468 unsigned computeMOFlags(
const SDNode *Parent, SDValue
N,
1469 SelectionDAG &DAG)
const;
1475 const TargetLibraryInfo *LibInfo);
1490 #endif // LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
This is an optimization pass for GlobalISel generic memory operations.
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
@ FSQRT
Square root instruction.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
@ RFEBB
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
@ VABSD
An SDNode for Power9 vector absolute value difference.
bool isIntS34Immediate(SDNode *N, int64_t &Imm)
isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...
Context object for machine code objects.
@ CLRBHRB
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
bool shouldKeepZExtForFP16Conv() const override
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=None) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
bool isAccessedAsGotIndirect(SDValue N) const
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
@ SEXT_LD_SPLAT
VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that sign-extends.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
@ MOInvariant
The memory access always returns the same value (or traps).
@ ACC_BUILD
ACC_BUILD = Build an accumulator register from 4 VSX registers.
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
@ VPERM
VPERM - The PPC VPERM Instruction.
Represents one node in the SelectionDAG.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
The instances of the Type class are immutable: once they are created, they are never changed.
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
Function Alias Analysis Results
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
@ MFBHRBE
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
@ ZEXT_LD_SPLAT
VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that zero-extends.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
unsigned const TargetRegisterInfo * TRI
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
bool convertToNonDenormSingle(APInt &ArgAPInt)
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
bool isEqualityCmpFoldedWithSignedCmp() const override
Return true if instruction generated for equality comparison is folded with instruction generated for...
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
bool isArrayTy() const
True if this is an instance of ArrayType.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
@ STFIWX
STFIWX - The STFIWX instruction.
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
@ TC_RETURN
TC_RETURN - A tail call return.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
(vector float) vec_cmpeq(*A, *B) C
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
uint64_t getScalarSizeInBits() const
@ VCMP_rec
RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.
const CallingConv::ID CallConv
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Structure that collects some common arguments that get passed around between the functions for call l...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
@ MFVSR
Direct move from a VSX register to a GPR.
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
Analysis containing CSE Info
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
This struct is a compact representation of a valid (non-zero power of two) alignment.
@ SRL
These nodes represent PPC shifts.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const
SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
bool hasInlineStackProbe(MachineFunction &MF) const override
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
This is an important base class in LLVM.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Representation of each machine instruction.
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
@ CALL_RM
The variants that implicitly define rounding mode for calls with strictfp semantics.
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
NegatibleCost
Enum that specifies when a float negation is beneficial.
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Flags
Flags values. These may be or'd together.
unsigned getVectorNumElements() const
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
unsigned getStackProbeSize(MachineFunction &MF) const
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
@ EXTRACT_VSX_REG
EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
A Module instance is used to store all the information related to an LLVM module.
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
@ XSMAXC
XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
Class for arbitrary precision integers.
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
StringRef - Represent a constant reference to a string, i.e.
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
@ STRICT_FADDRTZ
Constrained floating point add in round-to-zero mode.
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
Common base class shared among various IRBuilders.
bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ LXVRZX
LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero...
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
bool isJumpTableRelative() const override
@ PADDI_DTPREL
G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 inst...
an instruction that atomically reads a memory location, combines it with another value,...
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Wrapper class representing virtual and physical registers.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
@ FSEL
FSEL - Traditional three-operand fsel node.
@ RET_FLAG
Return with a flag operand, matched by 'blr'.
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
@ STBRX
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Provides information about what library functions are available for the current target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
@ CALL
CALL - A direct function call.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
Common code between 32-bit and 64-bit PowerPC targets.
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
@ TLSGD_AIX
GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two re...
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
@ PAIR_BUILD
PAIR_BUILD = Build a vector pair register from 2 VSX registers.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool useSoftFloat() const override
@ FRE
Reciprocal estimate instructions (unary FP ops).
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
should just be implemented with a CLZ instruction Since there are other e PPC
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
const char LLVMTargetMachineRef TM
This class represents a function call, abstracting a target machine's calling convention.
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
@ FP_TO_UINT_IN_VSR
Floating-point-to-integer conversion instructions.
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
@ STRICT_FCFID
Constrained integer-to-floating-point conversion instructions.
@ FTSQRT
Test instruction for software square root.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
bool shouldInlineQuadwordAtomics() const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isSelectSupported(SelectSupportKind Kind) const override
LLVM Value Representation.
An instruction that atomically checks whether a specified value is in a memory location,...
@ TLS_LOCAL_EXEC_MAT_ADDR
TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access ...
Base class for the full range of assembler expressions which are needed for parsing.
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
SelectSupportKind
Enum that describes what type of support for selects the target has.
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
@ TLS_DYNAMIC_MAT_PCREL_ADDR
TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dyna...
@ VECSHL
VECSHL - The PPC vector shift left instruction.