llvm::PPCISD Namespace Reference

Enumerations
enum	NodeType : unsigned {   GlobalBaseReg = GENERATED_OPCODE_END , SRA_ADDZE , MFOCRF , ANDI_rec_1_EQ_BIT ,   ANDI_rec_1_GT_BIT , READ_TIME_BASE , BDNZ , BDZ ,   PPC32_PICGOT , VADD_SPLAT }

Enumeration Type Documentation

NodeType

enum llvm::PPCISD::NodeType : unsigned

Enumerator
GlobalBaseReg	The result of the mflr at function entry, used for PIC code.
SRA_ADDZE	The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2. The first operand is the dividend, and the second is the constant shift amount (representing the divisor).
MFOCRF	R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. This copies the bits corresponding to the specified CRREG into the resultant GPR. Bits corresponding to other CR regs are undefined.
ANDI_rec_1_EQ_BIT	i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after executing andi. x, 1. This is used to implement truncation of i32 or i64 to i1.
ANDI_rec_1_GT_BIT
READ_TIME_BASE
BDNZ	CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
BDZ
PPC32_PICGOT	GPRC = address of GLOBAL_OFFSET_TABLE. Used by general dynamic and local dynamic TLS and position indendepent code on PPC32.
VADD_SPLAT	VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimize a BUILD_VECTOR into operations on splats. This is necessary to avoid losing these optimizations due to constant folding.

Definition at line 20 of file PPCSelectionDAGInfo.h.