#include "PPCInstrInfo.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/MachineValueType.h"
#include <utility>

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Classes
class	llvm::PPCTargetLowering

Namespaces
	llvm
	This class represents lattice values for constants.

	llvm::PPCISD

	llvm::PPC
	Define some predicates that are used for node matching.

Enumerations
enum	llvm::PPCISD::NodeType : unsigned { llvm::PPCISD::FIRST_NUMBER = ISD::BUILTIN_OP_END, llvm::PPCISD::FSEL, llvm::PPCISD::FCFID, llvm::PPCISD::FCFIDU, llvm::PPCISD::FCFIDS, llvm::PPCISD::FCFIDUS, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::PPCISD::FCTIDUZ, llvm::PPCISD::FCTIWUZ, llvm::PPCISD::FP_TO_UINT_IN_VSR, llvm::PPCISD::FP_TO_SINT_IN_VSR, llvm::PPCISD::VEXTS, llvm::PPCISD::SExtVElems, llvm::PPCISD::FRE, llvm::PPCISD::FRSQRTE, llvm::PPCISD::VMADDFP, llvm::PPCISD::VNMSUBFP, llvm::PPCISD::VPERM, llvm::PPCISD::XXSPLT, llvm::PPCISD::VECINSERT, llvm::PPCISD::XXREVERSE, llvm::PPCISD::VECSHL, llvm::PPCISD::XXPERMDI, llvm::PPCISD::CMPB, llvm::PPCISD::Hi, llvm::PPCISD::Lo, llvm::PPCISD::DYNALLOC, llvm::PPCISD::DYNAREAOFFSET, llvm::PPCISD::GlobalBaseReg, llvm::PPCISD::SRL, llvm::PPCISD::SRA, llvm::PPCISD::SHL, llvm::PPCISD::EXTSWSLI, llvm::PPCISD::SRA_ADDZE, llvm::PPCISD::CALL, llvm::PPCISD::CALL_NOP, llvm::PPCISD::MTCTR, llvm::PPCISD::BCTRL, llvm::PPCISD::BCTRL_LOAD_TOC, llvm::PPCISD::RET_FLAG, llvm::PPCISD::MFOCRF, llvm::PPCISD::MFVSR, llvm::PPCISD::MTVSRA, llvm::PPCISD::MTVSRZ, llvm::PPCISD::BUILD_FP128, llvm::PPCISD::BUILD_SPE64, llvm::PPCISD::EXTRACT_SPE, llvm::PPCISD::SINT_VEC_TO_FP, llvm::PPCISD::UINT_VEC_TO_FP, llvm::PPCISD::ANDIo_1_EQ_BIT, llvm::PPCISD::ANDIo_1_GT_BIT, llvm::PPCISD::READ_TIME_BASE, llvm::PPCISD::EH_SJLJ_SETJMP, llvm::PPCISD::EH_SJLJ_LONGJMP, llvm::PPCISD::VCMP, llvm::PPCISD::VCMPo, llvm::PPCISD::COND_BRANCH, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::PPCISD::FADDRTZ, llvm::PPCISD::MFFS, llvm::PPCISD::TC_RETURN, llvm::PPCISD::CR6SET, llvm::PPCISD::CR6UNSET, llvm::PPCISD::PPC32_GOT, llvm::PPCISD::PPC32_PICGOT, llvm::PPCISD::ADDIS_GOT_TPREL_HA, llvm::PPCISD::LD_GOT_TPREL_L, llvm::PPCISD::ADD_TLS, llvm::PPCISD::ADDIS_TLSGD_HA, llvm::PPCISD::ADDI_TLSGD_L, llvm::PPCISD::GET_TLS_ADDR, llvm::PPCISD::ADDI_TLSGD_L_ADDR, llvm::PPCISD::ADDIS_TLSLD_HA, llvm::PPCISD::ADDI_TLSLD_L, llvm::PPCISD::GET_TLSLD_ADDR, llvm::PPCISD::ADDI_TLSLD_L_ADDR, llvm::PPCISD::ADDIS_DTPREL_HA, llvm::PPCISD::ADDI_DTPREL_L, llvm::PPCISD::VADD_SPLAT, llvm::PPCISD::SC, llvm::PPCISD::CLRBHRB, llvm::PPCISD::MFBHRBE, llvm::PPCISD::RFEBB, llvm::PPCISD::XXSWAPD, llvm::PPCISD::SWAP_NO_CHAIN, llvm::PPCISD::VABSD, llvm::PPCISD::QVFPERM, llvm::PPCISD::QVGPCI, llvm::PPCISD::QVALIGNI, llvm::PPCISD::QVESPLATI, llvm::PPCISD::QBFLT, llvm::PPCISD::FP_EXTEND_LH, llvm::PPCISD::STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, llvm::PPCISD::LBRX, llvm::PPCISD::STFIWX, llvm::PPCISD::LFIWAX, llvm::PPCISD::LFIWZX, llvm::PPCISD::LXSIZX, llvm::PPCISD::STXSIX, llvm::PPCISD::LXVD2X, llvm::PPCISD::LOAD_VEC_BE, llvm::PPCISD::LD_VSX_LH, llvm::PPCISD::STXVD2X, llvm::PPCISD::STORE_VEC_BE, llvm::PPCISD::ST_VSR_SCAL_INT, llvm::PPCISD::QVLFSb, llvm::PPCISD::ATOMIC_CMP_SWAP_8, llvm::PPCISD::ATOMIC_CMP_SWAP_16, llvm::PPCISD::TOC_ENTRY }

Functions
bool	llvm::PPC::isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction. More...

bool	llvm::PPC::isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction. More...

bool	llvm::PPC::isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction. More...

bool	llvm::PPC::isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes). More...

bool	llvm::PPC::isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes). More...

bool	llvm::PPC::isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction More...

bool	llvm::PPC::isXXSLDWIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
	isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction. More...

bool	llvm::PPC::isXXBRHShuffleMask (ShuffleVectorSDNode *N)
	isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction. More...

bool	llvm::PPC::isXXBRWShuffleMask (ShuffleVectorSDNode *N)
	isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction. More...

bool	llvm::PPC::isXXBRDShuffleMask (ShuffleVectorSDNode *N)
	isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction. More...

bool	llvm::PPC::isXXBRQShuffleMask (ShuffleVectorSDNode *N)
	isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction. More...

bool	llvm::PPC::isXXPERMDIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
	isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction. More...

int	llvm::PPC::isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1. More...

bool	llvm::PPC::isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize)
	isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW. More...

bool	llvm::PPC::isXXINSERTWMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
	isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0. More...

unsigned	llvm::PPC::getVSPLTImmediate (SDNode *N, unsigned EltSize, SelectionDAG &DAG)
	getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask. More...

SDValue	llvm::PPC::get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
	get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. More...

int	llvm::PPC::isQVALIGNIShuffleMask (SDNode *N)
	If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. More...

FastISel *	llvm::PPC::createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)

bool	llvm::isIntS16Immediate (SDNode *N, int16_t &Imm)
	isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value. More...

bool	llvm::isIntS16Immediate (SDValue Op, int16_t &Imm)

Classes

Namespaces

Enumerations

Functions