LLVM 22.0.0git
Public Member Functions | Friends | List of all members
llvm::SDValue Class Reference

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation. More...

#include "llvm/CodeGen/SelectionDAGNodes.h"

Public Member Functions

 SDValue ()=default
 
 SDValue (SDNode *node, unsigned resno)
 
unsigned getResNo () const
 get the index which selects a specific result in the SDNode
 
SDNode * getNode () const
 get the SDNode which holds the desired result
 
void setNode (SDNode *N)
 set the SDNode
 
SDNode * operator-> () const
 
bool operator== (const SDValue &O) const
 
bool operator!= (const SDValue &O) const
 
bool operator< (const SDValue &O) const
 
 operator bool () const
 
SDValue getValue (unsigned R) const
 
LLVM_ABI bool isOperandOf (const SDNode *N) const
 Return true if the referenced return value is an operand of N.
 
EVT getValueType () const
 Return the ValueType of the referenced return value.
 
MVT getSimpleValueType () const
 Return the simple ValueType of the referenced return value.
 
TypeSize getValueSizeInBits () const
 Returns the size of the value in bits.
 
uint64_t getScalarValueSizeInBits () const
 
unsigned getOpcode () const
 
unsigned getNumOperands () const
 
const SDValue & getOperand (unsigned i) const
 
uint64_t getConstantOperandVal (unsigned i) const
 
const APInt & getConstantOperandAPInt (unsigned i) const
 
bool isTargetOpcode () const
 
bool isMachineOpcode () const
 
bool isUndef () const
 
bool isAnyAdd () const
 
unsigned getMachineOpcode () const
 
const DebugLoc & getDebugLoc () const
 
void dump () const
 
void dump (const SelectionDAG *G) const
 
void dumpr () const
 
void dumpr (const SelectionDAG *G) const
 
LLVM_ABI bool reachesChainWithoutSideEffects (SDValue Dest, unsigned Depth=2) const
 Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.
 
bool use_empty () const
 Return true if there are no nodes using value ResNo of Node.
 
bool hasOneUse () const
 Return true if there is exactly one node using value ResNo of Node.
 

Friends

struct DenseMapInfo< SDValue >
 

Detailed Description

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

Many nodes return multiple values, from loads (which define a token and a return value) to ADDC (which returns a result and a carry value), to calls (which may return an arbitrary number of values).

As such, each use of a SelectionDAG computation must indicate the node that computes it as well as which return value to use from that node. This pair of information is represented with the SDValue value type.

Definition at line 147 of file SelectionDAGNodes.h.

Constructor & Destructor Documentation

◆ SDValue() [1/2]

llvm::SDValue::SDValue ( )
default

Referenced by getValue().

◆ SDValue() [2/2]

llvm::SDValue::SDValue ( SDNode *  node,
unsigned  resno 
)
inline

Definition at line 1246 of file SelectionDAGNodes.h.

References assert().

Member Function Documentation

◆ dump() [1/2]

void llvm::SDValue::dump ( ) const
inline

Definition at line 1310 of file SelectionDAGNodes.h.

References Node::dump().

Referenced by lowerStatepointMetaArgs(), PerformSHLSimplify(), llvm::AArch64TargetLowering::ReconstructShuffle(), and llvm::SelectionDAGBuilder::resolveDanglingDebugInfo().

◆ dump() [2/2]

void llvm::SDValue::dump ( const SelectionDAG *  G) const
inline

Definition at line 1314 of file SelectionDAGNodes.h.

References Node::dump(), and G.

◆ dumpr() [1/2]

void llvm::SDValue::dumpr ( ) const
inline

Definition at line 1318 of file SelectionDAGNodes.h.

◆ dumpr() [2/2]

void llvm::SDValue::dumpr ( const SelectionDAG *  G) const
inline

Definition at line 1322 of file SelectionDAGNodes.h.

References G.

◆ getConstantOperandAPInt()

const APInt & llvm::SDValue::getConstantOperandAPInt ( unsigned  i) const
inline

Definition at line 1276 of file SelectionDAGNodes.h.

Referenced by combineAndShuffleNot(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineOr(), combineShiftLeft(), foldXorTruncShiftIntoCmp(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), LowerBuildVectorv4x32(), lowerShuffleOfExtractsAsVperm(), llvm::SelectionDAG::matchBinOpReduction(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformMinMaxToSatCombine(), llvm::RISCVDAGToDAGISel::selectShiftMask(), and llvm::TargetLowering::SimplifySetCC().

◆ getConstantOperandVal()

uint64_t llvm::SDValue::getConstantOperandVal ( unsigned  i) const
inline

Definition at line 1272 of file SelectionDAGNodes.h.

Referenced by canonicalizeLaneShuffleWithRepeatedOps(), checkBoolTestSetCCCombine(), combine_CC(), combineAnd(), combineAndOrForCcmpCtest(), combineCarryThroughADD(), combineCMP(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineOr(), combineStore(), combineSubABS(), combineSubSetcc(), combineTargetShuffle(), combineVectorShiftImm(), combineX86ShuffleChainWithExtract(), constructDup(), foldConcatVector(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), getBaseWithOffsetUsingSplitOR(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getVectorCompareInfo(), getVPermMask(), isAbsolute(), IsCMPZCSINC(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), isHopBuildVector(), isHorizontalBinOpPart(), isI128MovedFromParts(), isStoreConditional(), LowerBUILD_VECTORToVIDUP(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), mergeEltWithShuffle(), PeepholePPC64ZExtGather(), performANDORCSELCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSetCCPunpkCombine(), performSRACombine(), performUADDVAddCombine(), performUzpCombine(), PerformVMOVRRDCombine(), PerformVSetCCToVCTPCombine(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), ReorganizeVector(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and vectorizeExtractedCast().

◆ getDebugLoc()

const DebugLoc & llvm::SDValue::getDebugLoc ( ) const
inline

Definition at line 1306 of file SelectionDAGNodes.h.

◆ getMachineOpcode()

unsigned llvm::SDValue::getMachineOpcode ( ) const
inline

Definition at line 1288 of file SelectionDAGNodes.h.

Referenced by isEligibleToFoldADDIForFasterLocalAccesses(), isF128MovedFromParts(), PeepholePPC64ZExtGather(), llvm::SITargetLowering::PostISelFolding(), and usesAllOnesMask().

◆ getNode()

SDNode * llvm::SDValue::getNode ( ) const
inline

get the SDNode which holds the desired result

Definition at line 161 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), AddGlue(), llvm::AMDGPUTargetLowering::addTokenForArgument(), adjustBitcastSrcVectorSSE1(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), calculatePreExtendType(), canonicalizeShuffleMaskWithHorizOp(), llvm::checkForCycles(), CheckForMaskedLoad(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndnp(), combineBitcast(), combineBoolVectorAndTruncateStore(), combineCarryDiamond(), combineCarryThroughADD(), combineCCMask(), combineCMov(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineFaddCFmul(), combineHorizOpWithShuffle(), combineINSERT_SUBVECTOR(), combineOrXorWithSETCC(), combinePTESTCC(), combineSelectAndUse(), combineSelectAndUseCommutative(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftLeft(), combineShiftRightLogical(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendCMOV(), combineUADDO_CARRYDiamond(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), CombineVLDDUP(), combineVSelectWithAllOnesOrZeros(), combineX86SubCmpForFlags(), combineXor(), combineZext(), computeZeroableShuffleElements(), llvm::SelectionDAG::copyExtraInfo(), createGPRPairNode2xi32(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), emitCmp(), emitConjunctionRec(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandPartialReduceMLA(), ExpandPowI(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), findConsecutiveLoad(), findEltLoadSrc(), findMemSDNode(), foldADDIForFasterLocalAccesses(), foldBoolSelectToLogic(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), foldRemainderIdiom(), foldSubCtlzNot(), foldVectorXorShiftIntoCmp(), GenerateTBL(), llvm::PPC::get_VSPLTI_elt(), getBuildPairElt(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::TargetLowering::getCheaperOrNeutralNegatedExpression(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::ScheduleDAGSDNodes::getCustomGraphFeatures(), getFauxShuffleMask(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::SDNode::getGluedNode(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getNode(), llvm::SelectionDAG::getNode(), llvm::MipsTargetLowering::getOpndList(), getPointerConstIncrement(), getPopFromX87Reg(), getPowerOf2Factor(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), llvm::simplify_type< const SDValue >::getSimplifiedValue(), llvm::simplify_type< SDValue >::getSimplifiedValue(), llvm::SelectionDAG::getStrictFPExtendOrRound(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), insert1BitVector(), insertDAGNode(), isBitfieldExtractOpFromAnd(), isBitfieldPositioningOpFromAnd(), isBLACompatibleAddress(), isBSwapHWordElement(), isCalleeLoad(), isConsecutiveLSLoc(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), isEligibleToFoldADDIForFasterLocalAccesses(), isExtendedFrom16Bits(), isF128MovedFromParts(), isFNEG(), isFusableLoadOpStorePattern(), llvm::TargetLowering::isGAPlusOffset(), isI128MovedFromParts(), isMemOPCandidate(), llvm::AArch64TargetLowering::isReassocProfitable(), isSeveralBitsPositioningOpFromShl(), IsSVECntIntrinsic(), llvm::SelectionDAG::isUndef(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), isWorthFoldingIntoOrrWithShift(), llvm::SelectionDAG::Legalize(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerAVXCONCAT_VECTORS(), lowerBUILD_VECTORAsBroadCastLoad(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallFromStatepointLoweringInfo(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORSvXi1(), lowerDSPIntr(), LowerF128Load(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerIntrinsicVoid(), lowerLaneOp(), llvm::HexagonTargetLowering::LowerLoad(), lowerLoadF128(), lowerLoadI1(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), LowerMUL(), llvm::TargetLowering::LowerOperationWrapper(), LowerPtrAuthGlobalAddressStatically(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerRotate(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEv8i8(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::VPMatchContext::match(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), matchShuffleAsBlend(), moveBelowOrigChain(), narrowIndex(), parseTexFail(), llvm::SITargetLowering::passSpecialInputs(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddDotCombine(), PerformADDVecReduce(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performConcatVectorsCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performExtendCombine(), PerformExtractEltToVMOVRRD(), PerformFADDCombineWithOperands(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), PerformHWLoopCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), performInsertSubvectorCombine(), performIntToFpCombine(), PerformLongShiftCombine(), PerformMinMaxCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), performMulVectorCmpZeroCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performORCombine(), PerformORCombine(), performPostLD1Combine(), performSETCC_BITCASTCombine(), performSETCCCombine(), performSignExtendSetCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), PerformSTORECombine(), PerformSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMLALCombine(), performUnpackCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVDRRCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), performVSelectCombine(), performXORCombine(), llvm::SITargetLowering::PostISelFolding(), prepareIndirectCall(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), reduceANDOfAtomicLoad(), removeRedundantInsertVectorElt(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), ReplaceINTRINSIC_W_CHAIN(), llvm::ARMTargetLowering::ReplaceNodeResults(), reservePreviousStackSlotForValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), llvm::SelectionDAG::salvageDebugInfo(), scalarizeExtractedBinOp(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HvxSelector::selectRor(), llvm::HvxSelector::selectShuffle(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SelectionDAG::transferDbgValues(), tryBitfieldInsertOpFromOr(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryFoldMADwithSRL(), llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(), tryLowerToBSL(), tryLowerToSLI(), tryMemPairCombine(), tryOrrWithShift(), tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), and useSinCos().

◆ getNumOperands()

unsigned llvm::SDValue::getNumOperands ( ) const
inline

Definition at line 1264 of file SelectionDAGNodes.h.

Referenced by combineBitcast(), ExtendToType(), fnegFoldsIntoOp(), foldShuffleOfConcatUndefs(), isCalleeLoad(), isFusableLoadOpStorePattern(), isLoadOrMultipleLoads(), LowerVECTOR_SHUFFLE(), matchPMADDWD_2(), moveBelowOrigChain(), partitionShuffleOfConcats(), PerformADDVecReduce(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformExtractEltCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), PerformSplittingMVETruncToNarrowingStores(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformVECTOR_SHUFFLECombine(), performVSelectCombine(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ getOpcode()

unsigned llvm::SDValue::getOpcode ( ) const
inline

Definition at line 1256 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitUMAAL(), AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), areLoadedOffsetButOtherwiseSame(), BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), calculatePreExtendType(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canonicalizeBitSelect(), llvm::SelectionDAG::canonicalizeCommutativeBinop(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), checkBoolTestAndOrSetCCCombine(), checkBoolTestSetCCCombine(), combine_CC(), combineAdd(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndOrForCcmpCtest(), combineAndShuffleNot(), combineArithReduction(), combineAVX512SetCCToKMOV(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBoolVectorAndTruncateStore(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineBVZEXTLOAD(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOfSplats(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFneg(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineOrOfCZERO(), combineOrXorWithSETCC(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSelectToBinOp(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleOfBitcast(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineToVWMACC(), combineTruncationShuffle(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorShiftImm(), combineVPDPBUSDPattern(), combineVqdotAccum(), combineVWADDSUBWSelect(), combineX86CloadCstore(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), combineX86SubCmpForFlags(), combineXor(), combineXorSubCTLZ(), combineZext(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeOverflowForUnsignedAdd(), constructDup(), convertIntLogicToFPLogic(), detectExtMul(), detectPMADDUBSW(), eliminateFPCastPair(), EmitAVX512Test(), EmitCmp(), EmitTest(), ExtendToType(), extractShiftForRotate(), extractSubVector(), findEltLoadSrc(), fnegFoldsIntoOp(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), foldBitOrderCrossLogicOp(), foldConcatVector(), llvm::SelectionDAG::FoldConstantArithmetic(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldCSELofLASTB(), foldExtendedSignBitTest(), foldFPToIntToFP(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), FoldIntToFPToInt(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldReduceOperandViaVQDOT(), foldRemainderIdiom(), foldSelectOfCTTZOrCTLZ(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getBaseWithOffsetUsingSplitOR(), llvm::getBitwiseNotOperand(), getBT(), getBuildPairElt(), getCmp(), getFauxShuffleMask(), getIndexFromUnindexedLoad(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), getOutputChainFromCallSeq(), getPowerOf2Factor(), getSToVPermuted(), getTargetVShiftNode(), getVectorBitwiseReduce(), getVPermMask(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isAddSubOrSubAdd(), isBitfieldPositioningOpFromAnd(), isBSwapHWordElement(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), IsCMPZCSINC(), isConditionalZeroOrAllOnes(), isConsecutiveLSLoc(), IsCopyFromSGPR(), llvm::TargetLowering::isDesirableToCommuteWithShift(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), llvm::AMDGPUTargetLowering::isDesirableToCommuteWithShift(), llvm::ARMTargetLowering::isDesirableToCommuteWithShift(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), IsElementEquivalent(), isExtendedFrom16Bits(), isFMAddSubOrFMSubAdd(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOpPart(), isI128MovedFromParts(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::SelectionDAG::isKnownToBeAPowerOfTwoFP(), isLoadOrMultipleLoads(), llvm::AArch64TargetLowering::isReassocProfitable(), isSaturatingMinMax(), isSubBorrowChain(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lookThroughSignExtension(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORToVIDUP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), LowerFABSorFNEG(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), LowerMLOAD(), LowerSaturatingConditional(), LowerSELECTWithCmpZero(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerSMELdrStr(), lowerV4F64Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), llvm::SelectionDAG::matchBinOpReduction(), matchBSwapHWordOrAndAnd(), MatchingStackOffset(), matchMergedBFX(), matchPMADDWD_2(), matchRotateSub(), matchSplatAsGather(), matchUnaryShuffle(), mayUseP9Setb(), mergeEltWithShuffle(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowIndex(), narrowInsertExtractVectorBinOp(), peekFNeg(), peekFPSignOps(), performADDCombine(), PerformADDCombineWithOperands(), performAddDotCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), performANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBuildShuffleExtendCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtendCombine(), performExtendCombine(), PerformExtractEltCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), PerformFADDCombineWithOperands(), PerformFAddVSelectCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performINSERT_VECTOR_ELTCombine(), performLowerPartialReduction(), performMADD_MSUBCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), performMOVGR2FR_WCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performNegCSelCombine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), performScalarToVectorCombine(), performSELECTCombine(), performSelectCombine(), performSETCCCombine(), performSetCCPunpkCombine(), performSHLCombine(), PerformShuffleVMOVNCombine(), performSignExtendCombine(), PerformSplittingToWideningLoad(), performSRACombine(), performSRLCombine(), performSubAddMULCombine(), performSUBCombine(), performSVEAndCombine(), performSVEMulAddSubCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTRUNCATECombine(), performTruncateCombine(), performUADDVAddCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), performVP_REVERSECombine(), performVP_STORECombine(), PerformVQDMULHCombine(), performVSelectCombine(), performVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PromoteMaskArithmetic(), pushAddIntoCmovOfConsts(), reachesChainWithoutSideEffects(), reassociateCSELOperandsForCSE(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), reduceANDOfAtomicLoad(), reduceBuildVecToShuffleWithZero(), removeRedundantInsertVectorElt(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinOp(), llvm::RISCVDAGToDAGISel::Select(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), SelectSAddrFI(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), shouldLowerTailCallStackArg(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), llvm::X86TargetLowering::shouldScalarizeBinop(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::AMDGPUTargetLowering::stripBitcast(), tryCombineCRC32(), tryCombineExtendRShTrunc(), tryCombineFixedPointConvert(), tryCombineMULLWithUZP1(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), TryDistrubutionADDVecReduce(), tryFoldMADwithSRL(), tryLowerToBSL(), tryLowerToSLI(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), llvm::RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(), trySQDMULHCombine(), trySwapVSelectOperands(), tryToConvertShuffleOfTbl2ToTbl4(), vectorizeExtractedCast(), visitORCommutative(), widenAbs(), widenBuildVec(), widenCtPop(), and widenSubVector().

◆ getOperand()

const SDValue & llvm::SDValue::getOperand ( unsigned  i) const
inline

Definition at line 1268 of file SelectionDAGNodes.h.

Referenced by AddCombineVUZPToVPADDL(), adjustBitcastSrcVectorSSE1(), areBitwiseNotOfEachother(), areLoadedOffsetButOtherwiseSame(), calculatePreExtendType(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), checkBoolTestSetCCCombine(), combine_CC(), combineAdd(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndOrForCcmpCtest(), combineAndShuffleNot(), combineAVX512SetCCToKMOV(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOfSplats(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFneg(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineOrOfCZERO(), combineOrXorWithSETCC(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSelectToBinOp(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineShuffleToFMAddSub(), combineSignExtendInReg(), combineStore(), combineSub(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineToVWMACC(), combineTruncationShuffle(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineVectorCompareAndMaskUnaryOp(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineVqdotAccum(), combineX86CloadCstore(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), combineX86SubCmpForFlags(), combineXor(), combineXorSubCTLZ(), combineZext(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), constructDup(), convertIntLogicToFPLogic(), detectPMADDUBSW(), distributeOpThroughSelect(), eliminateFPCastPair(), EmitAVX512Test(), EmitCmp(), ExtendToType(), extractShiftForRotate(), extractSubVector(), findEltLoadSrc(), fnegFoldsIntoOp(), foldADDIForFasterLocalAccesses(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), foldConcatVector(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldCSELofLASTB(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldOverflowCheck(), foldReduceOperandViaVQDOT(), foldRemainderIdiom(), foldSelectOfCTTZOrCTLZ(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldToMaskedStore(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getBaseWithConstantOffset(), getBaseWithOffsetUsingSplitOR(), llvm::getBitwiseNotOperand(), getBT(), getBuildPairElt(), getFauxShuffleMask(), getIndexFromUnindexedLoad(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getReductionSDNode(), getSToVPermuted(), getTargetVShiftNode(), getVectorBitwiseReduce(), getVPermMask(), isAbsolute(), isADDADDMUL(), isAddCarryChain(), isAddSubOrSubAdd(), isBitfieldExtractOpFromAnd(), isBitfieldPositioningOpFromAnd(), isBSwapHWordElement(), isCalleeLoad(), llvm::SITargetLowering::isCanonicalized(), IsCMPZCSINC(), IsCopyFromSGPR(), llvm::TargetLowering::isDesirableToCommuteWithShift(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), llvm::AMDGPUTargetLowering::isDesirableToCommuteWithShift(), llvm::ARMTargetLowering::isDesirableToCommuteWithShift(), IsElementEquivalent(), isEligibleToFoldADDIForFasterLocalAccesses(), isExtendedFrom16Bits(), isFMAddSubOrFMSubAdd(), isFusableLoadOpStorePattern(), isHopBuildVector(), isHorizontalBinOpPart(), isI128MovedFromParts(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::SelectionDAG::isKnownToBeAPowerOfTwoFP(), isLoadOrMultipleLoads(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isSaturatingMinMax(), isSeveralBitsPositioningOpFromShl(), isSubBorrowChain(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), isWorthFoldingIntoOrrWithShift(), LookThroughSetCC(), lookThroughSignExtension(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORToVIDUP(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), LowerFABSorFNEG(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), LowerSaturatingConditional(), LowerSELECTWithCmpZero(), LowerShift(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), LowerSMELdrStr(), LowerTruncateToBTST(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::VPMatchContext::match(), llvm::SelectionDAG::matchBinOpReduction(), matchBSwapHWordOrAndAnd(), MatchingStackOffset(), matchMergedBFX(), matchPMADDWD_2(), matchRotateSub(), matchSetCC(), matchSplatAsGather(), mayUseP9Setb(), mergeEltWithShuffle(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), narrowIndex(), narrowInsertExtractVectorBinOp(), partitionShuffleOfConcats(), peekFNeg(), peekFPSignOps(), PeepholePPC64ZExtGather(), performADDCombine(), performAddDotCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), PerformADDVecReduce(), performANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBRCONDCombine(), performBuildShuffleExtendCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), PerformFADDCombineWithOperands(), PerformFAddVSelectCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performINSERT_VECTOR_ELTCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), performMOVFR2GR_SCombine(), performMOVGR2FR_WCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performMulVectorCmpZeroCombine(), performNegCSelCombine(), performORCombine(), PerformORCombineToBFI(), performScalarToVectorCombine(), performSELECTCombine(), performSelectCombine(), performSETCCCombine(), performSetCCPunpkCombine(), performSHLCombine(), PerformShuffleVMOVNCombine(), performSignExtendCombine(), performSignExtendSetCCCombine(), performSPLIT_PAIR_F64Combine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), performSRACombine(), performSRLCombine(), PerformSTORECombine(), performSUBCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTRUNCATECombine(), performTruncateCombine(), performUADDVAddCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVECTOR_SHUFFLECombine(), performVectorExtendCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performVP_REVERSECombine(), performVP_STORECombine(), PerformVQDMULHCombine(), performVSelectCombine(), performVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PromoteMaskArithmetic(), pushAddIntoCmovOfConsts(), reassociateCSELOperandsForCSE(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), reduceBuildVecToShuffleWithZero(), reduceVSXSwap(), removeRedundantInsertVectorElt(), replaceSplatVectorStore(), replaceZeroVectorStore(), scalarizeExtEltFP(), scalarizeExtractedBinOp(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), SelectSAddrFI(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), shouldLowerTailCallStackArg(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::AMDGPUTargetLowering::stripBitcast(), tryCombineCRC32(), tryCombineExtendRShTrunc(), tryCombineFixedPointConvert(), tryCombineMULLWithUZP1(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), TryDistrubutionADDVecReduce(), tryFoldMADwithSRL(), tryLowerToSLI(), tryOrrWithShift(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), llvm::RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(), trySQDMULHCombine(), trySwapVSelectOperands(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), vectorizeExtractedCast(), visitORCommutative(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), widenAbs(), widenBuildVec(), and widenCtPop().

◆ getResNo()

unsigned llvm::SDValue::getResNo ( ) const
inline

get the index which selects a specific result in the SDNode

Definition at line 158 of file SelectionDAGNodes.h.

Referenced by carryFlagToValue(), combineAddOrSubToADCOrSBB(), combineCarryThroughADD(), combineExtractVectorElt(), combineUADDO_CARRYDiamond(), llvm::SelectionDAG::computeOverflowForUnsignedAdd(), llvm::SelectionDAG::expandMultipleResultFPLibCall(), ExtendUsesToFormExtLoad(), foldRemainderIdiom(), getBuildPairElt(), getCmp(), llvm::RegsForValue::getCopyToRegs(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getResNo(), isFusableLoadOpStorePattern(), overflowFlagToValue(), PerformADDVecReduce(), PerformExtractEltToVMOVRRD(), PerformVMOVDRRCombine(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::SelectionDAG::salvageDebugInfo(), and llvm::SelectionDAG::transferDbgValues().

◆ getScalarValueSizeInBits()

uint64_t llvm::SDValue::getScalarValueSizeInBits ( ) const
inline

Definition at line 205 of file SelectionDAGNodes.h.

References llvm::EVT::getFixedSizeInBits(), llvm::EVT::getScalarType(), and getValueType().

Referenced by calculateByteProvider(), canonicalizeShuffleWithOp(), combineConcatVectorOps(), combineExtractWithShuffle(), combineMulToPMADDWD(), combinePredicateReduction(), combineTargetShuffle(), combineTruncationShuffle(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineZext(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeOverflowForSignedMul(), constructDup(), findEltLoadSrc(), foldSetCCWithFunnelShift(), foldVectorXorShiftIntoCmp(), llvm::getBitwiseNotOperand(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), isFNEG(), isSaturatingMinMax(), LowerEXTRACT_VECTOR_ELT(), lowerShuffleAsBroadcast(), matchBinaryShuffle(), matchRotateSub(), matchShuffleWithPACK(), matchUnaryShuffle(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), truncateVecElts(), and widenSubVector().

◆ getSimpleValueType()

MVT llvm::SDValue::getSimpleValueType ( ) const
inline

Return the simple ValueType of the referenced return value.

Definition at line 192 of file SelectionDAGNodes.h.

References llvm::EVT::getSimpleVT(), and getValueType().

Referenced by canonicalizeShuffleMaskWithHorizOp(), combineAddOfPMADDWD(), combineAnd(), combineAVX512SetCCToKMOV(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithPACK(), combineConcatVectorOps(), combineINSERT_SUBVECTOR(), combinePTESTCC(), combineSelect(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineTruncToVnclip(), combineVectorPack(), combineVEXTRACT_STORE(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), constructDup(), convertShiftLeftToScale(), EmitAVX512Test(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), foldMaskedShiftToScaledMask(), getCopyFromPartsVector(), getReductionSDNode(), getScalarValueForVectorElement(), getShuffleHalfVectors(), getShuffleVectorZeroOrUndef(), getTargetVShiftNode(), getUnderlyingExtractedFromVec(), getWideningInterleave(), insert1BitVector(), InsertBitToMaskVector(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORSvXi1(), lowerCttzElts(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFCOPYSIGN(), LowerFGETSIGN(), llvm::SITargetLowering::LowerFormalArguments(), lowerFPToIntToFP(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINTRINSIC_W_CHAIN(), LowerMSTORE(), lowerReductionSeq(), lowerScalarInsert(), lowerShuffleAsInsertPS(), lowerShuffleAsTruncBroadcast(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPERMV(), LowerStore(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerV16F32Shuffle(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV32I16Shuffle(), lowerV32I8Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV64I8Shuffle(), lowerV8F16Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), lowerVectorIntrinsicScalars(), LowerVSETCC(), lowerVZIP(), matchShuffleAsInsertPS(), narrowExtractedVectorSelect(), llvm::PPCTargetLowering::PerformDAGCombine(), performSHLCombine(), performUzpCombine(), promoteVCIXScalar(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), splitAndLowerShuffle(), vectorizeExtractedCast(), widenMaskVector(), and widenSubVector().

◆ getValue()

SDValue llvm::SDValue::getValue ( unsigned  R) const
inline

Definition at line 181 of file SelectionDAGNodes.h.

References SDValue().

Referenced by AddCombineTo64bitMLAL(), AVRDAGToDAGISel::select< AVRISD::CALL >(), AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::AArch64TargetLowering::changeStreamingMode(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineBitcast(), combineCarryDiamond(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTRACT_SUBVECTOR(), combineFP_EXTEND(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineLoad(), combineMaskedLoadConstantMask(), combineMOVDQ2Q(), combineSetCCAtomicArith(), combineSIntToFP(), combineTargetShuffle(), combineUADDO_CARRYDiamond(), combineVectorCompareAndMaskUnaryOp(), combineVectorSizedSetCCEquality(), combineX86INT_TO_FP(), ConvertBooleanCarryToCarryFlag(), ConvertCarryValueToCarryFlag(), EmitCmp(), emitComparison(), emitRepmovs(), emitRepstos(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFP_TO_UINT(), expandFSH64(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::SelectionDAG::expandMultipleResultFPLibCall(), llvm::TargetLowering::expandREM(), llvm::TargetLowering::expandUnalignedLoad(), llvm::SelectionDAG::expandVAArg(), llvm::SelectionDAG::expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), GeneratePerfectShuffle(), getAArch64XALUOOp(), getAVX2GatherNode(), getBROADCAST_LOAD(), llvm::RegsForValue::getCopyToRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFPBinOp(), getFPTernOp(), getGatherNode(), getMemCmpLoad(), llvm::MipsTargetLowering::getOpndList(), getOutputChainFromCallSeq(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::TargetLowering::LegalizeSetCCCondCode(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerABD(), LowerADDSUBO_CARRY(), lowerADDSUBO_CARRY(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerAtomicArith(), lowerBUILD_VECTORAsBroadCastLoad(), lowerBuildVectorAsBroadcast(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), llvm::TargetLowering::LowerOperationWrapper(), llvm::SystemZTargetLowering::LowerOperationWrapper(), lowerOverflowArithmetic(), LowerPARITY(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVECTOR_SHUFFLE(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), llvm::ARMTargetLowering::PerformCMOVCombine(), performConcatVectorsCombine(), performCSELCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDivRemCombine(), performExtractVectorEltCombine(), performFPExtendCombine(), performGatherLoadCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performScatterStoreCombine(), PerformSETCCCombine(), performSignExtendInRegCombine(), PerformSTORECombine(), performSubsToAndsCombine(), performUnpackCombine(), PerformVDUPCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVhrCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), llvm::SITargetLowering::PostISelFolding(), prepareDescriptorIndirectCall(), prepareIndirectCall(), PrepareTailCall(), reassociateCSELOperandsForCSE(), reduceANDOfAtomicLoad(), ReplaceCopyFromReg_128(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), ReplaceTcgen05Ld(), replaceVecCondBranchResults(), replaceVPICKVE2GRResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SkipExtensionForVMULL(), splitStores(), splitStoreSplat(), SplitStrictFPVectorOp(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryMemPairCombine(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), and widenVectorOpsToi8().

◆ getValueSizeInBits()

TypeSize llvm::SDValue::getValueSizeInBits ( ) const
inline

Returns the size of the value in bits.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 201 of file SelectionDAGNodes.h.

References llvm::EVT::getSizeInBits(), and getValueType().

Referenced by calculateByteProvider(), CalculateTailCallArgDest(), checkDot4MulSignedness(), combine_CC(), combineArithReduction(), combineBT(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineINSERT_SUBVECTOR(), combineMulToPMADDWD(), combinePredicateReduction(), combineSetCCMOVMSK(), combineShiftLeft(), combineStore(), combineTargetShuffle(), combineVectorCompareAndMaskUnaryOp(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), combineXorSubCTLZ(), combineZext(), llvm::SelectionDAG::computeKnownBits(), computeZeroableShuffleElements(), constructDup(), createVariablePermute(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandMULO(), fnegFoldsIntoOp(), foldSelectOfCTTZOrCTLZ(), getBT(), getFauxShuffleMask(), getHopForBuildVector(), llvm::SelectionDAG::getNode(), getVectorBitwiseReduce(), isHorizontalBinOp(), isTruncWithZeroHighBitsInput(), lookThroughSignExtension(), LowerAndToBT(), LowerAndToBTST(), lowerBuildVectorAsBroadcast(), lowerFCOPYSIGN(), lowerFP_TO_SINT_STORE(), matchBinaryShuffle(), MatchingStackOffset(), matchPERM(), matchPMADDWD_2(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMulCombine(), performSUBCombine(), reduceBuildVecToShuffleWithZero(), llvm::SelectionDAG::salvageDebugInfo(), llvm::SelectionDAGISel::SelectCodeCommon(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), and widenSubVector().

◆ getValueType()

EVT llvm::SDValue::getValueType ( ) const
inline

Return the ValueType of the referenced return value.

Definition at line 1260 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustBitcastSrcVectorSSE1(), llvm::VECustomDAG::annotateLegalAVL(), areLoadedOffsetButOtherwiseSame(), buildFromShuffleMostly(), BuildIntrinsicOp(), calculatePreExtendType(), calculateSrcByte(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canEmitConjunction(), canLowerSRLToRoundingShiftForVT(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithOp(), checkZExtBool(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndShuffleNot(), combineArithReduction(), combineAVX512SetCCToKMOV(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineBoolVectorAndTruncateStore(), combineBVOfVecSExt(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineFneg(), combineFP_EXTEND(), combineFP_ROUND(), combineGatherScatter(), combineHorizOpWithShuffle(), combineMaskedStore(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineSext(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineStoreValueFPToInt(), combineSubOfBoolean(), combineSVEReductionFP(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncate(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUIntToFP(), combineVectorPack(), combineVectorShiftImm(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combineX86CloadCstore(), combineX86ShuffleChain(), combineXor(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), concatSubVectors(), constructDup(), ConvertBooleanCarryToCarryFlag(), convertFixedMaskToScalableVector(), convertIntLogicToFPLogic(), createCMovFP(), createPSADBW(), createVariablePermute(), detectPMADDUBSW(), distributeOpThroughSelect(), eliminateFPCastPair(), EltsFromConsecutiveLoads(), EmitCmp(), emitFloatCompareMask(), emitIntrinsicWithCC(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandMULO(), llvm::SelectionDAG::expandMultipleResultFPLibCall(), llvm::TargetLowering::expandPartialReduceMLA(), ExpandPowI(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandUnalignedStore(), llvm::SelectionDAG::expandVAArg(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVECTOR_COMPRESS(), ExtendToType(), ExtendUsesToFormExtLoad(), extract128BitVector(), extract256BitVector(), ExtractBitFromMaskVector(), extractShiftForRotate(), extractSubVector(), FixupMMXIntrinsicTypes(), fnegFoldsIntoOp(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndOrOfSETCC(), foldConcatVector(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendedSignBitTest(), foldFPToIntToFP(), FoldIntToFPToInt(), foldReduceOperandViaVQDOT(), foldSelectOfCTTZOrCTLZ(), llvm::SelectionDAG::FoldSetCC(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldSubCtlzNot(), foldTruncStoreOfExt(), foldVectorXorShiftIntoCmp(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), GeneratePerfectShuffle(), generateSToVPermutedForVecShuffle(), llvm::SelectionDAG::getAssertAlign(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getAtomicCmpSwap(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), getBitTestCondition(), llvm::getBitwiseNotOperand(), getBT(), getBuildDwordsVector(), getBuildVectorizedValue(), getConstantLaneNumOfExtractHalfOperand(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getEstimate(), getFauxShuffleMask(), llvm::SelectionDAG::getGetFPEnv(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedLoadVP(), llvm::SelectionDAG::getIndexedMaskedLoad(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getInsertVectorElt(), getKnownUndefForVectorBinop(), llvm::VECustomDAG::getLegalReductionOpVVP(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadFFVP(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getNode(), getOutputChainFromCallSeq(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), getPRMT(), getPTest(), llvm::AMDGPUTargetLowering::getRecipEstimate(), llvm::LoongArchTargetLowering::getRecipEstimate(), getReductionSDNode(), getScalarValueSizeInBits(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetFPEnv(), getShuffleHalfVectors(), getSimpleValueType(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::LoongArchTargetLowering::getSqrtEstimate(), llvm::TargetLowering::getSqrtResultForDenormInput(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getStoreVP(), getSToVPermuted(), llvm::SelectionDAG::getStridedStoreVP(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), getValueSizeInBits(), llvm::SDUse::getValueType(), getVectorBitwiseReduce(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLowering::getVectorSubVecPointer(), getVPermMask(), insert128BitVector(), insertSubVector(), InvertCarryFlag(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOpFromAnd(), llvm::SITargetLowering::isCanonicalized(), isConditionalZeroOrAllOnes(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(), IsElementEquivalent(), isExtendedFrom16Bits(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), isHorizontalBinOpPart(), isI128MovedFromParts(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isSaturatingMinMax(), isTargetShuffleEquivalent(), llvm::TargetLoweringBase::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), llvm::TargetLoweringBase::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), llvm::SITargetLowering::legalizeTargetIndependentNode(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), LowerADDSUBO_CARRY(), lowerBuildVectorAsBroadcast(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORS_i1(), LowerConvertLow(), lowerDSPIntr(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), LowerF128Load(), LowerF128Store(), LowerF64Op(), LowerFCanonicalize(), lowerFCMPIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), lowerFP_TO_INT(), LowerFSINCOS(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), lowerLaneOp(), lowerLoadF128(), lowerMasksToReg(), LowerMUL(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::SITargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), lowerScalarInsert(), LowerSELECTWithCmpZero(), llvm::SITargetLowering::lowerSET_ROUNDING(), lowerShuffleAsElementInsertion(), lowerShuffleWithEXPAND(), lowerShuffleWithPACK(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), lowerStatepointMetaArgs(), LowerStore(), lowerStoreF128(), lowerSTOREVector(), LowerSVEIntrinsicIndex(), LowerTcgen05St(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVecReduce(), LowerVecReduceMinMax(), lowerVECTOR_COMPRESS(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), LowerVSETCC(), LowerWRITE_REGISTER(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::TargetLowering::makeLibCall(), llvm::SelectionDAG::makeStateFunctionCall(), llvm::ISD::matchBinaryPredicate(), matchBinaryShuffle(), matchExtFromI32orI32(), MatchingStackOffset(), matchMergedBFX(), matchPERM(), matchPMADDWD_2(), matchSetCC(), MatchVectorAllEqualTest(), mergeEltWithShuffle(), narrowExtractedVectorBinOp(), narrowIndex(), narrowInsertExtractVectorBinOp(), NarrowVector(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), PerformADDCombine(), PerformADDCombineWithOperands(), performAddSubIntoVectorOp(), performAddUADDVCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), performBitcastCombine(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performDupLane128Combine(), performExtBinopLoadFold(), PerformExtendCombine(), performExtendCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), PerformExtractFpToIntStores(), performExtractLastActiveCombine(), PerformFADDCombine(), PerformFADDCombineWithOperands(), performFirstTrueTestVectorCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performIntrinsicCombine(), performLastTrueTestVectorCombine(), PerformMinMaxFpToSatCombine(), performMOVFR2GR_SCombine(), PerformMULCombineWithOperands(), performNegCSelCombine(), performReinterpretCastCombine(), performScalarToVectorCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), performSETCCCombine(), PerformShuffleVMOVNCombine(), performSignExtendCombine(), performSignExtendInRegCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSTORECombine(), performSVEMulAddSubCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTRUNCATECombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVAddCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceBitwiseCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), performVectorExtCombine(), performVectorExtendCombine(), PerformVMOVRRDCombine(), performVP_STORECombine(), PerformVQDMULHCombine(), performVSelectCombine(), PerformVSELECTCombine(), performXORCombine(), llvm::SITargetLowering::PostISelFolding(), prepareTS1AM(), PromoteMaskArithmetic(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), refineUniformBase(), removeRedundantInsertVectorElt(), ReorganizeVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceVPICKVE2GRResults(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinOp(), scalarizeVectorStore(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HvxSelector::selectShuffle(), selectUmullSmull(), llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), llvm::X86TargetLowering::shouldScalarizeBinop(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splatPartsI64WithVL(), splitAndLowerShuffle(), splitStores(), splitStoreSplat(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::PPCTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), stripModuloOnShift(), tryBitfieldInsertOpFromOr(), tryCombineFixedPointConvert(), tryCombineMULLWithUZP1(), tryDemorganOfBooleanCondition(), tryFoldMADwithSRL(), tryFoldSelectIntoOp(), tryFormConcatFromShuffle(), tryGetOriginalBoolVectorType(), llvm::RISCVDAGToDAGISel::tryIndexedLoad(), tryLowerPartialReductionToDot(), tryLowerPartialReductionToWideAdd(), trySQDMULHCombine(), trySwapVSelectOperands(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), tryToFoldExtOfLoad(), tryToReplaceScalarFPConversionWithSVE(), llvm::SelectionDAG::UnrollVectorOp(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), visitORCommutative(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), llvm::VPMatchContext::VPMatchContext(), widenAbs(), widenBuildVec(), widenCtPop(), widenSubVector(), widenVec(), WidenVector(), and widenVectorToPartType().

◆ hasOneUse()

bool llvm::SDValue::hasOneUse ( ) const
inline

Return true if there is exactly one node using value ResNo of Node.

Definition at line 1302 of file SelectionDAGNodes.h.

Referenced by areLoadedOffsetButOtherwiseSame(), canEmitConjunction(), canonicalizeBitSelect(), CheckForMaskedLoad(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineAndShuffleNot(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBlendOfPermutes(), combineCMP(), combineDeMorganOfBoolean(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineINSERT_SUBVECTOR(), combineOr(), combineOrOfCZERO(), combineOrXorWithSETCC(), combineSelectAndUse(), combineSetCCAtomicArith(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineShuffleToFMAddSub(), combineSIntToFP(), combineStore(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineTargetShuffle(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineVWADDSUBWSelect(), combineX86ShufflesRecursively(), combineXor(), combineXorSubCTLZ(), combineZext(), convertIntLogicToFPLogic(), EmitAVX512Test(), EmitCmp(), foldBinOpIntoSelectIfProfitable(), foldExtendedSignBitTest(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), isADDADDMUL(), isBitfieldPositioningOpFromAnd(), isCalleeLoad(), isLoadOrMultipleLoads(), llvm::TargetLowering::isReassocProfitable(), llvm::AArch64TargetLowering::isReassocProfitable(), llvm::SITargetLowering::isReassocProfitable(), isWorthFoldingIntoOrrWithShift(), LowerAVXCONCAT_VECTORS(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleOfExtractsAsVperm(), LowerStore(), lowerV2X128Shuffle(), LowerVSETCC(), mayUseP9Setb(), narrowExtractedVectorBinOp(), narrowVectorSelect(), performANDCombine(), PerformBFICombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPExtendCombine(), performINSERT_VECTOR_ELTCombine(), performIntToFpCombine(), PerformORCombine(), performSETCCCombine(), performSHLCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), performSRACombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), performSUBCombine(), performSVEMulAddSubCombine(), performTRUNCATECombine(), performTruncateCombine(), PerformVMOVrhCombine(), performVP_STORECombine(), performVSelectCombine(), performXORCombine(), pushAddIntoCmovOfConsts(), reachesChainWithoutSideEffects(), reassociateCSELOperandsForCSE(), reduceANDOfAtomicLoad(), reduceBuildVecToShuffleWithZero(), replaceZeroVectorStore(), scalarizeExtEltFP(), scalarizeExtractedBinOp(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), tryBitfieldInsertOpFromOr(), tryDemorganOfBooleanCondition(), tryOrrWithShift(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), llvm::RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(), trySQDMULHCombine(), trySwapVSelectOperands(), tryToFoldExtendSelectLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), usePartialVectorLoads(), widenAbs(), widenBuildVec(), and widenCtPop().

◆ isAnyAdd()

bool llvm::SDValue::isAnyAdd ( ) const
inline

Definition at line 1296 of file SelectionDAGNodes.h.

◆ isMachineOpcode()

bool llvm::SDValue::isMachineOpcode ( ) const
inline

Definition at line 1284 of file SelectionDAGNodes.h.

Referenced by isEligibleToFoldADDIForFasterLocalAccesses(), isF128MovedFromParts(), PeepholePPC64ZExtGather(), and llvm::SITargetLowering::PostISelFolding().

◆ isOperandOf()

bool SDValue::isOperandOf ( const SDNode *  N) const

Return true if the referenced return value is an operand of N.

Definition at line 12970 of file SelectionDAG.cpp.

References llvm::is_contained(), and N.

◆ isTargetOpcode()

bool llvm::SDValue::isTargetOpcode ( ) const
inline

Definition at line 1280 of file SelectionDAGNodes.h.

◆ isUndef()

bool llvm::SDValue::isUndef ( ) const
inline

Definition at line 1292 of file SelectionDAGNodes.h.

Referenced by buildMergeScalars(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleVectorByLane(), combineAndnp(), combineAndShuffleNot(), combineConcatVectorOfExtracts(), combineConcatVectorOfShuffleAndItsOperands(), combineINSERT_SUBVECTOR(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineTargetShuffle(), combineToVWMACC(), combineVectorHADDSUB(), combineVectorInsert(), combineVectorPack(), combineVectorShiftImm(), combineVqdotAccum(), combineVWADDSUBWSelect(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), combineXor(), combineZext(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandVECTOR_COMPRESS(), ExtendToType(), extractSubVector(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::foldConstantFPMath(), llvm::SelectionDAG::FoldSetCC(), foldShuffleOfConcatUndefs(), formSplatFromShuffles(), GenerateTBL(), getFauxShuffleMask(), getHopForBuildVector(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), llvm::BuildVectorSDNode::getRepeatedSequence(), getScalarMaskingNode(), getSingleShuffleSrc(), getTargetShuffleAndZeroables(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), getVectorShuffle(), getVSlidedown(), getVSlideup(), getWideningInterleave(), insert1BitVector(), insertSubVector(), isAddSubOrSubAdd(), llvm::BuildVectorSDNode::isConstantSplat(), isFNEG(), isHopBuildVector(), isHorizontalBinOpPart(), isSplatBV(), llvm::SelectionDAG::isUndef(), joinDwords(), lower128BitShuffle(), lower1BitShuffleAsKSHIFTR(), lower256BitShuffle(), LowerAVXCONCAT_VECTORS(), lowerBitreverseShuffle(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTTZ(), LowerF128Load(), LowerF128Store(), lowerLoadF128(), lowerLoadI1(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarSplat(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), llvm::VETargetLowering::lowerSTORE(), lowerStoreF128(), lowerStoreI1(), LowerToHorizontalOp(), lowerV16F32Shuffle(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV2X128Shuffle(), lowerV32I16Shuffle(), lowerV32I8Shuffle(), lowerV4F64Shuffle(), lowerV4I64Shuffle(), lowerV64I8Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), lowerVECTOR_COMPRESS(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVectorIntrinsicScalars(), lowerVZIP(), llvm::ISD::matchBinaryPredicate(), matchShuffleAsBlend(), matchShuffleWithPACK(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), PerformSplittingToNarrowingStores(), PerformVECTOR_SHUFFLECombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), llvm::HvxSelector::selectShuffle(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), simplifyOp_VL(), simplifyShuffleOfShuffle(), and llvm::X86TargetLowering::visitMaskedLoad().

◆ operator bool()

llvm::SDValue::operator bool ( ) const
inlineexplicit

Definition at line 177 of file SelectionDAGNodes.h.

◆ operator!=()

bool llvm::SDValue::operator!= ( const SDValue &  O) const
inline

Definition at line 171 of file SelectionDAGNodes.h.

References operator==().

◆ operator->()

SDNode * llvm::SDValue::operator-> ( ) const
inline

Definition at line 166 of file SelectionDAGNodes.h.

◆ operator<()

bool llvm::SDValue::operator< ( const SDValue &  O) const
inline

Definition at line 174 of file SelectionDAGNodes.h.

◆ operator==()

bool llvm::SDValue::operator== ( const SDValue &  O) const
inline

Definition at line 168 of file SelectionDAGNodes.h.

Referenced by operator!=().

◆ reachesChainWithoutSideEffects()

bool SDValue::reachesChainWithoutSideEffects ( SDValue  Dest,
unsigned  Depth = 2 
) const

Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.

reachesChainWithoutSideEffects - Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions on any chain path.

In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.

In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.

Note that we only need to examine chains when we're searching for side-effects; SelectionDAG requires that all side-effects are represented by chains, even if another operand would force a specific ordering. This constraint is necessary to allow transformations like splitting loads.

Definition at line 12989 of file SelectionDAG.cpp.

References llvm::all_of(), llvm::Depth, getOpcode(), hasOneUse(), llvm::is_contained(), and llvm::ISD::TokenFactor.

◆ setNode()

void llvm::SDValue::setNode ( SDNode *  N)
inline

set the SDNode

Definition at line 164 of file SelectionDAGNodes.h.

References N.

Referenced by tryCombineMULLWithUZP1().

◆ use_empty()

bool llvm::SDValue::use_empty ( ) const
inline

Return true if there are no nodes using value ResNo of Node.

Definition at line 1298 of file SelectionDAGNodes.h.

Referenced by llvm::TargetLowering::getNegatedExpression(), and llvm::SelectionDAG::makeEquivalentMemoryOrdering().

Friends And Related Function Documentation

◆ DenseMapInfo< SDValue >

friend struct DenseMapInfo< SDValue >
friend

Definition at line 132 of file SelectionDAGNodes.h.

The documentation for this class was generated from the following files:
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