LLVM  16.0.0git
X86SelectionDAGInfo.cpp
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1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86SelectionDAGInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86SelectionDAGInfo.h"
14 #include "X86ISelLowering.h"
15 #include "X86InstrInfo.h"
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
21 #include "llvm/IR/DerivedTypes.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "x86-selectiondag-info"
26 
27 static cl::opt<bool>
28  UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false),
29  cl::desc("Use fast short rep mov in memcpy lowering"));
30 
31 bool X86SelectionDAGInfo::isBaseRegConflictPossible(
32  SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
33  // We cannot use TRI->hasBasePointer() until *after* we select all basic
34  // blocks. Legalization may introduce new stack temporaries with large
35  // alignment requirements. Fall back to generic code if there are any
36  // dynamic stack adjustments (hopefully rare) and the base pointer would
37  // conflict if we had to use it.
39  if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
40  return false;
41 
42  const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
44  return llvm::is_contained(ClobberSet, TRI->getBaseRegister());
45 }
46 
48  SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
49  SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
50  MachinePointerInfo DstPtrInfo) const {
51  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
52  const X86Subtarget &Subtarget =
54 
55 #ifndef NDEBUG
56  // If the base register might conflict with our physical registers, bail out.
57  const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
59  assert(!isBaseRegConflictPossible(DAG, ClobberSet));
60 #endif
61 
62  // If to a segment-relative address space, use the default lowering.
63  if (DstPtrInfo.getAddrSpace() >= 256)
64  return SDValue();
65 
66  // If not DWORD aligned or size is more than the threshold, call the library.
67  // The libc version is likely to be faster for these cases. It can use the
68  // address value and run time information about the CPU.
69  if (Alignment < Align(4) || !ConstantSize ||
70  ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold())
71  return SDValue();
72 
73  uint64_t SizeVal = ConstantSize->getZExtValue();
74  SDValue InFlag;
75  EVT AVT;
76  SDValue Count;
77  ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Val);
78  unsigned BytesLeft = 0;
79  if (ValC) {
80  unsigned ValReg;
81  uint64_t Val = ValC->getZExtValue() & 255;
82 
83  // If the value is a constant, then we can potentially use larger sets.
84  if (Alignment > Align(2)) {
85  // DWORD aligned
86  AVT = MVT::i32;
87  ValReg = X86::EAX;
88  Val = (Val << 8) | Val;
89  Val = (Val << 16) | Val;
90  if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
91  AVT = MVT::i64;
92  ValReg = X86::RAX;
93  Val = (Val << 32) | Val;
94  }
95  } else if (Alignment == Align(2)) {
96  // WORD aligned
97  AVT = MVT::i16;
98  ValReg = X86::AX;
99  Val = (Val << 8) | Val;
100  } else {
101  // Byte aligned
102  AVT = MVT::i8;
103  ValReg = X86::AL;
104  Count = DAG.getIntPtrConstant(SizeVal, dl);
105  }
106 
107  if (AVT.bitsGT(MVT::i8)) {
108  unsigned UBytes = AVT.getSizeInBits() / 8;
109  Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
110  BytesLeft = SizeVal % UBytes;
111  }
112 
113  Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
114  InFlag);
115  InFlag = Chain.getValue(1);
116  } else {
117  AVT = MVT::i8;
118  Count = DAG.getIntPtrConstant(SizeVal, dl);
119  Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Val, InFlag);
120  InFlag = Chain.getValue(1);
121  }
122 
123  bool Use64BitRegs = Subtarget.isTarget64BitLP64();
124  Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX,
125  Count, InFlag);
126  InFlag = Chain.getValue(1);
127  Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RDI : X86::EDI,
128  Dst, InFlag);
129  InFlag = Chain.getValue(1);
130 
132  SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
133  Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
134 
135  if (BytesLeft) {
136  // Handle the last 1 - 7 bytes.
137  unsigned Offset = SizeVal - BytesLeft;
138  EVT AddrVT = Dst.getValueType();
139  EVT SizeVT = Size.getValueType();
140 
141  Chain =
142  DAG.getMemset(Chain, dl,
143  DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
144  DAG.getConstant(Offset, dl, AddrVT)),
145  Val, DAG.getConstant(BytesLeft, dl, SizeVT), Alignment,
146  isVolatile, AlwaysInline,
147  /* isTailCall */ false, DstPtrInfo.getWithOffset(Offset));
148  }
149 
150  // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
151  return Chain;
152 }
153 
154 /// Emit a single REP MOVS{B,W,D,Q} instruction.
155 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG,
156  const SDLoc &dl, SDValue Chain, SDValue Dst,
157  SDValue Src, SDValue Size, MVT AVT) {
158  const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
159  const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX;
160  const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
161  const unsigned SI = Use64BitRegs ? X86::RSI : X86::ESI;
162 
163  SDValue InFlag;
164  Chain = DAG.getCopyToReg(Chain, dl, CX, Size, InFlag);
165  InFlag = Chain.getValue(1);
166  Chain = DAG.getCopyToReg(Chain, dl, DI, Dst, InFlag);
167  InFlag = Chain.getValue(1);
168  Chain = DAG.getCopyToReg(Chain, dl, SI, Src, InFlag);
169  InFlag = Chain.getValue(1);
170 
172  SDValue Ops[] = {Chain, DAG.getValueType(AVT), InFlag};
173  return DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
174 }
175 
176 /// Emit a single REP MOVSB instruction for a particular constant size.
177 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
178  const SDLoc &dl, SDValue Chain, SDValue Dst,
179  SDValue Src, uint64_t Size) {
180  return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
181  DAG.getIntPtrConstant(Size, dl), MVT::i8);
182 }
183 
184 /// Returns the best type to use with repmovs depending on alignment.
185 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget,
186  uint64_t Align) {
187  assert((Align != 0) && "Align is normalized");
188  assert(isPowerOf2_64(Align) && "Align is a power of 2");
189  switch (Align) {
190  case 1:
191  return MVT::i8;
192  case 2:
193  return MVT::i16;
194  case 4:
195  return MVT::i32;
196  default:
197  return Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
198  }
199 }
200 
201 /// Returns a REP MOVS instruction, possibly with a few load/stores to implement
202 /// a constant size memory copy. In some cases where we know REP MOVS is
203 /// inefficient we return an empty SDValue so the calling code can either
204 /// generate a load/store sequence or call the runtime memcpy function.
206  SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl,
207  SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT,
208  unsigned Align, bool isVolatile, bool AlwaysInline,
209  MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) {
210 
211  /// TODO: Revisit next line: big copy with ERMSB on march >= haswell are very
212  /// efficient.
213  if (!AlwaysInline && Size > Subtarget.getMaxInlineSizeThreshold())
214  return SDValue();
215 
216  /// If we have enhanced repmovs we use it.
217  if (Subtarget.hasERMSB())
218  return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
219 
220  assert(!Subtarget.hasERMSB() && "No efficient RepMovs");
221  /// We assume runtime memcpy will do a better job for unaligned copies when
222  /// ERMS is not present.
223  if (!AlwaysInline && (Align & 3) != 0)
224  return SDValue();
225 
226  const MVT BlockType = getOptimalRepmovsType(Subtarget, Align);
227  const uint64_t BlockBytes = BlockType.getSizeInBits() / 8;
228  const uint64_t BlockCount = Size / BlockBytes;
229  const uint64_t BytesLeft = Size % BlockBytes;
230  SDValue RepMovs =
231  emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
232  DAG.getIntPtrConstant(BlockCount, dl), BlockType);
233 
234  /// RepMov can process the whole length.
235  if (BytesLeft == 0)
236  return RepMovs;
237 
238  assert(BytesLeft && "We have leftover at this point");
239 
240  /// In case we optimize for size we use repmovsb even if it's less efficient
241  /// so we can save the loads/stores of the leftover.
243  return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
244 
245  // Handle the last 1 - 7 bytes.
247  Results.push_back(RepMovs);
248  unsigned Offset = Size - BytesLeft;
249  EVT DstVT = Dst.getValueType();
250  EVT SrcVT = Src.getValueType();
251  Results.push_back(DAG.getMemcpy(
252  Chain, dl,
253  DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
254  DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
255  DAG.getConstant(BytesLeft, dl, SizeVT), llvm::Align(Align), isVolatile,
256  /*AlwaysInline*/ true, /*isTailCall*/ false,
257  DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset)));
258  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
259 }
260 
262  SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
263  SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
264  MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
265  // If to a segment-relative address space, use the default lowering.
266  if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256)
267  return SDValue();
268 
269  // If the base registers conflict with our physical registers, use the default
270  // lowering.
271  const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
273  if (isBaseRegConflictPossible(DAG, ClobberSet))
274  return SDValue();
275 
276  const X86Subtarget &Subtarget =
278 
279  // If enabled and available, use fast short rep mov.
280  if (UseFSRMForMemcpy && Subtarget.hasFSRM())
281  return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8);
282 
283  /// Handle constant sizes,
284  if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size))
285  return emitConstantSizeRepmov(
286  DAG, Subtarget, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
287  Size.getValueType(), Alignment.value(), isVolatile, AlwaysInline,
288  DstPtrInfo, SrcPtrInfo);
289 
290  return SDValue();
291 }
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
Definition: SelectionDAG.cpp:7330
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
X86Subtarget.h
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:767
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1858
X86SelectionDAGInfo.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9378
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:282
UseFSRMForMemcpy
static cl::opt< bool > UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false), cl::desc("Use fast short rep mov in memcpy lowering"))
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
emitConstantSizeRepmov
static SDValue emitConstantSizeRepmov(SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
Returns a REP MOVS instruction, possibly with a few load/stores to implement a constant size memory c...
Definition: X86SelectionDAGInfo.cpp:205
SelectionDAG.h
llvm::SelectionDAG::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:471
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
emitRepmovsB
static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size)
Emit a single REP MOVSB instruction for a particular constant size.
Definition: X86SelectionDAGInfo.cpp:177
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1514
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override
Emit target-specific code that performs a memcpy.
Definition: X86SelectionDAGInfo.cpp:261
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:184
emitRepmovs
static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, MVT AVT)
Emit a single REP MOVS{B,W,D,Q} instruction.
Definition: X86SelectionDAGInfo.cpp:155
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::cl::opt< bool >
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
getOptimalRepmovsType
static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, uint64_t Align)
Returns the best type to use with repmovs depending on alignment.
Definition: X86SelectionDAGInfo.cpp:185
uint64_t
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1634
llvm::SelectionDAG::getMemset
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7546
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9072
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1868
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::X86ISD::REP_STOS
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
Definition: X86ISelLowering.h:137
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1597
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:79
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::X86ISD::REP_MOVS
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
Definition: X86ISelLowering.h:140
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:994
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
uint16_t
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
X86ISelLowering.h
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
X86RegisterInfo.h
llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const override
Emit target-specific code that performs a memset.
Definition: X86SelectionDAGInfo.cpp:47
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::WebAssembly::BlockType
BlockType
Used as immediate MachineOperands for block signatures.
Definition: WebAssemblyTypeUtilities.h:31
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
DerivedTypes.h
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
Definition: ValueTypes.h:256
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::MachineFrameInfo::hasOpaqueSPAdjustment
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
Definition: MachineFrameInfo.h:617
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:466
llvm::cl::desc
Definition: CommandLine.h:413
llvm::X86Subtarget::getMaxInlineSizeThreshold
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition: X86Subtarget.h:152
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
X86InstrInfo.h
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:463
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24