LLVM  16.0.0git
X86ISelLowering.cpp
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1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
16 #include "X86.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86IntrinsicsInfo.h"
21 #include "X86MachineFunctionInfo.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DerivedTypes.h"
47 #include "llvm/IR/DiagnosticInfo.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalAlias.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/IRBuilder.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/Intrinsics.h"
54 #include "llvm/IR/PatternMatch.h"
55 #include "llvm/MC/MCAsmInfo.h"
56 #include "llvm/MC/MCContext.h"
57 #include "llvm/MC/MCExpr.h"
58 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/KnownBits.h"
65 #include <algorithm>
66 #include <bitset>
67 #include <cctype>
68 #include <numeric>
69 using namespace llvm;
70 
71 #define DEBUG_TYPE "x86-isel"
72 
73 STATISTIC(NumTailCalls, "Number of tail calls");
74 
76  "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77  cl::desc(
78  "Sets the preferable loop alignment for experiments (as log2 bytes) "
79  "for innermost loops only. If specified, this option overrides "
80  "alignment set by x86-experimental-pref-loop-alignment."),
81  cl::Hidden);
82 
84  "mul-constant-optimization", cl::init(true),
85  cl::desc("Replace 'mul x, Const' with more effective instructions like "
86  "SHIFT, LEA, etc."),
87  cl::Hidden);
88 
90  "x86-experimental-unordered-atomic-isel", cl::init(false),
91  cl::desc("Use LoadSDNode and StoreSDNode instead of "
92  "AtomicSDNode for unordered atomic loads and "
93  "stores respectively."),
94  cl::Hidden);
95 
96 /// Call this when the user attempts to do something unsupported, like
97 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98 /// report_fatal_error, so calling code should attempt to recover without
99 /// crashing.
100 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101  const char *Msg) {
103  DAG.getContext()->diagnose(
105 }
106 
108  const X86Subtarget &STI)
109  : TargetLowering(TM), Subtarget(STI) {
110  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
112 
113  // Set up the TargetLowering object.
114 
115  // X86 is weird. It always uses i8 for shift amounts and setcc results.
117  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
119 
120  // For 64-bit, since we have so many registers, use the ILP scheduler.
121  // For 32-bit, use the register pressure specific scheduling.
122  // For Atom, always use ILP scheduling.
123  if (Subtarget.isAtom())
125  else if (Subtarget.is64Bit())
127  else
129  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
131 
132  // Bypass expensive divides and use cheaper ones.
133  if (TM.getOptLevel() >= CodeGenOpt::Default) {
134  if (Subtarget.hasSlowDivide32())
135  addBypassSlowDiv(32, 8);
136  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
137  addBypassSlowDiv(64, 32);
138  }
139 
140  // Setup Windows compiler runtime calls.
141  if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
142  static const struct {
143  const RTLIB::Libcall Op;
144  const char * const Name;
145  const CallingConv::ID CC;
146  } LibraryCalls[] = {
147  { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
148  { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
149  { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
150  { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
151  { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
152  };
153 
154  for (const auto &LC : LibraryCalls) {
155  setLibcallName(LC.Op, LC.Name);
156  setLibcallCallingConv(LC.Op, LC.CC);
157  }
158  }
159 
160  if (Subtarget.getTargetTriple().isOSMSVCRT()) {
161  // MSVCRT doesn't have powi; fall back to pow
162  setLibcallName(RTLIB::POWI_F32, nullptr);
163  setLibcallName(RTLIB::POWI_F64, nullptr);
164  }
165 
166  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
167  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
168  // FIXME: Should we be limiting the atomic size on other configs? Default is
169  // 1024.
170  if (!Subtarget.canUseCMPXCHG8B())
172 
173  setMaxDivRemBitWidthSupported(Subtarget.is64Bit() ? 128 : 64);
174 
175  // Set up the register classes.
176  addRegisterClass(MVT::i8, &X86::GR8RegClass);
177  addRegisterClass(MVT::i16, &X86::GR16RegClass);
178  addRegisterClass(MVT::i32, &X86::GR32RegClass);
179  if (Subtarget.is64Bit())
180  addRegisterClass(MVT::i64, &X86::GR64RegClass);
181 
182  for (MVT VT : MVT::integer_valuetypes())
184 
185  // We don't accept any truncstore of integer registers.
192 
194 
195  // SETOEQ and SETUNE require checking two conditions.
196  for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
199  }
200 
201  // Integer absolute.
202  if (Subtarget.canUseCMOV()) {
205  if (Subtarget.is64Bit())
207  }
208 
209  // Signed saturation subtraction.
213  if (Subtarget.is64Bit())
215 
216  // Funnel shifts.
217  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
218  // For slow shld targets we only lower for code size.
219  LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
220 
221  setOperationAction(ShiftOp , MVT::i8 , Custom);
222  setOperationAction(ShiftOp , MVT::i16 , Custom);
223  setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
224  if (Subtarget.is64Bit())
225  setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
226  }
227 
228  if (!Subtarget.useSoftFloat()) {
229  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
230  // operation.
235  // We have an algorithm for SSE2, and we turn this into a 64-bit
236  // FILD or VCVTUSI2SS/SD for other targets.
239  // We have an algorithm for SSE2->double, and we turn this into a
240  // 64-bit FILD followed by conditional FADD for other targets.
243 
244  // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
245  // this operation.
248  // SSE has no i16 to fp conversion, only i32. We promote in the handler
249  // to allow f80 to use i16 and f64 to use i16 with sse1 only
252  // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
255  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
256  // are Legal, f80 is custom lowered.
259 
260  // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
261  // this operation.
263  // FIXME: This doesn't generate invalid exception when it should. PR44019.
269  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
270  // are Legal, f80 is custom lowered.
273 
274  // Handle FP_TO_UINT by promoting the destination to a larger signed
275  // conversion.
277  // FIXME: This doesn't generate invalid exception when it should. PR44019.
280  // FIXME: This doesn't generate invalid exception when it should. PR44019.
286 
291 
292  if (!Subtarget.is64Bit()) {
295  }
296  }
297 
298  if (Subtarget.hasSSE2()) {
299  // Custom lowering for saturating float to int conversions.
300  // We handle promotion to larger result types manually.
301  for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
304  }
305  if (Subtarget.is64Bit()) {
308  }
309  }
310 
311  // Handle address space casts between mixed sized pointers.
314 
315  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
316  if (!Subtarget.hasSSE2()) {
319  if (Subtarget.is64Bit()) {
321  // Without SSE, i64->f64 goes through memory.
323  }
324  } else if (!Subtarget.is64Bit())
326 
327  // Scalar integer divide and remainder are lowered to use operations that
328  // produce two results, to match the available instructions. This exposes
329  // the two-result form to trivial CSE, which is able to combine x/y and x%y
330  // into a single instruction.
331  //
332  // Scalar integer multiply-high is also lowered to use two-result
333  // operations, to match the available instructions. However, plain multiply
334  // (low) operations are left as Legal, as there are single-result
335  // instructions for this in x86. Using the two-result multiply instructions
336  // when both high and low results are needed must be arranged by dagcombine.
337  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
344  }
345 
348  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
352  }
353  if (Subtarget.is64Bit())
358 
363 
364  if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
367  }
368 
369  // Promote the i8 variants and force them on up to i32 which has a shorter
370  // encoding.
373  // Promoted i16. tzcntw has a false dependency on Intel CPUs. For BSF, we emit
374  // a REP prefix to encode it as TZCNT for modern CPUs so it makes sense to
375  // promote that too.
378 
379  if (!Subtarget.hasBMI()) {
382  if (Subtarget.is64Bit()) {
385  }
386  }
387 
388  if (Subtarget.hasLZCNT()) {
389  // When promoting the i8 variants, force them to i32 for a shorter
390  // encoding.
393  } else {
394  for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
395  if (VT == MVT::i64 && !Subtarget.is64Bit())
396  continue;
399  }
400  }
401 
404  // Special handling for half-precision floating point conversions.
405  // If we don't have F16C support, then lower half float conversions
406  // into library calls.
408  Op, MVT::f32,
409  (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
410  // There's never any support for operations beyond MVT::f32.
414  }
415 
416  for (MVT VT : {MVT::f32, MVT::f64, MVT::f80, MVT::f128}) {
421 
424  }
425 
429  if (Subtarget.is64Bit())
431  if (Subtarget.hasPOPCNT()) {
433  // popcntw is longer to encode than popcntl and also has a false dependency
434  // on the dest that popcntl hasn't had since Cannon Lake.
436  } else {
440  if (Subtarget.is64Bit())
442  else
444  }
445 
447 
448  if (!Subtarget.hasMOVBE())
450 
451  // X86 wants to expand cmov itself.
452  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
457  }
458  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
459  if (VT == MVT::i64 && !Subtarget.is64Bit())
460  continue;
463  }
464 
465  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
468 
470  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
471  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
475  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
476  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
477 
478  // Darwin ABI issue.
479  for (auto VT : { MVT::i32, MVT::i64 }) {
480  if (VT == MVT::i64 && !Subtarget.is64Bit())
481  continue;
488  }
489 
490  // 64-bit shl, sra, srl (iff 32-bit x86)
491  for (auto VT : { MVT::i32, MVT::i64 }) {
492  if (VT == MVT::i64 && !Subtarget.is64Bit())
493  continue;
497  }
498 
499  if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
501 
503 
504  // Expand certain atomics
505  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
513  }
514 
515  if (!Subtarget.is64Bit())
517 
518  if (Subtarget.canUseCMPXCHG16B())
520 
521  // FIXME - use subtarget debug flags
522  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
523  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
524  TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
526  }
527 
530 
533 
536  if (Subtarget.isTargetPS())
538  else
540 
541  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544  bool Is64Bit = Subtarget.is64Bit();
547 
550 
552 
553  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
556 
558 
559  auto setF16Action = [&] (MVT VT, LegalizeAction Action) {
560  setOperationAction(ISD::FABS, VT, Action);
561  setOperationAction(ISD::FNEG, VT, Action);
563  setOperationAction(ISD::FREM, VT, Action);
564  setOperationAction(ISD::FMA, VT, Action);
565  setOperationAction(ISD::FMINNUM, VT, Action);
566  setOperationAction(ISD::FMAXNUM, VT, Action);
567  setOperationAction(ISD::FMINIMUM, VT, Action);
568  setOperationAction(ISD::FMAXIMUM, VT, Action);
569  setOperationAction(ISD::FSIN, VT, Action);
570  setOperationAction(ISD::FCOS, VT, Action);
571  setOperationAction(ISD::FSINCOS, VT, Action);
572  setOperationAction(ISD::FSQRT, VT, Action);
573  setOperationAction(ISD::FPOW, VT, Action);
574  setOperationAction(ISD::FLOG, VT, Action);
575  setOperationAction(ISD::FLOG2, VT, Action);
576  setOperationAction(ISD::FLOG10, VT, Action);
577  setOperationAction(ISD::FEXP, VT, Action);
578  setOperationAction(ISD::FEXP2, VT, Action);
579  setOperationAction(ISD::FCEIL, VT, Action);
580  setOperationAction(ISD::FFLOOR, VT, Action);
581  setOperationAction(ISD::FNEARBYINT, VT, Action);
582  setOperationAction(ISD::FRINT, VT, Action);
583  setOperationAction(ISD::BR_CC, VT, Action);
584  setOperationAction(ISD::SETCC, VT, Action);
586  setOperationAction(ISD::SELECT_CC, VT, Action);
587  setOperationAction(ISD::FROUND, VT, Action);
588  setOperationAction(ISD::FROUNDEVEN, VT, Action);
589  setOperationAction(ISD::FTRUNC, VT, Action);
590  };
591 
592  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
593  // f16, f32 and f64 use SSE.
594  // Set up the FP register classes.
595  addRegisterClass(MVT::f16, Subtarget.hasAVX512() ? &X86::FR16XRegClass
596  : &X86::FR16RegClass);
597  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
598  : &X86::FR32RegClass);
599  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
600  : &X86::FR64RegClass);
601 
602  // Disable f32->f64 extload as we can only generate this in one instruction
603  // under optsize. So its easier to pattern match (fpext (load)) for that
604  // case instead of needing to emit 2 instructions for extload in the
605  // non-optsize case.
607 
608  for (auto VT : { MVT::f32, MVT::f64 }) {
609  // Use ANDPD to simulate FABS.
611 
612  // Use XORP to simulate FNEG.
614 
615  // Use ANDPD and ORPD to simulate FCOPYSIGN.
617 
618  // These might be better off as horizontal vector ops.
621 
622  // We don't support sin/cos/fmod
626  }
627 
628  // Half type will be promoted by default.
629  setF16Action(MVT::f16, Promote);
637 
666 
667  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
668  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
669 
670  // Lower this to MOVMSK plus an AND.
673 
674  } else if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1() &&
675  (UseX87 || Is64Bit)) {
676  // Use SSE for f32, x87 for f64.
677  // Set up the FP register classes.
678  addRegisterClass(MVT::f32, &X86::FR32RegClass);
679  if (UseX87)
680  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
681 
682  // Use ANDPS to simulate FABS.
684 
685  // Use XORP to simulate FNEG.
687 
688  if (UseX87)
690 
691  // Use ANDPS and ORPS to simulate FCOPYSIGN.
692  if (UseX87)
695 
696  // We don't support sin/cos/fmod
700 
701  if (UseX87) {
702  // Always expand sin/cos functions even though x87 has an instruction.
706  }
707  } else if (UseX87) {
708  // f32 and f64 in x87.
709  // Set up the FP register classes.
710  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
711  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
712 
713  for (auto VT : { MVT::f32, MVT::f64 }) {
716 
717  // Always expand sin/cos functions even though x87 has an instruction.
721  }
722  }
723 
724  // Expand FP32 immediates into loads from the stack, save special cases.
725  if (isTypeLegal(MVT::f32)) {
726  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
727  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
728  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
729  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
730  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
731  } else // SSE immediates.
732  addLegalFPImmediate(APFloat(+0.0f)); // xorps
733  }
734  // Expand FP64 immediates into loads from the stack, save special cases.
735  if (isTypeLegal(MVT::f64)) {
736  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
737  addLegalFPImmediate(APFloat(+0.0)); // FLD0
738  addLegalFPImmediate(APFloat(+1.0)); // FLD1
739  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
740  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
741  } else // SSE immediates.
742  addLegalFPImmediate(APFloat(+0.0)); // xorpd
743  }
744  // Support fp16 0 immediate.
745  if (isTypeLegal(MVT::f16))
746  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
747 
748  // Handle constrained floating-point operations of scalar.
761 
762  // We don't support FMA.
765 
766  // f80 always uses X87.
767  if (UseX87) {
768  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
771  {
773  addLegalFPImmediate(TmpFlt); // FLD0
774  TmpFlt.changeSign();
775  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
776 
777  bool ignored;
778  APFloat TmpFlt2(+1.0);
780  &ignored);
781  addLegalFPImmediate(TmpFlt2); // FLD1
782  TmpFlt2.changeSign();
783  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
784  }
785 
786  // Always expand sin/cos functions even though x87 has an instruction.
790 
801 
802  // Handle constrained floating-point operations of scalar.
808  if (isTypeLegal(MVT::f16)) {
811  } else {
813  }
814  // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
815  // as Custom.
817  }
818 
819  // f128 uses xmm registers, but most operations require libcalls.
820  if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
821  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
822  : &X86::VR128RegClass);
823 
824  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
825 
836 
840 
846  // No STRICT_FSINCOS
849 
852  // We need to custom handle any FP_ROUND with an f128 input, but
853  // LegalizeDAG uses the result type to know when to run a custom handler.
854  // So we have to list all legal floating point result types here.
855  if (isTypeLegal(MVT::f32)) {
858  }
859  if (isTypeLegal(MVT::f64)) {
862  }
863  if (isTypeLegal(MVT::f80)) {
866  }
867 
869 
876  }
877 
878  // Always use a library call for pow.
883 
891 
892  // Some FP actions are always expanded for vector types.
893  for (auto VT : { MVT::v8f16, MVT::v16f16, MVT::v32f16,
907  }
908 
909  // First set operation action for all vector types to either promote
910  // (for widening) or expand (for scalarization). Then we will selectively
911  // turn on ones that can be effectively codegen'd.
912  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
950  for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
951  setTruncStoreAction(InnerVT, VT, Expand);
952 
953  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
954  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
955 
956  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
957  // types, we have to deal with them whether we ask for Expansion or not.
958  // Setting Expand causes its own optimisation problems though, so leave
959  // them legal.
960  if (VT.getVectorElementType() == MVT::i1)
961  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
962 
963  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
964  // split/scalarized right now.
965  if (VT.getVectorElementType() == MVT::f16 ||
967  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
968  }
969  }
970 
971  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
972  // with -msoft-float, disable use of MMX as well.
973  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
974  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
975  // No operations on x86mmx supported, everything uses intrinsics.
976  }
977 
978  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
979  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
980  : &X86::VR128RegClass);
981 
990 
993 
999  }
1000 
1001  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
1002  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
1003  : &X86::VR128RegClass);
1004 
1005  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
1006  // registers cannot be used even for integer operations.
1007  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
1008  : &X86::VR128RegClass);
1009  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
1010  : &X86::VR128RegClass);
1011  addRegisterClass(MVT::v8f16, Subtarget.hasVLX() ? &X86::VR128XRegClass
1012  : &X86::VR128RegClass);
1013  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
1014  : &X86::VR128RegClass);
1015  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
1016  : &X86::VR128RegClass);
1017 
1018  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
1024  }
1025 
1029 
1042 
1046 
1050 
1051  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1056  }
1057 
1068 
1073 
1074  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1080 
1081  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1082  // setcc all the way to isel and prefer SETGT in some isel patterns.
1085  }
1086 
1087  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1093  }
1094 
1095  for (auto VT : { MVT::v8f16, MVT::v2f64, MVT::v2i64 }) {
1099 
1100  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1101  continue;
1102 
1105  }
1106  setF16Action(MVT::v8f16, Expand);
1111 
1112  // Custom lower v2i64 and v2f64 selects.
1119 
1126 
1127  // Custom legalize these to avoid over promotion or custom promotion.
1128  for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1133  }
1134 
1139 
1142 
1145 
1146  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1151 
1156 
1157  // We want to legalize this to an f64 load rather than an i64 load on
1158  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1159  // store.
1166 
1167  // Add 32-bit vector stores to help vectorization opportunities.
1170 
1174  if (!Subtarget.hasAVX512())
1176 
1180 
1182 
1189 
1190  // In the customized shift lowering, the legal v4i32/v2i64 cases
1191  // in AVX2 will be recognized.
1192  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1196  if (VT == MVT::v2i64) continue;
1201  }
1202 
1208  }
1209 
1210  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1219 
1220  // These might be better off as horizontal vector ops.
1225  }
1226 
1227  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1228  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1229  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1231  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1233  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1235  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1241 
1242  setOperationAction(ISD::FROUND, RoundedTy, Custom);
1243  }
1244 
1253 
1257 
1258  // FIXME: Do we need to handle scalar-to-vector here?
1261 
1262  // We directly match byte blends in the backend as they match the VSELECT
1263  // condition form.
1265 
1266  // SSE41 brings specific instructions for doing vector sign extend even in
1267  // cases where we don't have SRA.
1268  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1271  }
1272 
1273  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1274  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1281  }
1282 
1283  if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1284  // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1285  // do the pre and post work in the vector domain.
1288  // We need to mark SINT_TO_FP as Custom even though we want to expand it
1289  // so that DAG combine doesn't try to turn it into uint_to_fp.
1292  }
1293  }
1294 
1295  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1297  }
1298 
1299  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1300  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1304  }
1305 
1306  // XOP can efficiently perform BITREVERSE with VPPERM.
1307  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1309 
1310  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1313  }
1314 
1315  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1316  bool HasInt256 = Subtarget.hasInt256();
1317 
1318  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1319  : &X86::VR256RegClass);
1320  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1321  : &X86::VR256RegClass);
1322  addRegisterClass(MVT::v16f16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1323  : &X86::VR256RegClass);
1324  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1325  : &X86::VR256RegClass);
1326  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1327  : &X86::VR256RegClass);
1328  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1329  : &X86::VR256RegClass);
1330  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1331  : &X86::VR256RegClass);
1332 
1333  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1346 
1348 
1352  }
1353 
1354  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1355  // even though v8i16 is a legal type.
1363 
1370 
1382 
1383  if (!Subtarget.hasAVX512())
1385 
1386  // In the customized shift lowering, the legal v8i32/v4i64 cases
1387  // in AVX2 will be recognized.
1388  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1392  if (VT == MVT::v4i64) continue;
1397  }
1398 
1399  // These types need custom splitting if their input is a 128-bit vector.
1404 
1412 
1413  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1417  }
1418 
1423 
1424  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1430 
1431  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1432  // setcc all the way to isel and prefer SETGT in some isel patterns.
1435  }
1436 
1437  if (Subtarget.hasAnyFMA()) {
1438  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1439  MVT::v2f64, MVT::v4f64 }) {
1442  }
1443  }
1444 
1445  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1446  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1447  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1448  }
1449 
1454 
1463 
1466 
1472 
1485 
1486  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1487  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1488  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1489  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1490  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1491  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1492  }
1493 
1494  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1497  }
1498 
1499  if (HasInt256) {
1500  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1501  // when we have a 256bit-wide blend with immediate.
1504 
1505  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1506  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1513  }
1514  }
1515 
1516  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1518  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1520  }
1521 
1522  // Extract subvector is special because the value type
1523  // (result) is 128-bit but the source is 256-bit wide.
1524  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1527  }
1528 
1529  // Custom lower several nodes for 256-bit types.
1541  }
1542  setF16Action(MVT::v16f16, Expand);
1547 
1548  if (HasInt256) {
1550 
1551  // Custom legalize 2x32 to get a little better code.
1554 
1555  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1558  }
1559  }
1560 
1561  if (!Subtarget.useSoftFloat() && !Subtarget.hasFP16() &&
1562  Subtarget.hasF16C()) {
1563  for (MVT VT : { MVT::f16, MVT::v2f16, MVT::v4f16, MVT::v8f16 }) {
1566  }
1567  for (MVT VT : { MVT::f32, MVT::v2f32, MVT::v4f32 }) {
1570  }
1571  for (unsigned Opc : {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV}) {
1574  }
1575 
1578  }
1579 
1580  // This block controls legalization of the mask vector sizes that are
1581  // available with AVX512. 512-bit vectors are in a separate block controlled
1582  // by useAVX512Regs.
1583  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1584  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1585  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1586  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1587  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1588  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1589 
1593 
1606 
1607  // There is no byte sized k-register load or store without AVX512DQ.
1608  if (!Subtarget.hasDQI()) {
1613 
1618  }
1619 
1620  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1621  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1625  }
1626 
1627  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1629 
1630  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1636 
1643  }
1644 
1645  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1647  }
1648 
1649  // This block controls legalization for 512-bit operations with 32/64 bit
1650  // elements. 512-bits can be disabled based on prefer-vector-width and
1651  // required-vector-width function attributes.
1652  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1653  bool HasBWI = Subtarget.hasBWI();
1654 
1655  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1656  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1657  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1658  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1659  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1660  addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
1661  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1662 
1663  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1669  if (HasBWI)
1671  }
1672 
1673  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1679  }
1680 
1681  for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1686  }
1697 
1709 
1715  if (HasBWI)
1717 
1718  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1719  // to 512-bit rather than use the AVX2 instructions so that we can use
1720  // k-masks.
1721  if (!Subtarget.hasVLX()) {
1722  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1726  }
1727  }
1728 
1742 
1743  if (HasBWI) {
1744  // Extends from v64i1 masks to 512-bit vectors.
1748  }
1749 
1750  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1763 
1765  }
1766 
1767  for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1770  }
1771 
1776 
1781 
1790 
1793 
1795 
1796  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1803 
1804  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1805  // setcc all the way to isel and prefer SETGT in some isel patterns.
1808  }
1809  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1818  }
1819 
1820  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1821  setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1822  setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1824  setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1825  setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1826  setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1827  setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1828  setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1829  setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1830  setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1831  setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1832  }
1833 
1840 
1841  if (Subtarget.hasDQI()) {
1847  }
1848 
1849  if (Subtarget.hasCDI()) {
1850  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1851  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1853  }
1854  } // Subtarget.hasCDI()
1855 
1856  if (Subtarget.hasVPOPCNTDQ()) {
1857  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1859  }
1860 
1861  // Extract subvector is special because the value type
1862  // (result) is 256-bit but the source is 512-bit wide.
1863  // 128-bit was made Legal under AVX1.
1864  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1867 
1868  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1879  }
1880  setF16Action(MVT::v32f16, Expand);
1885  for (unsigned Opc : {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV}) {
1888  }
1889 
1890  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1895  }
1896  if (HasBWI) {
1897  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1900  }
1901  } else {
1904  }
1905 
1906  if (Subtarget.hasVBMI2()) {
1907  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1912  }
1913 
1918  }
1919  }// useAVX512Regs
1920 
1921  // This block controls legalization for operations that don't have
1922  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1923  // narrower widths.
1924  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1925  // These operations are handled on non-VLX by artificially widening in
1926  // isel patterns.
1927 
1931 
1932  if (Subtarget.hasDQI()) {
1933  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1934  // v2f32 UINT_TO_FP is already custom under SSE2.
1937  "Unexpected operation action!");
1938  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1943  }
1944 
1945  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1951  }
1952 
1953  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1956  }
1957 
1958  // Custom legalize 2x32 to get a little better code.
1961 
1962  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1965 
1966  if (Subtarget.hasDQI()) {
1972  }
1975  }
1976 
1977  if (Subtarget.hasCDI()) {
1978  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1980  }
1981  } // Subtarget.hasCDI()
1982 
1983  if (Subtarget.hasVPOPCNTDQ()) {
1984  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1986  }
1987  }
1988 
1989  // This block control legalization of v32i1/v64i1 which are available with
1990  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1991  // useBWIRegs.
1992  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1993  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1994  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1995 
1996  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
2007  }
2008 
2009  for (auto VT : { MVT::v16i1, MVT::v32i1 })
2011 
2012  // Extends from v32i1 masks to 256-bit vectors.
2016 
2017  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
2018  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
2019  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
2020  }
2021 
2022  // These operations are handled on non-VLX by artificially widening in
2023  // isel patterns.
2024  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
2025 
2026  if (Subtarget.hasBITALG()) {
2027  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
2029  }
2030  }
2031 
2032  if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
2033  auto setGroup = [&] (MVT VT) {
2044 
2055 
2058 
2064 
2070  };
2071 
2072  // AVX512_FP16 scalar operations
2073  setGroup(MVT::f16);
2089 
2092 
2093  if (Subtarget.useAVX512Regs()) {
2094  setGroup(MVT::v32f16);
2107 
2114  MVT::v32i16);
2117  MVT::v32i16);
2120  MVT::v32i16);
2123  MVT::v32i16);
2124 
2128 
2131 
2134  }
2135 
2136  if (Subtarget.hasVLX()) {
2137  setGroup(MVT::v8f16);
2138  setGroup(MVT::v16f16);
2139 
2150 
2161 
2162  // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2165 
2169 
2174 
2175  // Need to custom widen these to prevent scalarization.
2178  }
2179  }
2180 
2181  if (!Subtarget.useSoftFloat() &&
2182  (Subtarget.hasAVXNECONVERT() || Subtarget.hasBF16())) {
2183  addRegisterClass(MVT::v8bf16, &X86::VR128XRegClass);
2184  addRegisterClass(MVT::v16bf16, &X86::VR256XRegClass);
2185  // We set the type action of bf16 to TypeSoftPromoteHalf, but we don't
2186  // provide the method to promote BUILD_VECTOR. Set the operation action
2187  // Custom to do the customization later.
2189  for (auto VT : {MVT::v8bf16, MVT::v16bf16}) {
2190  setF16Action(VT, Expand);
2196  }
2197  addLegalFPImmediate(APFloat::getZero(APFloat::BFloat()));
2198  }
2199 
2200  if (!Subtarget.useSoftFloat() && Subtarget.hasBF16()) {
2201  addRegisterClass(MVT::v32bf16, &X86::VR512RegClass);
2202  setF16Action(MVT::v32bf16, Expand);
2208  }
2209 
2210  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2216 
2222 
2223  if (Subtarget.hasBWI()) {
2226  }
2227 
2228  if (Subtarget.hasFP16()) {
2229  // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2238  // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2247  // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2252  // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2257  }
2258 
2262  }
2263 
2264  if (Subtarget.hasAMXTILE()) {
2265  addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2266  }
2267 
2268  // We want to custom lower some of our intrinsics.
2272  if (!Subtarget.is64Bit()) {
2274  }
2275 
2276  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2277  // handle type legalization for these operations here.
2278  //
2279  // FIXME: We really should do custom legalization for addition and
2280  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2281  // than generic legalization for 64-bit multiplication-with-overflow, though.
2282  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2283  if (VT == MVT::i64 && !Subtarget.is64Bit())
2284  continue;
2285  // Add/Sub/Mul with overflow operations are custom lowered.
2292 
2293  // Support carry in as value rather than glue.
2299  }
2300 
2301  if (!Subtarget.is64Bit()) {
2302  // These libcalls are not available in 32-bit.
2303  setLibcallName(RTLIB::SHL_I128, nullptr);
2304  setLibcallName(RTLIB::SRL_I128, nullptr);
2305  setLibcallName(RTLIB::SRA_I128, nullptr);
2306  setLibcallName(RTLIB::MUL_I128, nullptr);
2307  // The MULO libcall is not part of libgcc, only compiler-rt.
2308  setLibcallName(RTLIB::MULO_I64, nullptr);
2309  }
2310  // The MULO libcall is not part of libgcc, only compiler-rt.
2311  setLibcallName(RTLIB::MULO_I128, nullptr);
2312 
2313  // Combine sin / cos into _sincos_stret if it is available.
2314  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2315  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2318  }
2319 
2320  if (Subtarget.isTargetWin64()) {
2333  }
2334 
2335  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2336  // is. We should promote the value to 64-bits to solve this.
2337  // This is what the CRT headers do - `fmodf` is an inline header
2338  // function casting to f64 and calling `fmod`.
2339  if (Subtarget.is32Bit() &&
2340  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2341  for (ISD::NodeType Op :
2353 
2354  // We have target-specific dag combine patterns for the following nodes:
2362  ISD::BITCAST,
2363  ISD::VSELECT,
2364  ISD::SELECT,
2365  ISD::SHL,
2366  ISD::SRA,
2367  ISD::SRL,
2368  ISD::OR,
2369  ISD::AND,
2370  ISD::ADD,
2371  ISD::FADD,
2372  ISD::FSUB,
2373  ISD::FNEG,
2374  ISD::FMA,
2376  ISD::FMINNUM,
2377  ISD::FMAXNUM,
2378  ISD::SUB,
2379  ISD::LOAD,
2380  ISD::MLOAD,
2381  ISD::STORE,
2382  ISD::MSTORE,
2383  ISD::TRUNCATE,
2395  ISD::SETCC,
2396  ISD::MUL,
2397  ISD::XOR,
2398  ISD::MSCATTER,
2399  ISD::MGATHER,
2403  ISD::FP_ROUND,
2405 
2407 
2408  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2410  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2412  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2414 
2415  // TODO: These control memcmp expansion in CGP and could be raised higher, but
2416  // that needs to benchmarked and balanced with the potential use of vector
2417  // load/store types (PR33329, PR33914).
2418  MaxLoadsPerMemcmp = 2;
2420 
2421  // Default loop alignment, which can be overridden by -align-loops.
2423 
2424  // An out-of-order CPU can speculatively execute past a predictable branch,
2425  // but a conditional move could be stalled by an expensive earlier operation.
2426  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2427  EnableExtLdPromotion = true;
2429 
2431 
2432  // Default to having -disable-strictnode-mutation on
2433  IsStrictFPEnabled = true;
2434 }
2435 
2436 // This has so far only been implemented for 64-bit MachO.
2438  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2439 }
2440 
2442  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2443  return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2444 }
2445 
2447  const SDLoc &DL) const {
2448  EVT PtrTy = getPointerTy(DAG.getDataLayout());
2449  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2450  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2451  return SDValue(Node, 0);
2452 }
2453 
2456  if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2457  !Subtarget.hasBWI())
2458  return TypeSplitVector;
2459 
2460  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2461  !Subtarget.hasF16C() && VT.getVectorElementType() == MVT::f16)
2462  return TypeSplitVector;
2463 
2464  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2465  VT.getVectorElementType() != MVT::i1)
2466  return TypeWidenVector;
2467 
2469 }
2470 
2471 static std::pair<MVT, unsigned>
2473  const X86Subtarget &Subtarget) {
2474  // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2475  // convention is one that uses k registers.
2476  if (NumElts == 2)
2477  return {MVT::v2i64, 1};
2478  if (NumElts == 4)
2479  return {MVT::v4i32, 1};
2480  if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2482  return {MVT::v8i16, 1};
2483  if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2485  return {MVT::v16i8, 1};
2486  // v32i1 passes in ymm unless we have BWI and the calling convention is
2487  // regcall.
2488  if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2489  return {MVT::v32i8, 1};
2490  // Split v64i1 vectors if we don't have v64i8 available.
2491  if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2492  if (Subtarget.useAVX512Regs())
2493  return {MVT::v64i8, 1};
2494  return {MVT::v32i8, 2};
2495  }
2496 
2497  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2498  if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2499  NumElts > 64)
2500  return {MVT::i8, NumElts};
2501 
2502  return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2503 }
2504 
2507  EVT VT) const {
2508  if (VT.isVector()) {
2509  if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
2510  unsigned NumElts = VT.getVectorNumElements();
2511 
2512  MVT RegisterVT;
2513  unsigned NumRegisters;
2514  std::tie(RegisterVT, NumRegisters) =
2515  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2516  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2517  return RegisterVT;
2518  }
2519 
2520  if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
2521  return MVT::v8f16;
2522  }
2523 
2524  // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
2525  if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
2526  !Subtarget.hasX87())
2527  return MVT::i32;
2528 
2529  if (VT.isVector() && VT.getVectorElementType() == MVT::bf16)
2532 
2534 }
2535 
2538  EVT VT) const {
2539  if (VT.isVector()) {
2540  if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
2541  unsigned NumElts = VT.getVectorNumElements();
2542 
2543  MVT RegisterVT;
2544  unsigned NumRegisters;
2545  std::tie(RegisterVT, NumRegisters) =
2546  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2547  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2548  return NumRegisters;
2549  }
2550 
2551  if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
2552  return 1;
2553  }
2554 
2555  // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
2556  // x87 is disabled.
2557  if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
2558  if (VT == MVT::f64)
2559  return 2;
2560  if (VT == MVT::f80)
2561  return 3;
2562  }
2563 
2564  if (VT.isVector() && VT.getVectorElementType() == MVT::bf16)
2567 
2569 }
2570 
2572  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2573  unsigned &NumIntermediates, MVT &RegisterVT) const {
2574  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2575  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2576  Subtarget.hasAVX512() &&
2578  (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2579  VT.getVectorNumElements() > 64)) {
2580  RegisterVT = MVT::i8;
2581  IntermediateVT = MVT::i1;
2582  NumIntermediates = VT.getVectorNumElements();
2583  return NumIntermediates;
2584  }
2585 
2586  // Split v64i1 vectors if we don't have v64i8 available.
2587  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2589  RegisterVT = MVT::v32i8;
2590  IntermediateVT = MVT::v32i1;
2591  NumIntermediates = 2;
2592  return 2;
2593  }
2594 
2596  NumIntermediates, RegisterVT);
2597 }
2598 
2601  EVT VT) const {
2602  if (!VT.isVector())
2603  return MVT::i8;
2604 
2605  if (Subtarget.hasAVX512()) {
2606  // Figure out what this type will be legalized to.
2607  EVT LegalVT = VT;
2608  while (getTypeAction(Context, LegalVT) != TypeLegal)
2609  LegalVT = getTypeToTransformTo(Context, LegalVT);
2610 
2611  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2612  if (LegalVT.getSimpleVT().is512BitVector())
2614 
2615  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2616  // If we legalized to less than a 512-bit vector, then we will use a vXi1
2617  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2618  // vXi16/vXi8.
2619  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2620  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2622  }
2623  }
2624 
2626 }
2627 
2628 /// Helper for getByValTypeAlignment to determine
2629 /// the desired ByVal argument alignment.
2630 static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2631  if (MaxAlign == 16)
2632  return;
2633  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2634  if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2635  MaxAlign = Align(16);
2636  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2637  Align EltAlign;
2638  getMaxByValAlign(ATy->getElementType(), EltAlign);
2639  if (EltAlign > MaxAlign)
2640  MaxAlign = EltAlign;
2641  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2642  for (auto *EltTy : STy->elements()) {
2643  Align EltAlign;
2644  getMaxByValAlign(EltTy, EltAlign);
2645  if (EltAlign > MaxAlign)
2646  MaxAlign = EltAlign;
2647  if (MaxAlign == 16)
2648  break;
2649  }
2650  }
2651 }
2652 
2653 /// Return the desired alignment for ByVal aggregate
2654 /// function arguments in the caller parameter area. For X86, aggregates
2655 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2656 /// are at 4-byte boundaries.
2658  const DataLayout &DL) const {
2659  if (Subtarget.is64Bit()) {
2660  // Max of 8 and alignment of type.
2661  Align TyAlign = DL.getABITypeAlign(Ty);
2662  if (TyAlign > 8)
2663  return TyAlign.value();
2664  return 8;
2665  }
2666 
2667  Align Alignment(4);
2668  if (Subtarget.hasSSE1())
2669  getMaxByValAlign(Ty, Alignment);
2670  return Alignment.value();
2671 }
2672 
2673 /// It returns EVT::Other if the type should be determined using generic
2674 /// target-independent logic.
2675 /// For vector ops we check that the overall size isn't larger than our
2676 /// preferred vector width.
2678  const MemOp &Op, const AttributeList &FuncAttributes) const {
2679  if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2680  if (Op.size() >= 16 &&
2681  (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2682  // FIXME: Check if unaligned 64-byte accesses are slow.
2683  if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2684  (Subtarget.getPreferVectorWidth() >= 512)) {
2685  return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2686  }
2687  // FIXME: Check if unaligned 32-byte accesses are slow.
2688  if (Op.size() >= 32 && Subtarget.hasAVX() &&
2689  (Subtarget.getPreferVectorWidth() >= 256)) {
2690  // Although this isn't a well-supported type for AVX1, we'll let
2691  // legalization and shuffle lowering produce the optimal codegen. If we
2692  // choose an optimal type with a vector element larger than a byte,
2693  // getMemsetStores() may create an intermediate splat (using an integer
2694  // multiply) before we splat as a vector.
2695  return MVT::v32i8;
2696  }
2697  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2698  return MVT::v16i8;
2699  // TODO: Can SSE1 handle a byte vector?
2700  // If we have SSE1 registers we should be able to use them.
2701  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2702  (Subtarget.getPreferVectorWidth() >= 128))
2703  return MVT::v4f32;
2704  } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2705  Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2706  // Do not use f64 to lower memcpy if source is string constant. It's
2707  // better to use i32 to avoid the loads.
2708  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2709  // The gymnastics of splatting a byte value into an XMM register and then
2710  // only using 8-byte stores (because this is a CPU with slow unaligned
2711  // 16-byte accesses) makes that a loser.
2712  return MVT::f64;
2713  }
2714  }
2715  // This is a compromise. If we reach here, unaligned accesses may be slow on
2716  // this target. However, creating smaller, aligned accesses could be even
2717  // slower and would certainly be a lot more code.
2718  if (Subtarget.is64Bit() && Op.size() >= 8)
2719  return MVT::i64;
2720  return MVT::i32;
2721 }
2722 
2724  if (VT == MVT::f32)
2725  return Subtarget.hasSSE1();
2726  if (VT == MVT::f64)
2727  return Subtarget.hasSSE2();
2728  return true;
2729 }
2730 
2732  EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2733  unsigned *Fast) const {
2734  if (Fast) {
2735  switch (VT.getSizeInBits()) {
2736  default:
2737  // 8-byte and under are always assumed to be fast.
2738  *Fast = 1;
2739  break;
2740  case 128:
2741  *Fast = !Subtarget.isUnalignedMem16Slow();
2742  break;
2743  case 256:
2744  *Fast = !Subtarget.isUnalignedMem32Slow();
2745  break;
2746  // TODO: What about AVX-512 (512-bit) accesses?
2747  }
2748  }
2749  // NonTemporal vector memory ops must be aligned.
2750  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2751  // NT loads can only be vector aligned, so if its less aligned than the
2752  // minimum vector size (which we can split the vector down to), we might as
2753  // well use a regular unaligned vector load.
2754  // We don't have any NT loads pre-SSE41.
2755  if (!!(Flags & MachineMemOperand::MOLoad))
2756  return (Alignment < 16 || !Subtarget.hasSSE41());
2757  return false;
2758  }
2759  // Misaligned accesses of any size are always allowed.
2760  return true;
2761 }
2762 
2763 /// Return the entry encoding for a jump table in the
2764 /// current function. The returned value is a member of the
2765 /// MachineJumpTableInfo::JTEntryKind enum.
2767  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2768  // symbol.
2769  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2771 
2772  // Otherwise, use the normal jump table encoding heuristics.
2774 }
2775 
2776 bool X86TargetLowering::splitValueIntoRegisterParts(
2777  SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
2778  unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
2779  bool IsABIRegCopy = CC.has_value();
2780  EVT ValueVT = Val.getValueType();
2781  if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) {
2782  unsigned ValueBits = ValueVT.getSizeInBits();
2783  unsigned PartBits = PartVT.getSizeInBits();
2784  Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
2785  Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
2786  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
2787  Parts[0] = Val;
2788  return true;
2789  }
2790  return false;
2791 }
2792 
2793 SDValue X86TargetLowering::joinRegisterPartsIntoValue(
2794  SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
2795  MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
2796  bool IsABIRegCopy = CC.has_value();
2797  if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) {
2798  unsigned ValueBits = ValueVT.getSizeInBits();
2799  unsigned PartBits = PartVT.getSizeInBits();
2800  SDValue Val = Parts[0];
2801 
2802  Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
2803  Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
2804  Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
2805  return Val;
2806  }
2807  return SDValue();
2808 }
2809 
2811  return Subtarget.useSoftFloat();
2812 }
2813 
2815  ArgListTy &Args) const {
2816 
2817  // Only relabel X86-32 for C / Stdcall CCs.
2818  if (Subtarget.is64Bit())
2819  return;
2821  return;
2822  unsigned ParamRegs = 0;
2823  if (auto *M = MF->getFunction().getParent())
2824  ParamRegs = M->getNumberRegisterParameters();
2825 
2826  // Mark the first N int arguments as having reg
2827  for (auto &Arg : Args) {
2828  Type *T = Arg.Ty;
2829  if (T->isIntOrPtrTy())
2830  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2831  unsigned numRegs = 1;
2832  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2833  numRegs = 2;
2834  if (ParamRegs < numRegs)
2835  return;
2836  ParamRegs -= numRegs;
2837  Arg.IsInReg = true;
2838  }
2839  }
2840 }
2841 
2842 const MCExpr *
2844  const MachineBasicBlock *MBB,
2845  unsigned uid,MCContext &Ctx) const{
2846  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2847  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2848  // entries.
2851 }
2852 
2853 /// Returns relocation base for the given PIC jumptable.
2855  SelectionDAG &DAG) const {
2856  if (!Subtarget.is64Bit())
2857  // This doesn't have SDLoc associated with it, but is not really the
2858  // same as a Register.
2859  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2860  getPointerTy(DAG.getDataLayout()));
2861  return Table;
2862 }
2863 
2864 /// This returns the relocation base for the given PIC jumptable,
2865 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2868  MCContext &Ctx) const {
2869  // X86-64 uses RIP relative addressing based on the jump table label.
2870  if (Subtarget.isPICStyleRIPRel())
2871  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2872 
2873  // Otherwise, the reference is relative to the PIC base.
2874  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2875 }
2876 
2877 std::pair<const TargetRegisterClass *, uint8_t>
2879  MVT VT) const {
2880  const TargetRegisterClass *RRC = nullptr;
2881  uint8_t Cost = 1;
2882  switch (VT.SimpleTy) {
2883  default:
2885  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2886  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2887  break;
2888  case MVT::x86mmx:
2889  RRC = &X86::VR64RegClass;
2890  break;
2891  case MVT::f32: case MVT::f64:
2892  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2893  case MVT::v4f32: case MVT::v2f64:
2894  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2895  case MVT::v8f32: case MVT::v4f64:
2896  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2897  case MVT::v16f32: case MVT::v8f64:
2898  RRC = &X86::VR128XRegClass;
2899  break;
2900  }
2901  return std::make_pair(RRC, Cost);
2902 }
2903 
2904 unsigned X86TargetLowering::getAddressSpace() const {
2905  if (Subtarget.is64Bit())
2906  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2907  return 256;
2908 }
2909 
2910 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2911  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2912  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));