LLVM  15.0.0git
X86ISelLowering.cpp
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1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
16 #include "X86.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86IntrinsicsInfo.h"
21 #include "X86MachineFunctionInfo.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DerivedTypes.h"
47 #include "llvm/IR/DiagnosticInfo.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalAlias.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/IRBuilder.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/Intrinsics.h"
54 #include "llvm/IR/PatternMatch.h"
55 #include "llvm/MC/MCAsmInfo.h"
56 #include "llvm/MC/MCContext.h"
57 #include "llvm/MC/MCExpr.h"
58 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/KnownBits.h"
65 #include <algorithm>
66 #include <bitset>
67 #include <cctype>
68 #include <numeric>
69 using namespace llvm;
70 
71 #define DEBUG_TYPE "x86-isel"
72 
73 STATISTIC(NumTailCalls, "Number of tail calls");
74 
76  "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77  cl::desc(
78  "Sets the preferable loop alignment for experiments (as log2 bytes) "
79  "for innermost loops only. If specified, this option overrides "
80  "alignment set by x86-experimental-pref-loop-alignment."),
81  cl::Hidden);
82 
84  "mul-constant-optimization", cl::init(true),
85  cl::desc("Replace 'mul x, Const' with more effective instructions like "
86  "SHIFT, LEA, etc."),
87  cl::Hidden);
88 
90  "x86-experimental-unordered-atomic-isel", cl::init(false),
91  cl::desc("Use LoadSDNode and StoreSDNode instead of "
92  "AtomicSDNode for unordered atomic loads and "
93  "stores respectively."),
94  cl::Hidden);
95 
96 /// Call this when the user attempts to do something unsupported, like
97 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98 /// report_fatal_error, so calling code should attempt to recover without
99 /// crashing.
100 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101  const char *Msg) {
103  DAG.getContext()->diagnose(
105 }
106 
108  const X86Subtarget &STI)
109  : TargetLowering(TM), Subtarget(STI) {
110  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
112 
113  // Set up the TargetLowering object.
114 
115  // X86 is weird. It always uses i8 for shift amounts and setcc results.
117  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
119 
120  // For 64-bit, since we have so many registers, use the ILP scheduler.
121  // For 32-bit, use the register pressure specific scheduling.
122  // For Atom, always use ILP scheduling.
123  if (Subtarget.isAtom())
125  else if (Subtarget.is64Bit())
127  else
129  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
131 
132  // Bypass expensive divides and use cheaper ones.
133  if (TM.getOptLevel() >= CodeGenOpt::Default) {
134  if (Subtarget.hasSlowDivide32())
135  addBypassSlowDiv(32, 8);
136  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
137  addBypassSlowDiv(64, 32);
138  }
139 
140  // Setup Windows compiler runtime calls.
141  if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
142  static const struct {
143  const RTLIB::Libcall Op;
144  const char * const Name;
145  const CallingConv::ID CC;
146  } LibraryCalls[] = {
147  { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
148  { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
149  { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
150  { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
151  { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
152  };
153 
154  for (const auto &LC : LibraryCalls) {
155  setLibcallName(LC.Op, LC.Name);
156  setLibcallCallingConv(LC.Op, LC.CC);
157  }
158  }
159 
160  if (Subtarget.getTargetTriple().isOSMSVCRT()) {
161  // MSVCRT doesn't have powi; fall back to pow
162  setLibcallName(RTLIB::POWI_F32, nullptr);
163  setLibcallName(RTLIB::POWI_F64, nullptr);
164  }
165 
166  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
167  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
168  // FIXME: Should we be limiting the atomic size on other configs? Default is
169  // 1024.
170  if (!Subtarget.canUseCMPXCHG8B())
172 
173  // Set up the register classes.
174  addRegisterClass(MVT::i8, &X86::GR8RegClass);
175  addRegisterClass(MVT::i16, &X86::GR16RegClass);
176  addRegisterClass(MVT::i32, &X86::GR32RegClass);
177  if (Subtarget.is64Bit())
178  addRegisterClass(MVT::i64, &X86::GR64RegClass);
179 
180  for (MVT VT : MVT::integer_valuetypes())
182 
183  // We don't accept any truncstore of integer registers.
190 
192 
193  // SETOEQ and SETUNE require checking two conditions.
194  for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
197  }
198 
199  // Integer absolute.
200  if (Subtarget.canUseCMOV()) {
203  if (Subtarget.is64Bit())
205  }
206 
207  // Signed saturation subtraction.
211  if (Subtarget.is64Bit())
213 
214  // Funnel shifts.
215  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
216  // For slow shld targets we only lower for code size.
217  LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
218 
219  setOperationAction(ShiftOp , MVT::i8 , Custom);
220  setOperationAction(ShiftOp , MVT::i16 , Custom);
221  setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
222  if (Subtarget.is64Bit())
223  setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
224  }
225 
226  if (!Subtarget.useSoftFloat()) {
227  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
228  // operation.
233  // We have an algorithm for SSE2, and we turn this into a 64-bit
234  // FILD or VCVTUSI2SS/SD for other targets.
237  // We have an algorithm for SSE2->double, and we turn this into a
238  // 64-bit FILD followed by conditional FADD for other targets.
241 
242  // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
243  // this operation.
246  // SSE has no i16 to fp conversion, only i32. We promote in the handler
247  // to allow f80 to use i16 and f64 to use i16 with sse1 only
250  // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
253  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
254  // are Legal, f80 is custom lowered.
257 
258  // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
259  // this operation.
261  // FIXME: This doesn't generate invalid exception when it should. PR44019.
267  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
268  // are Legal, f80 is custom lowered.
271 
272  // Handle FP_TO_UINT by promoting the destination to a larger signed
273  // conversion.
275  // FIXME: This doesn't generate invalid exception when it should. PR44019.
278  // FIXME: This doesn't generate invalid exception when it should. PR44019.
284 
289 
290  if (!Subtarget.is64Bit()) {
293  }
294  }
295 
296  if (Subtarget.hasSSE2()) {
297  // Custom lowering for saturating float to int conversions.
298  // We handle promotion to larger result types manually.
299  for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
302  }
303  if (Subtarget.is64Bit()) {
306  }
307  }
308 
309  // Handle address space casts between mixed sized pointers.
312 
313  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
314  if (!Subtarget.hasSSE2()) {
317  if (Subtarget.is64Bit()) {
319  // Without SSE, i64->f64 goes through memory.
321  }
322  } else if (!Subtarget.is64Bit())
324 
325  // Scalar integer divide and remainder are lowered to use operations that
326  // produce two results, to match the available instructions. This exposes
327  // the two-result form to trivial CSE, which is able to combine x/y and x%y
328  // into a single instruction.
329  //
330  // Scalar integer multiply-high is also lowered to use two-result
331  // operations, to match the available instructions. However, plain multiply
332  // (low) operations are left as Legal, as there are single-result
333  // instructions for this in x86. Using the two-result multiply instructions
334  // when both high and low results are needed must be arranged by dagcombine.
335  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
342  }
343 
346  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
350  }
351  if (Subtarget.is64Bit())
356 
361 
362  if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
365  }
366 
367  // Promote the i8 variants and force them on up to i32 which has a shorter
368  // encoding.
371 
372  if (Subtarget.hasBMI()) {
373  // Promote the i16 zero undef variant and force it on up to i32 when tzcnt
374  // is enabled.
376  } else {
381  if (Subtarget.is64Bit()) {
384  }
385  }
386 
387  if (Subtarget.hasLZCNT()) {
388  // When promoting the i8 variants, force them to i32 for a shorter
389  // encoding.
392  } else {
393  for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
394  if (VT == MVT::i64 && !Subtarget.is64Bit())
395  continue;
398  }
399  }
400 
403  // Special handling for half-precision floating point conversions.
404  // If we don't have F16C support, then lower half float conversions
405  // into library calls.
407  Op, MVT::f32,
408  (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
409  // There's never any support for operations beyond MVT::f32.
413  }
414 
415  for (MVT VT : {MVT::f32, MVT::f64, MVT::f80, MVT::f128}) {
420 
423  }
424 
428  if (Subtarget.is64Bit())
430  if (Subtarget.hasPOPCNT()) {
432  // popcntw is longer to encode than popcntl and also has a false dependency
433  // on the dest that popcntl hasn't had since Cannon Lake.
435  } else {
439  if (Subtarget.is64Bit())
441  else
443  }
444 
446 
447  if (!Subtarget.hasMOVBE())
449 
450  // X86 wants to expand cmov itself.
451  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
456  }
457  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
458  if (VT == MVT::i64 && !Subtarget.is64Bit())
459  continue;
462  }
463 
464  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
467 
469  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
470  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
474  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
475  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
476 
477  // Darwin ABI issue.
478  for (auto VT : { MVT::i32, MVT::i64 }) {
479  if (VT == MVT::i64 && !Subtarget.is64Bit())
480  continue;
487  }
488 
489  // 64-bit shl, sra, srl (iff 32-bit x86)
490  for (auto VT : { MVT::i32, MVT::i64 }) {
491  if (VT == MVT::i64 && !Subtarget.is64Bit())
492  continue;
496  }
497 
498  if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
500 
502 
503  // Expand certain atomics
504  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
512  }
513 
514  if (!Subtarget.is64Bit())
516 
517  if (Subtarget.canUseCMPXCHG16B())
519 
520  // FIXME - use subtarget debug flags
521  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
522  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
523  TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
525  }
526 
529 
532 
535  if (Subtarget.isTargetPS())
537  else
539 
540  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
543  bool Is64Bit = Subtarget.is64Bit();
546 
549 
551 
552  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
555 
557 
558  auto setF16Action = [&] (MVT VT, LegalizeAction Action) {
559  setOperationAction(ISD::FABS, VT, Action);
560  setOperationAction(ISD::FNEG, VT, Action);
562  setOperationAction(ISD::FREM, VT, Action);
563  setOperationAction(ISD::FMA, VT, Action);
564  setOperationAction(ISD::FMINNUM, VT, Action);
565  setOperationAction(ISD::FMAXNUM, VT, Action);
566  setOperationAction(ISD::FMINIMUM, VT, Action);
567  setOperationAction(ISD::FMAXIMUM, VT, Action);
568  setOperationAction(ISD::FSIN, VT, Action);
569  setOperationAction(ISD::FCOS, VT, Action);
570  setOperationAction(ISD::FSINCOS, VT, Action);
571  setOperationAction(ISD::FSQRT, VT, Action);
572  setOperationAction(ISD::FPOW, VT, Action);
573  setOperationAction(ISD::FLOG, VT, Action);
574  setOperationAction(ISD::FLOG2, VT, Action);
575  setOperationAction(ISD::FLOG10, VT, Action);
576  setOperationAction(ISD::FEXP, VT, Action);
577  setOperationAction(ISD::FEXP2, VT, Action);
578  setOperationAction(ISD::FCEIL, VT, Action);
579  setOperationAction(ISD::FFLOOR, VT, Action);
580  setOperationAction(ISD::FNEARBYINT, VT, Action);
581  setOperationAction(ISD::FRINT, VT, Action);
582  setOperationAction(ISD::BR_CC, VT, Action);
583  setOperationAction(ISD::SETCC, VT, Action);
585  setOperationAction(ISD::SELECT_CC, VT, Action);
586  setOperationAction(ISD::FROUND, VT, Action);
587  setOperationAction(ISD::FROUNDEVEN, VT, Action);
588  setOperationAction(ISD::FTRUNC, VT, Action);
589  };
590 
591  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
592  // f16, f32 and f64 use SSE.
593  // Set up the FP register classes.
594  addRegisterClass(MVT::f16, Subtarget.hasAVX512() ? &X86::FR16XRegClass
595  : &X86::FR16RegClass);
596  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
597  : &X86::FR32RegClass);
598  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
599  : &X86::FR64RegClass);
600 
601  // Disable f32->f64 extload as we can only generate this in one instruction
602  // under optsize. So its easier to pattern match (fpext (load)) for that
603  // case instead of needing to emit 2 instructions for extload in the
604  // non-optsize case.
606 
607  for (auto VT : { MVT::f32, MVT::f64 }) {
608  // Use ANDPD to simulate FABS.
610 
611  // Use XORP to simulate FNEG.
613 
614  // Use ANDPD and ORPD to simulate FCOPYSIGN.
616 
617  // These might be better off as horizontal vector ops.
620 
621  // We don't support sin/cos/fmod
625  }
626 
627  // Half type will be promoted by default.
628  setF16Action(MVT::f16, Promote);
636 
665 
666  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
667  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
668 
669  // Lower this to MOVMSK plus an AND.
672 
673  } else if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1() &&
674  (UseX87 || Is64Bit)) {
675  // Use SSE for f32, x87 for f64.
676  // Set up the FP register classes.
677  addRegisterClass(MVT::f32, &X86::FR32RegClass);
678  if (UseX87)
679  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
680 
681  // Use ANDPS to simulate FABS.
683 
684  // Use XORP to simulate FNEG.
686 
687  if (UseX87)
689 
690  // Use ANDPS and ORPS to simulate FCOPYSIGN.
691  if (UseX87)
694 
695  // We don't support sin/cos/fmod
699 
700  if (UseX87) {
701  // Always expand sin/cos functions even though x87 has an instruction.
705  }
706  } else if (UseX87) {
707  // f32 and f64 in x87.
708  // Set up the FP register classes.
709  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
710  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
711 
712  for (auto VT : { MVT::f32, MVT::f64 }) {
715 
716  // Always expand sin/cos functions even though x87 has an instruction.
720  }
721  }
722 
723  // Expand FP32 immediates into loads from the stack, save special cases.
724  if (isTypeLegal(MVT::f32)) {
725  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
726  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
727  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
728  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
729  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
730  } else // SSE immediates.
731  addLegalFPImmediate(APFloat(+0.0f)); // xorps
732  }
733  // Expand FP64 immediates into loads from the stack, save special cases.
734  if (isTypeLegal(MVT::f64)) {
735  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
736  addLegalFPImmediate(APFloat(+0.0)); // FLD0
737  addLegalFPImmediate(APFloat(+1.0)); // FLD1
738  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
739  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
740  } else // SSE immediates.
741  addLegalFPImmediate(APFloat(+0.0)); // xorpd
742  }
743  // Support fp16 0 immediate.
744  if (isTypeLegal(MVT::f16))
745  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
746 
747  // Handle constrained floating-point operations of scalar.
760 
761  // We don't support FMA.
764 
765  // f80 always uses X87.
766  if (UseX87) {
767  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770  {
772  addLegalFPImmediate(TmpFlt); // FLD0
773  TmpFlt.changeSign();
774  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
775 
776  bool ignored;
777  APFloat TmpFlt2(+1.0);
779  &ignored);
780  addLegalFPImmediate(TmpFlt2); // FLD1
781  TmpFlt2.changeSign();
782  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
783  }
784 
785  // Always expand sin/cos functions even though x87 has an instruction.
789 
800 
801  // Handle constrained floating-point operations of scalar.
807  if (isTypeLegal(MVT::f16)) {
810  } else {
812  }
813  // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
814  // as Custom.
816  }
817 
818  // f128 uses xmm registers, but most operations require libcalls.
819  if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
820  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
821  : &X86::VR128RegClass);
822 
823  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
824 
835 
839 
845  // No STRICT_FSINCOS
848 
851  // We need to custom handle any FP_ROUND with an f128 input, but
852  // LegalizeDAG uses the result type to know when to run a custom handler.
853  // So we have to list all legal floating point result types here.
854  if (isTypeLegal(MVT::f32)) {
857  }
858  if (isTypeLegal(MVT::f64)) {
861  }
862  if (isTypeLegal(MVT::f80)) {
865  }
866 
868 
875  }
876 
877  // Always use a library call for pow.
882 
890 
891  // Some FP actions are always expanded for vector types.
892  for (auto VT : { MVT::v8f16, MVT::v16f16, MVT::v32f16,
906  }
907 
908  // First set operation action for all vector types to either promote
909  // (for widening) or expand (for scalarization). Then we will selectively
910  // turn on ones that can be effectively codegen'd.
911  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
949  for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
950  setTruncStoreAction(InnerVT, VT, Expand);
951 
952  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
953  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
954 
955  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
956  // types, we have to deal with them whether we ask for Expansion or not.
957  // Setting Expand causes its own optimisation problems though, so leave
958  // them legal.
959  if (VT.getVectorElementType() == MVT::i1)
960  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
961 
962  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
963  // split/scalarized right now.
964  if (VT.getVectorElementType() == MVT::f16 ||
966  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
967  }
968  }
969 
970  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
971  // with -msoft-float, disable use of MMX as well.
972  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
973  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
974  // No operations on x86mmx supported, everything uses intrinsics.
975  }
976 
977  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
978  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
979  : &X86::VR128RegClass);
980 
989 
992 
998  }
999 
1000  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
1001  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
1002  : &X86::VR128RegClass);
1003 
1004  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
1005  // registers cannot be used even for integer operations.
1006  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
1007  : &X86::VR128RegClass);
1008  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
1009  : &X86::VR128RegClass);
1010  addRegisterClass(MVT::v8f16, Subtarget.hasVLX() ? &X86::VR128XRegClass
1011  : &X86::VR128RegClass);
1012  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
1013  : &X86::VR128RegClass);
1014  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
1015  : &X86::VR128RegClass);
1016 
1017  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
1023  }
1024 
1028 
1041 
1044 
1048 
1049  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1054  }
1055 
1066 
1071 
1072  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1078 
1079  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1080  // setcc all the way to isel and prefer SETGT in some isel patterns.
1083  }
1084 
1085  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1091  }
1092 
1093  for (auto VT : { MVT::v8f16, MVT::v2f64, MVT::v2i64 }) {
1097 
1098  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1099  continue;
1100 
1103  }
1104  setF16Action(MVT::v8f16, Expand);
1109 
1110  // Custom lower v2i64 and v2f64 selects.
1117 
1124 
1125  // Custom legalize these to avoid over promotion or custom promotion.
1126  for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1131  }
1132 
1137 
1140 
1143 
1144  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1149 
1154 
1155  // We want to legalize this to an f64 load rather than an i64 load on
1156  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1157  // store.
1164 
1165  // Add 32-bit vector stores to help vectorization opportunities.
1168 
1172  if (!Subtarget.hasAVX512())
1174 
1178 
1180 
1187 
1188  // In the customized shift lowering, the legal v4i32/v2i64 cases
1189  // in AVX2 will be recognized.
1190  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1194  if (VT == MVT::v2i64) continue;
1199  }
1200 
1206  }
1207 
1208  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1217 
1218  // These might be better off as horizontal vector ops.
1223  }
1224 
1225  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1226  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1227  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1229  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1231  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1233  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1239 
1240  setOperationAction(ISD::FROUND, RoundedTy, Custom);
1241  }
1242 
1251 
1255 
1256  // FIXME: Do we need to handle scalar-to-vector here?
1258 
1259  // We directly match byte blends in the backend as they match the VSELECT
1260  // condition form.
1262 
1263  // SSE41 brings specific instructions for doing vector sign extend even in
1264  // cases where we don't have SRA.
1265  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1268  }
1269 
1270  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1271  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1278  }
1279 
1280  if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1281  // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1282  // do the pre and post work in the vector domain.
1285  // We need to mark SINT_TO_FP as Custom even though we want to expand it
1286  // so that DAG combine doesn't try to turn it into uint_to_fp.
1289  }
1290  }
1291 
1292  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1294  }
1295 
1296  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1297  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1301  }
1302 
1303  // XOP can efficiently perform BITREVERSE with VPPERM.
1304  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1306 
1307  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1310  }
1311 
1312  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1313  bool HasInt256 = Subtarget.hasInt256();
1314 
1315  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1316  : &X86::VR256RegClass);
1317  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1318  : &X86::VR256RegClass);
1319  addRegisterClass(MVT::v16f16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1320  : &X86::VR256RegClass);
1321  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1322  : &X86::VR256RegClass);
1323  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1324  : &X86::VR256RegClass);
1325  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1326  : &X86::VR256RegClass);
1327  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1328  : &X86::VR256RegClass);
1329 
1330  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1343 
1345 
1349  }
1350 
1351  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1352  // even though v8i16 is a legal type.
1360 
1365 
1377 
1378  if (!Subtarget.hasAVX512())
1380 
1381  // In the customized shift lowering, the legal v8i32/v4i64 cases
1382  // in AVX2 will be recognized.
1383  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1387  if (VT == MVT::v4i64) continue;
1392  }
1393 
1394  // These types need custom splitting if their input is a 128-bit vector.
1399 
1407 
1408  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1412  }
1413 
1418 
1419  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1425 
1426  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1427  // setcc all the way to isel and prefer SETGT in some isel patterns.
1430  }
1431 
1432  if (Subtarget.hasAnyFMA()) {
1433  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1434  MVT::v2f64, MVT::v4f64 }) {
1437  }
1438  }
1439 
1440  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1441  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1442  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1443  }
1444 
1449 
1458 
1461 
1467 
1480 
1481  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1482  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1483  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1484  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1485  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1486  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1487  }
1488 
1489  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1492  }
1493 
1494  if (HasInt256) {
1495  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1496  // when we have a 256bit-wide blend with immediate.
1499 
1500  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1501  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1508  }
1509  }
1510 
1511  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1513  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1515  }
1516 
1517  // Extract subvector is special because the value type
1518  // (result) is 128-bit but the source is 256-bit wide.
1519  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1520  MVT::v4f32, MVT::v2f64 }) {
1522  }
1523 
1524  // Custom lower several nodes for 256-bit types.
1536  }
1537  setF16Action(MVT::v16f16, Expand);
1542 
1543  if (HasInt256) {
1545 
1546  // Custom legalize 2x32 to get a little better code.
1549 
1550  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1553  }
1554  }
1555 
1556  if (!Subtarget.useSoftFloat() && !Subtarget.hasFP16() &&
1557  Subtarget.hasF16C()) {
1558  for (MVT VT : { MVT::f16, MVT::v2f16, MVT::v4f16, MVT::v8f16 }) {
1561  }
1562  for (MVT VT : { MVT::f32, MVT::v2f32, MVT::v4f32 }) {
1565  }
1566  for (unsigned Opc : {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV}) {
1569  }
1570 
1573  }
1574 
1575  // This block controls legalization of the mask vector sizes that are
1576  // available with AVX512. 512-bit vectors are in a separate block controlled
1577  // by useAVX512Regs.
1578  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1579  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1580  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1581  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1582  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1583  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1584 
1588 
1601 
1602  // There is no byte sized k-register load or store without AVX512DQ.
1603  if (!Subtarget.hasDQI()) {
1608 
1613  }
1614 
1615  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1616  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1620  }
1621 
1622  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1624 
1625  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1631 
1638  }
1639 
1640  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1642  }
1643 
1644  // This block controls legalization for 512-bit operations with 32/64 bit
1645  // elements. 512-bits can be disabled based on prefer-vector-width and
1646  // required-vector-width function attributes.
1647  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1648  bool HasBWI = Subtarget.hasBWI();
1649 
1650  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1651  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1652  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1653  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1654  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1655  addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
1656  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1657 
1658  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1664  if (HasBWI)
1666  }
1667 
1668  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1674  }
1675 
1676  for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1681  }
1692 
1704 
1710  if (HasBWI)
1712 
1713  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1714  // to 512-bit rather than use the AVX2 instructions so that we can use
1715  // k-masks.
1716  if (!Subtarget.hasVLX()) {
1717  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1721  }
1722  }
1723 
1737 
1738  if (HasBWI) {
1739  // Extends from v64i1 masks to 512-bit vectors.
1743  }
1744 
1745  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1758 
1760  }
1761 
1762  for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1765  }
1766 
1771 
1776 
1785 
1788 
1790 
1791  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1798 
1799  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1800  // setcc all the way to isel and prefer SETGT in some isel patterns.
1803  }
1804  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1813  }
1814 
1815  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1816  setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1817  setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1819  setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1820  setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1821  setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1822  setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1823  setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1824  setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1825  setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1826  setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1827  }
1828 
1835 
1836  if (Subtarget.hasDQI()) {
1842  }
1843 
1844  if (Subtarget.hasCDI()) {
1845  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1846  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1848  }
1849  } // Subtarget.hasCDI()
1850 
1851  if (Subtarget.hasVPOPCNTDQ()) {
1852  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1854  }
1855 
1856  // Extract subvector is special because the value type
1857  // (result) is 256-bit but the source is 512-bit wide.
1858  // 128-bit was made Legal under AVX1.
1859  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1862 
1863  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1874  }
1875  setF16Action(MVT::v32f16, Expand);
1880  for (unsigned Opc : {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV}) {
1883  }
1884 
1885  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1890  }
1891  if (HasBWI) {
1892  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1895  }
1896  } else {
1899  }
1900 
1901  if (Subtarget.hasVBMI2()) {
1902  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1907  }
1908 
1913  }
1914  }// useAVX512Regs
1915 
1916  // This block controls legalization for operations that don't have
1917  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1918  // narrower widths.
1919  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1920  // These operations are handled on non-VLX by artificially widening in
1921  // isel patterns.
1922 
1926 
1927  if (Subtarget.hasDQI()) {
1928  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1929  // v2f32 UINT_TO_FP is already custom under SSE2.
1932  "Unexpected operation action!");
1933  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1938  }
1939 
1940  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1946  }
1947 
1948  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1951  }
1952 
1953  // Custom legalize 2x32 to get a little better code.
1956 
1957  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1960 
1961  if (Subtarget.hasDQI()) {
1967  }
1970  }
1971 
1972  if (Subtarget.hasCDI()) {
1973  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1975  }
1976  } // Subtarget.hasCDI()
1977 
1978  if (Subtarget.hasVPOPCNTDQ()) {
1979  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1981  }
1982  }
1983 
1984  // This block control legalization of v32i1/v64i1 which are available with
1985  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1986  // useBWIRegs.
1987  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1988  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1989  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1990 
1991  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
2002  }
2003 
2004  for (auto VT : { MVT::v16i1, MVT::v32i1 })
2006 
2007  // Extends from v32i1 masks to 256-bit vectors.
2011 
2012  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
2013  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
2014  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
2015  }
2016 
2017  // These operations are handled on non-VLX by artificially widening in
2018  // isel patterns.
2019  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
2020 
2021  if (Subtarget.hasBITALG()) {
2022  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
2024  }
2025  }
2026 
2027  if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
2028  auto setGroup = [&] (MVT VT) {
2039 
2050 
2053 
2059 
2065  };
2066 
2067  // AVX512_FP16 scalar operations
2068  setGroup(MVT::f16);
2084 
2087 
2088  if (Subtarget.useAVX512Regs()) {
2089  setGroup(MVT::v32f16);
2102 
2109  MVT::v32i16);
2112  MVT::v32i16);
2115  MVT::v32i16);
2118  MVT::v32i16);
2119 
2123 
2126 
2129  }
2130 
2131  if (Subtarget.hasVLX()) {
2132  setGroup(MVT::v8f16);
2133  setGroup(MVT::v16f16);
2134 
2145 
2156 
2157  // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2160 
2164 
2169 
2170  // Need to custom widen these to prevent scalarization.
2173  }
2174  }
2175 
2176  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2182 
2188 
2189  if (Subtarget.hasBWI()) {
2192  }
2193 
2194  if (Subtarget.hasFP16()) {
2195  // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2204  // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2213  // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2218  // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2223  }
2224 
2228  }
2229 
2230  if (Subtarget.hasAMXTILE()) {
2231  addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2232  }
2233 
2234  // We want to custom lower some of our intrinsics.
2238  if (!Subtarget.is64Bit()) {
2240  }
2241 
2242  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2243  // handle type legalization for these operations here.
2244  //
2245  // FIXME: We really should do custom legalization for addition and
2246  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2247  // than generic legalization for 64-bit multiplication-with-overflow, though.
2248  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2249  if (VT == MVT::i64 && !Subtarget.is64Bit())
2250  continue;
2251  // Add/Sub/Mul with overflow operations are custom lowered.
2258 
2259  // Support carry in as value rather than glue.
2265  }
2266 
2267  if (!Subtarget.is64Bit()) {
2268  // These libcalls are not available in 32-bit.
2269  setLibcallName(RTLIB::SHL_I128, nullptr);
2270  setLibcallName(RTLIB::SRL_I128, nullptr);
2271  setLibcallName(RTLIB::SRA_I128, nullptr);
2272  setLibcallName(RTLIB::MUL_I128, nullptr);
2273  // The MULO libcall is not part of libgcc, only compiler-rt.
2274  setLibcallName(RTLIB::MULO_I64, nullptr);
2275  }
2276  // The MULO libcall is not part of libgcc, only compiler-rt.
2277  setLibcallName(RTLIB::MULO_I128, nullptr);
2278 
2279  // Combine sin / cos into _sincos_stret if it is available.
2280  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2281  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2284  }
2285 
2286  if (Subtarget.isTargetWin64()) {
2299  }
2300 
2301  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2302  // is. We should promote the value to 64-bits to solve this.
2303  // This is what the CRT headers do - `fmodf` is an inline header
2304  // function casting to f64 and calling `fmod`.
2305  if (Subtarget.is32Bit() &&
2306  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2307  for (ISD::NodeType Op :
2319 
2320  // We have target-specific dag combine patterns for the following nodes:
2328  ISD::BITCAST,
2329  ISD::VSELECT,
2330  ISD::SELECT,
2331  ISD::SHL,
2332  ISD::SRA,
2333  ISD::SRL,
2334  ISD::OR,
2335  ISD::AND,
2336  ISD::ADD,
2337  ISD::FADD,
2338  ISD::FSUB,
2339  ISD::FNEG,
2340  ISD::FMA,
2342  ISD::FMINNUM,
2343  ISD::FMAXNUM,
2344  ISD::SUB,
2345  ISD::LOAD,
2346  ISD::MLOAD,
2347  ISD::STORE,
2348  ISD::MSTORE,
2349  ISD::TRUNCATE,
2361  ISD::SETCC,
2362  ISD::MUL,
2363  ISD::XOR,
2364  ISD::MSCATTER,
2365  ISD::MGATHER,
2369  ISD::FP_ROUND,
2371 
2373 
2374  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2376  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2378  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2380 
2381  // TODO: These control memcmp expansion in CGP and could be raised higher, but
2382  // that needs to benchmarked and balanced with the potential use of vector
2383  // load/store types (PR33329, PR33914).
2384  MaxLoadsPerMemcmp = 2;
2386 
2387  // Default loop alignment, which can be overridden by -align-loops.
2389 
2390  // An out-of-order CPU can speculatively execute past a predictable branch,
2391  // but a conditional move could be stalled by an expensive earlier operation.
2392  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2393  EnableExtLdPromotion = true;
2395 
2397 
2398  // Default to having -disable-strictnode-mutation on
2399  IsStrictFPEnabled = true;
2400 }
2401 
2402 // This has so far only been implemented for 64-bit MachO.
2404  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2405 }
2406 
2408  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2409  return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2410 }
2411 
2413  const SDLoc &DL) const {
2414  EVT PtrTy = getPointerTy(DAG.getDataLayout());
2415  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2416  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2417  return SDValue(Node, 0);
2418 }
2419 
2422  if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2423  !Subtarget.hasBWI())
2424  return TypeSplitVector;
2425 
2426  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2427  !Subtarget.hasF16C() && VT.getVectorElementType() == MVT::f16)
2428  return TypeSplitVector;
2429 
2430  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2431  VT.getVectorElementType() != MVT::i1)
2432  return TypeWidenVector;
2433 
2435 }
2436 
2437 static std::pair<MVT, unsigned>
2439  const X86Subtarget &Subtarget) {
2440  // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2441  // convention is one that uses k registers.
2442  if (NumElts == 2)
2443  return {MVT::v2i64, 1};
2444  if (NumElts == 4)
2445  return {MVT::v4i32, 1};
2446  if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2448  return {MVT::v8i16, 1};
2449  if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2451  return {MVT::v16i8, 1};
2452  // v32i1 passes in ymm unless we have BWI and the calling convention is
2453  // regcall.
2454  if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2455  return {MVT::v32i8, 1};
2456  // Split v64i1 vectors if we don't have v64i8 available.
2457  if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2458  if (Subtarget.useAVX512Regs())
2459  return {MVT::v64i8, 1};
2460  return {MVT::v32i8, 2};
2461  }
2462 
2463  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2464  if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2465  NumElts > 64)
2466  return {MVT::i8, NumElts};
2467 
2468  return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2469 }
2470 
2472  CallingConv::ID CC,
2473  EVT VT) const {
2474  if (VT.isVector()) {
2475  if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
2476  unsigned NumElts = VT.getVectorNumElements();
2477 
2478  MVT RegisterVT;
2479  unsigned NumRegisters;
2480  std::tie(RegisterVT, NumRegisters) =
2481  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2482  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2483  return RegisterVT;
2484  }
2485 
2486  if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
2487  return MVT::v8f16;
2488  }
2489 
2490  // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
2491  if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
2492  !Subtarget.hasX87())
2493  return MVT::i32;
2494 
2496 }
2497 
2499  CallingConv::ID CC,
2500  EVT VT) const {
2501  if (VT.isVector()) {
2502  if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
2503  unsigned NumElts = VT.getVectorNumElements();
2504 
2505  MVT RegisterVT;
2506  unsigned NumRegisters;
2507  std::tie(RegisterVT, NumRegisters) =
2508  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2509  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2510  return NumRegisters;
2511  }
2512 
2513  if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
2514  return 1;
2515  }
2516 
2517  // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
2518  // x87 is disabled.
2519  if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
2520  if (VT == MVT::f64)
2521  return 2;
2522  if (VT == MVT::f80)
2523  return 3;
2524  }
2525 
2527 }
2528 
2530  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2531  unsigned &NumIntermediates, MVT &RegisterVT) const {
2532  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2533  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2534  Subtarget.hasAVX512() &&
2536  (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2537  VT.getVectorNumElements() > 64)) {
2538  RegisterVT = MVT::i8;
2539  IntermediateVT = MVT::i1;
2540  NumIntermediates = VT.getVectorNumElements();
2541  return NumIntermediates;
2542  }
2543 
2544  // Split v64i1 vectors if we don't have v64i8 available.
2545  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2546  CC != CallingConv::X86_RegCall) {
2547  RegisterVT = MVT::v32i8;
2548  IntermediateVT = MVT::v32i1;
2549  NumIntermediates = 2;
2550  return 2;
2551  }
2552 
2553  return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2554  NumIntermediates, RegisterVT);
2555 }
2556 
2559  EVT VT) const {
2560  if (!VT.isVector())
2561  return MVT::i8;
2562 
2563  if (Subtarget.hasAVX512()) {
2564  // Figure out what this type will be legalized to.
2565  EVT LegalVT = VT;
2566  while (getTypeAction(Context, LegalVT) != TypeLegal)
2567  LegalVT = getTypeToTransformTo(Context, LegalVT);
2568 
2569  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2570  if (LegalVT.getSimpleVT().is512BitVector())
2572 
2573  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2574  // If we legalized to less than a 512-bit vector, then we will use a vXi1
2575  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2576  // vXi16/vXi8.
2577  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2578  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2580  }
2581  }
2582 
2584 }
2585 
2586 /// Helper for getByValTypeAlignment to determine
2587 /// the desired ByVal argument alignment.
2588 static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2589  if (MaxAlign == 16)
2590  return;
2591  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2592  if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2593  MaxAlign = Align(16);
2594  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2595  Align EltAlign;
2596  getMaxByValAlign(ATy->getElementType(), EltAlign);
2597  if (EltAlign > MaxAlign)
2598  MaxAlign = EltAlign;
2599  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2600  for (auto *EltTy : STy->elements()) {
2601  Align EltAlign;
2602  getMaxByValAlign(EltTy, EltAlign);
2603  if (EltAlign > MaxAlign)
2604  MaxAlign = EltAlign;
2605  if (MaxAlign == 16)
2606  break;
2607  }
2608  }
2609 }
2610 
2611 /// Return the desired alignment for ByVal aggregate
2612 /// function arguments in the caller parameter area. For X86, aggregates
2613 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2614 /// are at 4-byte boundaries.
2616  const DataLayout &DL) const {
2617  if (Subtarget.is64Bit()) {
2618  // Max of 8 and alignment of type.
2619  Align TyAlign = DL.getABITypeAlign(Ty);
2620  if (TyAlign > 8)
2621  return TyAlign.value();
2622  return 8;
2623  }
2624 
2625  Align Alignment(4);
2626  if (Subtarget.hasSSE1())
2627  getMaxByValAlign(Ty, Alignment);
2628  return Alignment.value();
2629 }
2630 
2631 /// It returns EVT::Other if the type should be determined using generic
2632 /// target-independent logic.
2633 /// For vector ops we check that the overall size isn't larger than our
2634 /// preferred vector width.
2636  const MemOp &Op, const AttributeList &FuncAttributes) const {
2637  if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2638  if (Op.size() >= 16 &&
2639  (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2640  // FIXME: Check if unaligned 64-byte accesses are slow.
2641  if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2642  (Subtarget.getPreferVectorWidth() >= 512)) {
2643  return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2644  }
2645  // FIXME: Check if unaligned 32-byte accesses are slow.
2646  if (Op.size() >= 32 && Subtarget.hasAVX() &&
2647  (Subtarget.getPreferVectorWidth() >= 256)) {
2648  // Although this isn't a well-supported type for AVX1, we'll let
2649  // legalization and shuffle lowering produce the optimal codegen. If we
2650  // choose an optimal type with a vector element larger than a byte,
2651  // getMemsetStores() may create an intermediate splat (using an integer
2652  // multiply) before we splat as a vector.
2653  return MVT::v32i8;
2654  }
2655  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2656  return MVT::v16i8;
2657  // TODO: Can SSE1 handle a byte vector?
2658  // If we have SSE1 registers we should be able to use them.
2659  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2660  (Subtarget.getPreferVectorWidth() >= 128))
2661  return MVT::v4f32;
2662  } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2663  Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2664  // Do not use f64 to lower memcpy if source is string constant. It's
2665  // better to use i32 to avoid the loads.
2666  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2667  // The gymnastics of splatting a byte value into an XMM register and then
2668  // only using 8-byte stores (because this is a CPU with slow unaligned
2669  // 16-byte accesses) makes that a loser.
2670  return MVT::f64;
2671  }
2672  }
2673  // This is a compromise. If we reach here, unaligned accesses may be slow on
2674  // this target. However, creating smaller, aligned accesses could be even
2675  // slower and would certainly be a lot more code.
2676  if (Subtarget.is64Bit() && Op.size() >= 8)
2677  return MVT::i64;
2678  return MVT::i32;
2679 }
2680 
2682  if (VT == MVT::f32)
2683  return Subtarget.hasSSE1();
2684  if (VT == MVT::f64)
2685  return Subtarget.hasSSE2();
2686  return true;
2687 }
2688 
2690  EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2691  bool *Fast) const {
2692  if (Fast) {
2693  switch (VT.getSizeInBits()) {
2694  default:
2695  // 8-byte and under are always assumed to be fast.
2696  *Fast = true;
2697  break;
2698  case 128:
2699  *Fast = !Subtarget.isUnalignedMem16Slow();
2700  break;
2701  case 256:
2702  *Fast = !Subtarget.isUnalignedMem32Slow();
2703  break;
2704  // TODO: What about AVX-512 (512-bit) accesses?
2705  }
2706  }
2707  // NonTemporal vector memory ops must be aligned.
2708  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2709  // NT loads can only be vector aligned, so if its less aligned than the
2710  // minimum vector size (which we can split the vector down to), we might as
2711  // well use a regular unaligned vector load.
2712  // We don't have any NT loads pre-SSE41.
2713  if (!!(Flags & MachineMemOperand::MOLoad))
2714  return (Alignment < 16 || !Subtarget.hasSSE41());
2715  return false;
2716  }
2717  // Misaligned accesses of any size are always allowed.
2718  return true;
2719 }
2720 
2721 /// Return the entry encoding for a jump table in the
2722 /// current function. The returned value is a member of the
2723 /// MachineJumpTableInfo::JTEntryKind enum.
2725  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2726  // symbol.
2727  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2729 
2730  // Otherwise, use the normal jump table encoding heuristics.
2732 }
2733 
2735  return Subtarget.useSoftFloat();
2736 }
2737 
2739  ArgListTy &Args) const {
2740 
2741  // Only relabel X86-32 for C / Stdcall CCs.
2742  if (Subtarget.is64Bit())
2743  return;
2744  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2745  return;
2746  unsigned ParamRegs = 0;
2747  if (auto *M = MF->getFunction().getParent())
2748  ParamRegs = M->getNumberRegisterParameters();
2749 
2750  // Mark the first N int arguments as having reg
2751  for (auto &Arg : Args) {
2752  Type *T = Arg.Ty;
2753  if (T->isIntOrPtrTy())
2754  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2755  unsigned numRegs = 1;
2756  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2757  numRegs = 2;
2758  if (ParamRegs < numRegs)
2759  return;
2760  ParamRegs -= numRegs;
2761  Arg.IsInReg = true;
2762  }
2763  }
2764 }
2765 
2766 const MCExpr *
2768  const MachineBasicBlock *MBB,
2769  unsigned uid,MCContext &Ctx) const{
2770  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2771  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2772  // entries.
2775 }
2776 
2777 /// Returns relocation base for the given PIC jumptable.
2779  SelectionDAG &DAG) const {
2780  if (!Subtarget.is64Bit())
2781  // This doesn't have SDLoc associated with it, but is not really the
2782  // same as a Register.
2783  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2784  getPointerTy(DAG.getDataLayout()));
2785  return Table;
2786 }
2787 
2788 /// This returns the relocation base for the given PIC jumptable,
2789 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2792  MCContext &Ctx) const {
2793  // X86-64 uses RIP relative addressing based on the jump table label.
2794  if (Subtarget.isPICStyleRIPRel())
2795  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2796 
2797  // Otherwise, the reference is relative to the PIC base.
2798  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2799 }
2800 
2801 std::pair<const TargetRegisterClass *, uint8_t>
2803  MVT VT) const {
2804  const TargetRegisterClass *RRC = nullptr;
2805  uint8_t Cost = 1;
2806  switch (VT.SimpleTy) {
2807  default:
2809  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2810  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2811  break;
2812  case MVT::x86mmx:
2813  RRC = &X86::VR64RegClass;
2814  break;
2815  case MVT::f32: case MVT::f64:
2816  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2817  case MVT::v4f32: case MVT::v2f64:
2818  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2819  case MVT::v8f32: case MVT::v4f64:
2820  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2821  case MVT::v16f32: case MVT::v8f64:
2822  RRC = &X86::VR128XRegClass;
2823  break;
2824  }
2825  return std::make_pair(RRC, Cost);
2826 }
2827 
2828 unsigned X86TargetLowering::getAddressSpace() const {
2829  if (Subtarget.is64Bit())
2830  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2831  return 256;
2832 }
2833 
2834 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2835  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2836  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2837 }
2838 
2840  int Offset, unsigned AddressSpace) {
2844 }
2845 
2847  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2848  // tcbhead_t; use it instead of the usual global variable (see
2849  // sysdeps/{i386,x86_64}/nptl/tls.h)
2850  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2851  if (Subtarget.isTargetFuchsia()) {
2852  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2853  return SegmentOffset(IRB, 0x10, getAddressSpace());
2854  } else {
2855  unsigned AddressSpace = getAddressSpace();
2856  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2857  // Specially, some users may customize the base reg and offset.
2858  int Offset = M->getStackProtectorGuardOffset();
2859  // If we don't set -stack-protector-guard-offset value:
2860  // %fs:0x28, unless we're using a Kernel code model, in which case
2861  // it's %gs:0x28. gs:0x14 on i386.
2862  if (Offset == INT_MAX)
2863  Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2864 
2865  StringRef GuardReg = M->getStackProtectorGuardReg();
2866  if (GuardReg == "fs")
2868  else if (GuardReg == "gs")
2870 
2871  // Use symbol guard if user specify.
2872  StringRef GuardSymb = M->getStackProtectorGuardSymbol();
2873  if (!GuardSymb.empty()) {
2874  GlobalVariable *GV = M->getGlobalVariable(GuardSymb);
2875  if (!GV) {
2876  Type *Ty = Subtarget.is64Bit() ? Type::getInt64Ty(M->getContext())
2877  : Type::getInt32Ty(M->getContext());
2878  GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage,
2879  nullptr, GuardSymb, nullptr,
2881  }
2882  return GV;
2883  }
2884 
2885  return SegmentOffset(IRB, Offset, AddressSpace);
2886  }
2887  }
2888  return TargetLowering::getIRStackGuard(IRB);
2889 }
2890 
2892  // MSVC CRT provides functionalities for stack protection.
2893  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2895  // MSVC CRT has a global variable holding security cookie.
2896  M.getOrInsertGlobal("__security_cookie",
2897  Type::getInt8PtrTy(M.getContext()));
2898 
2899  // MSVC CRT has a function to validate security cookie.
2900  FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2901  "__security_check_cookie", Type::getVoidTy(M.getContext()),
2902  Type::getInt8PtrTy(M.getContext()));
2903  if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2904  F->setCallingConv(CallingConv::X86_FastCall);
2905  F->addParamAttr(0, Attribute::AttrKind::InReg);
2906  }
2907  return;
2908  }
2909 
2910  StringRef GuardMode = M.getStackProtectorGuard();
2911 
2912  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2913  if ((GuardMode == "tls" || GuardMode.empty()) &&
2915  return;
2917 }
2918 
2920  // MSVC CRT has a global variable holding security cookie.
2921  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2923  return M.getGlobalVariable("__security_cookie");
2924  }
2926 }
2927 
2929  // MSVC CRT has a function to validate security cookie.
2930  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2932  return M.getFunction("__security_check_cookie");
2933  }
2935 }
2936 
2937 Value *
2939  if (Subtarget.getTargetTriple().isOSContiki())
2940  return getDefaultSafeStackPointerLocation(IRB, false);
2941 
2942  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2943  // definition of TLS_SLOT_SAFESTACK in
2944  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2945  if (Subtarget.isTargetAndroid()) {
2946  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2947  // %gs:0x24 on i386
2948  int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2949  return SegmentOffset(IRB, Offset, getAddressSpace());
2950  }
2951 
2952  // Fuchsia is similar.
2953  if (Subtarget.