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LLVM 20.0.0git
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X86II - This namespace holds all of the target specific flags that instruction info tracks. More...
Enumerations | |
| enum | TOF { MO_NO_FLAG , MO_GOT_ABSOLUTE_ADDRESS , MO_PIC_BASE_OFFSET , MO_GOT , MO_GOTOFF , MO_GOTPCREL , MO_GOTPCREL_NORELAX , MO_PLT , MO_TLSGD , MO_TLSLD , MO_TLSLDM , MO_GOTTPOFF , MO_INDNTPOFF , MO_TPOFF , MO_DTPOFF , MO_NTPOFF , MO_GOTNTPOFF , MO_DLLIMPORT , MO_DARWIN_NONLAZY , MO_DARWIN_NONLAZY_PIC_BASE , MO_TLVP , MO_TLVP_PIC_BASE , MO_SECREL , MO_ABS8 , MO_COFFSTUB } |
| Target Operand Flag enum. More... | |
| enum | : uint64_t { Pseudo = 0 , RawFrm = 1 , AddRegFrm = 2 , RawFrmMemOffs = 3 , RawFrmSrc = 4 , RawFrmDst = 5 , RawFrmDstSrc = 6 , RawFrmImm8 = 7 , RawFrmImm16 = 8 , AddCCFrm = 9 , PrefixByte = 10 , MRMDestRegCC = 18 , MRMDestMemCC = 19 , MRMDestMem4VOp3CC = 20 , MRMr0 = 21 , MRMSrcMemFSIB = 22 , MRMDestMemFSIB = 23 , MRMDestMem = 24 , MRMSrcMem = 25 , MRMSrcMem4VOp3 = 26 , MRMSrcMemOp4 = 27 , MRMSrcMemCC = 28 , MRMXmCC = 30 , MRMXm = 31 , MRM0m = 32 , MRM1m = 33 , MRM2m = 34 , MRM3m = 35 , MRM4m = 36 , MRM5m = 37 , MRM6m = 38 , MRM7m = 39 , MRMDestReg = 40 , MRMSrcReg = 41 , MRMSrcReg4VOp3 = 42 , MRMSrcRegOp4 = 43 , MRMSrcRegCC = 44 , MRMXrCC = 46 , MRMXr = 47 , MRM0r = 48 , MRM1r = 49 , MRM2r = 50 , MRM3r = 51 , MRM4r = 52 , MRM5r = 53 , MRM6r = 54 , MRM7r = 55 , MRM0X = 56 , MRM1X = 57 , MRM2X = 58 , MRM3X = 59 , MRM4X = 60 , MRM5X = 61 , MRM6X = 62 , MRM7X = 63 , MRM_C0 = 64 , MRM_C1 = 65 , MRM_C2 = 66 , MRM_C3 = 67 , MRM_C4 = 68 , MRM_C5 = 69 , MRM_C6 = 70 , MRM_C7 = 71 , MRM_C8 = 72 , MRM_C9 = 73 , MRM_CA = 74 , MRM_CB = 75 , MRM_CC = 76 , MRM_CD = 77 , MRM_CE = 78 , MRM_CF = 79 , MRM_D0 = 80 , MRM_D1 = 81 , MRM_D2 = 82 , MRM_D3 = 83 , MRM_D4 = 84 , MRM_D5 = 85 , MRM_D6 = 86 , MRM_D7 = 87 , MRM_D8 = 88 , MRM_D9 = 89 , MRM_DA = 90 , MRM_DB = 91 , MRM_DC = 92 , MRM_DD = 93 , MRM_DE = 94 , MRM_DF = 95 , MRM_E0 = 96 , MRM_E1 = 97 , MRM_E2 = 98 , MRM_E3 = 99 , MRM_E4 = 100 , MRM_E5 = 101 , MRM_E6 = 102 , MRM_E7 = 103 , MRM_E8 = 104 , MRM_E9 = 105 , MRM_EA = 106 , MRM_EB = 107 , MRM_EC = 108 , MRM_ED = 109 , MRM_EE = 110 , MRM_EF = 111 , MRM_F0 = 112 , MRM_F1 = 113 , MRM_F2 = 114 , MRM_F3 = 115 , MRM_F4 = 116 , MRM_F5 = 117 , MRM_F6 = 118 , MRM_F7 = 119 , MRM_F8 = 120 , MRM_F9 = 121 , MRM_FA = 122 , MRM_FB = 123 , MRM_FC = 124 , MRM_FD = 125 , MRM_FE = 126 , MRM_FF = 127 , FormMask = 127 , OpSizeShift = 7 , OpSizeMask = 0x3 << OpSizeShift , OpSizeFixed = 0 << OpSizeShift , OpSize16 = 1 << OpSizeShift , OpSize32 = 2 << OpSizeShift , AdSizeShift = OpSizeShift + 2 , AdSizeMask = 0x3 << AdSizeShift , AdSizeX = 0 << AdSizeShift , AdSize16 = 1 << AdSizeShift , AdSize32 = 2 << AdSizeShift , AdSize64 = 3 << AdSizeShift , OpPrefixShift = AdSizeShift + 2 , OpPrefixMask = 0x3 << OpPrefixShift , PD = 1 << OpPrefixShift , XS = 2 << OpPrefixShift , XD = 3 << OpPrefixShift , OpMapShift = OpPrefixShift + 2 , OpMapMask = 0xF << OpMapShift , OB = 0 << OpMapShift , TB = 1 << OpMapShift , T8 = 2 << OpMapShift , TA = 3 << OpMapShift , XOP8 = 4 << OpMapShift , XOP9 = 5 << OpMapShift , XOPA = 6 << OpMapShift , ThreeDNow = 7 << OpMapShift , T_MAP4 = 8 << OpMapShift , T_MAP5 = 9 << OpMapShift , T_MAP6 = 10 << OpMapShift , T_MAP7 = 11 << OpMapShift , REXShift = OpMapShift + 4 , REX_W = 1 << REXShift , ImmShift = REXShift + 1 , Imm8 = 1 << ImmShift , Imm8PCRel = 2 << ImmShift , Imm8Reg = 3 << ImmShift , Imm16 = 4 << ImmShift , Imm16PCRel = 5 << ImmShift , Imm32 = 6 << ImmShift , Imm32PCRel = 7 << ImmShift , Imm32S = 8 << ImmShift , Imm64 = 9 << ImmShift , ImmMask = 15 << ImmShift , FPTypeShift = ImmShift + 4 , FPTypeMask = 7 << FPTypeShift , NotFP = 0 << FPTypeShift , ZeroArgFP = 1 << FPTypeShift , OneArgFP = 2 << FPTypeShift , OneArgFPRW = 3 << FPTypeShift , TwoArgFP = 4 << FPTypeShift , CompareFP = 5 << FPTypeShift , CondMovFP = 6 << FPTypeShift , SpecialFP = 7 << FPTypeShift , LOCKShift = FPTypeShift + 3 , LOCK = 1 << LOCKShift , REPShift = LOCKShift + 1 , REP = 1 << REPShift , SSEDomainShift = REPShift + 1 , EncodingShift = SSEDomainShift + 2 , EncodingMask = 0x3 << EncodingShift , LEGACY = 0 << EncodingShift , VEX = 1 << EncodingShift , XOP = 2 << EncodingShift , EVEX = 3 << EncodingShift , OpcodeShift = EncodingShift + 2 , VEX_4VShift = OpcodeShift + 8 , VEX_4V = 1ULL << VEX_4VShift , VEX_LShift = VEX_4VShift + 1 , VEX_L = 1ULL << VEX_LShift , EVEX_KShift = VEX_LShift + 1 , EVEX_K = 1ULL << EVEX_KShift , EVEX_ZShift = EVEX_KShift + 1 , EVEX_Z = 1ULL << EVEX_ZShift , EVEX_L2Shift = EVEX_ZShift + 1 , EVEX_L2 = 1ULL << EVEX_L2Shift , EVEX_BShift = EVEX_L2Shift + 1 , EVEX_B = 1ULL << EVEX_BShift , CD8_Scale_Shift = EVEX_BShift + 1 , CD8_Scale_Mask = 7ULL << CD8_Scale_Shift , EVEX_RCShift = CD8_Scale_Shift + 3 , EVEX_RC = 1ULL << EVEX_RCShift , NoTrackShift = EVEX_RCShift + 1 , NOTRACK = 1ULL << NoTrackShift , ExplicitOpPrefixShift = NoTrackShift + 1 , ExplicitREX2Prefix = 1ULL << ExplicitOpPrefixShift , ExplicitVEXPrefix = 2ULL << ExplicitOpPrefixShift , ExplicitEVEXPrefix = 3ULL << ExplicitOpPrefixShift , ExplicitOpPrefixMask = 3ULL << ExplicitOpPrefixShift , EVEX_NFShift = ExplicitOpPrefixShift + 2 , EVEX_NF = 1ULL << EVEX_NFShift , TwoConditionalOps_Shift = EVEX_NFShift + 1 , TwoConditionalOps = 1ULL << TwoConditionalOps_Shift , EVEX_UShift = TwoConditionalOps_Shift + 1 , EVEX_U = 1ULL << EVEX_UShift } |
X86II - This namespace holds all of the target specific flags that instruction info tracks.
| anonymous enum : uint64_t |
| Enumerator | |
|---|---|
| Pseudo | PseudoFrm - This represents an instruction that is a pseudo instruction or one that has not been implemented yet. It is illegal to code generate it, but tolerated for intermediate implementation stages. |
| RawFrm | Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode value, like 'leave'. |
| AddRegFrm | AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand added to their opcode. |
| RawFrmMemOffs | RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate with a possible segment override. |
| RawFrmSrc | RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possible segment override. |
| RawFrmDst | RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI. |
| RawFrmDstSrc | RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possible segment override, and also the destination index register DI/EDI/RDI. |
| RawFrmImm8 | RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is a 16-bit immediate (specified by the imm encoding) and the second is a 8-bit fixed value. |
| RawFrmImm16 | RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which is a 16 or 32-bit immediate (specified by the imm encoding) and the second is a 16-bit fixed value. In the AMD manual, this operand is described as pntr16:32 and pntr16:16 |
| AddCCFrm | AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode. |
| PrefixByte | PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep. |
| MRMDestRegCC | MRMDestRegCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify the operands reg(r/m) and reg(reg) and also encodes a condition code. |
| MRMDestMemCC | MRMDestMemCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify the operands mem(r/m) and reg(reg) and also encodes a condition code. |
| MRMDestMem4VOp3CC | MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destination which in this case is memory and operand 3 with VEX.VVVV, and also encodes a condition code. |
| MRMr0 | Instructions operate on a register Reg/Opcode operand not the r/m field. |
| MRMSrcMemFSIB | MRMSrcMem - But force to use the SIB field. |
| MRMDestMemFSIB | MRMDestMem - But force to use the SIB field. |
| MRMDestMem | MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination, which in this case is memory. |
| MRMSrcMem | MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source, which in this case is memory. |
| MRMSrcMem4VOp3 | MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory. |
| MRMSrcMemOp4 | MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth source, which in this case is memory. |
| MRMSrcMemCC | MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and also encodes a condition code. |
| MRMXmCC | MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source, but doesn't use the middle field. And has a condition code. |
| MRMXm | MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source, but doesn't use the middle field. |
| MRM0m | MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use reg field to hold extended opcode, which is represented as /0, /1, ... |
| MRM1m | |
| MRM2m | |
| MRM3m | |
| MRM4m | |
| MRM5m | |
| MRM6m | |
| MRM7m | |
| MRMDestReg | MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination, which in this case is a register. |
| MRMSrcReg | MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source, which in this case is a register. |
| MRMSrcReg4VOp3 | MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory. |
| MRMSrcRegOp4 | MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth source, which in this case is a register. |
| MRMSrcRegCC | MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and also encodes a condition code. |
| MRMXrCC | MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source, but doesn't use the middle field. And has a condition code. |
| MRMXr | MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source, but doesn't use the middle field. |
| MRM0r | MRM0r-MRM7r - Instructions that operate on a register r/m operand and use reg field to hold extended opcode, which is represented as /0, /1, ... |
| MRM1r | |
| MRM2r | |
| MRM3r | |
| MRM4r | |
| MRM5r | |
| MRM6r | |
| MRM7r | |
| MRM0X | MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but ignore r/m. |
| MRM1X | |
| MRM2X | |
| MRM3X | |
| MRM4X | |
| MRM5X | |
| MRM6X | |
| MRM7X | |
| MRM_C0 | MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX. |
| MRM_C1 | |
| MRM_C2 | |
| MRM_C3 | |
| MRM_C4 | |
| MRM_C5 | |
| MRM_C6 | |
| MRM_C7 | |
| MRM_C8 | |
| MRM_C9 | |
| MRM_CA | |
| MRM_CB | |
| MRM_CC | |
| MRM_CD | |
| MRM_CE | |
| MRM_CF | |
| MRM_D0 | |
| MRM_D1 | |
| MRM_D2 | |
| MRM_D3 | |
| MRM_D4 | |
| MRM_D5 | |
| MRM_D6 | |
| MRM_D7 | |
| MRM_D8 | |
| MRM_D9 | |
| MRM_DA | |
| MRM_DB | |
| MRM_DC | |
| MRM_DD | |
| MRM_DE | |
| MRM_DF | |
| MRM_E0 | |
| MRM_E1 | |
| MRM_E2 | |
| MRM_E3 | |
| MRM_E4 | |
| MRM_E5 | |
| MRM_E6 | |
| MRM_E7 | |
| MRM_E8 | |
| MRM_E9 | |
| MRM_EA | |
| MRM_EB | |
| MRM_EC | |
| MRM_ED | |
| MRM_EE | |
| MRM_EF | |
| MRM_F0 | |
| MRM_F1 | |
| MRM_F2 | |
| MRM_F3 | |
| MRM_F4 | |
| MRM_F5 | |
| MRM_F6 | |
| MRM_F7 | |
| MRM_F8 | |
| MRM_F9 | |
| MRM_FA | |
| MRM_FB | |
| MRM_FC | |
| MRM_FD | |
| MRM_FE | |
| MRM_FF | |
| FormMask | |
| OpSizeShift | OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 prefix in 16-bit mode. |
| OpSizeMask | |
| OpSizeFixed | |
| OpSize16 | |
| OpSize32 | |
| AdSizeShift | AsSize - AdSizeX implies this instruction determines its need of 0x67 prefix from a normal ModRM memory operand. The other types indicate that an operand is encoded with a specific width and a prefix is needed if it differs from the current mode. |
| AdSizeMask | |
| AdSizeX | |
| AdSize16 | |
| AdSize32 | |
| AdSize64 | |
| OpPrefixShift | OpPrefix - There are several prefix bytes that are used as opcode extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is no prefix. |
| OpPrefixMask | |
| PD | PD - Prefix code for packed double precision vector floating point operations performed in the SSE registers. |
| XS | XS, XD - These prefix codes are for single and double precision scalar floating point operations performed in the SSE registers. |
| XD | |
| OpMapShift | OpMap - This field determines which opcode map this instruction belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. |
| OpMapMask | |
| OB | OB - OneByte - Set if this instruction has a one byte opcode. |
| TB | TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before the real opcode. |
| T8 | T8, TA - Prefix after the 0x0F prefix. |
| TA | |
| XOP8 | XOP8 - Prefix to include use of imm byte. |
| XOP9 | XOP9 - Prefix to exclude use of imm byte. |
| XOPA | XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. |
| ThreeDNow | ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents this as having a 0x0F prefix with a 0x0F opcode, and each instruction storing a classifier in the imm8 field. To simplify our implementation, we handle this by storeing the classifier in the opcode field and using this flag to indicate that the encoder should do the wacky 3DNow! thing. |
| T_MAP4 | MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix. |
| T_MAP5 | |
| T_MAP6 | |
| T_MAP7 | |
| REXShift | REX_W - REX prefixes are instruction prefixes used in 64-bit mode. They are used to specify GPRs and SSE registers, 64-bit operand size, etc. We only cares about REX.W and REX.R bits and only the former is statically determined. |
| REX_W | |
| ImmShift | |
| Imm8 | |
| Imm8PCRel | |
| Imm8Reg | |
| Imm16 | |
| Imm16PCRel | |
| Imm32 | |
| Imm32PCRel | |
| Imm32S | |
| Imm64 | |
| ImmMask | |
| FPTypeShift | FP Instruction Classification... Zero is non-fp instruction. FPTypeMask - Mask for all of the FP types... |
| FPTypeMask | |
| NotFP | NotFP - The default, set for instructions that do not use FP registers. |
| ZeroArgFP | ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0. |
| OneArgFP | OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst. |
| OneArgFPRW | OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a result back to ST(0). For example, fcos, fsqrt, etc. |
| TwoArgFP | TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an explicit argument, storing the result to either ST(0) or the implicit argument. For example: fadd, fsub, fmul, etc... |
| CompareFP | CompareFP - 2 arg FP instructions which implicitly read ST(0) and an explicit argument, but have no destination. Example: fucom, fucomi, ... |
| CondMovFP | CondMovFP - "2 operand" floating point conditional move instructions. |
| SpecialFP | SpecialFP - Special instruction forms. Dispatch by opcode explicitly. |
| LOCKShift | Lock prefix. |
| LOCK | |
| REPShift | REP prefix. |
| REP | |
| SSEDomainShift | Execution domain for SSE instructions. 0 means normal, non-SSE instruction. |
| EncodingShift | Encoding. |
| EncodingMask | |
| LEGACY | LEGACY - encoding using REX/REX2 or w/o opcode prefix. |
| VEX | VEX - encoding using 0xC4/0xC5. |
| XOP | XOP - Opcode prefix used by XOP instructions. |
| EVEX | EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit register operands and up to 7 16-bit mask operands as well as source operand data swizzling/memory operand conversion, eviction hint, and rounding mode. |
| OpcodeShift | Opcode. |
| VEX_4VShift | VEX_4V - Used to specify an additional AVX/SSE register. Several 2 address instructions in SSE are represented as 3 address ones in AVX and the additional register is encoded in VEX_VVVV prefix. |
| VEX_4V | |
| VEX_LShift | VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide registers. This is usually auto detected if a VR256 register is used, but some AVX instructions also have this field marked when using a f256 memory references. |
| VEX_L | |
| EVEX_KShift | EVEX_K - Set if this instruction requires masking. |
| EVEX_K | |
| EVEX_ZShift | EVEX_Z - Set if this instruction has EVEX.Z field set. |
| EVEX_Z | |
| EVEX_L2Shift | EVEX_L2 - Set if this instruction has EVEX.L' field set. |
| EVEX_L2 | |
| EVEX_BShift | EVEX_B - Set if this instruction has EVEX.B field set. |
| EVEX_B | |
| CD8_Scale_Shift | The scaling factor for the AVX512's 8-bit compressed displacement. |
| CD8_Scale_Mask | |
| EVEX_RCShift | Explicitly specified rounding control. |
| EVEX_RC | |
| NoTrackShift | NOTRACK prefix. |
| NOTRACK | |
| ExplicitOpPrefixShift | Force REX2/VEX/EVEX encoding. |
| ExplicitREX2Prefix | For instructions that require REX2 prefix even if EGPR is not used. |
| ExplicitVEXPrefix | For instructions that use VEX encoding only when {vex}, {vex2} or {vex3} is present. |
| ExplicitEVEXPrefix | For instructions that are promoted to EVEX space for EGPR. |
| ExplicitOpPrefixMask | |
| EVEX_NFShift | EVEX_NF - Set if this instruction has EVEX.NF field set. |
| EVEX_NF | |
| TwoConditionalOps_Shift | |
| TwoConditionalOps | |
| EVEX_UShift | |
| EVEX_U | |
Definition at line 491 of file X86BaseInfo.h.
| enum llvm::X86II::TOF |
Target Operand Flag enum.
| Enumerator | |
|---|---|
| MO_NO_FLAG | MO_NO_FLAG - No flag for the operand. |
| MO_GOT_ABSOLUTE_ADDRESS | MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
|
| MO_PIC_BASE_OFFSET | MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of the symbol minus the PIC base label: SYMBOL_LABEL - PICBASELABEL. |
| MO_GOT | MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the symbol name from the base of the GOT. See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL @GOT |
| MO_GOTOFF | MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of the symbol name from the base of the GOT. See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL @GOTOFF |
| MO_GOTPCREL | MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name from the current code location. See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL @GOTPCREL |
| MO_GOTPCREL_NORELAX | MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to be emitted by the integrated assembler instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations. |
| MO_PLT | MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol name from the current code location. See the X86-64 ELF ABI supplement for more details. SYMBOL_LABEL @PLT |
| MO_TLSGD | MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS index structure that contains the module number and variable offset for the symbol. Used in the general dynamic TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @TLSGD |
| MO_TLSLD | MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS index for the module that contains the symbol. When this index is passed to a call to __tls_get_addr, the function will return the base address of the TLS block for the symbol. Used in the x86-64 local dynamic TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @TLSLD |
| MO_TLSLDM | MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS index for the module that contains the symbol. When this index is passed to a call to ___tls_get_addr, the function will return the base address of the TLS block for the symbol. Used in the IA32 local dynamic TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @TLSLDM |
| MO_GOTTPOFF | MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the thread-pointer offset for the symbol. Used in the x86-64 initial exec TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @GOTTPOFF |
| MO_INDNTPOFF | MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the GOT entry with the negative thread-pointer offset for the symbol. Used in the non-PIC IA32 initial exec TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @INDNTPOFF |
| MO_TPOFF | MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the symbol. Used in the x86-64 local exec TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @TPOFF |
| MO_DTPOFF | MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the TLS offset of the symbol. Used in the local dynamic TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @DTPOFF |
| MO_NTPOFF | MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offset for the symbol. Used in the IA32 local exec TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @NTPOFF |
| MO_GOTNTPOFF | MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with the negative thread-pointer offset for the symbol. Used in the PIC IA32 initial exec TLS access model. See 'ELF Handling for Thread-Local Storage' for more details. SYMBOL_LABEL @GOTNTPOFF |
| MO_DLLIMPORT | MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp_FOO" symbol. This is used for dllimport linkage on windows. |
| MO_DARWIN_NONLAZY | MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "FOO$non_lazy_ptr" symbol, which is a non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. |
| MO_DARWIN_NONLAZY_PIC_BASE | MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. |
| MO_TLVP | MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset. This is the TLS offset for the Darwin TLS mechanism. |
| MO_TLVP_PIC_BASE | MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the picbase. This is the 32-bit TLS offset for Darwin TLS in PIC mode. |
| MO_SECREL | MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of section. This is the TLS offset for the COFF/Windows TLS mechanism. |
| MO_ABS8 | MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in range [0,128), so we can use the @ABS8 symbol modifier. |
| MO_COFFSTUB | MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the ".refptr.FOO" symbol. This is used for stub symbols on windows. |
Definition at line 358 of file X86BaseInfo.h.
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Definition at line 1260 of file X86BaseInfo.h.
References EncodingMask, EVEX, isPseudo(), OB, OpMapMask, and TB.
Referenced by llvm::X86InstrInfo::getRegClass().
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Definition at line 893 of file X86BaseInfo.h.
References OpcodeShift.
Referenced by llvm::getFMA3Group().
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Definition at line 1011 of file X86BaseInfo.h.
References AddCCFrm, AddRegFrm, EVEX_K, FormMask, hasNewDataDest(), llvm_unreachable, MRM0m, MRM0r, MRM0X, MRM1m, MRM1r, MRM1X, MRM2m, MRM2r, MRM2X, MRM3m, MRM3r, MRM3X, MRM4m, MRM4r, MRM4X, MRM5m, MRM5r, MRM5X, MRM6m, MRM6r, MRM6X, MRM7m, MRM7r, MRM7X, MRM_C0, MRM_C1, MRM_C2, MRM_C3, MRM_C4, MRM_C5, MRM_C6, MRM_C7, MRM_C8, MRM_C9, MRM_CA, MRM_CB, MRM_CC, MRM_CD, MRM_CE, MRM_CF, MRM_D0, MRM_D1, MRM_D2, MRM_D3, MRM_D4, MRM_D5, MRM_D6, MRM_D7, MRM_D8, MRM_D9, MRM_DA, MRM_DB, MRM_DC, MRM_DD, MRM_DE, MRM_DF, MRM_E0, MRM_E1, MRM_E2, MRM_E3, MRM_E4, MRM_E5, MRM_E6, MRM_E7, MRM_E8, MRM_E9, MRM_EA, MRM_EB, MRM_EC, MRM_ED, MRM_EE, MRM_EF, MRM_F0, MRM_F1, MRM_F2, MRM_F3, MRM_F4, MRM_F5, MRM_F6, MRM_F7, MRM_F8, MRM_F9, MRM_FA, MRM_FB, MRM_FC, MRM_FD, MRM_FE, MRM_FF, MRMDestMem, MRMDestMem4VOp3CC, MRMDestMemCC, MRMDestMemFSIB, MRMDestReg, MRMDestRegCC, MRMr0, MRMSrcMem, MRMSrcMem4VOp3, MRMSrcMemCC, MRMSrcMemFSIB, MRMSrcMemOp4, MRMSrcReg, MRMSrcReg4VOp3, MRMSrcRegCC, MRMSrcRegOp4, MRMXm, MRMXmCC, MRMXr, MRMXrCC, PrefixByte, Pseudo, RawFrm, RawFrmDst, RawFrmDstSrc, RawFrmImm16, RawFrmImm8, RawFrmMemOffs, RawFrmSrc, and VEX_4V.
Referenced by llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), getAddrOffset(), llvm::X86::getFirstAddrOperandIdx(), getJumpTableIndexFromAddr(), llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(), llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset(), isRIPRelative(), llvm::X86InstPrinterCommon::printInstFlags(), and usedAsAddr().
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Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
This determines the start of the unique operand list. We need to determine if all of the defs have a corresponding tied operand in the uses. Unfortunately, the tied operand information is encoded in the uses not the defs so we have to use some heuristics to find which operands to query.
Definition at line 968 of file X86BaseInfo.h.
References llvm_unreachable, and llvm::MCOI::TIED_TO.
Referenced by llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), getAddrOffset(), llvm::X86::getFirstAddrOperandIdx(), getJumpTableIndexFromAddr(), llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(), llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset(), isPCRel32Branch(), isRIPRelative(), llvm::X86InstPrinterCommon::printInstFlags(), and usedAsAddr().
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition at line 901 of file X86BaseInfo.h.
References Imm16, Imm16PCRel, Imm32, Imm32PCRel, Imm32S, Imm64, Imm8, Imm8PCRel, Imm8Reg, ImmMask, and llvm_unreachable.
Referenced by getImmFixupKind().
Definition at line 897 of file X86BaseInfo.h.
References ImmMask.
Definition at line 1001 of file X86BaseInfo.h.
References EVEX_B, OpMapMask, T_MAP4, and VEX_4V.
Referenced by CompressEVEXImpl(), and getMemoryOperandNo().
Definition at line 1302 of file X86BaseInfo.h.
RegNo is an apx extended register. Definition at line 1186 of file X86BaseInfo.h.
Referenced by isX86_64ExtendedReg(), and usesExtendedRegister().
Definition at line 923 of file X86BaseInfo.h.
References Imm16, Imm16PCRel, Imm32, Imm32PCRel, Imm32S, Imm64, Imm8, Imm8PCRel, Imm8Reg, ImmMask, and llvm_unreachable.
Referenced by getImmFixupKind().
Definition at line 943 of file X86BaseInfo.h.
References Imm16, Imm16PCRel, Imm32, Imm32PCRel, Imm32S, Imm64, Imm8, Imm8PCRel, Imm8Reg, ImmMask, and llvm_unreachable.
Referenced by getImmFixupKind().
Definition at line 1314 of file X86BaseInfo.h.
References EVEX_K.
Referenced by llvm::X86InstrInfo::findCommutedOpIndices(), getSrcIdx(), getThreeSrcCommuteCase(), isKMergeMasked(), and printDstRegisterName().
Definition at line 1319 of file X86BaseInfo.h.
References EVEX_Z, and isKMasked().
Referenced by llvm::X86InstrInfo::findCommutedOpIndices(), getSrcIdx(), and printDstRegisterName().
Definition at line 882 of file X86BaseInfo.h.
References FormMask, and PrefixByte.
Referenced by isPrefix().
Definition at line 887 of file X86BaseInfo.h.
References FormMask, and Pseudo.
Referenced by canUseApxExtendedReg(), and llvm::X86::getFirstAddrOperandIdx().
Definition at line 1193 of file X86BaseInfo.h.
References isApxExtendedReg().
Referenced by llvm::X86::optimizeInstFromVEX3ToVEX2().
Definition at line 1308 of file X86BaseInfo.h.
Definition at line 1159 of file X86BaseInfo.h.
Referenced by getVectorRegSize(), llvm::X86Operand::isMem128_RC128X(), llvm::X86Operand::isMem256_RC128X(), and llvm::X86Operand::isMem64_RC128X().
Definition at line 1169 of file X86BaseInfo.h.
Referenced by getVectorRegSize(), llvm::X86Operand::isMem128_RC256X(), llvm::X86Operand::isMem256_RC256X(), and llvm::X86Operand::isMem512_RC256X().
Definition at line 1179 of file X86BaseInfo.h.
Referenced by getVectorRegSize(), llvm::X86Operand::isMem256_RC512(), llvm::X86Operand::isMem512_RC512(), and usesExtendedRegister().
1.9.6