LLVM 20.0.0git
X86InstComments.cpp
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1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This defines functionality used to emit comments about X86 instructions to
10// an output stream for -fverbose-asm.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstComments.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86MCTargetDesc.h"
18#include "X86ShuffleDecode.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/Support/raw_ostream.h"
22
23using namespace llvm;
24
25#define CASE_SSE_INS_COMMON(Inst, src) \
26 case X86::Inst##src:
27
28#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
29 case X86::V##Inst##Suffix##src:
30
31#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
32 case X86::V##Inst##Suffix##src##k:
33
34#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
35 case X86::V##Inst##Suffix##src##kz:
36
37#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
38 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
39 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
40 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
41
42#define CASE_MOVDUP(Inst, src) \
43 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
44 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
45 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
46 CASE_AVX_INS_COMMON(Inst, , r##src) \
47 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
48 CASE_SSE_INS_COMMON(Inst, r##src)
49
50#define CASE_MASK_MOVDUP(Inst, src) \
51 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
52 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
53 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
54
55#define CASE_MASKZ_MOVDUP(Inst, src) \
56 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
57 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
58 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
59
60#define CASE_PMOVZX(Inst, src) \
61 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
62 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
63 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
64 CASE_AVX_INS_COMMON(Inst, , r##src) \
65 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
66 CASE_SSE_INS_COMMON(Inst, r##src)
67
68#define CASE_UNPCK(Inst, src) \
69 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
70 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
71 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
72 CASE_AVX_INS_COMMON(Inst, , r##src) \
73 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
74 CASE_SSE_INS_COMMON(Inst, r##src)
75
76#define CASE_MASK_UNPCK(Inst, src) \
77 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
78 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
79 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
80
81#define CASE_MASKZ_UNPCK(Inst, src) \
82 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
83 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
84 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
85
86#define CASE_SHUF(Inst, suf) \
87 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
88 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
89 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
90 CASE_AVX_INS_COMMON(Inst, , suf) \
91 CASE_AVX_INS_COMMON(Inst, Y, suf) \
92 CASE_SSE_INS_COMMON(Inst, suf)
93
94#define CASE_MASK_SHUF(Inst, src) \
95 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
96 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
97 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
98
99#define CASE_MASKZ_SHUF(Inst, src) \
100 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
101 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
102 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
103
104#define CASE_VPERMILPI(Inst, src) \
105 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
106 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
107 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
108 CASE_AVX_INS_COMMON(Inst, , src##i) \
109 CASE_AVX_INS_COMMON(Inst, Y, src##i)
110
111#define CASE_MASK_VPERMILPI(Inst, src) \
112 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
113 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
114 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
115
116#define CASE_MASKZ_VPERMILPI(Inst, src) \
117 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
118 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
119 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
120
121#define CASE_VPERM(Inst, src) \
122 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
123 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
124 CASE_AVX_INS_COMMON(Inst, Y, src##i)
125
126#define CASE_MASK_VPERM(Inst, src) \
127 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
128 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
129
130#define CASE_MASKZ_VPERM(Inst, src) \
131 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
132 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
133
134#define CASE_VSHUF(Inst, src) \
135 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
136 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
137 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
138 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
139
140#define CASE_MASK_VSHUF(Inst, src) \
141 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
142 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
143 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
144 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
145
146#define CASE_MASKZ_VSHUF(Inst, src) \
147 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
148 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
149 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
150 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
151
152#define CASE_AVX512_FMA(Inst, suf) \
153 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
154 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
155 CASE_AVX512_INS_COMMON(Inst, Z128, suf)
156
157#define CASE_FMA(Inst, suf) \
158 CASE_AVX512_FMA(Inst, suf) \
159 CASE_AVX_INS_COMMON(Inst, , suf) \
160 CASE_AVX_INS_COMMON(Inst, Y, suf)
161
162#define CASE_FMA_PACKED_REG(Inst) \
163 CASE_FMA(Inst##PD, r) \
164 CASE_FMA(Inst##PS, r)
165
166#define CASE_FMA_PACKED_MEM(Inst) \
167 CASE_FMA(Inst##PD, m) \
168 CASE_FMA(Inst##PS, m) \
169 CASE_AVX512_FMA(Inst##PD, mb) \
170 CASE_AVX512_FMA(Inst##PS, mb)
171
172#define CASE_FMA_SCALAR_REG(Inst) \
173 CASE_AVX_INS_COMMON(Inst##SD, , r) \
174 CASE_AVX_INS_COMMON(Inst##SS, , r) \
175 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \
176 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
177 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
178 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
179 CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int) \
180 CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int)
181
182#define CASE_FMA_SCALAR_MEM(Inst) \
183 CASE_AVX_INS_COMMON(Inst##SD, , m) \
184 CASE_AVX_INS_COMMON(Inst##SS, , m) \
185 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \
186 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
187 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
188 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
189 CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int) \
190 CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int)
191
192#define CASE_FMA4(Inst, suf) \
193 CASE_AVX_INS_COMMON(Inst, 4, suf) \
194 CASE_AVX_INS_COMMON(Inst, 4Y, suf)
195
196#define CASE_FMA4_PACKED_RR(Inst) \
197 CASE_FMA4(Inst##PD, rr) \
198 CASE_FMA4(Inst##PS, rr)
199
200#define CASE_FMA4_PACKED_RM(Inst) \
201 CASE_FMA4(Inst##PD, rm) \
202 CASE_FMA4(Inst##PS, rm)
203
204#define CASE_FMA4_PACKED_MR(Inst) \
205 CASE_FMA4(Inst##PD, mr) \
206 CASE_FMA4(Inst##PS, mr)
207
208#define CASE_FMA4_SCALAR_RR(Inst) \
209 CASE_AVX_INS_COMMON(Inst##SD4, , rr) \
210 CASE_AVX_INS_COMMON(Inst##SS4, , rr) \
211 CASE_AVX_INS_COMMON(Inst##SD4, , rr_Int) \
212 CASE_AVX_INS_COMMON(Inst##SS4, , rr_Int)
213
214#define CASE_FMA4_SCALAR_RM(Inst) \
215 CASE_AVX_INS_COMMON(Inst##SD4, , rm) \
216 CASE_AVX_INS_COMMON(Inst##SS4, , rm) \
217 CASE_AVX_INS_COMMON(Inst##SD4, , rm_Int) \
218 CASE_AVX_INS_COMMON(Inst##SS4, , rm_Int)
219
220#define CASE_FMA4_SCALAR_MR(Inst) \
221 CASE_AVX_INS_COMMON(Inst##SD4, , mr) \
222 CASE_AVX_INS_COMMON(Inst##SS4, , mr) \
223 CASE_AVX_INS_COMMON(Inst##SD4, , mr_Int) \
224 CASE_AVX_INS_COMMON(Inst##SS4, , mr_Int)
225
226static unsigned getVectorRegSize(unsigned RegNo) {
227 if (X86II::isZMMReg(RegNo))
228 return 512;
229 if (X86II::isYMMReg(RegNo))
230 return 256;
231 if (X86II::isXMMReg(RegNo))
232 return 128;
233 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
234 return 64;
235
236 llvm_unreachable("Unknown vector reg!");
237}
238
239static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
240 unsigned OperandIndex) {
241 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
242 return getVectorRegSize(OpReg) / ScalarSize;
243}
244
245static const char *getRegName(MCRegister Reg) {
246 return X86ATTInstPrinter::getRegisterName(Reg);
247}
248
249/// Wraps the destination register name with AVX512 mask/maskz filtering.
250static void printMasking(raw_ostream &OS, const MCInst *MI,
251 const MCInstrInfo &MCII) {
252 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
253 uint64_t TSFlags = Desc.TSFlags;
254
255 if (!(TSFlags & X86II::EVEX_K))
256 return;
257
258 bool MaskWithZero = (TSFlags & X86II::EVEX_Z);
259 unsigned MaskOp = Desc.getNumDefs();
260
261 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
262 ++MaskOp;
263
264 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
265
266 // MASK: zmmX {%kY}
267 OS << " {%" << MaskRegName << "}";
268
269 // MASKZ: zmmX {%kY} {z}
270 if (MaskWithZero)
271 OS << " {z}";
272}
273
274static bool printFMAComments(const MCInst *MI, raw_ostream &OS,
275 const MCInstrInfo &MCII) {
276 const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr;
277 unsigned NumOperands = MI->getNumOperands();
278 bool RegForm = false;
279 bool Negate = false;
280 StringRef AccStr = "+";
281
282 // The operands for FMA3 instructions without rounding fall into two forms:
283 // dest, src1, src2, src3
284 // dest, src1, mask, src2, src3
285 // Where src3 is either a register or 5 memory address operands. So to find
286 // dest and src1 we can index from the front. To find src2 and src3 we can
287 // index from the end by taking into account memory vs register form when
288 // finding src2.
289
290 // The operands for FMA4 instructions:
291 // dest, src1, src2, src3
292 // Where src2 OR src3 are either a register or 5 memory address operands. So
293 // to find dest and src1 we can index from the front, src2 (reg/mem) follows
294 // and then src3 (reg) will be at the end.
295
296 switch (MI->getOpcode()) {
297 default:
298 return false;
299
300 CASE_FMA4_PACKED_RR(FMADD)
301 CASE_FMA4_SCALAR_RR(FMADD)
302 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
303 [[fallthrough]];
304 CASE_FMA4_PACKED_RM(FMADD)
305 CASE_FMA4_SCALAR_RM(FMADD)
306 Mul2Name = getRegName(MI->getOperand(2).getReg());
307 Mul1Name = getRegName(MI->getOperand(1).getReg());
308 break;
309 CASE_FMA4_PACKED_MR(FMADD)
310 CASE_FMA4_SCALAR_MR(FMADD)
311 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
312 Mul1Name = getRegName(MI->getOperand(1).getReg());
313 break;
314
315 CASE_FMA4_PACKED_RR(FMSUB)
316 CASE_FMA4_SCALAR_RR(FMSUB)
317 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
318 [[fallthrough]];
319 CASE_FMA4_PACKED_RM(FMSUB)
320 CASE_FMA4_SCALAR_RM(FMSUB)
321 Mul2Name = getRegName(MI->getOperand(2).getReg());
322 Mul1Name = getRegName(MI->getOperand(1).getReg());
323 AccStr = "-";
324 break;
325 CASE_FMA4_PACKED_MR(FMSUB)
326 CASE_FMA4_SCALAR_MR(FMSUB)
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
328 Mul1Name = getRegName(MI->getOperand(1).getReg());
329 AccStr = "-";
330 break;
331
332 CASE_FMA4_PACKED_RR(FNMADD)
333 CASE_FMA4_SCALAR_RR(FNMADD)
334 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
335 [[fallthrough]];
336 CASE_FMA4_PACKED_RM(FNMADD)
337 CASE_FMA4_SCALAR_RM(FNMADD)
338 Mul2Name = getRegName(MI->getOperand(2).getReg());
339 Mul1Name = getRegName(MI->getOperand(1).getReg());
340 Negate = true;
341 break;
342 CASE_FMA4_PACKED_MR(FNMADD)
343 CASE_FMA4_SCALAR_MR(FNMADD)
344 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
345 Mul1Name = getRegName(MI->getOperand(1).getReg());
346 Negate = true;
347 break;
348
349 CASE_FMA4_PACKED_RR(FNMSUB)
350 CASE_FMA4_SCALAR_RR(FNMSUB)
351 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
352 [[fallthrough]];
353 CASE_FMA4_PACKED_RM(FNMSUB)
354 CASE_FMA4_SCALAR_RM(FNMSUB)
355 Mul2Name = getRegName(MI->getOperand(2).getReg());
356 Mul1Name = getRegName(MI->getOperand(1).getReg());
357 AccStr = "-";
358 Negate = true;
359 break;
360 CASE_FMA4_PACKED_MR(FNMSUB)
361 CASE_FMA4_SCALAR_MR(FNMSUB)
362 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
363 Mul1Name = getRegName(MI->getOperand(1).getReg());
364 AccStr = "-";
365 Negate = true;
366 break;
367
368 CASE_FMA4_PACKED_RR(FMADDSUB)
369 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
370 [[fallthrough]];
371 CASE_FMA4_PACKED_RM(FMADDSUB)
372 Mul2Name = getRegName(MI->getOperand(2).getReg());
373 Mul1Name = getRegName(MI->getOperand(1).getReg());
374 AccStr = "+/-";
375 break;
376 CASE_FMA4_PACKED_MR(FMADDSUB)
377 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
378 Mul1Name = getRegName(MI->getOperand(1).getReg());
379 AccStr = "+/-";
380 break;
381
382 CASE_FMA4_PACKED_RR(FMSUBADD)
383 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
384 [[fallthrough]];
385 CASE_FMA4_PACKED_RM(FMSUBADD)
386 Mul2Name = getRegName(MI->getOperand(2).getReg());
387 Mul1Name = getRegName(MI->getOperand(1).getReg());
388 AccStr = "-/+";
389 break;
390 CASE_FMA4_PACKED_MR(FMSUBADD)
391 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
392 Mul1Name = getRegName(MI->getOperand(1).getReg());
393 AccStr = "-/+";
394 break;
395
396 CASE_FMA_PACKED_REG(FMADD132)
397 CASE_FMA_SCALAR_REG(FMADD132)
398 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
399 RegForm = true;
400 [[fallthrough]];
401 CASE_FMA_PACKED_MEM(FMADD132)
402 CASE_FMA_SCALAR_MEM(FMADD132)
403 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
404 Mul1Name = getRegName(MI->getOperand(1).getReg());
405 break;
406
407 CASE_FMA_PACKED_REG(FMADD213)
408 CASE_FMA_SCALAR_REG(FMADD213)
409 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
410 RegForm = true;
411 [[fallthrough]];
412 CASE_FMA_PACKED_MEM(FMADD213)
413 CASE_FMA_SCALAR_MEM(FMADD213)
414 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
415 Mul2Name = getRegName(MI->getOperand(1).getReg());
416 break;
417
418 CASE_FMA_PACKED_REG(FMADD231)
419 CASE_FMA_SCALAR_REG(FMADD231)
420 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
421 RegForm = true;
422 [[fallthrough]];
423 CASE_FMA_PACKED_MEM(FMADD231)
424 CASE_FMA_SCALAR_MEM(FMADD231)
425 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
426 AccName = getRegName(MI->getOperand(1).getReg());
427 break;
428
429 CASE_FMA_PACKED_REG(FMSUB132)
430 CASE_FMA_SCALAR_REG(FMSUB132)
431 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
432 RegForm = true;
433 [[fallthrough]];
434 CASE_FMA_PACKED_MEM(FMSUB132)
435 CASE_FMA_SCALAR_MEM(FMSUB132)
436 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
437 Mul1Name = getRegName(MI->getOperand(1).getReg());
438 AccStr = "-";
439 break;
440
441 CASE_FMA_PACKED_REG(FMSUB213)
442 CASE_FMA_SCALAR_REG(FMSUB213)
443 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
444 RegForm = true;
445 [[fallthrough]];
446 CASE_FMA_PACKED_MEM(FMSUB213)
447 CASE_FMA_SCALAR_MEM(FMSUB213)
448 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
449 Mul2Name = getRegName(MI->getOperand(1).getReg());
450 AccStr = "-";
451 break;
452
453 CASE_FMA_PACKED_REG(FMSUB231)
454 CASE_FMA_SCALAR_REG(FMSUB231)
455 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
456 RegForm = true;
457 [[fallthrough]];
458 CASE_FMA_PACKED_MEM(FMSUB231)
459 CASE_FMA_SCALAR_MEM(FMSUB231)
460 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
461 AccName = getRegName(MI->getOperand(1).getReg());
462 AccStr = "-";
463 break;
464
465 CASE_FMA_PACKED_REG(FNMADD132)
466 CASE_FMA_SCALAR_REG(FNMADD132)
467 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
468 RegForm = true;
469 [[fallthrough]];
470 CASE_FMA_PACKED_MEM(FNMADD132)
471 CASE_FMA_SCALAR_MEM(FNMADD132)
472 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
473 Mul1Name = getRegName(MI->getOperand(1).getReg());
474 Negate = true;
475 break;
476
477 CASE_FMA_PACKED_REG(FNMADD213)
478 CASE_FMA_SCALAR_REG(FNMADD213)
479 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
480 RegForm = true;
481 [[fallthrough]];
482 CASE_FMA_PACKED_MEM(FNMADD213)
483 CASE_FMA_SCALAR_MEM(FNMADD213)
484 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
485 Mul2Name = getRegName(MI->getOperand(1).getReg());
486 Negate = true;
487 break;
488
489 CASE_FMA_PACKED_REG(FNMADD231)
490 CASE_FMA_SCALAR_REG(FNMADD231)
491 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
492 RegForm = true;
493 [[fallthrough]];
494 CASE_FMA_PACKED_MEM(FNMADD231)
495 CASE_FMA_SCALAR_MEM(FNMADD231)
496 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
497 AccName = getRegName(MI->getOperand(1).getReg());
498 Negate = true;
499 break;
500
501 CASE_FMA_PACKED_REG(FNMSUB132)
502 CASE_FMA_SCALAR_REG(FNMSUB132)
503 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
504 RegForm = true;
505 [[fallthrough]];
506 CASE_FMA_PACKED_MEM(FNMSUB132)
507 CASE_FMA_SCALAR_MEM(FNMSUB132)
508 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
509 Mul1Name = getRegName(MI->getOperand(1).getReg());
510 AccStr = "-";
511 Negate = true;
512 break;
513
514 CASE_FMA_PACKED_REG(FNMSUB213)
515 CASE_FMA_SCALAR_REG(FNMSUB213)
516 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
517 RegForm = true;
518 [[fallthrough]];
519 CASE_FMA_PACKED_MEM(FNMSUB213)
520 CASE_FMA_SCALAR_MEM(FNMSUB213)
521 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
522 Mul2Name = getRegName(MI->getOperand(1).getReg());
523 AccStr = "-";
524 Negate = true;
525 break;
526
527 CASE_FMA_PACKED_REG(FNMSUB231)
528 CASE_FMA_SCALAR_REG(FNMSUB231)
529 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
530 RegForm = true;
531 [[fallthrough]];
532 CASE_FMA_PACKED_MEM(FNMSUB231)
533 CASE_FMA_SCALAR_MEM(FNMSUB231)
534 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
535 AccName = getRegName(MI->getOperand(1).getReg());
536 AccStr = "-";
537 Negate = true;
538 break;
539
540 CASE_FMA_PACKED_REG(FMADDSUB132)
541 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
542 RegForm = true;
543 [[fallthrough]];
544 CASE_FMA_PACKED_MEM(FMADDSUB132)
545 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
546 Mul1Name = getRegName(MI->getOperand(1).getReg());
547 AccStr = "+/-";
548 break;
549
550 CASE_FMA_PACKED_REG(FMADDSUB213)
551 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
552 RegForm = true;
553 [[fallthrough]];
554 CASE_FMA_PACKED_MEM(FMADDSUB213)
555 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
556 Mul2Name = getRegName(MI->getOperand(1).getReg());
557 AccStr = "+/-";
558 break;
559
560 CASE_FMA_PACKED_REG(FMADDSUB231)
561 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
562 RegForm = true;
563 [[fallthrough]];
564 CASE_FMA_PACKED_MEM(FMADDSUB231)
565 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
566 AccName = getRegName(MI->getOperand(1).getReg());
567 AccStr = "+/-";
568 break;
569
570 CASE_FMA_PACKED_REG(FMSUBADD132)
571 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
572 RegForm = true;
573 [[fallthrough]];
574 CASE_FMA_PACKED_MEM(FMSUBADD132)
575 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
576 Mul1Name = getRegName(MI->getOperand(1).getReg());
577 AccStr = "-/+";
578 break;
579
580 CASE_FMA_PACKED_REG(FMSUBADD213)
581 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
582 RegForm = true;
583 [[fallthrough]];
584 CASE_FMA_PACKED_MEM(FMSUBADD213)
585 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
586 Mul2Name = getRegName(MI->getOperand(1).getReg());
587 AccStr = "-/+";
588 break;
589
590 CASE_FMA_PACKED_REG(FMSUBADD231)
591 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
592 RegForm = true;
593 [[fallthrough]];
594 CASE_FMA_PACKED_MEM(FMSUBADD231)
595 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
596 AccName = getRegName(MI->getOperand(1).getReg());
597 AccStr = "-/+";
598 break;
599 }
600
601 const char *DestName = getRegName(MI->getOperand(0).getReg());
602
603 if (!Mul1Name) Mul1Name = "mem";
604 if (!Mul2Name) Mul2Name = "mem";
605 if (!AccName) AccName = "mem";
606
607 OS << DestName;
608 printMasking(OS, MI, MCII);
609 OS << " = ";
610
611 if (Negate)
612 OS << '-';
613
614 OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' '
615 << AccName << '\n';
616
617 return true;
618}
619
620
621//===----------------------------------------------------------------------===//
622// Top Level Entrypoint
623//===----------------------------------------------------------------------===//
624
625/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
626/// newline terminated strings to the specified string if desired. This
627/// information is shown in disassembly dumps when verbose assembly is enabled.
628bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
629 const MCInstrInfo &MCII) {
630 // If this is a shuffle operation, the switch should fill in this state.
631 SmallVector<int, 8> ShuffleMask;
632 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
633 unsigned NumOperands = MI->getNumOperands();
634 bool RegForm = false;
635
636 if (printFMAComments(MI, OS, MCII))
637 return true;
638
639 switch (MI->getOpcode()) {
640 default:
641 // Not an instruction for which we can decode comments.
642 return false;
643
644 case X86::BLENDPDrri:
645 case X86::VBLENDPDrri:
646 case X86::VBLENDPDYrri:
647 Src2Name = getRegName(MI->getOperand(2).getReg());
648 [[fallthrough]];
649 case X86::BLENDPDrmi:
650 case X86::VBLENDPDrmi:
651 case X86::VBLENDPDYrmi:
652 if (MI->getOperand(NumOperands - 1).isImm())
653 DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),
654 MI->getOperand(NumOperands - 1).getImm(),
655 ShuffleMask);
656 Src1Name = getRegName(MI->getOperand(1).getReg());
657 DestName = getRegName(MI->getOperand(0).getReg());
658 break;
659
660 case X86::BLENDPSrri:
661 case X86::VBLENDPSrri:
662 case X86::VBLENDPSYrri:
663 Src2Name = getRegName(MI->getOperand(2).getReg());
664 [[fallthrough]];
665 case X86::BLENDPSrmi:
666 case X86::VBLENDPSrmi:
667 case X86::VBLENDPSYrmi:
668 if (MI->getOperand(NumOperands - 1).isImm())
669 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
670 MI->getOperand(NumOperands - 1).getImm(),
671 ShuffleMask);
672 Src1Name = getRegName(MI->getOperand(1).getReg());
673 DestName = getRegName(MI->getOperand(0).getReg());
674 break;
675
676 case X86::PBLENDWrri:
677 case X86::VPBLENDWrri:
678 case X86::VPBLENDWYrri:
679 Src2Name = getRegName(MI->getOperand(2).getReg());
680 [[fallthrough]];
681 case X86::PBLENDWrmi:
682 case X86::VPBLENDWrmi:
683 case X86::VPBLENDWYrmi:
684 if (MI->getOperand(NumOperands - 1).isImm())
685 DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),
686 MI->getOperand(NumOperands - 1).getImm(),
687 ShuffleMask);
688 Src1Name = getRegName(MI->getOperand(1).getReg());
689 DestName = getRegName(MI->getOperand(0).getReg());
690 break;
691
692 case X86::VPBLENDDrri:
693 case X86::VPBLENDDYrri:
694 Src2Name = getRegName(MI->getOperand(2).getReg());
695 [[fallthrough]];
696 case X86::VPBLENDDrmi:
697 case X86::VPBLENDDYrmi:
698 if (MI->getOperand(NumOperands - 1).isImm())
699 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
700 MI->getOperand(NumOperands - 1).getImm(),
701 ShuffleMask);
702 Src1Name = getRegName(MI->getOperand(1).getReg());
703 DestName = getRegName(MI->getOperand(0).getReg());
704 break;
705
706 case X86::INSERTPSrr:
707 case X86::VINSERTPSrr:
708 case X86::VINSERTPSZrr:
709 Src2Name = getRegName(MI->getOperand(2).getReg());
710 [[fallthrough]];
711 case X86::INSERTPSrm:
712 case X86::VINSERTPSrm:
713 case X86::VINSERTPSZrm:
714 DestName = getRegName(MI->getOperand(0).getReg());
715 Src1Name = getRegName(MI->getOperand(1).getReg());
716 if (MI->getOperand(NumOperands - 1).isImm())
717 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
718 ShuffleMask);
719 break;
720
721 case X86::MOVLHPSrr:
722 case X86::VMOVLHPSrr:
723 case X86::VMOVLHPSZrr:
724 Src2Name = getRegName(MI->getOperand(2).getReg());
725 Src1Name = getRegName(MI->getOperand(1).getReg());
726 DestName = getRegName(MI->getOperand(0).getReg());
727 DecodeMOVLHPSMask(2, ShuffleMask);
728 break;
729
730 case X86::MOVHLPSrr:
731 case X86::VMOVHLPSrr:
732 case X86::VMOVHLPSZrr:
733 Src2Name = getRegName(MI->getOperand(2).getReg());
734 Src1Name = getRegName(MI->getOperand(1).getReg());
735 DestName = getRegName(MI->getOperand(0).getReg());
736 DecodeMOVHLPSMask(2, ShuffleMask);
737 break;
738
739 case X86::MOVHPDrm:
740 case X86::VMOVHPDrm:
741 case X86::VMOVHPDZ128rm:
742 Src1Name = getRegName(MI->getOperand(1).getReg());
743 DestName = getRegName(MI->getOperand(0).getReg());
744 DecodeInsertElementMask(2, 1, 1, ShuffleMask);
745 break;
746
747 case X86::MOVHPSrm:
748 case X86::VMOVHPSrm:
749 case X86::VMOVHPSZ128rm:
750 Src1Name = getRegName(MI->getOperand(1).getReg());
751 DestName = getRegName(MI->getOperand(0).getReg());
752 DecodeInsertElementMask(4, 2, 2, ShuffleMask);
753 break;
754
755 case X86::MOVLPDrm:
756 case X86::VMOVLPDrm:
757 case X86::VMOVLPDZ128rm:
758 Src1Name = getRegName(MI->getOperand(1).getReg());
759 DestName = getRegName(MI->getOperand(0).getReg());
760 DecodeInsertElementMask(2, 0, 1, ShuffleMask);
761 break;
762
763 case X86::MOVLPSrm:
764 case X86::VMOVLPSrm:
765 case X86::VMOVLPSZ128rm:
766 Src1Name = getRegName(MI->getOperand(1).getReg());
767 DestName = getRegName(MI->getOperand(0).getReg());
768 DecodeInsertElementMask(4, 0, 2, ShuffleMask);
769 break;
770
771 CASE_MOVDUP(MOVSLDUP, r)
772 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
773 [[fallthrough]];
774
775 CASE_MOVDUP(MOVSLDUP, m)
776 DestName = getRegName(MI->getOperand(0).getReg());
777 DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
778 break;
779
780 CASE_MOVDUP(MOVSHDUP, r)
781 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
782 [[fallthrough]];
783
784 CASE_MOVDUP(MOVSHDUP, m)
785 DestName = getRegName(MI->getOperand(0).getReg());
786 DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
787 break;
788
789 CASE_MOVDUP(MOVDDUP, r)
790 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
791 [[fallthrough]];
792
793 CASE_MOVDUP(MOVDDUP, m)
794 DestName = getRegName(MI->getOperand(0).getReg());
795 DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);
796 break;
797
798 case X86::PSLLDQri:
799 case X86::VPSLLDQri:
800 case X86::VPSLLDQYri:
801 case X86::VPSLLDQZ128ri:
802 case X86::VPSLLDQZ256ri:
803 case X86::VPSLLDQZri:
804 Src1Name = getRegName(MI->getOperand(1).getReg());
805 [[fallthrough]];
806 case X86::VPSLLDQZ128mi:
807 case X86::VPSLLDQZ256mi:
808 case X86::VPSLLDQZmi:
809 DestName = getRegName(MI->getOperand(0).getReg());
810 if (MI->getOperand(NumOperands - 1).isImm())
811 DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
812 MI->getOperand(NumOperands - 1).getImm(),
813 ShuffleMask);
814 break;
815
816 case X86::PSRLDQri:
817 case X86::VPSRLDQri:
818 case X86::VPSRLDQYri:
819 case X86::VPSRLDQZ128ri:
820 case X86::VPSRLDQZ256ri:
821 case X86::VPSRLDQZri:
822 Src1Name = getRegName(MI->getOperand(1).getReg());
823 [[fallthrough]];
824 case X86::VPSRLDQZ128mi:
825 case X86::VPSRLDQZ256mi:
826 case X86::VPSRLDQZmi:
827 DestName = getRegName(MI->getOperand(0).getReg());
828 if (MI->getOperand(NumOperands - 1).isImm())
829 DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),
830 MI->getOperand(NumOperands - 1).getImm(),
831 ShuffleMask);
832 break;
833
834 CASE_SHUF(PALIGNR, rri)
835 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
836 RegForm = true;
837 [[fallthrough]];
838
839 CASE_SHUF(PALIGNR, rmi)
840 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
841 DestName = getRegName(MI->getOperand(0).getReg());
842 if (MI->getOperand(NumOperands - 1).isImm())
843 DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),
844 MI->getOperand(NumOperands - 1).getImm(),
845 ShuffleMask);
846 break;
847
848 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
849 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
850 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
851 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
852 RegForm = true;
853 [[fallthrough]];
854
855 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
856 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
857 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
858 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
859 DestName = getRegName(MI->getOperand(0).getReg());
860 if (MI->getOperand(NumOperands - 1).isImm())
861 DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),
862 MI->getOperand(NumOperands - 1).getImm(),
863 ShuffleMask);
864 break;
865
866 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
867 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
868 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
869 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
870 RegForm = true;
871 [[fallthrough]];
872
873 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
874 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
875 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
876 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
877 DestName = getRegName(MI->getOperand(0).getReg());
878 if (MI->getOperand(NumOperands - 1).isImm())
879 DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),
880 MI->getOperand(NumOperands - 1).getImm(),
881 ShuffleMask);
882 break;
883
884 CASE_SHUF(PSHUFD, ri)
885 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
886 [[fallthrough]];
887
888 CASE_SHUF(PSHUFD, mi)
889 DestName = getRegName(MI->getOperand(0).getReg());
890 if (MI->getOperand(NumOperands - 1).isImm())
891 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
892 MI->getOperand(NumOperands - 1).getImm(),
893 ShuffleMask);
894 break;
895
896 CASE_SHUF(PSHUFHW, ri)
897 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
898 [[fallthrough]];
899
900 CASE_SHUF(PSHUFHW, mi)
901 DestName = getRegName(MI->getOperand(0).getReg());
902 if (MI->getOperand(NumOperands - 1).isImm())
903 DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),
904 MI->getOperand(NumOperands - 1).getImm(),
905 ShuffleMask);
906 break;
907
908 CASE_SHUF(PSHUFLW, ri)
909 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
910 [[fallthrough]];
911
912 CASE_SHUF(PSHUFLW, mi)
913 DestName = getRegName(MI->getOperand(0).getReg());
914 if (MI->getOperand(NumOperands - 1).isImm())
915 DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),
916 MI->getOperand(NumOperands - 1).getImm(),
917 ShuffleMask);
918 break;
919
920 case X86::MMX_PSHUFWri:
921 Src1Name = getRegName(MI->getOperand(1).getReg());
922 [[fallthrough]];
923
924 case X86::MMX_PSHUFWmi:
925 DestName = getRegName(MI->getOperand(0).getReg());
926 if (MI->getOperand(NumOperands - 1).isImm())
927 DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(),
928 ShuffleMask);
929 break;
930
931 case X86::PSWAPDrr:
932 Src1Name = getRegName(MI->getOperand(1).getReg());
933 [[fallthrough]];
934
935 case X86::PSWAPDrm:
936 DestName = getRegName(MI->getOperand(0).getReg());
937 DecodePSWAPMask(2, ShuffleMask);
938 break;
939
940 CASE_UNPCK(PUNPCKHBW, r)
941 case X86::MMX_PUNPCKHBWrr:
942 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
943 RegForm = true;
944 [[fallthrough]];
945
946 CASE_UNPCK(PUNPCKHBW, m)
947 case X86::MMX_PUNPCKHBWrm:
948 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
949 DestName = getRegName(MI->getOperand(0).getReg());
950 DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
951 break;
952
953 CASE_UNPCK(PUNPCKHWD, r)
954 case X86::MMX_PUNPCKHWDrr:
955 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
956 RegForm = true;
957 [[fallthrough]];
958
959 CASE_UNPCK(PUNPCKHWD, m)
960 case X86::MMX_PUNPCKHWDrm:
961 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
962 DestName = getRegName(MI->getOperand(0).getReg());
963 DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
964 break;
965
966 CASE_UNPCK(PUNPCKHDQ, r)
967 case X86::MMX_PUNPCKHDQrr:
968 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
969 RegForm = true;
970 [[fallthrough]];
971
972 CASE_UNPCK(PUNPCKHDQ, m)
973 case X86::MMX_PUNPCKHDQrm:
974 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
975 DestName = getRegName(MI->getOperand(0).getReg());
976 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
977 break;
978
979 CASE_UNPCK(PUNPCKHQDQ, r)
980 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
981 RegForm = true;
982 [[fallthrough]];
983
984 CASE_UNPCK(PUNPCKHQDQ, m)
985 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
986 DestName = getRegName(MI->getOperand(0).getReg());
987 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
988 break;
989
990 CASE_UNPCK(PUNPCKLBW, r)
991 case X86::MMX_PUNPCKLBWrr:
992 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
993 RegForm = true;
994 [[fallthrough]];
995
996 CASE_UNPCK(PUNPCKLBW, m)
997 case X86::MMX_PUNPCKLBWrm:
998 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
999 DestName = getRegName(MI->getOperand(0).getReg());
1000 DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
1001 break;
1002
1003 CASE_UNPCK(PUNPCKLWD, r)
1004 case X86::MMX_PUNPCKLWDrr:
1005 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1006 RegForm = true;
1007 [[fallthrough]];
1008
1009 CASE_UNPCK(PUNPCKLWD, m)
1010 case X86::MMX_PUNPCKLWDrm:
1011 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1012 DestName = getRegName(MI->getOperand(0).getReg());
1013 DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
1014 break;
1015
1016 CASE_UNPCK(PUNPCKLDQ, r)
1017 case X86::MMX_PUNPCKLDQrr:
1018 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1019 RegForm = true;
1020 [[fallthrough]];
1021
1022 CASE_UNPCK(PUNPCKLDQ, m)
1023 case X86::MMX_PUNPCKLDQrm:
1024 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1025 DestName = getRegName(MI->getOperand(0).getReg());
1026 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1027 break;
1028
1029 CASE_UNPCK(PUNPCKLQDQ, r)
1030 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1031 RegForm = true;
1032 [[fallthrough]];
1033
1034 CASE_UNPCK(PUNPCKLQDQ, m)
1035 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1036 DestName = getRegName(MI->getOperand(0).getReg());
1037 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1038 break;
1039
1040 CASE_SHUF(SHUFPD, rri)
1041 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1042 RegForm = true;
1043 [[fallthrough]];
1044
1045 CASE_SHUF(SHUFPD, rmi)
1046 if (MI->getOperand(NumOperands - 1).isImm())
1047 DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,
1048 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
1049 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1050 DestName = getRegName(MI->getOperand(0).getReg());
1051 break;
1052
1053 CASE_SHUF(SHUFPS, rri)
1054 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1055 RegForm = true;
1056 [[fallthrough]];
1057
1058 CASE_SHUF(SHUFPS, rmi)
1059 if (MI->getOperand(NumOperands - 1).isImm())
1060 DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,
1061 MI->getOperand(NumOperands - 1).getImm(),
1062 ShuffleMask);
1063 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1064 DestName = getRegName(MI->getOperand(0).getReg());
1065 break;
1066
1067 CASE_VSHUF(64X2, r)
1068 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1069 RegForm = true;
1070 [[fallthrough]];
1071
1072 CASE_VSHUF(64X2, m)
1073 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,
1074 MI->getOperand(NumOperands - 1).getImm(),
1075 ShuffleMask);
1076 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1077 DestName = getRegName(MI->getOperand(0).getReg());
1078 break;
1079
1080 CASE_VSHUF(32X4, r)
1081 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1082 RegForm = true;
1083 [[fallthrough]];
1084
1085 CASE_VSHUF(32X4, m)
1086 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,
1087 MI->getOperand(NumOperands - 1).getImm(),
1088 ShuffleMask);
1089 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1090 DestName = getRegName(MI->getOperand(0).getReg());
1091 break;
1092
1093 CASE_UNPCK(UNPCKLPD, r)
1094 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1095 RegForm = true;
1096 [[fallthrough]];
1097
1098 CASE_UNPCK(UNPCKLPD, m)
1099 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1100 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1101 DestName = getRegName(MI->getOperand(0).getReg());
1102 break;
1103
1104 CASE_UNPCK(UNPCKLPS, r)
1105 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1106 RegForm = true;
1107 [[fallthrough]];
1108
1109 CASE_UNPCK(UNPCKLPS, m)
1110 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1111 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1112 DestName = getRegName(MI->getOperand(0).getReg());
1113 break;
1114
1115 CASE_UNPCK(UNPCKHPD, r)
1116 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1117 RegForm = true;
1118 [[fallthrough]];
1119
1120 CASE_UNPCK(UNPCKHPD, m)
1121 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1122 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1123 DestName = getRegName(MI->getOperand(0).getReg());
1124 break;
1125
1126 CASE_UNPCK(UNPCKHPS, r)
1127 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1128 RegForm = true;
1129 [[fallthrough]];
1130
1131 CASE_UNPCK(UNPCKHPS, m)
1132 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1133 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1134 DestName = getRegName(MI->getOperand(0).getReg());
1135 break;
1136
1137 CASE_VPERMILPI(PERMILPS, r)
1138 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1139 [[fallthrough]];
1140
1141 CASE_VPERMILPI(PERMILPS, m)
1142 if (MI->getOperand(NumOperands - 1).isImm())
1143 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1144 MI->getOperand(NumOperands - 1).getImm(),
1145 ShuffleMask);
1146 DestName = getRegName(MI->getOperand(0).getReg());
1147 break;
1148
1149 CASE_VPERMILPI(PERMILPD, r)
1150 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1151 [[fallthrough]];
1152
1153 CASE_VPERMILPI(PERMILPD, m)
1154 if (MI->getOperand(NumOperands - 1).isImm())
1155 DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,
1156 MI->getOperand(NumOperands - 1).getImm(),
1157 ShuffleMask);
1158 DestName = getRegName(MI->getOperand(0).getReg());
1159 break;
1160
1161 case X86::VPERM2F128rr:
1162 case X86::VPERM2I128rr:
1163 Src2Name = getRegName(MI->getOperand(2).getReg());
1164 [[fallthrough]];
1165
1166 case X86::VPERM2F128rm:
1167 case X86::VPERM2I128rm:
1168 // For instruction comments purpose, assume the 256-bit vector is v4i64.
1169 if (MI->getOperand(NumOperands - 1).isImm())
1170 DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
1171 ShuffleMask);
1172 Src1Name = getRegName(MI->getOperand(1).getReg());
1173 DestName = getRegName(MI->getOperand(0).getReg());
1174 break;
1175
1176 CASE_VPERM(PERMPD, r)
1177 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1178 [[fallthrough]];
1179
1180 CASE_VPERM(PERMPD, m)
1181 if (MI->getOperand(NumOperands - 1).isImm())
1182 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1183 MI->getOperand(NumOperands - 1).getImm(),
1184 ShuffleMask);
1185 DestName = getRegName(MI->getOperand(0).getReg());
1186 break;
1187
1188 CASE_VPERM(PERMQ, r)
1189 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1190 [[fallthrough]];
1191
1192 CASE_VPERM(PERMQ, m)
1193 if (MI->getOperand(NumOperands - 1).isImm())
1194 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1195 MI->getOperand(NumOperands - 1).getImm(),
1196 ShuffleMask);
1197 DestName = getRegName(MI->getOperand(0).getReg());
1198 break;
1199
1200 case X86::MOVSDrr:
1201 case X86::VMOVSDrr:
1202 case X86::VMOVSDZrr:
1203 Src2Name = getRegName(MI->getOperand(2).getReg());
1204 Src1Name = getRegName(MI->getOperand(1).getReg());
1205 DecodeScalarMoveMask(2, false, ShuffleMask);
1206 DestName = getRegName(MI->getOperand(0).getReg());
1207 break;
1208
1209 case X86::MOVSSrr:
1210 case X86::VMOVSSrr:
1211 case X86::VMOVSSZrr:
1212 Src2Name = getRegName(MI->getOperand(2).getReg());
1213 Src1Name = getRegName(MI->getOperand(1).getReg());
1214 DecodeScalarMoveMask(4, false, ShuffleMask);
1215 DestName = getRegName(MI->getOperand(0).getReg());
1216 break;
1217
1218 case X86::MOVPQI2QIrr:
1219 case X86::MOVZPQILo2PQIrr:
1220 case X86::VMOVPQI2QIrr:
1221 case X86::VMOVPQI2QIZrr:
1222 case X86::VMOVZPQILo2PQIrr:
1223 case X86::VMOVZPQILo2PQIZrr:
1224 Src1Name = getRegName(MI->getOperand(1).getReg());
1225 DecodeZeroMoveLowMask(2, ShuffleMask);
1226 DestName = getRegName(MI->getOperand(0).getReg());
1227 break;
1228
1229 case X86::EXTRQI:
1230 if (MI->getOperand(2).isImm() &&
1231 MI->getOperand(3).isImm())
1232 DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(),
1233 MI->getOperand(3).getImm(), ShuffleMask);
1234
1235 DestName = getRegName(MI->getOperand(0).getReg());
1236 Src1Name = getRegName(MI->getOperand(1).getReg());
1237 break;
1238
1239 case X86::INSERTQI:
1240 if (MI->getOperand(3).isImm() &&
1241 MI->getOperand(4).isImm())
1242 DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(),
1243 MI->getOperand(4).getImm(), ShuffleMask);
1244
1245 DestName = getRegName(MI->getOperand(0).getReg());
1246 Src1Name = getRegName(MI->getOperand(1).getReg());
1247 Src2Name = getRegName(MI->getOperand(2).getReg());
1248 break;
1249
1250 case X86::VBROADCASTF128rm:
1251 case X86::VBROADCASTI128rm:
1252 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1253 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
1254 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1255 DestName = getRegName(MI->getOperand(0).getReg());
1256 break;
1257 CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1258 CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1259 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1260 DestName = getRegName(MI->getOperand(0).getReg());
1261 break;
1262 CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1263 CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1264 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1265 DestName = getRegName(MI->getOperand(0).getReg());
1266 break;
1267 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1268 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1269 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1270 DestName = getRegName(MI->getOperand(0).getReg());
1271 break;
1272 CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1273 CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1274 DecodeSubVectorBroadcast(16, 4, ShuffleMask);
1275 DestName = getRegName(MI->getOperand(0).getReg());
1276 break;
1277 CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1278 CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1279 DecodeSubVectorBroadcast(16, 8, ShuffleMask);
1280 DestName = getRegName(MI->getOperand(0).getReg());
1281 break;
1282 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rr)
1283 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1284 [[fallthrough]];
1285 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rm)
1286 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1287 DestName = getRegName(MI->getOperand(0).getReg());
1288 break;
1289 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rr)
1290 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rr)
1291 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1292 [[fallthrough]];
1293 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rm)
1294 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rm)
1295 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1296 DestName = getRegName(MI->getOperand(0).getReg());
1297 break;
1298 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rr)
1299 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rr)
1300 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1301 [[fallthrough]];
1302 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rm)
1303 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rm)
1304 DecodeSubVectorBroadcast(16, 2, ShuffleMask);
1305 DestName = getRegName(MI->getOperand(0).getReg());
1306 break;
1307
1308 CASE_PMOVZX(PMOVZXBW, r)
1309 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1310 DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
1311 ShuffleMask);
1312 DestName = getRegName(MI->getOperand(0).getReg());
1313 break;
1314
1315 CASE_PMOVZX(PMOVZXBD, r)
1316 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1317 DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
1318 ShuffleMask);
1319 DestName = getRegName(MI->getOperand(0).getReg());
1320 break;
1321
1322 CASE_PMOVZX(PMOVZXBQ, r)
1323 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1324 DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
1325 ShuffleMask);
1326 DestName = getRegName(MI->getOperand(0).getReg());
1327 break;
1328
1329 CASE_PMOVZX(PMOVZXWD, r)
1330 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1331 DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
1332 ShuffleMask);
1333 DestName = getRegName(MI->getOperand(0).getReg());
1334 break;
1335
1336 CASE_PMOVZX(PMOVZXWQ, r)
1337 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1338 DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
1339 ShuffleMask);
1340 DestName = getRegName(MI->getOperand(0).getReg());
1341 break;
1342
1343 CASE_PMOVZX(PMOVZXDQ, r)
1344 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1345 DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
1346 ShuffleMask);
1347 DestName = getRegName(MI->getOperand(0).getReg());
1348 break;
1349 }
1350
1351 // The only comments we decode are shuffles, so give up if we were unable to
1352 // decode a shuffle mask.
1353 if (ShuffleMask.empty())
1354 return false;
1355
1356 if (!DestName) DestName = Src1Name;
1357 if (DestName) {
1358 OS << DestName;
1359 printMasking(OS, MI, MCII);
1360 } else
1361 OS << "mem";
1362
1363 OS << " = ";
1364
1365 // If the two sources are the same, canonicalize the input elements to be
1366 // from the first src so that we get larger element spans.
1367 if (Src1Name == Src2Name) {
1368 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1369 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1370 ShuffleMask[i] >= (int)e) // From second mask.
1371 ShuffleMask[i] -= e;
1372 }
1373 }
1374
1375 // The shuffle mask specifies which elements of the src1/src2 fill in the
1376 // destination, with a few sentinel values. Loop through and print them
1377 // out.
1378 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1379 if (i != 0)
1380 OS << ',';
1381 if (ShuffleMask[i] == SM_SentinelZero) {
1382 OS << "zero";
1383 continue;
1384 }
1385
1386 // Otherwise, it must come from src1 or src2. Print the span of elements
1387 // that comes from this src.
1388 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1389 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1390 OS << (SrcName ? SrcName : "mem") << '[';
1391 bool IsFirst = true;
1392 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1393 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1394 if (!IsFirst)
1395 OS << ',';
1396 else
1397 IsFirst = false;
1398 if (ShuffleMask[i] == SM_SentinelUndef)
1399 OS << "u";
1400 else
1401 OS << ShuffleMask[i] % ShuffleMask.size();
1402 ++i;
1403 }
1404 OS << ']';
1405 --i; // For loop increments element #.
1406 }
1407 OS << '\n';
1408
1409 // We successfully added a comment to this instruction.
1410 return true;
1411}
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:113
OS
raw_pwrite_stream & OS
Definition: SampleProfWriter.cpp:53
CASE_VPERM
#define CASE_VPERM(Inst, src)
Definition: X86InstComments.cpp:121
CASE_FMA_SCALAR_REG
#define CASE_FMA_SCALAR_REG(Inst)
Definition: X86InstComments.cpp:172
CASE_VPERMILPI
#define CASE_VPERMILPI(Inst, src)
Definition: X86InstComments.cpp:104
CASE_FMA4_SCALAR_MR
#define CASE_FMA4_SCALAR_MR(Inst)
Definition: X86InstComments.cpp:220
printFMAComments
static bool printFMAComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition: X86InstComments.cpp:274
CASE_SHUF
#define CASE_SHUF(Inst, suf)
Definition: X86InstComments.cpp:86
CASE_FMA4_PACKED_RM
#define CASE_FMA4_PACKED_RM(Inst)
Definition: X86InstComments.cpp:200
CASE_MOVDUP
#define CASE_MOVDUP(Inst, src)
Definition: X86InstComments.cpp:42
CASE_FMA_SCALAR_MEM
#define CASE_FMA_SCALAR_MEM(Inst)
Definition: X86InstComments.cpp:182
CASE_FMA4_SCALAR_RR
#define CASE_FMA4_SCALAR_RR(Inst)
Definition: X86InstComments.cpp:208
getRegOperandNumElts
static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, unsigned OperandIndex)
Definition: X86InstComments.cpp:239
CASE_FMA4_PACKED_MR
#define CASE_FMA4_PACKED_MR(Inst)
Definition: X86InstComments.cpp:204
CASE_AVX512_INS_COMMON
#define CASE_AVX512_INS_COMMON(Inst, Suffix, src)
Definition: X86InstComments.cpp:37
getRegName
static const char * getRegName(MCRegister Reg)
Definition: X86InstComments.cpp:245
CASE_PMOVZX
#define CASE_PMOVZX(Inst, src)
Definition: X86InstComments.cpp:60
CASE_VSHUF
#define CASE_VSHUF(Inst, src)
Definition: X86InstComments.cpp:134
CASE_FMA_PACKED_MEM
#define CASE_FMA_PACKED_MEM(Inst)
Definition: X86InstComments.cpp:166
getVectorRegSize
static unsigned getVectorRegSize(unsigned RegNo)
Definition: X86InstComments.cpp:226
printMasking
static void printMasking(raw_ostream &OS, const MCInst *MI, const MCInstrInfo &MCII)
Wraps the destination register name with AVX512 mask/maskz filtering.
Definition: X86InstComments.cpp:250
CASE_FMA4_SCALAR_RM
#define CASE_FMA4_SCALAR_RM(Inst)
Definition: X86InstComments.cpp:214
CASE_FMA4_PACKED_RR
#define CASE_FMA4_PACKED_RR(Inst)
Definition: X86InstComments.cpp:196
CASE_FMA_PACKED_REG
#define CASE_FMA_PACKED_REG(Inst)
Definition: X86InstComments.cpp:162
CASE_UNPCK
#define CASE_UNPCK(Inst, src)
Definition: X86InstComments.cpp:68
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::SmallVectorBase::empty
bool empty() const
Definition: SmallVector.h:94
llvm::SmallVectorBase::size
size_t size() const
Definition: SmallVector.h:91
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::X86ATTInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg)
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::X86II::isXMMReg
bool isXMMReg(unsigned RegNo)
Definition: X86BaseInfo.h:1159
llvm::X86II::isZMMReg
bool isZMMReg(unsigned RegNo)
Definition: X86BaseInfo.h:1179
llvm::X86II::isYMMReg
bool isYMMReg(unsigned RegNo)
Definition: X86BaseInfo.h:1169
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::DecodeZeroExtendMask
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:370
llvm::EmitAnyX86InstComments
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
Definition: X86InstComments.cpp:628
llvm::DecodeMOVHLPSMask
void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVHLPS instruction as a v2f64/v4f32 shuffle mask.
Definition: X86ShuffleDecode.cpp:60
llvm::DecodeZeroMoveLowMask
void DecodeZeroMoveLowMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decode a move lower and zero upper instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:384
llvm::DecodeInsertElementMask
void DecodeInsertElementMask(unsigned NumElts, unsigned Idx, unsigned Len, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:49
llvm::SM_SentinelUndef
@ SM_SentinelUndef
Definition: X86ShuffleDecode.h:28
llvm::SM_SentinelZero
@ SM_SentinelZero
Definition: X86ShuffleDecode.h:28
llvm::DecodePSHUFLWMask
void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshuflw.
Definition: X86ShuffleDecode.cpp:177
llvm::DecodeBLENDMask
void DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a BLEND immediate mask into a shuffle mask.
Definition: X86ShuffleDecode.cpp:314
llvm::decodeVSHUF64x2FamilyMask
void decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a shuffle packed values at 128-bit granularity (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) immed...
Definition: X86ShuffleDecode.cpp:263
llvm::DecodeVPERMMask
void DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for VPERMQ/VPERMPD.
Definition: X86ShuffleDecode.cpp:363
llvm::DecodeEXTRQIMask
void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A EXTRQ instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:399
llvm::DecodePSRLDQMask
void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:111
llvm::DecodeVPERM2X128Mask
void DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:280
llvm::DecodeMOVLHPSMask
void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVLHPS instruction as a v2f64/v4f32 shuffle mask.
Definition: X86ShuffleDecode.cpp:69
llvm::DecodePSWAPMask
void DecodePSWAPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a PSWAPD 3DNow! instruction.
Definition: X86ShuffleDecode.cpp:191
llvm::DecodeINSERTQIMask
void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A INSERTQ instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:436
llvm::DecodeVALIGNMask
void DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:138
llvm::DecodeScalarMoveMask
void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad, SmallVectorImpl< int > &ShuffleMask)
Decode a scalar float move instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:390
llvm::DecodePALIGNRMask
void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:124
llvm::DecodeMOVSLDUPMask
void DecodeMOVSLDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:77
llvm::DecodeSubVectorBroadcast
void DecodeSubVectorBroadcast(unsigned DstNumElts, unsigned SrcNumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a broadcast of a subvector to a larger vector type.
Definition: X86ShuffleDecode.cpp:254
llvm::DecodeINSERTPSMask
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a 128-bit INSERTPS instruction as a v4f32 shuffle mask.
Definition: X86ShuffleDecode.cpp:26
llvm::DecodeUNPCKLMask
void DecodeUNPCKLMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpcklps/unpcklpd and punpckl*.
Definition: X86ShuffleDecode.cpp:233
llvm::DecodePSLLDQMask
void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:99
llvm::DecodeUNPCKHMask
void DecodeUNPCKHMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpckhps/unpckhpd and punpckh*.
Definition: X86ShuffleDecode.cpp:217
llvm::DecodePSHUFMask
void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufd/pshufw/vpermilpd/vpermilps.
Definition: X86ShuffleDecode.cpp:147
llvm::DecodeMOVDDUPMask
void DecodeMOVDDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:91
llvm::DecodeSHUFPMask
void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for shufp*.
Definition: X86ShuffleDecode.cpp:200
llvm::DecodePSHUFHWMask
void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufhw.
Definition: X86ShuffleDecode.cpp:163
llvm::DecodeMOVSHDUPMask
void DecodeMOVSHDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:84
raw_ostream.h
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
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