26#define CASE_SSE_INS_COMMON(Inst, src) \
29#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
30 case X86::V##Inst##Suffix##src:
32#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
33 case X86::V##Inst##Suffix##src##k:
35#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
36 case X86::V##Inst##Suffix##src##kz:
38#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
39 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
40 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
41 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
43#define CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \
44 case X86::V##Inst##Suffix##src##k_Int:
46#define CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src) \
47 case X86::V##Inst##Suffix##src##kz_Int:
49#define CASE_AVX512_INS_COMMON_INT(Inst, Suffix, src) \
50 CASE_AVX_INS_COMMON(Inst, Suffix, src##_Int) \
51 CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \
52 CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src)
54#define CASE_FPCLASS_PACKED(Inst, src) \
55 CASE_AVX_INS_COMMON(Inst, Z, src##i) \
56 CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
57 CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
58 CASE_MASK_INS_COMMON(Inst, Z, src##i)
60#define CASE_FPCLASS_PACKED_MEM(Inst) \
61 CASE_FPCLASS_PACKED(Inst, m) \
62 CASE_FPCLASS_PACKED(Inst, mb)
64#define CASE_FPCLASS_SCALAR(Inst, src) \
65 CASE_AVX_INS_COMMON(Inst, Z, src##i) \
66 CASE_MASK_INS_COMMON(Inst, Z, src##i)
68#define CASE_PTERNLOG(Inst, src) \
69 CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \
70 CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \
71 CASE_AVX512_INS_COMMON(Inst, Z128, r##src##i)
73#define CASE_MOVDUP(Inst, src) \
74 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
75 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
76 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
77 CASE_AVX_INS_COMMON(Inst, , r##src) \
78 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
79 CASE_SSE_INS_COMMON(Inst, r##src)
81#define CASE_MASK_MOVDUP(Inst, src) \
82 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
83 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
84 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
86#define CASE_MASKZ_MOVDUP(Inst, src) \
87 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
88 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
89 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
91#define CASE_PMOVZX(Inst, src) \
92 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
93 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
94 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
95 CASE_AVX_INS_COMMON(Inst, , r##src) \
96 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
97 CASE_SSE_INS_COMMON(Inst, r##src)
99#define CASE_UNPCK(Inst, src) \
100 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
101 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
102 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
103 CASE_AVX_INS_COMMON(Inst, , r##src) \
104 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
105 CASE_SSE_INS_COMMON(Inst, r##src)
107#define CASE_MASK_UNPCK(Inst, src) \
108 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
109 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
110 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
112#define CASE_MASKZ_UNPCK(Inst, src) \
113 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
114 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
115 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
117#define CASE_SHUF(Inst, suf) \
118 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
119 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
120 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
121 CASE_AVX_INS_COMMON(Inst, , suf) \
122 CASE_AVX_INS_COMMON(Inst, Y, suf) \
123 CASE_SSE_INS_COMMON(Inst, suf)
125#define CASE_MASK_SHUF(Inst, src) \
126 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
127 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
128 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
130#define CASE_MASKZ_SHUF(Inst, src) \
131 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
132 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
133 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
135#define CASE_VPERMILPI(Inst, src) \
136 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
137 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
138 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
139 CASE_AVX_INS_COMMON(Inst, , src##i) \
140 CASE_AVX_INS_COMMON(Inst, Y, src##i)
142#define CASE_MASK_VPERMILPI(Inst, src) \
143 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
144 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
145 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
147#define CASE_MASKZ_VPERMILPI(Inst, src) \
148 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
149 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
150 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
152#define CASE_VPERM(Inst, src) \
153 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
154 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
155 CASE_AVX_INS_COMMON(Inst, Y, src##i)
157#define CASE_MASK_VPERM(Inst, src) \
158 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
159 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
161#define CASE_MASKZ_VPERM(Inst, src) \
162 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
163 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
165#define CASE_VSHUF(Inst, src) \
166 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
167 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
168 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
169 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
171#define CASE_MASK_VSHUF(Inst, src) \
172 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
173 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
174 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
175 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
177#define CASE_MASKZ_VSHUF(Inst, src) \
178 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
179 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
180 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
181 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
183#define CASE_AVX512_FMA(Inst, suf) \
184 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
185 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
186 CASE_AVX512_INS_COMMON(Inst, Z128, suf)
188#define CASE_FMA(Inst, suf) \
189 CASE_AVX512_FMA(Inst, suf) \
190 CASE_AVX_INS_COMMON(Inst, , suf) \
191 CASE_AVX_INS_COMMON(Inst, Y, suf)
193#define CASE_FMA_PACKED_REG(Inst) \
194 CASE_FMA(Inst##PD, r) \
195 CASE_FMA(Inst##PS, r)
197#define CASE_FMA_PACKED_MEM(Inst) \
198 CASE_FMA(Inst##PD, m) \
199 CASE_FMA(Inst##PS, m) \
200 CASE_AVX512_FMA(Inst##PD, mb) \
201 CASE_AVX512_FMA(Inst##PS, mb)
203#define CASE_FMA_SCALAR_REG(Inst) \
204 CASE_AVX_INS_COMMON(Inst##SD, , r) \
205 CASE_AVX_INS_COMMON(Inst##SS, , r) \
206 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \
207 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
208 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
209 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
210 CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, r) \
211 CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, r)
213#define CASE_FMA_SCALAR_MEM(Inst) \
214 CASE_AVX_INS_COMMON(Inst##SD, , m) \
215 CASE_AVX_INS_COMMON(Inst##SS, , m) \
216 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \
217 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
218 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
219 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
220 CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, m) \
221 CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, m)
223#define CASE_FMA4(Inst, suf) \
224 CASE_AVX_INS_COMMON(Inst, 4, suf) \
225 CASE_AVX_INS_COMMON(Inst, 4Y, suf)
227#define CASE_FMA4_PACKED_RR(Inst) \
228 CASE_FMA4(Inst##PD, rr) \
229 CASE_FMA4(Inst##PS, rr)
231#define CASE_FMA4_PACKED_RM(Inst) \
232 CASE_FMA4(Inst##PD, rm) \
233 CASE_FMA4(Inst##PS, rm)
235#define CASE_FMA4_PACKED_MR(Inst) \
236 CASE_FMA4(Inst##PD, mr) \
237 CASE_FMA4(Inst##PS, mr)
239#define CASE_FMA4_SCALAR_RR(Inst) \
240 CASE_AVX_INS_COMMON(Inst##SD4, , rr) \
241 CASE_AVX_INS_COMMON(Inst##SS4, , rr) \
242 CASE_AVX_INS_COMMON(Inst##SD4, , rr_Int) \
243 CASE_AVX_INS_COMMON(Inst##SS4, , rr_Int)
245#define CASE_FMA4_SCALAR_RM(Inst) \
246 CASE_AVX_INS_COMMON(Inst##SD4, , rm) \
247 CASE_AVX_INS_COMMON(Inst##SS4, , rm) \
248 CASE_AVX_INS_COMMON(Inst##SD4, , rm_Int) \
249 CASE_AVX_INS_COMMON(Inst##SS4, , rm_Int)
251#define CASE_FMA4_SCALAR_MR(Inst) \
252 CASE_AVX_INS_COMMON(Inst##SD4, , mr) \
253 CASE_AVX_INS_COMMON(Inst##SS4, , mr) \
254 CASE_AVX_INS_COMMON(Inst##SD4, , mr_Int) \
255 CASE_AVX_INS_COMMON(Inst##SS4, , mr_Int)
264 if (Reg >= X86::MM0 && Reg <= X86::MM7)
271 unsigned OperandIndex) {
272 MCRegister OpReg =
MI->getOperand(OperandIndex).getReg();
290 unsigned MaskOp =
Desc.getNumDefs();
295 const char *MaskRegName =
getRegName(
MI->getOperand(MaskOp).getReg());
298 OS <<
" {%" << MaskRegName <<
"}";
307 const char *Mul1Name =
nullptr, *Mul2Name =
nullptr, *AccName =
nullptr;
308 unsigned NumOperands =
MI->getNumOperands();
309 bool RegForm =
false;
327 switch (
MI->getOpcode()) {
333 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
342 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
348 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
358 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
365 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
375 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
382 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
393 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
400 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
408 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
414 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
422 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
429 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
434 AccName =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
440 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
445 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
451 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
456 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
462 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
467 AccName =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
474 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
479 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
486 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
491 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
498 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
503 AccName =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
510 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
515 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
522 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
527 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
534 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
539 AccName =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
547 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
552 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
560 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
565 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
572 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
576 AccName =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
582 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
586 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
592 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
596 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
602 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
606 AccName =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
612 AccName =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
616 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
622 Mul2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
626 Mul1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
632 const char *DestName =
getRegName(
MI->getOperand(0).getReg());
634 if (!Mul1Name) Mul1Name =
"mem";
635 if (!Mul2Name) Mul2Name =
"mem";
636 if (!AccName) AccName =
"mem";
645 OS <<
'(' << Mul1Name <<
" * " << Mul2Name <<
") " << AccStr <<
' '
679 "a ^ ((a & b) | (b ^ c))",
680 "(a & (b ^ c)) ^ ~(b & c)",
682 "~((a & b) | (b ^ c))",
684 "(a & c) ^ (c | ~b)",
686 "(a & b) ^ (b | ~c)",
694 "~((a & b) | (a ^ c))",
696 "(b & c) ^ (c | ~a)",
698 "(a | b) ^ ((a & b) | ~c)",
700 "(c & (a ^ b)) | ~(a | b)",
710 "(a & b) ^ (a | ~c)",
718 "~(a | c) | (a ^ b)",
719 "(c & ~a) | (a ^ b)",
724 "~((a & c) | (a ^ b))",
728 "(b & c) ^ (b | ~a)",
730 "(a | c) ^ ((a & c) | ~b)",
734 "(b & (a ^ c)) | ~(a | c)",
740 "(a & c) ^ (a | ~b)",
748 "~(a | b) | (a ^ c)",
751 "(b & ~a) | (a ^ c)",
754 "~(b ^ c) ^ (a | (b & c))",
760 "~(a | b) | (b ^ c)",
761 "(a | b) & (c ^ (a & b))",
764 "~(a | b) | (c ^ (a & b))",
766 "~(a | c) | (b ^ (a & c))",
767 "(b & ~a) | (b ^ c)",
770 "(a & (b ^ c)) | ~(b | c)",
775 "(a & ~b) | (b ^ c)",
778 "~(b | c) | (a ^ (b & c))",
779 "(a & ~b) | (a ^ c)",
781 "(a & ~c) | (a ^ b)",
786 "~((a ^ b) | (a ^ c))",
788 "~(a ^ b) & (c | ~a)",
790 "~(a ^ c) & (b | ~a)",
791 "(b | c) & (a ^ b ^ c)",
794 "~(b ^ c) & (b | ~a)",
796 "~((b & c) ^ (a | b))",
798 "~((b & c) ^ (a | c))",
799 "a ^ ((a ^ b) | (a ^ c))",
802 "~(b ^ c) & (a | ~b)",
803 "(a | c) & (a ^ b ^ c)",
805 "(a | b) & (a ^ b ^ c)",
808 "~(a | b) | (a ^ b ^ c)",
809 "~(b ^ c) & (a | b)",
812 "~((a | b) & (b ^ c))",
814 "~((a | c) & (b ^ c))",
815 "(b & c) | (a ^ (b | c))",
818 "~(a ^ c) & (a | ~b)",
820 "~((a & c) ^ (a | b))",
821 "~(a ^ c) & (a | b)",
824 "~((a | b) & (a ^ c))",
830 "(b & c) | ~(a ^ c)",
834 "~((a & c) ^ (b | c))",
835 "a ^ ((a ^ c) & (b ^ c))",
838 "~((b | c) & (a ^ c))",
839 "(a & c) | (a ^ b ^ c)",
842 "(a & c) | ~(b ^ c)",
846 "~((a ^ c) & (b ^ c))",
850 "~(a ^ b) & (a | ~c)",
851 "~(a ^ b) & (a | c)",
854 "~((a & b) ^ (a | c))",
856 "~((a | c) & (a ^ b))",
860 "(b & c) | ~(a ^ b)",
866 "~((a & b) ^ (b | c))",
868 "~((b | c) & (a ^ b))",
869 "a ^ ((a ^ b) & (b ^ c))",
871 "(a & b) | (a ^ b ^ c)",
874 "(a & b) | ~(b ^ c)",
876 "~((a ^ b) & (b ^ c))",
884 "(a & c) | ~(a ^ b)",
886 "(a & b) | ~(a ^ c)",
888 "~((a ^ b) & (a ^ c))",
889 "(a | b) & ((a & b) | c)",
890 "(a & b) | (b ^ c ^ ~a)",
917 unsigned NumOperands =
MI->getNumOperands();
921 switch (
MI->getOpcode()) {
926 Src2Idx = NumOperands - 3;
927 Src3Idx = NumOperands - 2;
936 Src2Idx = NumOperands - 7;
947 Src3Idx != -1 ?
getRegName(
MI->getOperand(Src3Idx).getReg()) :
"mem";
948 uint8_t TruthTable =
MI->getOperand(NumOperands - 1).getImm();
950 StringRef SrcNames[] = {Src1Name, Src2Name, Src3Name};
959 while (!BooleanFunction.empty()) {
962 OS << BooleanFunction.substr(0, SymbolOffset);
963 if (SymbolOffset == std::string_view::npos) {
968 char Symbol = BooleanFunction[SymbolOffset];
969 OS << SrcNames[Symbol -
'a'];
971 BooleanFunction.remove_prefix(SymbolOffset + 1);
979 unsigned NumOperands =
MI->getNumOperands();
981 switch (
MI->getOpcode()) {
989 SrcIdx = NumOperands - 2;
1007 SrcIdx != -1 ?
getRegName(
MI->getOperand(SrcIdx).getReg()) :
"mem";
1013 uint8_t Categories =
MI->getOperand(NumOperands - 1).getImm();
1014 if (Categories == 0) {
1027 bool Conjoin =
false;
1028 for (
size_t I = 0, E = std::size(CategoryNames);
I != E; ++
I) {
1029 if (Categories & (1 <<
I)) {
1033 OS <<
"is" << CategoryNames[
I] <<
'(' << SrcName <<
')';
1052 const char *DestName =
nullptr, *Src1Name =
nullptr, *Src2Name =
nullptr;
1053 unsigned NumOperands =
MI->getNumOperands();
1054 bool RegForm =
false;
1065 switch (
MI->getOpcode()) {
1070 case X86::BLENDPDrri:
1071 case X86::VBLENDPDrri:
1072 case X86::VBLENDPDYrri:
1075 case X86::BLENDPDrmi:
1076 case X86::VBLENDPDrmi:
1077 case X86::VBLENDPDYrmi:
1078 if (
MI->getOperand(NumOperands - 1).isImm())
1080 MI->getOperand(NumOperands - 1).getImm(),
1086 case X86::BLENDPSrri:
1087 case X86::VBLENDPSrri:
1088 case X86::VBLENDPSYrri:
1091 case X86::BLENDPSrmi:
1092 case X86::VBLENDPSrmi:
1093 case X86::VBLENDPSYrmi:
1094 if (
MI->getOperand(NumOperands - 1).isImm())
1096 MI->getOperand(NumOperands - 1).getImm(),
1102 case X86::PBLENDWrri:
1103 case X86::VPBLENDWrri:
1104 case X86::VPBLENDWYrri:
1107 case X86::PBLENDWrmi:
1108 case X86::VPBLENDWrmi:
1109 case X86::VPBLENDWYrmi:
1110 if (
MI->getOperand(NumOperands - 1).isImm())
1112 MI->getOperand(NumOperands - 1).getImm(),
1118 case X86::VPBLENDDrri:
1119 case X86::VPBLENDDYrri:
1122 case X86::VPBLENDDrmi:
1123 case X86::VPBLENDDYrmi:
1124 if (
MI->getOperand(NumOperands - 1).isImm())
1126 MI->getOperand(NumOperands - 1).getImm(),
1132 case X86::INSERTPSrri:
1133 case X86::VINSERTPSrri:
1134 case X86::VINSERTPSZrri:
1138 if (
MI->getOperand(NumOperands - 1).isImm())
1143 case X86::INSERTPSrmi:
1144 case X86::VINSERTPSrmi:
1145 case X86::VINSERTPSZrmi:
1148 if (
MI->getOperand(NumOperands - 1).isImm())
1153 case X86::MOVLHPSrr:
1154 case X86::VMOVLHPSrr:
1155 case X86::VMOVLHPSZrr:
1162 case X86::MOVHLPSrr:
1163 case X86::VMOVHLPSrr:
1164 case X86::VMOVHLPSZrr:
1172 case X86::VMOVHPDrm:
1173 case X86::VMOVHPDZ128rm:
1180 case X86::VMOVHPSrm:
1181 case X86::VMOVHPSZ128rm:
1188 case X86::VMOVLPDrm:
1189 case X86::VMOVLPDZ128rm:
1196 case X86::VMOVLPSrm:
1197 case X86::VMOVLPSZ128rm:
1204 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1213 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1222 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1231 case X86::VPSLLDQri:
1232 case X86::VPSLLDQYri:
1233 case X86::VPSLLDQZ128ri:
1234 case X86::VPSLLDQZ256ri:
1235 case X86::VPSLLDQZri:
1238 case X86::VPSLLDQZ128mi:
1239 case X86::VPSLLDQZ256mi:
1240 case X86::VPSLLDQZmi:
1242 if (
MI->getOperand(NumOperands - 1).isImm())
1244 MI->getOperand(NumOperands - 1).getImm(),
1249 case X86::VPSRLDQri:
1250 case X86::VPSRLDQYri:
1251 case X86::VPSRLDQZ128ri:
1252 case X86::VPSRLDQZ256ri:
1253 case X86::VPSRLDQZri:
1256 case X86::VPSRLDQZ128mi:
1257 case X86::VPSRLDQZ256mi:
1258 case X86::VPSRLDQZmi:
1260 if (
MI->getOperand(NumOperands - 1).isImm())
1262 MI->getOperand(NumOperands - 1).getImm(),
1267 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1272 Src2Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1274 if (
MI->getOperand(NumOperands - 1).isImm())
1276 MI->getOperand(NumOperands - 1).getImm(),
1283 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1290 Src2Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1292 if (
MI->getOperand(NumOperands - 1).isImm())
1294 MI->getOperand(NumOperands - 1).getImm(),
1301 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1308 Src2Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1310 if (
MI->getOperand(NumOperands - 1).isImm())
1312 MI->getOperand(NumOperands - 1).getImm(),
1317 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1322 if (
MI->getOperand(NumOperands - 1).isImm())
1324 MI->getOperand(NumOperands - 1).getImm(),
1329 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1334 if (
MI->getOperand(NumOperands - 1).isImm())
1336 MI->getOperand(NumOperands - 1).getImm(),
1341 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1346 if (
MI->getOperand(NumOperands - 1).isImm())
1348 MI->getOperand(NumOperands - 1).getImm(),
1352 case X86::MMX_PSHUFWri:
1356 case X86::MMX_PSHUFWmi:
1358 if (
MI->getOperand(NumOperands - 1).isImm())
1373 case X86::MMX_PUNPCKHBWrr:
1374 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1379 case X86::MMX_PUNPCKHBWrm:
1380 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1386 case X86::MMX_PUNPCKHWDrr:
1387 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1392 case X86::MMX_PUNPCKHWDrm:
1393 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1399 case X86::MMX_PUNPCKHDQrr:
1400 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1405 case X86::MMX_PUNPCKHDQrm:
1406 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1412 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1417 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1423 case X86::MMX_PUNPCKLBWrr:
1424 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1429 case X86::MMX_PUNPCKLBWrm:
1430 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1436 case X86::MMX_PUNPCKLWDrr:
1437 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1442 case X86::MMX_PUNPCKLWDrm:
1443 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1449 case X86::MMX_PUNPCKLDQrr:
1450 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1455 case X86::MMX_PUNPCKLDQrm:
1456 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1462 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1467 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1473 Src2Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1478 if (
MI->getOperand(NumOperands - 1).isImm())
1480 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
1481 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1486 Src2Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1491 if (
MI->getOperand(NumOperands - 1).isImm())
1493 MI->getOperand(NumOperands - 1).getImm(),
1495 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1500 Src2Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1506 MI->getOperand(NumOperands - 1).getImm(),
1508 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1513 Src2Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1519 MI->getOperand(NumOperands - 1).getImm(),
1521 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1526 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1532 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1537 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1543 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1548 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1554 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1559 Src2Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1565 Src1Name =
getRegName(
MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1570 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1574 if (
MI->getOperand(NumOperands - 1).isImm())
1576 MI->getOperand(NumOperands - 1).getImm(),
1582 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1586 if (
MI->getOperand(NumOperands - 1).isImm())
1588 MI->getOperand(NumOperands - 1).getImm(),
1593 case X86::VPERM2F128rri:
1594 case X86::VPERM2I128rri:
1598 case X86::VPERM2F128rmi:
1599 case X86::VPERM2I128rmi:
1601 if (
MI->getOperand(NumOperands - 1).isImm())
1609 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1613 if (
MI->getOperand(NumOperands - 1).isImm())
1615 MI->getOperand(NumOperands - 1).getImm(),
1621 Src1Name =
getRegName(
MI->getOperand(NumOperands - 2).getReg());
1625 if (
MI->getOperand(NumOperands - 1).isImm())
1627 MI->getOperand(NumOperands - 1).getImm(),
1634 case X86::VMOVSDZrr:
1643 case X86::VMOVSSZrr:
1650 case X86::MOVPQI2QIrr:
1651 case X86::MOVZPQILo2PQIrr:
1652 case X86::VMOVPQI2QIrr:
1653 case X86::VMOVPQI2QIZrr:
1654 case X86::VMOVZPQILo2PQIrr:
1655 case X86::VMOVZPQILo2PQIZrr:
1662 if (
MI->getOperand(2).isImm() &&
1663 MI->getOperand(3).isImm())
1665 MI->getOperand(3).getImm(), ShuffleMask);
1672 if (
MI->getOperand(3).isImm() &&
1673 MI->getOperand(4).isImm())
1675 MI->getOperand(4).getImm(), ShuffleMask);
1682 case X86::VBROADCASTF128rm:
1683 case X86::VBROADCASTI128rm:
1715 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1723 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1732 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1741 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1748 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1755 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1762 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1769 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1776 Src1Name =
getRegName(
MI->getOperand(NumOperands - 1).getReg());
1785 if (ShuffleMask.
empty())
1788 if (!DestName) DestName = Src1Name;
1799 if (Src1Name == Src2Name) {
1800 for (
unsigned i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1801 if ((
int)ShuffleMask[i] >= 0 &&
1802 ShuffleMask[i] >= (
int)e)
1803 ShuffleMask[i] -= e;
1810 for (
unsigned i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1820 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.
size();
1821 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1822 OS << (SrcName ? SrcName :
"mem") <<
'[';
1823 bool IsFirst =
true;
1825 (ShuffleMask[i] < (int)ShuffleMask.
size()) == isSrc1) {
1833 OS << ShuffleMask[i] % ShuffleMask.
size();
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Wrapper class representing physical registers. Should be passed by value.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
static const char * getRegisterName(MCRegister Reg)
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isZMMReg(MCRegister Reg)
bool isXMMReg(MCRegister Reg)
bool isYMMReg(MCRegister Reg)
This is an optimization pass for GlobalISel generic memory operations.
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVHLPS instruction as a v2f64/v4f32 shuffle mask.
void DecodeZeroMoveLowMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decode a move lower and zero upper instruction as a shuffle mask.
void DecodeInsertElementMask(unsigned NumElts, unsigned Idx, unsigned Len, SmallVectorImpl< int > &ShuffleMask)
void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshuflw.
void DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a BLEND immediate mask into a shuffle mask.
void decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a shuffle packed values at 128-bit granularity (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) immed...
void DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for VPERMQ/VPERMPD.
void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A EXTRQ instruction as a shuffle mask.
void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl< int > &ShuffleMask, bool SrcIsMem)
Decode a 128-bit INSERTPS instruction as a v4f32 shuffle mask.
void DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVLHPS instruction as a v2f64/v4f32 shuffle mask.
void DecodePSWAPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a PSWAPD 3DNow! instruction.
void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A INSERTQ instruction as a shuffle mask.
void DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad, SmallVectorImpl< int > &ShuffleMask)
Decode a scalar float move instruction as a shuffle mask.
void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
void DecodeMOVSLDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
void DecodeSubVectorBroadcast(unsigned DstNumElts, unsigned SrcNumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a broadcast of a subvector to a larger vector type.
void DecodeUNPCKLMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpcklps/unpcklpd and punpckl*.
void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
void DecodeUNPCKHMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpckhps/unpckhpd and punpckh*.
void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufd/pshufw/vpermilpd/vpermilps.
void DecodeMOVDDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for shufp*.
void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufhw.
void DecodeMOVSHDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Description of the encoding of one expression Op.