LLVM 20.0.0git
X86InstComments.cpp
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1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This defines functionality used to emit comments about X86 instructions to
10// an output stream for -fverbose-asm.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstComments.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86MCTargetDesc.h"
18#include "X86ShuffleDecode.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/Support/raw_ostream.h"
22#include <string_view>
23
24using namespace llvm;
25
26#define CASE_SSE_INS_COMMON(Inst, src) \
27 case X86::Inst##src:
28
29#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
30 case X86::V##Inst##Suffix##src:
31
32#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
33 case X86::V##Inst##Suffix##src##k:
34
35#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
36 case X86::V##Inst##Suffix##src##kz:
37
38#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
39 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
40 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
41 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
42
43#define CASE_FPCLASS_PACKED(Inst, src) \
44 CASE_AVX_INS_COMMON(Inst, Z, src##i) \
45 CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
46 CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
47 CASE_MASK_INS_COMMON(Inst, Z, src##i)
48
49#define CASE_FPCLASS_PACKED_MEM(Inst) \
50 CASE_FPCLASS_PACKED(Inst, m) \
51 CASE_FPCLASS_PACKED(Inst, mb)
52
53#define CASE_FPCLASS_SCALAR(Inst, src) \
54 CASE_AVX_INS_COMMON(Inst, Z, src##i) \
55 CASE_MASK_INS_COMMON(Inst, Z, src##i)
56
57#define CASE_PTERNLOG(Inst, src) \
58 CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \
59 CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \
60 CASE_AVX512_INS_COMMON(Inst, Z128, r##src##i)
61
62#define CASE_MOVDUP(Inst, src) \
63 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
64 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
65 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
66 CASE_AVX_INS_COMMON(Inst, , r##src) \
67 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
68 CASE_SSE_INS_COMMON(Inst, r##src)
69
70#define CASE_MASK_MOVDUP(Inst, src) \
71 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
72 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
73 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
74
75#define CASE_MASKZ_MOVDUP(Inst, src) \
76 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
77 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
78 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
79
80#define CASE_PMOVZX(Inst, src) \
81 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
82 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
83 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
84 CASE_AVX_INS_COMMON(Inst, , r##src) \
85 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
86 CASE_SSE_INS_COMMON(Inst, r##src)
87
88#define CASE_UNPCK(Inst, src) \
89 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
90 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
91 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
92 CASE_AVX_INS_COMMON(Inst, , r##src) \
93 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
94 CASE_SSE_INS_COMMON(Inst, r##src)
95
96#define CASE_MASK_UNPCK(Inst, src) \
97 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
98 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
99 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
100
101#define CASE_MASKZ_UNPCK(Inst, src) \
102 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
103 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
104 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
105
106#define CASE_SHUF(Inst, suf) \
107 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
108 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
109 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
110 CASE_AVX_INS_COMMON(Inst, , suf) \
111 CASE_AVX_INS_COMMON(Inst, Y, suf) \
112 CASE_SSE_INS_COMMON(Inst, suf)
113
114#define CASE_MASK_SHUF(Inst, src) \
115 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
116 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
117 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
118
119#define CASE_MASKZ_SHUF(Inst, src) \
120 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
121 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
122 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
123
124#define CASE_VPERMILPI(Inst, src) \
125 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
126 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
127 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
128 CASE_AVX_INS_COMMON(Inst, , src##i) \
129 CASE_AVX_INS_COMMON(Inst, Y, src##i)
130
131#define CASE_MASK_VPERMILPI(Inst, src) \
132 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
133 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
134 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
135
136#define CASE_MASKZ_VPERMILPI(Inst, src) \
137 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
138 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
139 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
140
141#define CASE_VPERM(Inst, src) \
142 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
143 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
144 CASE_AVX_INS_COMMON(Inst, Y, src##i)
145
146#define CASE_MASK_VPERM(Inst, src) \
147 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
148 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
149
150#define CASE_MASKZ_VPERM(Inst, src) \
151 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
152 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
153
154#define CASE_VSHUF(Inst, src) \
155 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
156 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
157 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
158 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
159
160#define CASE_MASK_VSHUF(Inst, src) \
161 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
162 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
163 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
164 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
165
166#define CASE_MASKZ_VSHUF(Inst, src) \
167 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
168 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
169 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
170 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
171
172#define CASE_AVX512_FMA(Inst, suf) \
173 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
174 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
175 CASE_AVX512_INS_COMMON(Inst, Z128, suf)
176
177#define CASE_FMA(Inst, suf) \
178 CASE_AVX512_FMA(Inst, suf) \
179 CASE_AVX_INS_COMMON(Inst, , suf) \
180 CASE_AVX_INS_COMMON(Inst, Y, suf)
181
182#define CASE_FMA_PACKED_REG(Inst) \
183 CASE_FMA(Inst##PD, r) \
184 CASE_FMA(Inst##PS, r)
185
186#define CASE_FMA_PACKED_MEM(Inst) \
187 CASE_FMA(Inst##PD, m) \
188 CASE_FMA(Inst##PS, m) \
189 CASE_AVX512_FMA(Inst##PD, mb) \
190 CASE_AVX512_FMA(Inst##PS, mb)
191
192#define CASE_FMA_SCALAR_REG(Inst) \
193 CASE_AVX_INS_COMMON(Inst##SD, , r) \
194 CASE_AVX_INS_COMMON(Inst##SS, , r) \
195 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \
196 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
197 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
198 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
199 CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int) \
200 CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int)
201
202#define CASE_FMA_SCALAR_MEM(Inst) \
203 CASE_AVX_INS_COMMON(Inst##SD, , m) \
204 CASE_AVX_INS_COMMON(Inst##SS, , m) \
205 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \
206 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
207 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
208 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
209 CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int) \
210 CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int)
211
212#define CASE_FMA4(Inst, suf) \
213 CASE_AVX_INS_COMMON(Inst, 4, suf) \
214 CASE_AVX_INS_COMMON(Inst, 4Y, suf)
215
216#define CASE_FMA4_PACKED_RR(Inst) \
217 CASE_FMA4(Inst##PD, rr) \
218 CASE_FMA4(Inst##PS, rr)
219
220#define CASE_FMA4_PACKED_RM(Inst) \
221 CASE_FMA4(Inst##PD, rm) \
222 CASE_FMA4(Inst##PS, rm)
223
224#define CASE_FMA4_PACKED_MR(Inst) \
225 CASE_FMA4(Inst##PD, mr) \
226 CASE_FMA4(Inst##PS, mr)
227
228#define CASE_FMA4_SCALAR_RR(Inst) \
229 CASE_AVX_INS_COMMON(Inst##SD4, , rr) \
230 CASE_AVX_INS_COMMON(Inst##SS4, , rr) \
231 CASE_AVX_INS_COMMON(Inst##SD4, , rr_Int) \
232 CASE_AVX_INS_COMMON(Inst##SS4, , rr_Int)
233
234#define CASE_FMA4_SCALAR_RM(Inst) \
235 CASE_AVX_INS_COMMON(Inst##SD4, , rm) \
236 CASE_AVX_INS_COMMON(Inst##SS4, , rm) \
237 CASE_AVX_INS_COMMON(Inst##SD4, , rm_Int) \
238 CASE_AVX_INS_COMMON(Inst##SS4, , rm_Int)
239
240#define CASE_FMA4_SCALAR_MR(Inst) \
241 CASE_AVX_INS_COMMON(Inst##SD4, , mr) \
242 CASE_AVX_INS_COMMON(Inst##SS4, , mr) \
243 CASE_AVX_INS_COMMON(Inst##SD4, , mr_Int) \
244 CASE_AVX_INS_COMMON(Inst##SS4, , mr_Int)
245
246static unsigned getVectorRegSize(MCRegister Reg) {
247 if (X86II::isZMMReg(Reg))
248 return 512;
249 if (X86II::isYMMReg(Reg))
250 return 256;
251 if (X86II::isXMMReg(Reg))
252 return 128;
253 if (Reg >= X86::MM0 && Reg <= X86::MM7)
254 return 64;
255
256 llvm_unreachable("Unknown vector reg!");
257}
258
259static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
260 unsigned OperandIndex) {
261 MCRegister OpReg = MI->getOperand(OperandIndex).getReg();
262 return getVectorRegSize(OpReg) / ScalarSize;
263}
264
265static const char *getRegName(MCRegister Reg) {
266 return X86ATTInstPrinter::getRegisterName(Reg);
267}
268
269/// Wraps the destination register name with AVX512 mask/maskz filtering.
270static void printMasking(raw_ostream &OS, const MCInst *MI,
271 const MCInstrInfo &MCII) {
272 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
273 uint64_t TSFlags = Desc.TSFlags;
274
275 if (!(TSFlags & X86II::EVEX_K))
276 return;
277
278 bool MaskWithZero = (TSFlags & X86II::EVEX_Z);
279 unsigned MaskOp = Desc.getNumDefs();
280
281 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
282 ++MaskOp;
283
284 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
285
286 // MASK: zmmX {%kY}
287 OS << " {%" << MaskRegName << "}";
288
289 // MASKZ: zmmX {%kY} {z}
290 if (MaskWithZero)
291 OS << " {z}";
292}
293
294static bool printFMAComments(const MCInst *MI, raw_ostream &OS,
295 const MCInstrInfo &MCII) {
296 const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr;
297 unsigned NumOperands = MI->getNumOperands();
298 bool RegForm = false;
299 bool Negate = false;
300 StringRef AccStr = "+";
301
302 // The operands for FMA3 instructions without rounding fall into two forms:
303 // dest, src1, src2, src3
304 // dest, src1, mask, src2, src3
305 // Where src3 is either a register or 5 memory address operands. So to find
306 // dest and src1 we can index from the front. To find src2 and src3 we can
307 // index from the end by taking into account memory vs register form when
308 // finding src2.
309
310 // The operands for FMA4 instructions:
311 // dest, src1, src2, src3
312 // Where src2 OR src3 are either a register or 5 memory address operands. So
313 // to find dest and src1 we can index from the front, src2 (reg/mem) follows
314 // and then src3 (reg) will be at the end.
315
316 switch (MI->getOpcode()) {
317 default:
318 return false;
319
320 CASE_FMA4_PACKED_RR(FMADD)
321 CASE_FMA4_SCALAR_RR(FMADD)
322 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
323 [[fallthrough]];
324 CASE_FMA4_PACKED_RM(FMADD)
325 CASE_FMA4_SCALAR_RM(FMADD)
326 Mul2Name = getRegName(MI->getOperand(2).getReg());
327 Mul1Name = getRegName(MI->getOperand(1).getReg());
328 break;
329 CASE_FMA4_PACKED_MR(FMADD)
330 CASE_FMA4_SCALAR_MR(FMADD)
331 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
332 Mul1Name = getRegName(MI->getOperand(1).getReg());
333 break;
334
335 CASE_FMA4_PACKED_RR(FMSUB)
336 CASE_FMA4_SCALAR_RR(FMSUB)
337 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
338 [[fallthrough]];
339 CASE_FMA4_PACKED_RM(FMSUB)
340 CASE_FMA4_SCALAR_RM(FMSUB)
341 Mul2Name = getRegName(MI->getOperand(2).getReg());
342 Mul1Name = getRegName(MI->getOperand(1).getReg());
343 AccStr = "-";
344 break;
345 CASE_FMA4_PACKED_MR(FMSUB)
346 CASE_FMA4_SCALAR_MR(FMSUB)
347 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
348 Mul1Name = getRegName(MI->getOperand(1).getReg());
349 AccStr = "-";
350 break;
351
352 CASE_FMA4_PACKED_RR(FNMADD)
353 CASE_FMA4_SCALAR_RR(FNMADD)
354 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
355 [[fallthrough]];
356 CASE_FMA4_PACKED_RM(FNMADD)
357 CASE_FMA4_SCALAR_RM(FNMADD)
358 Mul2Name = getRegName(MI->getOperand(2).getReg());
359 Mul1Name = getRegName(MI->getOperand(1).getReg());
360 Negate = true;
361 break;
362 CASE_FMA4_PACKED_MR(FNMADD)
363 CASE_FMA4_SCALAR_MR(FNMADD)
364 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
365 Mul1Name = getRegName(MI->getOperand(1).getReg());
366 Negate = true;
367 break;
368
369 CASE_FMA4_PACKED_RR(FNMSUB)
370 CASE_FMA4_SCALAR_RR(FNMSUB)
371 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
372 [[fallthrough]];
373 CASE_FMA4_PACKED_RM(FNMSUB)
374 CASE_FMA4_SCALAR_RM(FNMSUB)
375 Mul2Name = getRegName(MI->getOperand(2).getReg());
376 Mul1Name = getRegName(MI->getOperand(1).getReg());
377 AccStr = "-";
378 Negate = true;
379 break;
380 CASE_FMA4_PACKED_MR(FNMSUB)
381 CASE_FMA4_SCALAR_MR(FNMSUB)
382 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
383 Mul1Name = getRegName(MI->getOperand(1).getReg());
384 AccStr = "-";
385 Negate = true;
386 break;
387
388 CASE_FMA4_PACKED_RR(FMADDSUB)
389 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
390 [[fallthrough]];
391 CASE_FMA4_PACKED_RM(FMADDSUB)
392 Mul2Name = getRegName(MI->getOperand(2).getReg());
393 Mul1Name = getRegName(MI->getOperand(1).getReg());
394 AccStr = "+/-";
395 break;
396 CASE_FMA4_PACKED_MR(FMADDSUB)
397 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
398 Mul1Name = getRegName(MI->getOperand(1).getReg());
399 AccStr = "+/-";
400 break;
401
402 CASE_FMA4_PACKED_RR(FMSUBADD)
403 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
404 [[fallthrough]];
405 CASE_FMA4_PACKED_RM(FMSUBADD)
406 Mul2Name = getRegName(MI->getOperand(2).getReg());
407 Mul1Name = getRegName(MI->getOperand(1).getReg());
408 AccStr = "-/+";
409 break;
410 CASE_FMA4_PACKED_MR(FMSUBADD)
411 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
412 Mul1Name = getRegName(MI->getOperand(1).getReg());
413 AccStr = "-/+";
414 break;
415
416 CASE_FMA_PACKED_REG(FMADD132)
417 CASE_FMA_SCALAR_REG(FMADD132)
418 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
419 RegForm = true;
420 [[fallthrough]];
421 CASE_FMA_PACKED_MEM(FMADD132)
422 CASE_FMA_SCALAR_MEM(FMADD132)
423 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
424 Mul1Name = getRegName(MI->getOperand(1).getReg());
425 break;
426
427 CASE_FMA_PACKED_REG(FMADD213)
428 CASE_FMA_SCALAR_REG(FMADD213)
429 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
430 RegForm = true;
431 [[fallthrough]];
432 CASE_FMA_PACKED_MEM(FMADD213)
433 CASE_FMA_SCALAR_MEM(FMADD213)
434 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
435 Mul2Name = getRegName(MI->getOperand(1).getReg());
436 break;
437
438 CASE_FMA_PACKED_REG(FMADD231)
439 CASE_FMA_SCALAR_REG(FMADD231)
440 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
441 RegForm = true;
442 [[fallthrough]];
443 CASE_FMA_PACKED_MEM(FMADD231)
444 CASE_FMA_SCALAR_MEM(FMADD231)
445 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
446 AccName = getRegName(MI->getOperand(1).getReg());
447 break;
448
449 CASE_FMA_PACKED_REG(FMSUB132)
450 CASE_FMA_SCALAR_REG(FMSUB132)
451 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
452 RegForm = true;
453 [[fallthrough]];
454 CASE_FMA_PACKED_MEM(FMSUB132)
455 CASE_FMA_SCALAR_MEM(FMSUB132)
456 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
457 Mul1Name = getRegName(MI->getOperand(1).getReg());
458 AccStr = "-";
459 break;
460
461 CASE_FMA_PACKED_REG(FMSUB213)
462 CASE_FMA_SCALAR_REG(FMSUB213)
463 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
464 RegForm = true;
465 [[fallthrough]];
466 CASE_FMA_PACKED_MEM(FMSUB213)
467 CASE_FMA_SCALAR_MEM(FMSUB213)
468 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
469 Mul2Name = getRegName(MI->getOperand(1).getReg());
470 AccStr = "-";
471 break;
472
473 CASE_FMA_PACKED_REG(FMSUB231)
474 CASE_FMA_SCALAR_REG(FMSUB231)
475 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
476 RegForm = true;
477 [[fallthrough]];
478 CASE_FMA_PACKED_MEM(FMSUB231)
479 CASE_FMA_SCALAR_MEM(FMSUB231)
480 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
481 AccName = getRegName(MI->getOperand(1).getReg());
482 AccStr = "-";
483 break;
484
485 CASE_FMA_PACKED_REG(FNMADD132)
486 CASE_FMA_SCALAR_REG(FNMADD132)
487 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
488 RegForm = true;
489 [[fallthrough]];
490 CASE_FMA_PACKED_MEM(FNMADD132)
491 CASE_FMA_SCALAR_MEM(FNMADD132)
492 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
493 Mul1Name = getRegName(MI->getOperand(1).getReg());
494 Negate = true;
495 break;
496
497 CASE_FMA_PACKED_REG(FNMADD213)
498 CASE_FMA_SCALAR_REG(FNMADD213)
499 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
500 RegForm = true;
501 [[fallthrough]];
502 CASE_FMA_PACKED_MEM(FNMADD213)
503 CASE_FMA_SCALAR_MEM(FNMADD213)
504 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
505 Mul2Name = getRegName(MI->getOperand(1).getReg());
506 Negate = true;
507 break;
508
509 CASE_FMA_PACKED_REG(FNMADD231)
510 CASE_FMA_SCALAR_REG(FNMADD231)
511 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
512 RegForm = true;
513 [[fallthrough]];
514 CASE_FMA_PACKED_MEM(FNMADD231)
515 CASE_FMA_SCALAR_MEM(FNMADD231)
516 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
517 AccName = getRegName(MI->getOperand(1).getReg());
518 Negate = true;
519 break;
520
521 CASE_FMA_PACKED_REG(FNMSUB132)
522 CASE_FMA_SCALAR_REG(FNMSUB132)
523 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
524 RegForm = true;
525 [[fallthrough]];
526 CASE_FMA_PACKED_MEM(FNMSUB132)
527 CASE_FMA_SCALAR_MEM(FNMSUB132)
528 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
529 Mul1Name = getRegName(MI->getOperand(1).getReg());
530 AccStr = "-";
531 Negate = true;
532 break;
533
534 CASE_FMA_PACKED_REG(FNMSUB213)
535 CASE_FMA_SCALAR_REG(FNMSUB213)
536 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
537 RegForm = true;
538 [[fallthrough]];
539 CASE_FMA_PACKED_MEM(FNMSUB213)
540 CASE_FMA_SCALAR_MEM(FNMSUB213)
541 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
542 Mul2Name = getRegName(MI->getOperand(1).getReg());
543 AccStr = "-";
544 Negate = true;
545 break;
546
547 CASE_FMA_PACKED_REG(FNMSUB231)
548 CASE_FMA_SCALAR_REG(FNMSUB231)
549 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
550 RegForm = true;
551 [[fallthrough]];
552 CASE_FMA_PACKED_MEM(FNMSUB231)
553 CASE_FMA_SCALAR_MEM(FNMSUB231)
554 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
555 AccName = getRegName(MI->getOperand(1).getReg());
556 AccStr = "-";
557 Negate = true;
558 break;
559
560 CASE_FMA_PACKED_REG(FMADDSUB132)
561 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
562 RegForm = true;
563 [[fallthrough]];
564 CASE_FMA_PACKED_MEM(FMADDSUB132)
565 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
566 Mul1Name = getRegName(MI->getOperand(1).getReg());
567 AccStr = "+/-";
568 break;
569
570 CASE_FMA_PACKED_REG(FMADDSUB213)
571 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
572 RegForm = true;
573 [[fallthrough]];
574 CASE_FMA_PACKED_MEM(FMADDSUB213)
575 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
576 Mul2Name = getRegName(MI->getOperand(1).getReg());
577 AccStr = "+/-";
578 break;
579
580 CASE_FMA_PACKED_REG(FMADDSUB231)
581 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
582 RegForm = true;
583 [[fallthrough]];
584 CASE_FMA_PACKED_MEM(FMADDSUB231)
585 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
586 AccName = getRegName(MI->getOperand(1).getReg());
587 AccStr = "+/-";
588 break;
589
590 CASE_FMA_PACKED_REG(FMSUBADD132)
591 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
592 RegForm = true;
593 [[fallthrough]];
594 CASE_FMA_PACKED_MEM(FMSUBADD132)
595 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
596 Mul1Name = getRegName(MI->getOperand(1).getReg());
597 AccStr = "-/+";
598 break;
599
600 CASE_FMA_PACKED_REG(FMSUBADD213)
601 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
602 RegForm = true;
603 [[fallthrough]];
604 CASE_FMA_PACKED_MEM(FMSUBADD213)
605 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
606 Mul2Name = getRegName(MI->getOperand(1).getReg());
607 AccStr = "-/+";
608 break;
609
610 CASE_FMA_PACKED_REG(FMSUBADD231)
611 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
612 RegForm = true;
613 [[fallthrough]];
614 CASE_FMA_PACKED_MEM(FMSUBADD231)
615 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
616 AccName = getRegName(MI->getOperand(1).getReg());
617 AccStr = "-/+";
618 break;
619 }
620
621 const char *DestName = getRegName(MI->getOperand(0).getReg());
622
623 if (!Mul1Name) Mul1Name = "mem";
624 if (!Mul2Name) Mul2Name = "mem";
625 if (!AccName) AccName = "mem";
626
627 OS << DestName;
628 printMasking(OS, MI, MCII);
629 OS << " = ";
630
631 if (Negate)
632 OS << '-';
633
634 OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' '
635 << AccName << '\n';
636
637 return true;
638}
639
640// This table is indexed by the imm8 binary function specified in a
641// vpternlog{d,q} instruction. The symbols {a,b,c} correspond to the three
642// inputs to the binary function. This table was taken from
643// https://gist.github.com/dougallj/81a80cd381988466c4e1c4889ecac95b#file-2-x86-base-txt
644// with slight massaging.
645constexpr StringLiteral TernlogFunctions[] = {
646 "0",
647 "~(a | b | c)",
648 "c & ~(a | b)",
649 "~(a | b)",
650 "b & ~(a | c)",
651 "~(a | c)",
652 "~a & (b ^ c)",
653 "~(a | (b & c))",
654 "b & c & ~a",
655 "~(a | (b ^ c))",
656 "c & ~a",
657 "~a & (c | ~b)",
658 "b & ~a",
659 "~a & (b | ~c)",
660 "~a & (b | c)",
661 "~a",
662 "a & ~(b | c)",
663 "~(b | c)",
664 "~b & (a ^ c)",
665 "~((a & c) | b)",
666 "~c & (a ^ b)",
667 "~((a & b) | c)",
668 "a ^ ((a & b) | (b ^ c))",
669 "(a & (b ^ c)) ^ ~(b & c)",
670 "(a ^ b) & (a ^ c)",
671 "~((a & b) | (b ^ c))",
672 "a ^ ((a & b) | c)",
673 "(a & c) ^ (c | ~b)",
674 "a ^ ((a & c) | b)",
675 "(a & b) ^ (b | ~c)",
676 "a ^ (b | c)",
677 "~(a & (b | c))",
678 "a & c & ~b",
679 "~(b | (a ^ c))",
680 "c & ~b",
681 "~b & (c | ~a)",
682 "(a ^ b) & (b ^ c)",
683 "~((a & b) | (a ^ c))",
684 "b ^ ((a & b) | c)",
685 "(b & c) ^ (c | ~a)",
686 "c & (a ^ b)",
687 "(a | b) ^ ((a & b) | ~c)",
688 "c & ~(a & b)",
689 "(c & (a ^ b)) | ~(a | b)",
690 "(b | c) & (a ^ b)",
691 "a ^ (b | ~c)",
692 "(a & b) ^ (b | c)",
693 "(c & ~b) | ~a",
694 "a & ~b",
695 "~b & (a | ~c)",
696 "~b & (a | c)",
697 "~b",
698 "b ^ (a | (b & c))",
699 "(a & b) ^ (a | ~c)",
700 "b ^ (a | c)",
701 "~(b & (a | c))",
702 "(a | c) & (a ^ b)",
703 "b ^ (a | ~c)",
704 "(a & b) ^ (a | c)",
705 "(c & ~a) | ~b",
706 "a ^ b",
707 "~(a | c) | (a ^ b)",
708 "(c & ~a) | (a ^ b)",
709 "~(a & b)",
710 "a & b & ~c",
711 "~(c | (a ^ b))",
712 "(a ^ c) & (b ^ c)",
713 "~((a & c) | (a ^ b))",
714 "b & ~c",
715 "~c & (b | ~a)",
716 "c ^ ((a & c) | b)",
717 "(b & c) ^ (b | ~a)",
718 "b & (a ^ c)",
719 "(a | c) ^ ((a & c) | ~b)",
720 "(b | c) & (a ^ c)",
721 "a ^ (c | ~b)",
722 "b & ~(a & c)",
723 "(b & (a ^ c)) | ~(a | c)",
724 "(a & c) ^ (b | c)",
725 "(b & ~c) | ~a",
726 "a & ~c",
727 "~c & (a | ~b)",
728 "c ^ (a | (b & c))",
729 "(a & c) ^ (a | ~b)",
730 "~c & (a | b)",
731 "~c",
732 "c ^ (a | b)",
733 "~(c & (a | b))",
734 "(a | b) & (a ^ c)",
735 "c ^ (a | ~b)",
736 "a ^ c",
737 "~(a | b) | (a ^ c)",
738 "(a & c) ^ (a | b)",
739 "(b & ~a) | ~c",
740 "(b & ~a) | (a ^ c)",
741 "~(a & c)",
742 "a & (b ^ c)",
743 "~(b ^ c) ^ (a | (b & c))",
744 "(a | c) & (b ^ c)",
745 "b ^ (c | ~a)",
746 "(a | b) & (b ^ c)",
747 "c ^ (b | ~a)",
748 "b ^ c",
749 "~(a | b) | (b ^ c)",
750 "(a | b) & (c ^ (a & b))",
751 "b ^ c ^ ~a",
752 "c ^ (a & b)",
753 "~(a | b) | (c ^ (a & b))",
754 "b ^ (a & c)",
755 "~(a | c) | (b ^ (a & c))",
756 "(b & ~a) | (b ^ c)",
757 "~a | (b ^ c)",
758 "a & ~(b & c)",
759 "(a & (b ^ c)) | ~(b | c)",
760 "(b & c) ^ (a | c)",
761 "(a & ~c) | ~b",
762 "(b & c) ^ (a | b)",
763 "(a & ~b) | ~c",
764 "(a & ~b) | (b ^ c)",
765 "~(b & c)",
766 "a ^ (b & c)",
767 "~(b | c) | (a ^ (b & c))",
768 "(a & ~b) | (a ^ c)",
769 "~b | (a ^ c)",
770 "(a & ~c) | (a ^ b)",
771 "~c | (a ^ b)",
772 "(a ^ b) | (a ^ c)",
773 "~(a & b & c)",
774 "a & b & c",
775 "~((a ^ b) | (a ^ c))",
776 "c & ~(a ^ b)",
777 "~(a ^ b) & (c | ~a)",
778 "b & ~(a ^ c)",
779 "~(a ^ c) & (b | ~a)",
780 "(b | c) & (a ^ b ^ c)",
781 "(b & c) ^ ~a",
782 "b & c",
783 "~(b ^ c) & (b | ~a)",
784 "c & (b | ~a)",
785 "~((b & c) ^ (a | b))",
786 "b & (c | ~a)",
787 "~((b & c) ^ (a | c))",
788 "a ^ ((a ^ b) | (a ^ c))",
789 "(b & c) | ~a",
790 "a & ~(b ^ c)",
791 "~(b ^ c) & (a | ~b)",
792 "(a | c) & (a ^ b ^ c)",
793 "(a & c) ^ ~b",
794 "(a | b) & (a ^ b ^ c)",
795 "(a & b) ^ ~c",
796 "a ^ b ^ c",
797 "~(a | b) | (a ^ b ^ c)",
798 "~(b ^ c) & (a | b)",
799 "~(b ^ c)",
800 "c ^ (a & ~b)",
801 "~((a | b) & (b ^ c))",
802 "b ^ (a & ~c)",
803 "~((a | c) & (b ^ c))",
804 "(b & c) | (a ^ (b | c))",
805 "~(a & (b ^ c))",
806 "a & c",
807 "~(a ^ c) & (a | ~b)",
808 "c & (a | ~b)",
809 "~((a & c) ^ (a | b))",
810 "~(a ^ c) & (a | b)",
811 "~(a ^ c)",
812 "c ^ (b & ~a)",
813 "~((a | b) & (a ^ c))",
814 "c & (a | b)",
815 "~c ^ (a | b)",
816 "c",
817 "c | ~(a | b)",
818 "b ^ (a & (b ^ c))",
819 "(b & c) | ~(a ^ c)",
820 "(b & ~a) | c",
821 "c | ~a",
822 "a & (c | ~b)",
823 "~((a & c) ^ (b | c))",
824 "a ^ ((a ^ c) & (b ^ c))",
825 "(a & c) | ~b",
826 "a ^ (b & ~c)",
827 "~((b | c) & (a ^ c))",
828 "(a & c) | (a ^ b ^ c)",
829 "~(b & (a ^ c))",
830 "a ^ (b & (a ^ c))",
831 "(a & c) | ~(b ^ c)",
832 "(a & ~b) | c",
833 "c | ~b",
834 "(a & c) | (a ^ b)",
835 "~((a ^ c) & (b ^ c))",
836 "c | (a ^ b)",
837 "c | ~(a & b)",
838 "a & b",
839 "~(a ^ b) & (a | ~c)",
840 "~(a ^ b) & (a | c)",
841 "~(a ^ b)",
842 "b & (a | ~c)",
843 "~((a & b) ^ (a | c))",
844 "b ^ (c & ~a)",
845 "~((a | c) & (a ^ b))",
846 "b & (a | c)",
847 "~b ^ (a | c)",
848 "c ^ (a & (b ^ c))",
849 "(b & c) | ~(a ^ b)",
850 "b",
851 "b | ~(a | c)",
852 "(c & ~a) | b",
853 "b | ~a",
854 "a & (b | ~c)",
855 "~((a & b) ^ (b | c))",
856 "a ^ (c & ~b)",
857 "~((b | c) & (a ^ b))",
858 "a ^ ((a ^ b) & (b ^ c))",
859 "(a & b) | ~c",
860 "(a & b) | (a ^ b ^ c)",
861 "~(c & (a ^ b))",
862 "a ^ (c & (a ^ b))",
863 "(a & b) | ~(b ^ c)",
864 "(a & b) | (a ^ c)",
865 "~((a ^ b) & (b ^ c))",
866 "(a & ~c) | b",
867 "b | ~c",
868 "b | (a ^ c)",
869 "b | ~(a & c)",
870 "a & (b | c)",
871 "~a ^ (b | c)",
872 "c ^ (b & (a ^ c))",
873 "(a & c) | ~(a ^ b)",
874 "b ^ (c & (a ^ b))",
875 "(a & b) | ~(a ^ c)",
876 "(a & b) | (b ^ c)",
877 "~((a ^ b) & (a ^ c))",
878 "(a | b) & ((a & b) | c)",
879 "(a & b) | (b ^ c ^ ~a)",
880 "(a & b) | c",
881 "c | ~(a ^ b)",
882 "(a & c) | b",
883 "b | ~(a ^ c)",
884 "b | c",
885 "~a | b | c",
886 "a",
887 "a | ~(b | c)",
888 "a | (c & ~b)",
889 "a | ~b",
890 "a | (b & ~c)",
891 "a | ~c",
892 "a | (b ^ c)",
893 "a | ~(b & c)",
894 "a | (b & c)",
895 "a | ~(b ^ c)",
896 "a | c",
897 "~b | a | c",
898 "a | b",
899 "~c | a | b",
900 "a | b | c",
901 "-1",
902};
903
904static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS,
905 const MCInstrInfo &MCII) {
906 unsigned NumOperands = MI->getNumOperands();
907
908 int Src2Idx;
909 int Src3Idx;
910 switch (MI->getOpcode()) {
911 // dest, src1, src2, src3, tbl
912 // dest, src1, mask, src2, src3, tbl
913 CASE_PTERNLOG(PTERNLOGD, r)
914 CASE_PTERNLOG(PTERNLOGQ, r)
915 Src2Idx = NumOperands - 3;
916 Src3Idx = NumOperands - 2;
917 break;
918
919 // dest, src1, src2, memory, tbl
920 // dest, src1, mask, src2, memory, tbl
921 CASE_PTERNLOG(PTERNLOGD, m)
922 CASE_PTERNLOG(PTERNLOGQ, m)
923 CASE_PTERNLOG(PTERNLOGD, mb)
924 CASE_PTERNLOG(PTERNLOGQ, mb)
925 Src2Idx = NumOperands - 7;
926 Src3Idx = -1;
927 break;
928
929 default:
930 return false;
931 }
932 StringRef DestName = getRegName(MI->getOperand(0).getReg());
933 StringRef Src1Name = getRegName(MI->getOperand(1).getReg());
934 StringRef Src2Name = getRegName(MI->getOperand(Src2Idx).getReg());
935 StringRef Src3Name =
936 Src3Idx != -1 ? getRegName(MI->getOperand(Src3Idx).getReg()) : "mem";
937 uint8_t TruthTable = MI->getOperand(NumOperands - 1).getImm();
938
939 StringRef SrcNames[] = {Src1Name, Src2Name, Src3Name};
940
941 OS << DestName;
942 printMasking(OS, MI, MCII);
943 OS << " = ";
944
945 static_assert(std::size(TernlogFunctions) == 256);
946 std::string_view BooleanFunction = TernlogFunctions[TruthTable];
947
948 while (!BooleanFunction.empty()) {
949 // Print the expression up to the next symbol.
950 size_t SymbolOffset = BooleanFunction.find_first_of("abc");
951 OS << BooleanFunction.substr(0, SymbolOffset);
952 if (SymbolOffset == std::string_view::npos) {
953 // No more symbols, that means we just printed everything.
954 break;
955 }
956 // Let's replace {a,b,c} with Src{1,2,3}Name.
957 char Symbol = BooleanFunction[SymbolOffset];
958 OS << SrcNames[Symbol - 'a'];
959 // Consume the part of the expression we handled.
960 BooleanFunction.remove_prefix(SymbolOffset + 1);
961 }
962 OS << '\n';
963 return true;
964}
965
966static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS,
967 const MCInstrInfo &MCII) {
968 unsigned NumOperands = MI->getNumOperands();
969 int SrcIdx;
970 switch (MI->getOpcode()) {
971 CASE_FPCLASS_PACKED(FPCLASSPBF16, r)
972 CASE_FPCLASS_PACKED(FPCLASSPH, r)
973 CASE_FPCLASS_PACKED(FPCLASSPS, r)
974 CASE_FPCLASS_PACKED(FPCLASSPD, r)
975 CASE_FPCLASS_SCALAR(FPCLASSSH, r)
976 CASE_FPCLASS_SCALAR(FPCLASSSS, r)
977 CASE_FPCLASS_SCALAR(FPCLASSSD, r) {
978 SrcIdx = NumOperands - 2;
979 break;
980 }
981 CASE_FPCLASS_PACKED_MEM(FPCLASSPBF16)
982 CASE_FPCLASS_PACKED_MEM(FPCLASSPH)
983 CASE_FPCLASS_PACKED_MEM(FPCLASSPS)
984 CASE_FPCLASS_PACKED_MEM(FPCLASSPD)
985 CASE_FPCLASS_SCALAR(FPCLASSSH, m)
986 CASE_FPCLASS_SCALAR(FPCLASSSS, m)
987 CASE_FPCLASS_SCALAR(FPCLASSSD, m) {
988 SrcIdx = -1;
989 break;
990 }
991 default:
992 return false;
993 }
994 StringRef DestName = getRegName(MI->getOperand(0).getReg());
995 StringRef SrcName =
996 SrcIdx != -1 ? getRegName(MI->getOperand(SrcIdx).getReg()) : "mem";
997
998 OS << DestName;
999 printMasking(OS, MI, MCII);
1000 OS << " = ";
1001
1002 uint8_t Categories = MI->getOperand(NumOperands - 1).getImm();
1003 if (Categories == 0) {
1004 OS << "false";
1005 } else {
1006 static constexpr StringLiteral CategoryNames[] = {
1007 "QuietNaN",
1008 "PositiveZero",
1009 "NegativeZero",
1010 "PositiveInfinity",
1011 "NegativeInfinity",
1012 "Subnormal",
1013 "Negative",
1014 "SignalingNaN",
1015 };
1016 bool Conjoin = false;
1017 for (size_t I = 0, E = std::size(CategoryNames); I != E; ++I) {
1018 if (Categories & (1 << I)) {
1019 if (Conjoin)
1020 OS << " | ";
1021 Conjoin = true;
1022 OS << "is" << CategoryNames[I] << '(' << SrcName << ')';
1023 }
1024 }
1025 }
1026 OS << '\n';
1027 return true;
1028}
1029
1030//===----------------------------------------------------------------------===//
1031// Top Level Entrypoint
1032//===----------------------------------------------------------------------===//
1033
1034/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
1035/// newline terminated strings to the specified string if desired. This
1036/// information is shown in disassembly dumps when verbose assembly is enabled.
1037bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
1038 const MCInstrInfo &MCII) {
1039 // If this is a shuffle operation, the switch should fill in this state.
1040 SmallVector<int, 8> ShuffleMask;
1041 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
1042 unsigned NumOperands = MI->getNumOperands();
1043 bool RegForm = false;
1044
1045 if (printFMAComments(MI, OS, MCII))
1046 return true;
1047
1048 if (printPTERNLOGComments(MI, OS, MCII))
1049 return true;
1050
1051 if (printFPCLASSComments(MI, OS, MCII))
1052 return true;
1053
1054 switch (MI->getOpcode()) {
1055 default:
1056 // Not an instruction for which we can decode comments.
1057 return false;
1058
1059 case X86::BLENDPDrri:
1060 case X86::VBLENDPDrri:
1061 case X86::VBLENDPDYrri:
1062 Src2Name = getRegName(MI->getOperand(2).getReg());
1063 [[fallthrough]];
1064 case X86::BLENDPDrmi:
1065 case X86::VBLENDPDrmi:
1066 case X86::VBLENDPDYrmi:
1067 if (MI->getOperand(NumOperands - 1).isImm())
1068 DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),
1069 MI->getOperand(NumOperands - 1).getImm(),
1070 ShuffleMask);
1071 Src1Name = getRegName(MI->getOperand(1).getReg());
1072 DestName = getRegName(MI->getOperand(0).getReg());
1073 break;
1074
1075 case X86::BLENDPSrri:
1076 case X86::VBLENDPSrri:
1077 case X86::VBLENDPSYrri:
1078 Src2Name = getRegName(MI->getOperand(2).getReg());
1079 [[fallthrough]];
1080 case X86::BLENDPSrmi:
1081 case X86::VBLENDPSrmi:
1082 case X86::VBLENDPSYrmi:
1083 if (MI->getOperand(NumOperands - 1).isImm())
1084 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
1085 MI->getOperand(NumOperands - 1).getImm(),
1086 ShuffleMask);
1087 Src1Name = getRegName(MI->getOperand(1).getReg());
1088 DestName = getRegName(MI->getOperand(0).getReg());
1089 break;
1090
1091 case X86::PBLENDWrri:
1092 case X86::VPBLENDWrri:
1093 case X86::VPBLENDWYrri:
1094 Src2Name = getRegName(MI->getOperand(2).getReg());
1095 [[fallthrough]];
1096 case X86::PBLENDWrmi:
1097 case X86::VPBLENDWrmi:
1098 case X86::VPBLENDWYrmi:
1099 if (MI->getOperand(NumOperands - 1).isImm())
1100 DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),
1101 MI->getOperand(NumOperands - 1).getImm(),
1102 ShuffleMask);
1103 Src1Name = getRegName(MI->getOperand(1).getReg());
1104 DestName = getRegName(MI->getOperand(0).getReg());
1105 break;
1106
1107 case X86::VPBLENDDrri:
1108 case X86::VPBLENDDYrri:
1109 Src2Name = getRegName(MI->getOperand(2).getReg());
1110 [[fallthrough]];
1111 case X86::VPBLENDDrmi:
1112 case X86::VPBLENDDYrmi:
1113 if (MI->getOperand(NumOperands - 1).isImm())
1114 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
1115 MI->getOperand(NumOperands - 1).getImm(),
1116 ShuffleMask);
1117 Src1Name = getRegName(MI->getOperand(1).getReg());
1118 DestName = getRegName(MI->getOperand(0).getReg());
1119 break;
1120
1121 case X86::INSERTPSrri:
1122 case X86::VINSERTPSrri:
1123 case X86::VINSERTPSZrri:
1124 Src2Name = getRegName(MI->getOperand(2).getReg());
1125 DestName = getRegName(MI->getOperand(0).getReg());
1126 Src1Name = getRegName(MI->getOperand(1).getReg());
1127 if (MI->getOperand(NumOperands - 1).isImm())
1128 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask,
1129 /*SrcIsMem=*/false);
1130 break;
1131
1132 case X86::INSERTPSrmi:
1133 case X86::VINSERTPSrmi:
1134 case X86::VINSERTPSZrmi:
1135 DestName = getRegName(MI->getOperand(0).getReg());
1136 Src1Name = getRegName(MI->getOperand(1).getReg());
1137 if (MI->getOperand(NumOperands - 1).isImm())
1138 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask,
1139 /*SrcIsMem=*/true);
1140 break;
1141
1142 case X86::MOVLHPSrr:
1143 case X86::VMOVLHPSrr:
1144 case X86::VMOVLHPSZrr:
1145 Src2Name = getRegName(MI->getOperand(2).getReg());
1146 Src1Name = getRegName(MI->getOperand(1).getReg());
1147 DestName = getRegName(MI->getOperand(0).getReg());
1148 DecodeMOVLHPSMask(2, ShuffleMask);
1149 break;
1150
1151 case X86::MOVHLPSrr:
1152 case X86::VMOVHLPSrr:
1153 case X86::VMOVHLPSZrr:
1154 Src2Name = getRegName(MI->getOperand(2).getReg());
1155 Src1Name = getRegName(MI->getOperand(1).getReg());
1156 DestName = getRegName(MI->getOperand(0).getReg());
1157 DecodeMOVHLPSMask(2, ShuffleMask);
1158 break;
1159
1160 case X86::MOVHPDrm:
1161 case X86::VMOVHPDrm:
1162 case X86::VMOVHPDZ128rm:
1163 Src1Name = getRegName(MI->getOperand(1).getReg());
1164 DestName = getRegName(MI->getOperand(0).getReg());
1165 DecodeInsertElementMask(2, 1, 1, ShuffleMask);
1166 break;
1167
1168 case X86::MOVHPSrm:
1169 case X86::VMOVHPSrm:
1170 case X86::VMOVHPSZ128rm:
1171 Src1Name = getRegName(MI->getOperand(1).getReg());
1172 DestName = getRegName(MI->getOperand(0).getReg());
1173 DecodeInsertElementMask(4, 2, 2, ShuffleMask);
1174 break;
1175
1176 case X86::MOVLPDrm:
1177 case X86::VMOVLPDrm:
1178 case X86::VMOVLPDZ128rm:
1179 Src1Name = getRegName(MI->getOperand(1).getReg());
1180 DestName = getRegName(MI->getOperand(0).getReg());
1181 DecodeInsertElementMask(2, 0, 1, ShuffleMask);
1182 break;
1183
1184 case X86::MOVLPSrm:
1185 case X86::VMOVLPSrm:
1186 case X86::VMOVLPSZ128rm:
1187 Src1Name = getRegName(MI->getOperand(1).getReg());
1188 DestName = getRegName(MI->getOperand(0).getReg());
1189 DecodeInsertElementMask(4, 0, 2, ShuffleMask);
1190 break;
1191
1192 CASE_MOVDUP(MOVSLDUP, r)
1193 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1194 [[fallthrough]];
1195
1196 CASE_MOVDUP(MOVSLDUP, m)
1197 DestName = getRegName(MI->getOperand(0).getReg());
1198 DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1199 break;
1200
1201 CASE_MOVDUP(MOVSHDUP, r)
1202 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1203 [[fallthrough]];
1204
1205 CASE_MOVDUP(MOVSHDUP, m)
1206 DestName = getRegName(MI->getOperand(0).getReg());
1207 DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1208 break;
1209
1210 CASE_MOVDUP(MOVDDUP, r)
1211 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1212 [[fallthrough]];
1213
1214 CASE_MOVDUP(MOVDDUP, m)
1215 DestName = getRegName(MI->getOperand(0).getReg());
1216 DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1217 break;
1218
1219 case X86::PSLLDQri:
1220 case X86::VPSLLDQri:
1221 case X86::VPSLLDQYri:
1222 case X86::VPSLLDQZ128ri:
1223 case X86::VPSLLDQZ256ri:
1224 case X86::VPSLLDQZri:
1225 Src1Name = getRegName(MI->getOperand(1).getReg());
1226 [[fallthrough]];
1227 case X86::VPSLLDQZ128mi:
1228 case X86::VPSLLDQZ256mi:
1229 case X86::VPSLLDQZmi:
1230 DestName = getRegName(MI->getOperand(0).getReg());
1231 if (MI->getOperand(NumOperands - 1).isImm())
1232 DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
1233 MI->getOperand(NumOperands - 1).getImm(),
1234 ShuffleMask);
1235 break;
1236
1237 case X86::PSRLDQri:
1238 case X86::VPSRLDQri:
1239 case X86::VPSRLDQYri:
1240 case X86::VPSRLDQZ128ri:
1241 case X86::VPSRLDQZ256ri:
1242 case X86::VPSRLDQZri:
1243 Src1Name = getRegName(MI->getOperand(1).getReg());
1244 [[fallthrough]];
1245 case X86::VPSRLDQZ128mi:
1246 case X86::VPSRLDQZ256mi:
1247 case X86::VPSRLDQZmi:
1248 DestName = getRegName(MI->getOperand(0).getReg());
1249 if (MI->getOperand(NumOperands - 1).isImm())
1250 DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),
1251 MI->getOperand(NumOperands - 1).getImm(),
1252 ShuffleMask);
1253 break;
1254
1255 CASE_SHUF(PALIGNR, rri)
1256 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1257 RegForm = true;
1258 [[fallthrough]];
1259
1260 CASE_SHUF(PALIGNR, rmi)
1261 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1262 DestName = getRegName(MI->getOperand(0).getReg());
1263 if (MI->getOperand(NumOperands - 1).isImm())
1264 DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),
1265 MI->getOperand(NumOperands - 1).getImm(),
1266 ShuffleMask);
1267 break;
1268
1269 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
1270 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
1271 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
1272 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1273 RegForm = true;
1274 [[fallthrough]];
1275
1276 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
1277 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
1278 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
1279 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1280 DestName = getRegName(MI->getOperand(0).getReg());
1281 if (MI->getOperand(NumOperands - 1).isImm())
1282 DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),
1283 MI->getOperand(NumOperands - 1).getImm(),
1284 ShuffleMask);
1285 break;
1286
1287 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
1288 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
1289 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
1290 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1291 RegForm = true;
1292 [[fallthrough]];
1293
1294 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
1295 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
1296 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
1297 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1298 DestName = getRegName(MI->getOperand(0).getReg());
1299 if (MI->getOperand(NumOperands - 1).isImm())
1300 DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),
1301 MI->getOperand(NumOperands - 1).getImm(),
1302 ShuffleMask);
1303 break;
1304
1305 CASE_SHUF(PSHUFD, ri)
1306 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1307 [[fallthrough]];
1308
1309 CASE_SHUF(PSHUFD, mi)
1310 DestName = getRegName(MI->getOperand(0).getReg());
1311 if (MI->getOperand(NumOperands - 1).isImm())
1312 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1313 MI->getOperand(NumOperands - 1).getImm(),
1314 ShuffleMask);
1315 break;
1316
1317 CASE_SHUF(PSHUFHW, ri)
1318 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1319 [[fallthrough]];
1320
1321 CASE_SHUF(PSHUFHW, mi)
1322 DestName = getRegName(MI->getOperand(0).getReg());
1323 if (MI->getOperand(NumOperands - 1).isImm())
1324 DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),
1325 MI->getOperand(NumOperands - 1).getImm(),
1326 ShuffleMask);
1327 break;
1328
1329 CASE_SHUF(PSHUFLW, ri)
1330 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1331 [[fallthrough]];
1332
1333 CASE_SHUF(PSHUFLW, mi)
1334 DestName = getRegName(MI->getOperand(0).getReg());
1335 if (MI->getOperand(NumOperands - 1).isImm())
1336 DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),
1337 MI->getOperand(NumOperands - 1).getImm(),
1338 ShuffleMask);
1339 break;
1340
1341 case X86::MMX_PSHUFWri:
1342 Src1Name = getRegName(MI->getOperand(1).getReg());
1343 [[fallthrough]];
1344
1345 case X86::MMX_PSHUFWmi:
1346 DestName = getRegName(MI->getOperand(0).getReg());
1347 if (MI->getOperand(NumOperands - 1).isImm())
1348 DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(),
1349 ShuffleMask);
1350 break;
1351
1352 case X86::PSWAPDrr:
1353 Src1Name = getRegName(MI->getOperand(1).getReg());
1354 [[fallthrough]];
1355
1356 case X86::PSWAPDrm:
1357 DestName = getRegName(MI->getOperand(0).getReg());
1358 DecodePSWAPMask(2, ShuffleMask);
1359 break;
1360
1361 CASE_UNPCK(PUNPCKHBW, r)
1362 case X86::MMX_PUNPCKHBWrr:
1363 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1364 RegForm = true;
1365 [[fallthrough]];
1366
1367 CASE_UNPCK(PUNPCKHBW, m)
1368 case X86::MMX_PUNPCKHBWrm:
1369 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1370 DestName = getRegName(MI->getOperand(0).getReg());
1371 DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
1372 break;
1373
1374 CASE_UNPCK(PUNPCKHWD, r)
1375 case X86::MMX_PUNPCKHWDrr:
1376 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1377 RegForm = true;
1378 [[fallthrough]];
1379
1380 CASE_UNPCK(PUNPCKHWD, m)
1381 case X86::MMX_PUNPCKHWDrm:
1382 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1383 DestName = getRegName(MI->getOperand(0).getReg());
1384 DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
1385 break;
1386
1387 CASE_UNPCK(PUNPCKHDQ, r)
1388 case X86::MMX_PUNPCKHDQrr:
1389 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1390 RegForm = true;
1391 [[fallthrough]];
1392
1393 CASE_UNPCK(PUNPCKHDQ, m)
1394 case X86::MMX_PUNPCKHDQrm:
1395 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1396 DestName = getRegName(MI->getOperand(0).getReg());
1397 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1398 break;
1399
1400 CASE_UNPCK(PUNPCKHQDQ, r)
1401 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1402 RegForm = true;
1403 [[fallthrough]];
1404
1405 CASE_UNPCK(PUNPCKHQDQ, m)
1406 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1407 DestName = getRegName(MI->getOperand(0).getReg());
1408 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1409 break;
1410
1411 CASE_UNPCK(PUNPCKLBW, r)
1412 case X86::MMX_PUNPCKLBWrr:
1413 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1414 RegForm = true;
1415 [[fallthrough]];
1416
1417 CASE_UNPCK(PUNPCKLBW, m)
1418 case X86::MMX_PUNPCKLBWrm:
1419 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1420 DestName = getRegName(MI->getOperand(0).getReg());
1421 DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
1422 break;
1423
1424 CASE_UNPCK(PUNPCKLWD, r)
1425 case X86::MMX_PUNPCKLWDrr:
1426 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1427 RegForm = true;
1428 [[fallthrough]];
1429
1430 CASE_UNPCK(PUNPCKLWD, m)
1431 case X86::MMX_PUNPCKLWDrm:
1432 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1433 DestName = getRegName(MI->getOperand(0).getReg());
1434 DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
1435 break;
1436
1437 CASE_UNPCK(PUNPCKLDQ, r)
1438 case X86::MMX_PUNPCKLDQrr:
1439 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1440 RegForm = true;
1441 [[fallthrough]];
1442
1443 CASE_UNPCK(PUNPCKLDQ, m)
1444 case X86::MMX_PUNPCKLDQrm:
1445 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1446 DestName = getRegName(MI->getOperand(0).getReg());
1447 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1448 break;
1449
1450 CASE_UNPCK(PUNPCKLQDQ, r)
1451 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1452 RegForm = true;
1453 [[fallthrough]];
1454
1455 CASE_UNPCK(PUNPCKLQDQ, m)
1456 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1457 DestName = getRegName(MI->getOperand(0).getReg());
1458 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1459 break;
1460
1461 CASE_SHUF(SHUFPD, rri)
1462 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1463 RegForm = true;
1464 [[fallthrough]];
1465
1466 CASE_SHUF(SHUFPD, rmi)
1467 if (MI->getOperand(NumOperands - 1).isImm())
1468 DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,
1469 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
1470 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1471 DestName = getRegName(MI->getOperand(0).getReg());
1472 break;
1473
1474 CASE_SHUF(SHUFPS, rri)
1475 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1476 RegForm = true;
1477 [[fallthrough]];
1478
1479 CASE_SHUF(SHUFPS, rmi)
1480 if (MI->getOperand(NumOperands - 1).isImm())
1481 DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,
1482 MI->getOperand(NumOperands - 1).getImm(),
1483 ShuffleMask);
1484 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1485 DestName = getRegName(MI->getOperand(0).getReg());
1486 break;
1487
1488 CASE_VSHUF(64X2, r)
1489 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1490 RegForm = true;
1491 [[fallthrough]];
1492
1493 CASE_VSHUF(64X2, m)
1494 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,
1495 MI->getOperand(NumOperands - 1).getImm(),
1496 ShuffleMask);
1497 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1498 DestName = getRegName(MI->getOperand(0).getReg());
1499 break;
1500
1501 CASE_VSHUF(32X4, r)
1502 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1503 RegForm = true;
1504 [[fallthrough]];
1505
1506 CASE_VSHUF(32X4, m)
1507 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,
1508 MI->getOperand(NumOperands - 1).getImm(),
1509 ShuffleMask);
1510 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
1511 DestName = getRegName(MI->getOperand(0).getReg());
1512 break;
1513
1514 CASE_UNPCK(UNPCKLPD, r)
1515 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1516 RegForm = true;
1517 [[fallthrough]];
1518
1519 CASE_UNPCK(UNPCKLPD, m)
1520 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1521 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1522 DestName = getRegName(MI->getOperand(0).getReg());
1523 break;
1524
1525 CASE_UNPCK(UNPCKLPS, r)
1526 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1527 RegForm = true;
1528 [[fallthrough]];
1529
1530 CASE_UNPCK(UNPCKLPS, m)
1531 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1532 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1533 DestName = getRegName(MI->getOperand(0).getReg());
1534 break;
1535
1536 CASE_UNPCK(UNPCKHPD, r)
1537 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1538 RegForm = true;
1539 [[fallthrough]];
1540
1541 CASE_UNPCK(UNPCKHPD, m)
1542 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
1543 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1544 DestName = getRegName(MI->getOperand(0).getReg());
1545 break;
1546
1547 CASE_UNPCK(UNPCKHPS, r)
1548 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1549 RegForm = true;
1550 [[fallthrough]];
1551
1552 CASE_UNPCK(UNPCKHPS, m)
1553 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1554 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1555 DestName = getRegName(MI->getOperand(0).getReg());
1556 break;
1557
1558 CASE_VPERMILPI(PERMILPS, r)
1559 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1560 [[fallthrough]];
1561
1562 CASE_VPERMILPI(PERMILPS, m)
1563 if (MI->getOperand(NumOperands - 1).isImm())
1564 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1565 MI->getOperand(NumOperands - 1).getImm(),
1566 ShuffleMask);
1567 DestName = getRegName(MI->getOperand(0).getReg());
1568 break;
1569
1570 CASE_VPERMILPI(PERMILPD, r)
1571 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1572 [[fallthrough]];
1573
1574 CASE_VPERMILPI(PERMILPD, m)
1575 if (MI->getOperand(NumOperands - 1).isImm())
1576 DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,
1577 MI->getOperand(NumOperands - 1).getImm(),
1578 ShuffleMask);
1579 DestName = getRegName(MI->getOperand(0).getReg());
1580 break;
1581
1582 case X86::VPERM2F128rri:
1583 case X86::VPERM2I128rri:
1584 Src2Name = getRegName(MI->getOperand(2).getReg());
1585 [[fallthrough]];
1586
1587 case X86::VPERM2F128rmi:
1588 case X86::VPERM2I128rmi:
1589 // For instruction comments purpose, assume the 256-bit vector is v4i64.
1590 if (MI->getOperand(NumOperands - 1).isImm())
1591 DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
1592 ShuffleMask);
1593 Src1Name = getRegName(MI->getOperand(1).getReg());
1594 DestName = getRegName(MI->getOperand(0).getReg());
1595 break;
1596
1597 CASE_VPERM(PERMPD, r)
1598 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1599 [[fallthrough]];
1600
1601 CASE_VPERM(PERMPD, m)
1602 if (MI->getOperand(NumOperands - 1).isImm())
1603 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1604 MI->getOperand(NumOperands - 1).getImm(),
1605 ShuffleMask);
1606 DestName = getRegName(MI->getOperand(0).getReg());
1607 break;
1608
1609 CASE_VPERM(PERMQ, r)
1610 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1611 [[fallthrough]];
1612
1613 CASE_VPERM(PERMQ, m)
1614 if (MI->getOperand(NumOperands - 1).isImm())
1615 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1616 MI->getOperand(NumOperands - 1).getImm(),
1617 ShuffleMask);
1618 DestName = getRegName(MI->getOperand(0).getReg());
1619 break;
1620
1621 case X86::MOVSDrr:
1622 case X86::VMOVSDrr:
1623 case X86::VMOVSDZrr:
1624 Src2Name = getRegName(MI->getOperand(2).getReg());
1625 Src1Name = getRegName(MI->getOperand(1).getReg());
1626 DecodeScalarMoveMask(2, false, ShuffleMask);
1627 DestName = getRegName(MI->getOperand(0).getReg());
1628 break;
1629
1630 case X86::MOVSSrr:
1631 case X86::VMOVSSrr:
1632 case X86::VMOVSSZrr:
1633 Src2Name = getRegName(MI->getOperand(2).getReg());
1634 Src1Name = getRegName(MI->getOperand(1).getReg());
1635 DecodeScalarMoveMask(4, false, ShuffleMask);
1636 DestName = getRegName(MI->getOperand(0).getReg());
1637 break;
1638
1639 case X86::MOVPQI2QIrr:
1640 case X86::MOVZPQILo2PQIrr:
1641 case X86::VMOVPQI2QIrr:
1642 case X86::VMOVPQI2QIZrr:
1643 case X86::VMOVZPQILo2PQIrr:
1644 case X86::VMOVZPQILo2PQIZrr:
1645 Src1Name = getRegName(MI->getOperand(1).getReg());
1646 DecodeZeroMoveLowMask(2, ShuffleMask);
1647 DestName = getRegName(MI->getOperand(0).getReg());
1648 break;
1649
1650 case X86::EXTRQI:
1651 if (MI->getOperand(2).isImm() &&
1652 MI->getOperand(3).isImm())
1653 DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(),
1654 MI->getOperand(3).getImm(), ShuffleMask);
1655
1656 DestName = getRegName(MI->getOperand(0).getReg());
1657 Src1Name = getRegName(MI->getOperand(1).getReg());
1658 break;
1659
1660 case X86::INSERTQI:
1661 if (MI->getOperand(3).isImm() &&
1662 MI->getOperand(4).isImm())
1663 DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(),
1664 MI->getOperand(4).getImm(), ShuffleMask);
1665
1666 DestName = getRegName(MI->getOperand(0).getReg());
1667 Src1Name = getRegName(MI->getOperand(1).getReg());
1668 Src2Name = getRegName(MI->getOperand(2).getReg());
1669 break;
1670
1671 case X86::VBROADCASTF128rm:
1672 case X86::VBROADCASTI128rm:
1673 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z256, rm)
1674 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z256, rm)
1675 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1676 DestName = getRegName(MI->getOperand(0).getReg());
1677 break;
1678 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z, rm)
1679 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z, rm)
1680 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1681 DestName = getRegName(MI->getOperand(0).getReg());
1682 break;
1683 CASE_AVX512_INS_COMMON(BROADCASTF64X4, Z, rm)
1684 CASE_AVX512_INS_COMMON(BROADCASTI64X4, Z, rm)
1685 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1686 DestName = getRegName(MI->getOperand(0).getReg());
1687 break;
1688 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1689 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1690 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1691 DestName = getRegName(MI->getOperand(0).getReg());
1692 break;
1693 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z, rm)
1694 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z, rm)
1695 DecodeSubVectorBroadcast(16, 4, ShuffleMask);
1696 DestName = getRegName(MI->getOperand(0).getReg());
1697 break;
1698 CASE_AVX512_INS_COMMON(BROADCASTF32X8, Z, rm)
1699 CASE_AVX512_INS_COMMON(BROADCASTI32X8, Z, rm)
1700 DecodeSubVectorBroadcast(16, 8, ShuffleMask);
1701 DestName = getRegName(MI->getOperand(0).getReg());
1702 break;
1703 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rr)
1704 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1705 [[fallthrough]];
1706 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, rm)
1707 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1708 DestName = getRegName(MI->getOperand(0).getReg());
1709 break;
1710 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rr)
1711 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rr)
1712 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1713 [[fallthrough]];
1714 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, rm)
1715 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, rm)
1716 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1717 DestName = getRegName(MI->getOperand(0).getReg());
1718 break;
1719 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rr)
1720 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rr)
1721 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1722 [[fallthrough]];
1723 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, rm)
1724 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, rm)
1725 DecodeSubVectorBroadcast(16, 2, ShuffleMask);
1726 DestName = getRegName(MI->getOperand(0).getReg());
1727 break;
1728
1729 CASE_PMOVZX(PMOVZXBW, r)
1730 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1731 DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
1732 ShuffleMask);
1733 DestName = getRegName(MI->getOperand(0).getReg());
1734 break;
1735
1736 CASE_PMOVZX(PMOVZXBD, r)
1737 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1738 DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
1739 ShuffleMask);
1740 DestName = getRegName(MI->getOperand(0).getReg());
1741 break;
1742
1743 CASE_PMOVZX(PMOVZXBQ, r)
1744 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1745 DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
1746 ShuffleMask);
1747 DestName = getRegName(MI->getOperand(0).getReg());
1748 break;
1749
1750 CASE_PMOVZX(PMOVZXWD, r)
1751 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1752 DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
1753 ShuffleMask);
1754 DestName = getRegName(MI->getOperand(0).getReg());
1755 break;
1756
1757 CASE_PMOVZX(PMOVZXWQ, r)
1758 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1759 DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
1760 ShuffleMask);
1761 DestName = getRegName(MI->getOperand(0).getReg());
1762 break;
1763
1764 CASE_PMOVZX(PMOVZXDQ, r)
1765 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1766 DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
1767 ShuffleMask);
1768 DestName = getRegName(MI->getOperand(0).getReg());
1769 break;
1770 }
1771
1772 // The only comments we decode are shuffles, so give up if we were unable to
1773 // decode a shuffle mask.
1774 if (ShuffleMask.empty())
1775 return false;
1776
1777 if (!DestName) DestName = Src1Name;
1778 if (DestName) {
1779 OS << DestName;
1780 printMasking(OS, MI, MCII);
1781 } else
1782 OS << "mem";
1783
1784 OS << " = ";
1785
1786 // If the two sources are the same, canonicalize the input elements to be
1787 // from the first src so that we get larger element spans.
1788 if (Src1Name == Src2Name) {
1789 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1790 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1791 ShuffleMask[i] >= (int)e) // From second mask.
1792 ShuffleMask[i] -= e;
1793 }
1794 }
1795
1796 // The shuffle mask specifies which elements of the src1/src2 fill in the
1797 // destination, with a few sentinel values. Loop through and print them
1798 // out.
1799 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1800 if (i != 0)
1801 OS << ',';
1802 if (ShuffleMask[i] == SM_SentinelZero) {
1803 OS << "zero";
1804 continue;
1805 }
1806
1807 // Otherwise, it must come from src1 or src2. Print the span of elements
1808 // that comes from this src.
1809 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1810 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1811 OS << (SrcName ? SrcName : "mem") << '[';
1812 bool IsFirst = true;
1813 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1814 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1815 if (!IsFirst)
1816 OS << ',';
1817 else
1818 IsFirst = false;
1819 if (ShuffleMask[i] == SM_SentinelUndef)
1820 OS << "u";
1821 else
1822 OS << ShuffleMask[i] % ShuffleMask.size();
1823 ++i;
1824 }
1825 OS << ']';
1826 --i; // For loop increments element #.
1827 }
1828 OS << '\n';
1829
1830 // We successfully added a comment to this instruction.
1831 return true;
1832}
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
I
#define I(x, y, z)
Definition: MD5.cpp:58
OS
raw_pwrite_stream & OS
Definition: SampleProfWriter.cpp:51
CASE_VPERM
#define CASE_VPERM(Inst, src)
Definition: X86InstComments.cpp:141
CASE_FPCLASS_PACKED_MEM
#define CASE_FPCLASS_PACKED_MEM(Inst)
Definition: X86InstComments.cpp:49
CASE_FMA_SCALAR_REG
#define CASE_FMA_SCALAR_REG(Inst)
Definition: X86InstComments.cpp:192
printPTERNLOGComments
static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition: X86InstComments.cpp:904
CASE_FPCLASS_PACKED
#define CASE_FPCLASS_PACKED(Inst, src)
Definition: X86InstComments.cpp:43
getVectorRegSize
static unsigned getVectorRegSize(MCRegister Reg)
Definition: X86InstComments.cpp:246
CASE_VPERMILPI
#define CASE_VPERMILPI(Inst, src)
Definition: X86InstComments.cpp:124
CASE_FMA4_SCALAR_MR
#define CASE_FMA4_SCALAR_MR(Inst)
Definition: X86InstComments.cpp:240
printFMAComments
static bool printFMAComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition: X86InstComments.cpp:294
CASE_SHUF
#define CASE_SHUF(Inst, suf)
Definition: X86InstComments.cpp:106
CASE_FMA4_PACKED_RM
#define CASE_FMA4_PACKED_RM(Inst)
Definition: X86InstComments.cpp:220
CASE_MOVDUP
#define CASE_MOVDUP(Inst, src)
Definition: X86InstComments.cpp:62
CASE_FMA_SCALAR_MEM
#define CASE_FMA_SCALAR_MEM(Inst)
Definition: X86InstComments.cpp:202
CASE_FMA4_SCALAR_RR
#define CASE_FMA4_SCALAR_RR(Inst)
Definition: X86InstComments.cpp:228
getRegOperandNumElts
static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, unsigned OperandIndex)
Definition: X86InstComments.cpp:259
CASE_FMA4_PACKED_MR
#define CASE_FMA4_PACKED_MR(Inst)
Definition: X86InstComments.cpp:224
TernlogFunctions
constexpr StringLiteral TernlogFunctions[]
Definition: X86InstComments.cpp:645
CASE_AVX512_INS_COMMON
#define CASE_AVX512_INS_COMMON(Inst, Suffix, src)
Definition: X86InstComments.cpp:38
printFPCLASSComments
static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
Definition: X86InstComments.cpp:966
getRegName
static const char * getRegName(MCRegister Reg)
Definition: X86InstComments.cpp:265
CASE_PMOVZX
#define CASE_PMOVZX(Inst, src)
Definition: X86InstComments.cpp:80
CASE_VSHUF
#define CASE_VSHUF(Inst, src)
Definition: X86InstComments.cpp:154
CASE_FMA_PACKED_MEM
#define CASE_FMA_PACKED_MEM(Inst)
Definition: X86InstComments.cpp:186
printMasking
static void printMasking(raw_ostream &OS, const MCInst *MI, const MCInstrInfo &MCII)
Wraps the destination register name with AVX512 mask/maskz filtering.
Definition: X86InstComments.cpp:270
CASE_FPCLASS_SCALAR
#define CASE_FPCLASS_SCALAR(Inst, src)
Definition: X86InstComments.cpp:53
CASE_FMA4_SCALAR_RM
#define CASE_FMA4_SCALAR_RM(Inst)
Definition: X86InstComments.cpp:234
CASE_FMA4_PACKED_RR
#define CASE_FMA4_PACKED_RR(Inst)
Definition: X86InstComments.cpp:216
CASE_FMA_PACKED_REG
#define CASE_FMA_PACKED_REG(Inst)
Definition: X86InstComments.cpp:182
CASE_PTERNLOG
#define CASE_PTERNLOG(Inst, src)
Definition: X86InstComments.cpp:57
CASE_UNPCK
#define CASE_UNPCK(Inst, src)
Definition: X86InstComments.cpp:88
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::SmallVectorBase::empty
bool empty() const
Definition: SmallVector.h:81
llvm::SmallVectorBase::size
size_t size() const
Definition: SmallVector.h:78
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1196
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:853
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
llvm::StringRef::find_first_of
size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
Definition: StringRef.h:377
llvm::X86ATTInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg)
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint64_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::X86II::isZMMReg
bool isZMMReg(MCRegister Reg)
Definition: X86BaseInfo.h:1179
llvm::X86II::isXMMReg
bool isXMMReg(MCRegister Reg)
Definition: X86BaseInfo.h:1159
llvm::X86II::isYMMReg
bool isYMMReg(MCRegister Reg)
Definition: X86BaseInfo.h:1169
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::DecodeZeroExtendMask
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:371
llvm::EmitAnyX86InstComments
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
Definition: X86InstComments.cpp:1037
llvm::DecodeMOVHLPSMask
void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVHLPS instruction as a v2f64/v4f32 shuffle mask.
Definition: X86ShuffleDecode.cpp:61
llvm::DecodeZeroMoveLowMask
void DecodeZeroMoveLowMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decode a move lower and zero upper instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:385
llvm::DecodeInsertElementMask
void DecodeInsertElementMask(unsigned NumElts, unsigned Idx, unsigned Len, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:50
llvm::DecodePSHUFLWMask
void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshuflw.
Definition: X86ShuffleDecode.cpp:178
llvm::DecodeBLENDMask
void DecodeBLENDMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a BLEND immediate mask into a shuffle mask.
Definition: X86ShuffleDecode.cpp:315
llvm::decodeVSHUF64x2FamilyMask
void decodeVSHUF64x2FamilyMask(unsigned NumElts, unsigned ScalarSize, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decode a shuffle packed values at 128-bit granularity (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) immed...
Definition: X86ShuffleDecode.cpp:264
llvm::DecodeVPERMMask
void DecodeVPERMMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for VPERMQ/VPERMPD.
Definition: X86ShuffleDecode.cpp:364
llvm::DecodeEXTRQIMask
void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A EXTRQ instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:400
llvm::DecodePSRLDQMask
void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:112
llvm::DecodeINSERTPSMask
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl< int > &ShuffleMask, bool SrcIsMem)
Decode a 128-bit INSERTPS instruction as a v4f32 shuffle mask.
Definition: X86ShuffleDecode.cpp:26
llvm::DecodeVPERM2X128Mask
void DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:281
llvm::DecodeMOVLHPSMask
void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl< int > &ShuffleMask)
Decode a MOVLHPS instruction as a v2f64/v4f32 shuffle mask.
Definition: X86ShuffleDecode.cpp:70
llvm::DecodePSWAPMask
void DecodePSWAPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a PSWAPD 3DNow! instruction.
Definition: X86ShuffleDecode.cpp:192
llvm::DecodeINSERTQIMask
void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, SmallVectorImpl< int > &ShuffleMask)
Decode a SSE4A INSERTQ instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:437
llvm::DecodeVALIGNMask
void DecodeVALIGNMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:139
llvm::SM_SentinelUndef
@ SM_SentinelUndef
Definition: X86ShuffleDecode.h:28
llvm::SM_SentinelZero
@ SM_SentinelZero
Definition: X86ShuffleDecode.h:28
llvm::DecodeScalarMoveMask
void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad, SmallVectorImpl< int > &ShuffleMask)
Decode a scalar float move instruction as a shuffle mask.
Definition: X86ShuffleDecode.cpp:391
llvm::DecodePALIGNRMask
void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:125
llvm::DecodeMOVSLDUPMask
void DecodeMOVSLDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:78
llvm::DecodeSubVectorBroadcast
void DecodeSubVectorBroadcast(unsigned DstNumElts, unsigned SrcNumElts, SmallVectorImpl< int > &ShuffleMask)
Decodes a broadcast of a subvector to a larger vector type.
Definition: X86ShuffleDecode.cpp:255
llvm::DecodeUNPCKLMask
void DecodeUNPCKLMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpcklps/unpcklpd and punpckl*.
Definition: X86ShuffleDecode.cpp:234
llvm::DecodePSLLDQMask
void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:100
llvm::DecodeUNPCKHMask
void DecodeUNPCKHMask(unsigned NumElts, unsigned ScalarBits, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for unpckhps/unpckhpd and punpckh*.
Definition: X86ShuffleDecode.cpp:218
llvm::DecodePSHUFMask
void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufd/pshufw/vpermilpd/vpermilps.
Definition: X86ShuffleDecode.cpp:148
llvm::DecodeMOVDDUPMask
void DecodeMOVDDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:92
llvm::DecodeSHUFPMask
void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for shufp*.
Definition: X86ShuffleDecode.cpp:201
llvm::DecodePSHUFHWMask
void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm, SmallVectorImpl< int > &ShuffleMask)
Decodes the shuffle masks for pshufhw.
Definition: X86ShuffleDecode.cpp:164
llvm::DecodeMOVSHDUPMask
void DecodeMOVSHDUPMask(unsigned NumElts, SmallVectorImpl< int > &ShuffleMask)
Definition: X86ShuffleDecode.cpp:85
raw_ostream.h
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
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