LLVM 20.0.0git
RISCVInstrInfo.h
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1//===-- RISCVInstrInfo.h - RISC-V Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15
16#include "RISCV.h"
17#include "RISCVRegisterInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#define GET_INSTRINFO_OPERAND_ENUM
23#include "RISCVGenInstrInfo.inc"
24#include "RISCVGenRegisterInfo.inc"
25
26namespace llvm {
27
28class RISCVSubtarget;
29
34
35namespace RISCVCC {
36
45};
46
48unsigned getBrCond(CondCode CC, bool Imm = false);
49
50} // end of namespace RISCVCC
51
52// RISCV MachineCombiner patterns
60};
61
63
64public:
66
67 MCInst getNop() const override;
68 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC, bool Imm = false) const;
69
71 int &FrameIndex) const override;
72 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
73 unsigned &MemBytes) const override;
75 int &FrameIndex) const override;
76 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
77 unsigned &MemBytes) const override;
78
79 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
80
82 return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
83 MI.getOperand(1).getReg() == RISCV::X0;
84 }
85
88 MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
89 const TargetRegisterClass *RegClass) const;
91 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
92 bool KillSrc, bool RenamableDest = false,
93 bool RenamableSrc = false) const override;
94
97 bool IsKill, int FrameIndex,
98 const TargetRegisterClass *RC,
100 Register VReg) const override;
101
104 int FrameIndex, const TargetRegisterClass *RC,
105 const TargetRegisterInfo *TRI,
106 Register VReg) const override;
107
112 int FrameIndex,
113 LiveIntervals *LIS = nullptr,
114 VirtRegMap *VRM = nullptr) const override;
115
116 // Materializes the given integer Val into DstReg.
118 const DebugLoc &DL, Register DstReg, uint64_t Val,
120 bool DstRenamable = false, bool DstIsDead = false) const;
121
122 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
123
125 MachineBasicBlock *&FBB,
127 bool AllowModify) const override;
128
131 const DebugLoc &dl,
132 int *BytesAdded = nullptr) const override;
133
135 MachineBasicBlock &NewDestBB,
136 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
137 int64_t BrOffset, RegScavenger *RS) const override;
138
140 int *BytesRemoved = nullptr) const override;
141
142 bool
144
145 bool optimizeCondBranch(MachineInstr &MI) const override;
146
147 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
148
149 bool isBranchOffsetInRange(unsigned BranchOpc,
150 int64_t BrOffset) const override;
151
152 bool analyzeSelect(const MachineInstr &MI,
153 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
154 unsigned &FalseOp, bool &Optimizable) const override;
155
158 bool) const override;
159
160 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
161
162 std::optional<DestSourcePair>
163 isCopyInstrImpl(const MachineInstr &MI) const override;
164
166 StringRef &ErrInfo) const override;
167
169 const MachineInstr &AddrI,
170 ExtAddrMode &AM) const override;
171
173 const ExtAddrMode &AM) const override;
174
177 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
178 const TargetRegisterInfo *TRI) const override;
179
181 int64_t Offset1, bool OffsetIsScalable1,
183 int64_t Offset2, bool OffsetIsScalable2,
184 unsigned ClusterSize,
185 unsigned NumBytes) const override;
186
188 const MachineOperand *&BaseOp,
189 int64_t &Offset, LocationSize &Width,
190 const TargetRegisterInfo *TRI) const;
191
193 const MachineInstr &MIb) const override;
194
195
196 std::pair<unsigned, unsigned>
197 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
198
201
202 // Return true if the function can safely be outlined from.
204 bool OutlineFromLinkOnceODRs) const override;
205
206 // Return true if MBB is safe to outline from, and return any target-specific
207 // information in Flags.
209 unsigned &Flags) const override;
210
212
213 // Calculate target-specific information for a set of outlining candidates.
214 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
216 const MachineModuleInfo &MMI,
217 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
218 unsigned MinRepeats) const override;
219
220 // Return if/how a given MachineInstr should be outlined.
221 virtual outliner::InstrType
224 unsigned Flags) const override;
225
226 // Insert a custom frame for outlined functions.
228 const outliner::OutlinedFunction &OF) const override;
229
230 // Insert a call to an outlined function into a given basic block.
234 outliner::Candidate &C) const override;
235
236 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
237 Register Reg) const override;
238
239 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
240 unsigned &SrcOpIdx2) const override;
242 unsigned OpIdx1,
243 unsigned OpIdx2) const override;
244
246 LiveIntervals *LIS) const override;
247
248 // MIR printer helper function to annotate Operands with a comment.
249 std::string
251 unsigned OpIdx,
252 const TargetRegisterInfo *TRI) const override;
253
254 /// Generate code to multiply the value in DestReg by Amt - handles all
255 /// the common optimizations for this idiom, and supports fallback for
256 /// subtargets which don't support multiply instructions.
259 Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const;
260
261 bool useMachineCombiner() const override { return true; }
262
264
265 CombinerObjective getCombinerObjective(unsigned Pattern) const override;
266
269 bool DoRegPressureReduce) const override;
270
271 void
272 finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
273 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
274
276 MachineInstr &Root, unsigned Pattern,
279 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
280
281 bool hasReassociableOperands(const MachineInstr &Inst,
282 const MachineBasicBlock *MBB) const override;
283
284 bool hasReassociableSibling(const MachineInstr &Inst,
285 bool &Commuted) const override;
286
288 bool Invert) const override;
289
290 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
291
293 const MachineInstr &Root, unsigned Pattern,
294 std::array<unsigned, 5> &OperandIndices) const override;
295
298
299 unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
300
301 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
302 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
303
304protected:
306
307private:
308 unsigned getInstBundleLength(const MachineInstr &MI) const;
309
310 bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
311 bool Invert = false) const;
312 bool areRVVInstsReassociable(const MachineInstr &MI1,
313 const MachineInstr &MI2) const;
314 bool hasReassociableVectorSibling(const MachineInstr &Inst,
315 bool &Commuted) const;
316};
317
318namespace RISCV {
319
320// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
321bool isSEXT_W(const MachineInstr &MI);
322bool isZEXT_W(const MachineInstr &MI);
323bool isZEXT_B(const MachineInstr &MI);
324
325// Returns true if the given MI is an RVV instruction opcode for which we may
326// expect to see a FrameIndex operand.
327bool isRVVSpill(const MachineInstr &MI);
328
329std::optional<std::pair<unsigned, unsigned>>
330isRVVSpillForZvlsseg(unsigned Opcode);
331
332bool isFaultFirstLoad(const MachineInstr &MI);
333
334// Implemented in RISCVGenInstrInfo.inc
335int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
336
337// Return true if both input instructions have equal rounding mode. If at least
338// one of the instructions does not have rounding mode, false will be returned.
339bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
340
341// If \p Opcode is a .vx vector instruction, returns the lower number of bits
342// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
343// returns null.
344std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
345 unsigned Log2SEW);
346
347// Returns the MC opcode of RVV pseudo instruction.
348unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
349
350// For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
351// the log2 EEW of the destination operand.
352unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
353
354// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
355static constexpr int64_t VLMaxSentinel = -1LL;
356
357/// Given two VL operands, do we know that LHS <= RHS?
358bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS);
359
360// Mask assignments for floating-point
361static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
362static constexpr unsigned FPMASK_Negative_Normal = 0x002;
363static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
364static constexpr unsigned FPMASK_Negative_Zero = 0x008;
365static constexpr unsigned FPMASK_Positive_Zero = 0x010;
366static constexpr unsigned FPMASK_Positive_Subnormal = 0x020;
367static constexpr unsigned FPMASK_Positive_Normal = 0x040;
368static constexpr unsigned FPMASK_Positive_Infinity = 0x080;
369static constexpr unsigned FPMASK_Signaling_NaN = 0x100;
370static constexpr unsigned FPMASK_Quiet_NaN = 0x200;
371} // namespace RISCV
372
373namespace RISCVVPseudosTable {
374
378};
379
380#define GET_RISCVVPseudosTable_DECL
381#include "RISCVGenSearchableTables.inc"
382
383} // end namespace RISCVVPseudosTable
384
385namespace RISCV {
386
391};
392#define GET_RISCVMaskedPseudosTable_DECL
393#include "RISCVGenSearchableTables.inc"
394} // end namespace RISCV
395
396} // end namespace llvm
397#endif
SmallVector< int16_t, MAX_SRC_OPERANDS_NUM > OperandIndices
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
unsigned Reg
uint64_t IntrinsicInst * II
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Value * RHS
Value * LHS
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
This class contains meta information specific to a module.
MachineOperand class - Representation of each machine instruction operand.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override
void mulImm(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const
Generate code to multiply the value in DestReg by Amt - handles all the common optimizations for this...
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override
void copyPhysRegVector(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RegClass) const
void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC, bool Imm=false) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override
void getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const override
const RISCVSubtarget & STI
bool useMachineCombiner() const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
virtual outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
MachineTraceStrategy getMachineCombinerTraceStrategy() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
MCInst getNop() const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
CombinerObjective getCombinerObjective(unsigned Pattern) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
bool optimizeCondBranch(MachineInstr &MI) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:363
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode getOppositeBranchCondition(CondCode)
unsigned getBrCond(CondCode CC, bool Imm=false)
static constexpr unsigned FPMASK_Negative_Zero
static constexpr unsigned FPMASK_Positive_Subnormal
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)
static constexpr unsigned FPMASK_Positive_Normal
static constexpr unsigned FPMASK_Negative_Subnormal
static constexpr unsigned FPMASK_Negative_Normal
bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS)
Given two VL operands, do we know that LHS <= RHS?
std::optional< unsigned > getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW)
static constexpr unsigned FPMASK_Positive_Infinity
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
static constexpr unsigned FPMASK_Negative_Infinity
static constexpr unsigned FPMASK_Quiet_NaN
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW)
bool isSEXT_W(const MachineInstr &MI)
bool isFaultFirstLoad(const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
static constexpr unsigned FPMASK_Signaling_NaN
bool isZEXT_B(const MachineInstr &MI)
static constexpr unsigned FPMASK_Positive_Zero
bool isRVVSpill(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
bool isZEXT_W(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
RISCVMachineCombinerPattern
@ SHXADD_ADD_SLLI_OP2
@ FMADD_AX
@ FMADD_XA
@ SHXADD_ADD_SLLI_OP1
MachineTraceStrategy
Strategies for selecting traces.
static const MachineMemOperand::Flags MONontemporalBit1
static const MachineMemOperand::Flags MONontemporalBit0
CombinerObjective
The combiner's goal may differ based on which pattern it is attempting to optimize.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
Description of the encoding of one expression Op.
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.