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13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
20 #define GET_INSTRINFO_HEADER
21 #define GET_INSTRINFO_OPERAND_ENUM
22 #include "RISCVGenInstrInfo.inc"
59 bool KillSrc)
const override;
92 bool AllowModify)
const override;
97 int *BytesAdded =
nullptr)
const override;
105 int *BytesRemoved =
nullptr)
const override;
113 int64_t BrOffset)
const override;
117 unsigned &FalseOp,
bool &Optimizable)
const override;
121 bool)
const override;
125 std::optional<DestSourcePair>
140 std::pair<unsigned, unsigned>
148 bool OutlineFromLinkOnceODRs)
const override;
153 unsigned &Flags)
const override;
159 std::vector<outliner::Candidate> &RepeatedSequenceLocs)
const override;
163 unsigned Flags)
const override;
176 unsigned &SrcOpIdx2)
const override;
179 unsigned OpIdx2)
const override;
203 bool DoRegPressureReduce)
const override;
216 bool &Commuted)
const override;
219 bool Invert)
const override;
226 unsigned NBits)
const;
249 std::optional<std::pair<unsigned, unsigned>>
266 namespace RISCVVPseudosTable {
273 #define GET_RISCVVPseudosTable_DECL
274 #include "RISCVGenSearchableTables.inc"
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
This is an optimization pass for GlobalISel generic memory operations.
RISCVInstrInfo(RISCVSubtarget &STI)
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC) const
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
CondCode getOppositeBranchCondition(CondCode)
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
bool hasAllNBitUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI, unsigned NBits) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
InstrType
Represents how an instruction should be mapped by the outliner.
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
const RISCVSubtarget & STI
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
static constexpr int64_t VLMaxSentinel
Instances of this class represent a single low-level machine instruction.
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
The information necessary to create an outlined function for some class of candidate.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned const TargetRegisterInfo * TRI
bool isZEXT_W(const MachineInstr &MI)
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool isFaultFirstLoad(const MachineInstr &MI)
bool hasAllWUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool useMachineCombiner() const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
(vector float) vec_cmpeq(*A, *B) C
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isZEXT_B(const MachineInstr &MI)
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
MCInst getNop() const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)
Representation of each machine instruction.
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
An individual sequence of instructions to be replaced with a call to an outlined function.
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
A Module instance is used to store all the information related to an LLVM module.
void getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool isRVVSpill(const MachineInstr &MI)
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isSEXT_W(const MachineInstr &MI)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Wrapper class representing physical registers. Should be passed by value.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.