LLVM  17.0.0git
RISCVInstrInfo.h
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1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15 
16 #include "RISCVRegisterInfo.h"
18 #include "llvm/IR/DiagnosticInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #define GET_INSTRINFO_OPERAND_ENUM
22 #include "RISCVGenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 class RISCVSubtarget;
27 
28 namespace RISCVCC {
29 
30 enum CondCode {
38 };
39 
41 
42 } // end of namespace RISCVCC
43 
45 
46 public:
48 
49  MCInst getNop() const override;
51 
52  unsigned isLoadFromStackSlot(const MachineInstr &MI,
53  int &FrameIndex) const override;
54  unsigned isStoreToStackSlot(const MachineInstr &MI,
55  int &FrameIndex) const override;
56 
58  const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
59  bool KillSrc) const override;
60 
63  bool IsKill, int FrameIndex,
64  const TargetRegisterClass *RC,
65  const TargetRegisterInfo *TRI,
66  Register VReg) const override;
67 
70  int FrameIndex, const TargetRegisterClass *RC,
71  const TargetRegisterInfo *TRI,
72  Register VReg) const override;
73 
78  int FrameIndex,
79  LiveIntervals *LIS = nullptr,
80  VirtRegMap *VRM = nullptr) const override;
81 
82  // Materializes the given integer Val into DstReg.
84  const DebugLoc &DL, Register DstReg, uint64_t Val,
86 
87  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
88 
90  MachineBasicBlock *&FBB,
92  bool AllowModify) const override;
93 
96  const DebugLoc &dl,
97  int *BytesAdded = nullptr) const override;
98 
100  MachineBasicBlock &NewDestBB,
101  MachineBasicBlock &RestoreBB, const DebugLoc &DL,
102  int64_t BrOffset, RegScavenger *RS) const override;
103 
105  int *BytesRemoved = nullptr) const override;
106 
107  bool
109 
110  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
111 
112  bool isBranchOffsetInRange(unsigned BranchOpc,
113  int64_t BrOffset) const override;
114 
115  bool analyzeSelect(const MachineInstr &MI,
116  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
117  unsigned &FalseOp, bool &Optimizable) const override;
118 
121  bool) const override;
122 
123  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
124 
125  std::optional<DestSourcePair>
126  isCopyInstrImpl(const MachineInstr &MI) const override;
127 
128  bool verifyInstruction(const MachineInstr &MI,
129  StringRef &ErrInfo) const override;
130 
132  const MachineOperand *&BaseOp,
133  int64_t &Offset, unsigned &Width,
134  const TargetRegisterInfo *TRI) const;
135 
137  const MachineInstr &MIb) const override;
138 
139 
140  std::pair<unsigned, unsigned>
141  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
142 
145 
146  // Return true if the function can safely be outlined from.
148  bool OutlineFromLinkOnceODRs) const override;
149 
150  // Return true if MBB is safe to outline from, and return any target-specific
151  // information in Flags.
153  unsigned &Flags) const override;
154 
155  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
156 
157  // Calculate target-specific information for a set of outlining candidates.
159  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
160 
161  // Return if/how a given MachineInstr should be outlined.
163  unsigned Flags) const override;
164 
165  // Insert a custom frame for outlined functions.
167  const outliner::OutlinedFunction &OF) const override;
168 
169  // Insert a call to an outlined function into a given basic block.
173  outliner::Candidate &C) const override;
174 
175  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
176  unsigned &SrcOpIdx2) const override;
178  unsigned OpIdx1,
179  unsigned OpIdx2) const override;
180 
182  LiveIntervals *LIS) const override;
183 
184  // MIR printer helper function to annotate Operands with a comment.
185  std::string
187  unsigned OpIdx,
188  const TargetRegisterInfo *TRI) const override;
189 
192  MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg,
193  int64_t Amount, MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
194 
195  bool useMachineCombiner() const override { return true; }
196 
197  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
198  MachineInstr &NewMI1,
199  MachineInstr &NewMI2) const override;
200  bool
203  bool DoRegPressureReduce) const override;
204 
205  void
207  SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
208 
213  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
214 
215  bool hasReassociableSibling(const MachineInstr &Inst,
216  bool &Commuted) const override;
217 
218  bool isAssociativeAndCommutative(const MachineInstr &Inst,
219  bool Invert) const override;
220 
221  std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
222 
223  // Returns true if all uses of OrigMI only depend on the lower \p NBits bits
224  // of its output.
226  unsigned NBits) const;
227  // Returns true if all uses of OrigMI only depend on the lower word of its
228  // output, so we can transform OrigMI to the corresponding W-version.
230  const MachineRegisterInfo &MRI) const {
231  return hasAllNBitUsers(MI, MRI, 32);
232  }
233 
234 protected:
236 };
237 
238 namespace RISCV {
239 
240 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
241 bool isSEXT_W(const MachineInstr &MI);
242 bool isZEXT_W(const MachineInstr &MI);
243 bool isZEXT_B(const MachineInstr &MI);
244 
245 // Returns true if the given MI is an RVV instruction opcode for which we may
246 // expect to see a FrameIndex operand.
247 bool isRVVSpill(const MachineInstr &MI);
248 
249 std::optional<std::pair<unsigned, unsigned>>
250 isRVVSpillForZvlsseg(unsigned Opcode);
251 
252 bool isFaultFirstLoad(const MachineInstr &MI);
253 
254 // Implemented in RISCVGenInstrInfo.inc
255 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
256 
257 // Return true if both input instructions have equal rounding mode. If at least
258 // one of the instructions does not have rounding mode, false will be returned.
259 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
260 
261 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
262 static constexpr int64_t VLMaxSentinel = -1LL;
263 
264 } // namespace RISCV
265 
266 namespace RISCVVPseudosTable {
267 
268 struct PseudoInfo {
271 };
272 
273 #define GET_RISCVVPseudosTable_DECL
274 #include "RISCVGenSearchableTables.inc"
275 
276 } // end namespace RISCVVPseudosTable
277 
278 } // end namespace llvm
279 #endif
llvm::RISCVInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: RISCVInstrInfo.cpp:1008
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: RISCVInstrInfo.cpp:1818
llvm::RISCVInstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Definition: RISCVInstrInfo.cpp:1863
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVInstrInfo::RISCVInstrInfo
RISCVInstrInfo(RISCVSubtarget &STI)
Definition: RISCVInstrInfo.cpp:56
llvm::RISCVInstrInfo::getBrCond
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC) const
Definition: RISCVInstrInfo.cpp:766
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::RISCVCC::COND_GEU
@ COND_GEU
Definition: RISCVInstrInfo.h:36
llvm::RISCVCC::getOppositeBranchCondition
CondCode getOppositeBranchCondition(CondCode)
Definition: RISCVInstrInfo.cpp:785
llvm::RISCVCC::COND_INVALID
@ COND_INVALID
Definition: RISCVInstrInfo.h:37
llvm::RISCVInstrInfo::isCopyInstrImpl
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:1236
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::RISCVInstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
Definition: RISCVInstrInfo.cpp:1909
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::RISCV::isRVVSpillForZvlsseg
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
Definition: RISCVInstrInfo.cpp:2817
llvm::RISCVInstrInfo::hasAllNBitUsers
bool hasAllNBitUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI, unsigned NBits) const
Definition: RISCVInstrInfo.cpp:2543
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::RISCVInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Definition: RISCVInstrInfo.cpp:547
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
TargetInstrInfo.h
llvm::RISCVInstrInfo::insertIndirectBranch
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
Definition: RISCVInstrInfo.cpp:943
llvm::RISCVInstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
Definition: RISCVInstrInfo.cpp:1998
llvm::RISCVInstrInfo::STI
const RISCVSubtarget & STI
Definition: RISCVInstrInfo.h:235
llvm::RISCVInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: RISCVInstrInfo.cpp:629
llvm::RISCVVPseudosTable::PseudoInfo
Definition: RISCVInstrInfo.h:268
llvm::RISCV::VLMaxSentinel
static constexpr int64_t VLMaxSentinel
Definition: RISCVInstrInfo.h:262
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::RISCVInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:1017
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::RISCVInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: RISCVInstrInfo.cpp:69
llvm::RISCVInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: RISCVInstrInfo.cpp:1024
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::RISCV::isZEXT_W
bool isZEXT_W(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2767
RISCVGenInstrInfo
llvm::RISCVInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: RISCVInstrInfo.cpp:2375
llvm::RISCV::isFaultFirstLoad
bool isFaultFirstLoad(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2857
llvm::RISCVVPseudosTable::PseudoInfo::BaseInstr
uint16_t BaseInstr
Definition: RISCVInstrInfo.h:270
llvm::RISCVInstrInfo::hasAllWUsers
bool hasAllWUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Definition: RISCVInstrInfo.h:229
llvm::RISCVInstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: RISCVInstrInfo.h:195
llvm::RISCVCC::COND_LT
@ COND_LT
Definition: RISCVInstrInfo.h:33
llvm::RISCVInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: RISCVInstrInfo.cpp:2085
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::RISCVInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: RISCVInstrInfo.cpp:804
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RISCVCC::COND_LTU
@ COND_LTU
Definition: RISCVInstrInfo.h:35
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
llvm::RISCVInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: RISCVInstrInfo.cpp:1812
llvm::RISCVInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: RISCVInstrInfo.cpp:872
llvm::RISCV::isZEXT_B
bool isZEXT_B(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2773
llvm::RISCVInstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: RISCVInstrInfo.cpp:1128
llvm::RISCVInstrInfo::getNop
MCInst getNop() const override
Definition: RISCVInstrInfo.cpp:60
llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: RISCVInstrInfo.cpp:1780
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVInstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Definition: RISCVInstrInfo.cpp:1488
llvm::RISCV::hasEqualFRM
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)
Definition: RISCVInstrInfo.cpp:2862
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::RISCVInstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: RISCVInstrInfo.cpp:1835
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::RISCVCC::COND_EQ
@ COND_EQ
Definition: RISCVInstrInfo.h:31
llvm::DenseMap< unsigned, unsigned >
llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Definition: RISCVInstrInfo.cpp:1757
llvm::RISCVInstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: RISCVInstrInfo.cpp:1852
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::RISCV::getNamedOperandIdx
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
llvm::RISCVInstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
Definition: RISCVInstrInfo.cpp:1260
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::RISCVInstrInfo::analyzeSelect
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
Definition: RISCVInstrInfo.cpp:1104
llvm::RISCVInstrInfo::createMIROperandComment
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
Definition: RISCVInstrInfo.cpp:2011
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::RISCVInstrInfo::getVLENFactoredAmount
void getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
Definition: RISCVInstrInfo.cpp:2451
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::RISCVInstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
Definition: RISCVInstrInfo.cpp:1351
llvm::ArrayRef< unsigned >
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm::RISCVInstrInfo::movImm
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
Definition: RISCVInstrInfo.cpp:687
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVInstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
Definition: RISCVInstrInfo.cpp:1571
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::RISCVInstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: RISCVInstrInfo.cpp:1970
llvm::RISCVInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
Definition: RISCVInstrInfo.cpp:906
llvm::RISCVInstrInfo::getInverseOpcode
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
Definition: RISCVInstrInfo.cpp:1404
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVInstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: RISCVInstrInfo.cpp:1868
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
DiagnosticInfo.h
llvm::RISCV::isRVVSpill
bool isRVVSpill(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2806
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::RISCVInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: RISCVInstrInfo.cpp:96
llvm::RISCVCC::COND_GE
@ COND_GE
Definition: RISCVInstrInfo.h:34
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::RISCVInstrInfo::isAsCheapAsAMove
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:1214
llvm::RISCVInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: RISCVInstrInfo.cpp:2230
llvm::RISCVVPseudosTable::PseudoInfo::Pseudo
uint16_t Pseudo
Definition: RISCVInstrInfo.h:269
llvm::RISCVInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
Definition: RISCVInstrInfo.cpp:257
llvm::RISCVCC::CondCode
CondCode
Definition: RISCVInstrInfo.h:30
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1265
llvm::RISCVInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: RISCVInstrInfo.cpp:1597
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::RISCVInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override
Definition: RISCVInstrInfo.cpp:1332
llvm::RISCVInstrInfo::finalizeInsInstrs
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Definition: RISCVInstrInfo.cpp:1269
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::RISCVInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Definition: RISCVInstrInfo.cpp:463
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::RISCV::isSEXT_W
bool isSEXT_W(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2761
llvm::RISCVInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: RISCVInstrInfo.cpp:1193
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
RISCVRegisterInfo.h
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::RISCVCC::COND_NE
@ COND_NE
Definition: RISCVInstrInfo.h:32