LLVM  10.0.0svn
RISCVInstrInfo.h
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1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15 
16 #include "RISCVRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "RISCVGenInstrInfo.inc"
21 
22 namespace llvm {
23 
25 
26 public:
28 
29  unsigned isLoadFromStackSlot(const MachineInstr &MI,
30  int &FrameIndex) const override;
31  unsigned isStoreToStackSlot(const MachineInstr &MI,
32  int &FrameIndex) const override;
33 
35  const DebugLoc &DL, unsigned DstReg, unsigned SrcReg,
36  bool KillSrc) const override;
37 
39  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
40  bool IsKill, int FrameIndex,
41  const TargetRegisterClass *RC,
42  const TargetRegisterInfo *TRI) const override;
43 
45  MachineBasicBlock::iterator MBBI, unsigned DstReg,
46  int FrameIndex, const TargetRegisterClass *RC,
47  const TargetRegisterInfo *TRI) const override;
48 
49  // Materializes the given integer Val into DstReg.
51  const DebugLoc &DL, Register DstReg, uint64_t Val,
53 
54  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
55 
57  MachineBasicBlock *&FBB,
59  bool AllowModify) const override;
60 
63  const DebugLoc &dl,
64  int *BytesAdded = nullptr) const override;
65 
67  MachineBasicBlock &NewDestBB,
68  const DebugLoc &DL, int64_t BrOffset,
69  RegScavenger *RS = nullptr) const override;
70 
71  unsigned removeBranch(MachineBasicBlock &MBB,
72  int *BytesRemoved = nullptr) const override;
73 
74  bool
76 
77  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
78 
79  bool isBranchOffsetInRange(unsigned BranchOpc,
80  int64_t BrOffset) const override;
81 
82  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
83 };
84 }
85 #endif
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, bool KillSrc) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
IRTranslator LLVM IR MI
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19