llvm::RISCVSubtarget Class Reference

#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:

Public Types
enum	RISCVProcFamilyEnum : uint8_t { Others , SiFive7 , VentanaVeyron , MIPSP8700 }

Public Member Functions
	RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
	~RISCVSubtarget () override
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVFrameLowering *	getFrameLowering () const override
const RISCVInstrInfo *	getInstrInfo () const override
const RISCVRegisterInfo *	getRegisterInfo () const override
const RISCVTargetLowering *	getTargetLowering () const override
bool	enableMachineScheduler () const override
bool	enablePostRAScheduler () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
RISCVProcFamilyEnum	getProcFamily () const
	Returns RISC-V processor family.
bool	hasStdExtCOrZca () const
bool	hasStdExtCOrZcd () const
bool	hasStdExtCOrZcfOrZce () const
bool	hasStdExtZvl () const
bool	hasStdExtFOrZfinx () const
bool	hasStdExtDOrZdinx () const
bool	hasStdExtZfhOrZhinx () const
bool	hasStdExtZfhminOrZhinxmin () const
bool	hasHalfFPLoadStoreMove () const
bool	hasConditionalMoveFusion () const
bool	is64Bit () const
MVT	getXLenVT () const
unsigned	getXLen () const
bool	useLoadStorePairs () const
bool	useCCMovInsn () const
unsigned	getFLen () const
unsigned	getELen () const
unsigned	getRealMinVLen () const
unsigned	getRealMaxVLen () const
std::optional< unsigned >	getRealVLen () const
template<typename Quantity >
Quantity	expandVScale (Quantity X) const
	If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted to a fixed quantity.
RISCVABI::ABI	getTargetABI () const
bool	isSoftFPABI () const
bool	isRegisterReservedByUser (Register i) const override
bool	isXRaySupported () const override
bool	hasVInstructions () const
bool	hasVInstructionsI64 () const
bool	hasVInstructionsF16Minimal () const
bool	hasVInstructionsF16 () const
bool	hasVInstructionsBF16Minimal () const
bool	hasVInstructionsF32 () const
bool	hasVInstructionsF64 () const
bool	hasVInstructionsAnyF () const
bool	hasVInstructionsFullMultiply () const
unsigned	getMaxInterleaveFactor () const
bool	hasOptimizedSegmentLoadStore (unsigned NF) const
unsigned	getDLenFactor () const
const SelectionDAGTargetInfo *	getSelectionDAGInfo () const override
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RISCVRegisterBankInfo *	getRegBankInfo () const override
bool	isTargetAndroid () const
bool	isTargetFuchsia () const
bool	useConstantPoolForLargeInts () const
unsigned	getMaxBuildIntsCost () const
unsigned	getMaxLMULForFixedLengthVectors () const
bool	useRVVForFixedLengthVectors () const
bool	enableSubRegLiveness () const override
bool	enableMachinePipeliner () const override
bool	useDFAforSMS () const override
bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
unsigned	getCacheLineSize () const override
unsigned	getPrefetchDistance () const override
unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
unsigned	getMaxPrefetchIterationsAhead () const override
unsigned	getMinimumJumpTableEntries () const
unsigned	getTailDupAggressiveThreshold () const
unsigned	getMaxStoresPerMemset (bool OptSize) const
unsigned	getMaxGluedStoresPerMemcpy () const
unsigned	getMaxStoresPerMemcpy (bool OptSize) const
unsigned	getMaxStoresPerMemmove (bool OptSize) const
unsigned	getMaxLoadsPerMemcmp (bool OptSize) const
MISched::Direction	getPostRASchedDirection () const
void	overrideSchedPolicy (MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
void	overridePostRASchedPolicy (MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override

Protected Member Functions
unsigned	getMaxRVVVectorSizeInBits () const
unsigned	getMinRVVVectorSizeInBits () const

Protected Attributes
std::unique_ptr< const SelectionDAGTargetInfo >	TSInfo
std::unique_ptr< CallLowering >	CallLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RISCVRegisterBankInfo >	RegBankInfo

Detailed Description

Definition at line 78 of file RISCVSubtarget.h.

Member Enumeration Documentation

RISCVProcFamilyEnum

enum llvm::RISCVSubtarget::RISCVProcFamilyEnum : uint8_t

Enumerator
Others
SiFive7
VentanaVeyron
MIPSP8700

Definition at line 81 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget	(	const Triple &	TT,
		StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS,
		StringRef	ABIName,
		unsigned	RVVVectorBitsMin,
		unsigned	RVVVectorLMULMax,
		const TargetMachine &	TM
	)

Definition at line 100 of file RISCVSubtarget.cpp.

References TSInfo.

~RISCVSubtarget()

RISCVSubtarget::~RISCVSubtarget ( )

overridedefault

Member Function Documentation

enableMachinePipeliner()

bool RISCVSubtarget::enableMachinePipeliner ( ) const

override

Definition at line 206 of file RISCVSubtarget.cpp.

enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const

inlineoverride

Definition at line 141 of file RISCVSubtarget.h.

enablePostRAScheduler()

bool llvm::RISCVSubtarget::enablePostRAScheduler ( ) const

inlineoverride

Definition at line 143 of file RISCVSubtarget.h.

enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const

override

Definition at line 204 of file RISCVSubtarget.cpp.

expandVScale()

template<typename Quantity >

Quantity llvm::RISCVSubtarget::expandVScale ( Quantity  X ) const

inline

If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted to a fixed quantity.

Otherwise returns X unmodified.

Definition at line 225 of file RISCVSubtarget.h.

References getRealVLen(), llvm::RISCV::RVVBitsPerBlock, and X.

Referenced by llvm::RISCVDAGToDAGISel::Select().

getCacheLineSize()

unsigned llvm::RISCVSubtarget::getCacheLineSize ( ) const

inlineoverride

Definition at line 335 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::CacheLineSize.

getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const

override

Definition at line 119 of file RISCVSubtarget.cpp.

References CallLoweringInfo, and getTargetLowering().

getDLenFactor()

unsigned llvm::RISCVSubtarget::getDLenFactor ( ) const

inline

Definition at line 285 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getLMULCost().

getELen()

unsigned llvm::RISCVSubtarget::getELen ( ) const

inline

Definition at line 202 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

Referenced by combineBinOpOfExtractToReduceTree(), llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), getContainerForFixedLengthVector(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVTTIImpl::getShuffleCost(), getWideningInterleave(), isInterleaveShuffle(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), lowerGetVectorLength(), lowerVECTOR_SHUFFLE(), performVECTOR_SHUFFLECombine(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const

inline

Definition at line 193 of file RISCVSubtarget.h.

Referenced by lowerBUILD_VECTOR().

getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 130 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::emitDynamicProbedAlloc(), and llvm::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo().

getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 133 of file RISCVSubtarget.h.

Referenced by llvm::RISCVFrameLowering::allocateStack(), llvm::RISCVTargetLowering::emitDynamicProbedAlloc(), llvm::RISCVFrameLowering::emitEpilogue(), emitFROUND(), EmitLoweredCascadedSelect(), llvm::RISCVFrameLowering::emitPrologue(), emitSelectPseudo(), llvm::RISCVCallLowering::lowerCall(), lowerRISCVVMachineInstrToMCInst(), llvm::RISCVRegisterInfo::lowerVRELOAD(), and llvm::RISCVRegisterInfo::lowerVSPILL().

getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const

override

Definition at line 125 of file RISCVSubtarget.cpp.

References llvm::createRISCVInstructionSelector(), getRegBankInfo(), llvm::TargetLoweringBase::getTargetMachine(), and InstSelector.

getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const

override

Definition at line 134 of file RISCVSubtarget.cpp.

getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost

(

)

const

Definition at line 150 of file RISCVSubtarget.cpp.

References RISCVMaxBuildIntsCost.

Referenced by lowerConstant(), and llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm().

getMaxGluedStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxGluedStoresPerMemcpy ( ) const

inline

Definition at line 362 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxGluedStoresPerMemcpy.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 258 of file RISCVSubtarget.h.

References hasVInstructions().

getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors

(

)

const

Definition at line 190 of file RISCVSubtarget.cpp.

References assert(), llvm::bit_floor(), hasVInstructions(), and RVVVectorLMULMax.

Referenced by llvm::RISCVTTIImpl::isLegalMaskedExpandLoad(), and useRVVForFixedLengthVectorVT().

getMaxLoadsPerMemcmp()

unsigned llvm::RISCVSubtarget::getMaxLoadsPerMemcmp ( bool  OptSize ) const

inline

Definition at line 376 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxLoadsPerMemcmp, and llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxLoadsPerMemcmpOptSize.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getMaxPrefetchIterationsAhead()

unsigned llvm::RISCVSubtarget::getMaxPrefetchIterationsAhead ( ) const

inlineoverride

Definition at line 347 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxPrefetchIterationsAhead.

getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const

protected

Definition at line 161 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

getMaxStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemcpy ( bool  OptSize ) const

inline

Definition at line 366 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxStoresPerMemcpy, and llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxStoresPerMemcpyOptSize.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getMaxStoresPerMemmove()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemmove ( bool  OptSize ) const

inline

Definition at line 371 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxStoresPerMemmove, and llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxStoresPerMemmoveOptSize.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getMaxStoresPerMemset()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemset ( bool  OptSize ) const

inline

Definition at line 357 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxStoresPerMemset, and llvm::RISCVTuneInfoTable::RISCVTuneInfo::MaxStoresPerMemsetOptSize.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getMinimumJumpTableEntries()

unsigned RISCVSubtarget::getMinimumJumpTableEntries

(

)

const

Definition at line 214 of file RISCVSubtarget.cpp.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MinimumJumpTableEntries, and RISCVMinimumJumpTableEntries.

getMinPrefetchStride()

unsigned llvm::RISCVSubtarget::getMinPrefetchStride ( unsigned  NumMemAccesses, unsigned  NumStridedMemAccesses, unsigned  NumPrefetches, bool  HasCall  ) const

inlineoverride

Definition at line 341 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::MinPrefetchStride.

getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const

protected

Definition at line 174 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMinVLen(), and useRVVForFixedLengthVectors().

getPostRASchedDirection()

MISched::Direction llvm::RISCVSubtarget::getPostRASchedDirection ( ) const

inline

Definition at line 381 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PostRASchedDirection.

Referenced by overridePostRASchedPolicy().

getPrefetchDistance()

unsigned llvm::RISCVSubtarget::getPrefetchDistance ( ) const

inlineoverride

Definition at line 338 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PrefetchDistance.

getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const

inline

Definition at line 145 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PrefFunctionAlignment.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const

inline

Definition at line 148 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::PrefLoopAlignment.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const

inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 156 of file RISCVSubtarget.h.

getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const

inline

Definition at line 210 of file RISCVSubtarget.h.

References getMaxRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTargetLowering::computeVLMAXBounds(), llvm::RISCVTTIImpl::getMaxVScale(), getRealVLen(), and llvm::RISCVTTIImpl::getShuffleCost().

getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const

inline

Definition at line 206 of file RISCVSubtarget.h.

References getMinRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTargetLowering::computeVLMAXBounds(), getContainerForFixedLengthVector(), llvm::RISCVTargetLowering::getLMULCost(), llvm::RISCVTargetLowering::getOptimalMemOpType(), getRealVLen(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTTIImpl::getShuffleCost(), getSmallestVTForIndex(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::RISCVTTIImpl::isLegalMaskedExpandLoad(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), and useRVVForFixedLengthVectorVT().

getRealVLen()

std::optional< unsigned > llvm::RISCVSubtarget::getRealVLen ( ) const

inline

Definition at line 215 of file RISCVSubtarget.h.

References getRealMaxVLen(), and getRealMinVLen().

Referenced by expandVScale(), llvm::RISCVTTIImpl::getVectorInstrCost(), lowerBUILD_VECTOR(), lowerShuffleViaVRegSplitting(), llvm::RISCVRegisterInfo::lowerVRELOAD(), llvm::RISCVRegisterInfo::lowerVSPILL(), and llvm::RISCVDAGToDAGISel::selectVSETVLI().

getRegBankInfo()

const RISCVRegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const

override

Definition at line 140 of file RISCVSubtarget.cpp.

References RegBankInfo.

Referenced by getInstructionSelector(), and llvm::RISCVCallLowering::lowerCall().

getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const

inlineoverride

Definition at line 134 of file RISCVSubtarget.h.

Referenced by llvm::RISCVFrameLowering::allocateStack(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVInstrInfo::copyPhysRegVector(), llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr(), llvm::RISCVFrameLowering::emitEpilogue(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVFrameLowering::hasBP(), isConvertibleToVMV_V_V(), llvm::RISCVCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), lowerRISCVVMachineInstrToMCInst(), llvm::RISCVRegisterInfo::lowerVRELOAD(), llvm::RISCVRegisterInfo::lowerVSPILL(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVDAGToDAGISel::Select().

getSelectionDAGInfo()

const SelectionDAGTargetInfo * RISCVSubtarget::getSelectionDAGInfo ( ) const

override

Definition at line 115 of file RISCVSubtarget.cpp.

References TSInfo.

getTailDupAggressiveThreshold()

unsigned llvm::RISCVSubtarget::getTailDupAggressiveThreshold ( ) const

inline

Definition at line 353 of file RISCVSubtarget.h.

References llvm::RISCVTuneInfoTable::RISCVTuneInfo::TailDupAggressiveThreshold.

Referenced by llvm::RISCVInstrInfo::getTailDuplicateSize().

getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const

inline

Definition at line 233 of file RISCVSubtarget.h.

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 137 of file RISCVSubtarget.h.

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), llvm::RISCVTargetLowering::emitDynamicProbedAlloc(), getCallLowering(), isLegalBitRotate(), lowerBitreverseShuffle(), and llvm::RISCVDAGToDAGISel::Select().

getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const

inline

Definition at line 188 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), combineSelectAndUse(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(), llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVInstrInfo::foldMemoryOperandImpl(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVTTIImpl::getIntImmCostInst(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getVectorInstrCost(), llvm::RISCVDAGToDAGISel::hasAllNBitUsers(), llvm::RISCVInstrInfo::isBranchOffsetInRange(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), lowerFABSorFNEG(), lowerFCOPYSIGN(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::lowerInterleavedLoad(), llvm::RISCVTargetLowering::lowerInterleavedStore(), llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore(), performBITREVERSECombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectShiftMaskXLen(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm(), llvm::RISCVTargetLowering::shouldExtendTypeInLibCall(), transformAddImmMulImm(), and transformAddShlImm().

getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const

inline

Definition at line 185 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), buildDefaultVLOps(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), combine_CC(), combineScalarCTPOPToVCPOP(), combineSubShiftToOrcB(), llvm::RISCVTargetLowering::computeVLMax(), convertFromScalableVector(), expandMul(), getDefaultScalableVLOps(), getDefaultVLOps(), getVSlidedown(), getVSlideup(), getWideningInterleave(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::RISCVTargetLowering::LowerCall(), lowerCttzElts(), lowerDisjointIndicesShuffle(), lowerFABSorFNEG(), lowerFCOPYSIGN(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), matchSplatAsGather(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performSRACombine(), performVECTOR_SHUFFLECombine(), performVP_REVERSECombine(), performVP_STORECombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), promoteVCIXScalar(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::RISCVDAGToDAGISel::selectRVVSimm5(), llvm::RISCVDAGToDAGISel::selectScalarFPAsInt(), llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), selectVSplatImmHelper(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), and tryMemPairCombine().

hasConditionalMoveFusion()

bool llvm::RISCVSubtarget::hasConditionalMoveFusion ( ) const

inline

Definition at line 178 of file RISCVSubtarget.h.

References hasStdExtCOrZca().

Referenced by combineSelectAndUse(), combineSelectToBinOp(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::PerformDAGCombine(), and performSELECTCombine().

hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const

inline

Definition at line 174 of file RISCVSubtarget.h.

hasOptimizedSegmentLoadStore()

bool llvm::RISCVSubtarget::hasOptimizedSegmentLoadStore ( unsigned  NF ) const

inline

Definition at line 262 of file RISCVSubtarget.h.

References llvm_unreachable.

Referenced by llvm::RISCVTTIImpl::getInterleavedMemoryOpCost(), llvm::RISCVTargetLowering::lowerInterleavedLoad(), and llvm::RISCVTargetLowering::lowerInterleavedStore().

hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const

inline

Definition at line 162 of file RISCVSubtarget.h.

Referenced by estimateFunctionSizeInBytes(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVInstrInfo::getInstSizeInBytes(), llvm::RISCVInstrInfo::getNop(), hasConditionalMoveFusion(), isCompressibleLoad(), isCompressibleStore(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtCOrZcd()

bool llvm::RISCVSubtarget::hasStdExtCOrZcd ( ) const

inline

Definition at line 163 of file RISCVSubtarget.h.

Referenced by isCompressibleLoad(), and isCompressibleStore().

hasStdExtCOrZcfOrZce()

bool llvm::RISCVSubtarget::hasStdExtCOrZcfOrZce ( ) const

inline

Definition at line 164 of file RISCVSubtarget.h.

Referenced by isCompressibleLoad(), and isCompressibleStore().

hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const

inline

Definition at line 169 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const

inline

Definition at line 168 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZfhminOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhminOrZhinxmin ( ) const

inline

Definition at line 171 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const

inline

Definition at line 170 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), lowerFP_TO_INT(), lowerFP_TO_INT_SAT(), lowerINT_TO_FP(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const

inline

Definition at line 167 of file RISCVSubtarget.h.

hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const

inline

Definition at line 248 of file RISCVSubtarget.h.

Referenced by llvm::RISCVCallLowering::canLowerReturn(), llvm::RISCVTTIImpl::canSplatOperand(), combineBinOpOfExtractToReduceTree(), llvm::RISCVTTIImpl::getCastInstrCost(), getELen(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), getMaxInterleaveFactor(), getMaxLMULForFixedLengthVectors(), getMaxRVVVectorSizeInBits(), llvm::RISCVTTIImpl::getMaxVScale(), getMinRVVVectorSizeInBits(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), getScavSlotsNumForRVV(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTTIImpl::hasActiveVectorLength(), llvm::RISCVTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::RISCVTTIImpl::isProfitableToSinkOperands(), isSupportedArgumentType(), isSupportedReturnType(), llvm::RISCVTargetLowering::isTruncateFree(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), llvm::RISCVTargetLowering::shouldExpandCttzElements(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), and useRVVForFixedLengthVectors().

hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const

inline

Definition at line 256 of file RISCVSubtarget.h.

References hasVInstructionsF32().

hasVInstructionsBF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsBF16Minimal ( ) const

inline

Definition at line 252 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const

inline

Definition at line 251 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), isLegalElementTypeForRVV(), isPromotedOpNeedingSplit(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLEAsVSlide1(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasVInstructionsF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsF16Minimal ( ) const

inline

Definition at line 250 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isPromotedOpNeedingSplit(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const

inline

Definition at line 253 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), hasVInstructionsAnyF(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const

inline

Definition at line 254 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const

inline

Definition at line 257 of file RISCVSubtarget.h.

hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const

inline

Definition at line 249 of file RISCVSubtarget.h.

Referenced by getELen(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const

inline

Definition at line 184 of file RISCVSubtarget.h.

Referenced by llvm::RISCVFrameLowering::allocateStack(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), llvm::CC_RISCV_FastCC(), llvm::CC_RISCV_GHC(), llvm::RISCVTargetLowering::emitDynamicProbedAlloc(), emitFROUND(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTTIImpl::enableMemCmpExpansion(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVInstrInfo::getInstSizeInBytes(), llvm::RISCVTargetLowering::getJumpTableEncoding(), llvm::RISCVTargetLowering::getNumRegisters(), getPACKOpcode(), llvm::RISCVTTIImpl::getPopcntSupport(), llvm::RISCVTargetLowering::getPostIndexedAddressParts(), llvm::RISCVTTIImpl::getPreferredAddressingMode(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), getXLen(), getXLenVT(), llvm::RISCVTargetLowering::isCheapToSpeculateCtlz(), llvm::RISCVTargetLowering::isCheapToSpeculateCttz(), isCompressibleLoad(), isCompressibleStore(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::isSExtCheaperThanZExt(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVInstrInfo::movImm(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSIGN_EXTEND_INREGCombine(), performTRUNCATECombine(), performXORCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), selectConstantAddr(), llvm::RISCVDAGToDAGISel::selectScalarFPAsInt(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall(), llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(), llvm::RISCVTargetLowering::signExtendConstant(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), and llvm::RISCVInstrInfo::verifyInstruction().

isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register  i ) const

inlineoverride

Definition at line 239 of file RISCVSubtarget.h.

References assert().

Referenced by llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), and llvm::RISCVTargetLowering::LowerReturn().

isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const

inline

Definition at line 234 of file RISCVSubtarget.h.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVTargetLowering::shouldExtendTypeInLibCall().

isTargetAndroid()

bool llvm::RISCVSubtarget::isTargetAndroid ( ) const

inline

Definition at line 315 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const

inline

Definition at line 316 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

isXRaySupported()

bool llvm::RISCVSubtarget::isXRaySupported ( ) const

inlineoverride

Definition at line 245 of file RISCVSubtarget.h.

overridePostRASchedPolicy()

void RISCVSubtarget::overridePostRASchedPolicy ( MachineSchedPolicy &  Policy, unsigned  NumRegionInstrs  ) const

override

Definition at line 236 of file RISCVSubtarget.cpp.

References llvm::MISched::Bidirectional, llvm::MISched::BottomUp, getPostRASchedDirection(), llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, and llvm::MISched::TopDown.

overrideSchedPolicy()

void RISCVSubtarget::overrideSchedPolicy ( MachineSchedPolicy &  Policy, unsigned  NumRegionInstrs  ) const

override

Definition at line 220 of file RISCVSubtarget.cpp.

References llvm::MachineSchedPolicy::DisableLatencyHeuristic, llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, and llvm::MachineSchedPolicy::ShouldTrackPressure.

ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS
	)

useAA()

bool RISCVSubtarget::useAA ( ) const

override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 212 of file RISCVSubtarget.cpp.

References UseAA.

useCCMovInsn()

bool RISCVSubtarget::useCCMovInsn

(

)

const

Definition at line 251 of file RISCVSubtarget.cpp.

References UseCCMovInsn.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts

(

)

const

Definition at line 146 of file RISCVSubtarget.cpp.

References RISCVDisableUsingConstantPoolForLargeInts.

Referenced by lowerConstant().

useDFAforSMS()

bool llvm::RISCVSubtarget::useDFAforSMS ( ) const

inlineoverride

Definition at line 331 of file RISCVSubtarget.h.

useLoadStorePairs()

bool llvm::RISCVSubtarget::useLoadStorePairs

(

)

const

useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors

(

)

const

Definition at line 199 of file RISCVSubtarget.cpp.

References getMinRVVVectorSizeInBits(), hasVInstructions(), and llvm::RISCV::RVVBitsPerBlock.

Referenced by llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

Member Data Documentation

CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo

mutableprotected

Definition at line 296 of file RISCVSubtarget.h.

Referenced by getCallLowering().

InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector

mutableprotected

Definition at line 297 of file RISCVSubtarget.h.

Referenced by getInstructionSelector().

Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer

mutableprotected

Definition at line 298 of file RISCVSubtarget.h.

RegBankInfo

std::unique_ptr<RISCVRegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo

mutableprotected

Definition at line 299 of file RISCVSubtarget.h.

Referenced by getRegBankInfo().

TSInfo

std::unique_ptr<const SelectionDAGTargetInfo> llvm::RISCVSubtarget::TSInfo

protected

Definition at line 293 of file RISCVSubtarget.h.

Referenced by getSelectionDAGInfo(), and RISCVSubtarget().

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVSubtarget.h
• lib/Target/RISCV/RISCVSubtarget.cpp