LLVM 19.0.0git
Public Types | Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::RISCVSubtarget Class Reference

#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:
Inheritance graph
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Public Types

enum  RISCVProcFamilyEnum : uint8_t { Others , SiFive7 , VentanaVeyron }
 

Public Member Functions

 RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
 
void ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
 
const RISCVFrameLoweringgetFrameLowering () const override
 
const RISCVInstrInfogetInstrInfo () const override
 
const RISCVRegisterInfogetRegisterInfo () const override
 
const RISCVTargetLoweringgetTargetLowering () const override
 
const SelectionDAGTargetInfogetSelectionDAGInfo () const override
 
bool enableMachineScheduler () const override
 
bool enablePostRAScheduler () const override
 
Align getPrefFunctionAlignment () const
 
Align getPrefLoopAlignment () const
 
RISCVProcFamilyEnum getProcFamily () const
 Returns RISC-V processor family.
 
bool hasStdExtCOrZca () const
 
bool hasStdExtCOrZcd () const
 
bool hasStdExtCOrZcfOrZce () const
 
bool hasStdExtZvl () const
 
bool hasStdExtFOrZfinx () const
 
bool hasStdExtDOrZdinx () const
 
bool hasStdExtZfhOrZhinx () const
 
bool hasStdExtZfhminOrZhinxmin () const
 
bool hasHalfFPLoadStoreMove () const
 
bool hasConditionalMoveFusion () const
 
bool is64Bit () const
 
MVT getXLenVT () const
 
unsigned getXLen () const
 
unsigned getFLen () const
 
unsigned getELen () const
 
unsigned getRealMinVLen () const
 
unsigned getRealMaxVLen () const
 
std::optional< unsignedgetRealVLen () const
 
RISCVABI::ABI getTargetABI () const
 
bool isSoftFPABI () const
 
bool isRegisterReservedByUser (Register i) const
 
bool hasVInstructions () const
 
bool hasVInstructionsI64 () const
 
bool hasVInstructionsF16Minimal () const
 
bool hasVInstructionsF16 () const
 
bool hasVInstructionsBF16 () const
 
bool hasVInstructionsF32 () const
 
bool hasVInstructionsF64 () const
 
bool hasVInstructionsAnyF () const
 
bool hasVInstructionsFullMultiply () const
 
unsigned getMaxInterleaveFactor () const
 
unsigned getDLenFactor () const
 
const CallLoweringgetCallLowering () const override
 
InstructionSelectorgetInstructionSelector () const override
 
const LegalizerInfogetLegalizerInfo () const override
 
const RegisterBankInfogetRegBankInfo () const override
 
bool isTargetFuchsia () const
 
bool useConstantPoolForLargeInts () const
 
unsigned getMaxBuildIntsCost () const
 
unsigned getMaxLMULForFixedLengthVectors () const
 
bool useRVVForFixedLengthVectors () const
 
bool enableSubRegLiveness () const override
 
void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
 
bool useAA () const override
 Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
 
unsigned getCacheLineSize () const override
 
unsigned getPrefetchDistance () const override
 
unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
 
unsigned getMaxPrefetchIterationsAhead () const override
 
unsigned getMinimumJumpTableEntries () const
 
bool supportsInitUndef () const override
 

Protected Member Functions

unsigned getMaxRVVVectorSizeInBits () const
 
unsigned getMinRVVVectorSizeInBits () const
 

Protected Attributes

std::unique_ptr< CallLoweringCallLoweringInfo
 
std::unique_ptr< InstructionSelectorInstSelector
 
std::unique_ptr< LegalizerInfoLegalizer
 
std::unique_ptr< RegisterBankInfoRegBankInfo
 

Detailed Description

Definition at line 59 of file RISCVSubtarget.h.

Member Enumeration Documentation

◆ RISCVProcFamilyEnum

Enumerator
Others 
SiFive7 
VentanaVeyron 

Definition at line 62 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

◆ RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget ( const Triple TT,
StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS,
StringRef  ABIName,
unsigned  RVVVectorBitsMin,
unsigned  RVVVectorLMULMax,
const TargetMachine TM 
)

Member Function Documentation

◆ enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const
inlineoverride

Definition at line 122 of file RISCVSubtarget.h.

◆ enablePostRAScheduler()

bool llvm::RISCVSubtarget::enablePostRAScheduler ( ) const
inlineoverride

Definition at line 124 of file RISCVSubtarget.h.

◆ enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const
override

Definition at line 186 of file RISCVSubtarget.cpp.

References EnableSubRegLiveness.

◆ getCacheLineSize()

unsigned llvm::RISCVSubtarget::getCacheLineSize ( ) const
inlineoverride

◆ getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const
override

Definition at line 113 of file RISCVSubtarget.cpp.

References CallLoweringInfo.

◆ getDLenFactor()

unsigned llvm::RISCVSubtarget::getDLenFactor ( ) const
inline

Definition at line 231 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getLMULCost().

◆ getELen()

unsigned llvm::RISCVSubtarget::getELen ( ) const
inline

◆ getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const
inline

Definition at line 174 of file RISCVSubtarget.h.

Referenced by lowerBUILD_VECTOR().

◆ getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const
inlineoverride

Definition at line 109 of file RISCVSubtarget.h.

◆ getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const
inlineoverride

◆ getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const
override

Definition at line 117 of file RISCVSubtarget.cpp.

References InstSelector.

◆ getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const
override

Definition at line 121 of file RISCVSubtarget.cpp.

◆ getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost ( ) const

◆ getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const
inline

Definition at line 225 of file RISCVSubtarget.h.

References hasVInstructions().

◆ getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors ( ) const

◆ getMaxPrefetchIterationsAhead()

unsigned llvm::RISCVSubtarget::getMaxPrefetchIterationsAhead ( ) const
inlineoverride

◆ getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const
protected

Definition at line 144 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

◆ getMinimumJumpTableEntries()

unsigned RISCVSubtarget::getMinimumJumpTableEntries ( ) const

◆ getMinPrefetchStride()

unsigned llvm::RISCVSubtarget::getMinPrefetchStride ( unsigned  NumMemAccesses,
unsigned  NumStridedMemAccesses,
unsigned  NumPrefetches,
bool  HasCall 
) const
inlineoverride

◆ getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const
protected

◆ getPostRAMutations()

void RISCVSubtarget::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation > > &  Mutations) const
override

Definition at line 192 of file RISCVSubtarget.cpp.

References llvm::createMacroFusionDAGMutation().

◆ getPrefetchDistance()

unsigned llvm::RISCVSubtarget::getPrefetchDistance ( ) const
inlineoverride

◆ getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const
inline

◆ getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const
inline

◆ getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const
inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 139 of file RISCVSubtarget.h.

◆ getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const
inline

◆ getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const
inline

◆ getRealVLen()

std::optional< unsigned > llvm::RISCVSubtarget::getRealVLen ( ) const
inline

◆ getRegBankInfo()

const RegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const
override

Definition at line 125 of file RISCVSubtarget.cpp.

References RegBankInfo.

Referenced by llvm::RISCVCallLowering::lowerCall().

◆ getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const
inlineoverride

◆ getSelectionDAGInfo()

const SelectionDAGTargetInfo * llvm::RISCVSubtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 119 of file RISCVSubtarget.h.

◆ getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const
inline

◆ getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const
inlineoverride

◆ getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const
inline

Definition at line 171 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), combineSelectAndUse(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(), llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVTTIImpl::getIntImmCostInst(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getVectorInstrCost(), llvm::RISCVDAGToDAGISel::hasAllNBitUsers(), llvm::RISCVInstrInfo::isBranchOffsetInRange(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), isSupportedArgumentType(), isSupportedReturnType(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::lowerInterleavedLoad(), llvm::RISCVTargetLowering::lowerInterleavedStore(), llvm::RISCVTargetLowering::lowerInterleaveIntrinsicToStore(), performBITREVERSECombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectShiftMaskXLen(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm(), llvm::RISCVTargetLowering::shouldExtendTypeInLibCall(), transformAddImmMulImm(), and transformAddShlImm().

◆ getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const
inline

Definition at line 168 of file RISCVSubtarget.h.

References is64Bit().

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), llvm::RISCV::CC_RISCV_FastCC(), combine_CC(), llvm::RISCVTargetLowering::computeVLMax(), convertFromScalableVector(), getDefaultScalableVLOps(), getDeinterleaveViaVNSRL(), getVLOp(), getVSlidedown(), getVSlideup(), getWideningInterleave(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), llvm::RISCVTargetLowering::LowerCall(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), promoteVCIXScalar(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::RISCVDAGToDAGISel::selectRVVSimm5(), llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), selectVSplatImmHelper(), and tryMemPairCombine().

◆ hasConditionalMoveFusion()

bool llvm::RISCVSubtarget::hasConditionalMoveFusion ( ) const
inline

◆ hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const
inline

Definition at line 157 of file RISCVSubtarget.h.

◆ hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const
inline

◆ hasStdExtCOrZcd()

bool llvm::RISCVSubtarget::hasStdExtCOrZcd ( ) const
inline

Definition at line 146 of file RISCVSubtarget.h.

Referenced by isCompressibleLoad(), and isCompressibleStore().

◆ hasStdExtCOrZcfOrZce()

bool llvm::RISCVSubtarget::hasStdExtCOrZcfOrZce ( ) const
inline

Definition at line 147 of file RISCVSubtarget.h.

Referenced by isCompressibleLoad(), and isCompressibleStore().

◆ hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const
inline

◆ hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const
inline

◆ hasStdExtZfhminOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhminOrZhinxmin ( ) const
inline

◆ hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const
inline

◆ hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const
inline

Definition at line 150 of file RISCVSubtarget.h.

◆ hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const
inline

◆ hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const
inline

Definition at line 223 of file RISCVSubtarget.h.

References hasVInstructionsF32().

◆ hasVInstructionsBF16()

bool llvm::RISCVSubtarget::hasVInstructionsBF16 ( ) const
inline

◆ hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const
inline

◆ hasVInstructionsF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsF16Minimal ( ) const
inline

◆ hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const
inline

◆ hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const
inline

◆ hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const
inline

Definition at line 224 of file RISCVSubtarget.h.

◆ hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const
inline

◆ is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const
inline

Definition at line 167 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::canFoldIntoAddrMode(), llvm::RISCV::CC_RISCV_FastCC(), llvm::RISCV::CC_RISCV_GHC(), emitFROUND(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVFrameLowering::getFirstSPAdjustAmount(), llvm::RISCVTargetLowering::getJumpTableEncoding(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(), getXLen(), getXLenVT(), isCompressibleLoad(), isCompressibleStore(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::isSExtCheaperThanZExt(), llvm::RISCVTargetLowering::isTruncateFree(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVInstrInfo::movImm(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSRACombine(), performTRUNCATECombine(), performXORCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), selectConstantAddr(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall(), llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(), llvm::RISCVTargetLowering::signExtendConstant(), and llvm::RISCVInstrInfo::verifyInstruction().

◆ isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register  i) const
inline

◆ isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const
inline

◆ isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const
inline

Definition at line 257 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

◆ ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS 
)

◆ supportsInitUndef()

bool llvm::RISCVSubtarget::supportsInitUndef ( ) const
inlineoverride

Definition at line 293 of file RISCVSubtarget.h.

References hasVInstructions().

◆ useAA()

bool RISCVSubtarget::useAA ( ) const
override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 199 of file RISCVSubtarget.cpp.

References UseAA.

◆ useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts ( ) const

Definition at line 129 of file RISCVSubtarget.cpp.

References RISCVDisableUsingConstantPoolForLargeInts.

Referenced by lowerConstant().

◆ useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors ( ) const

Member Data Documentation

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo
protected

Definition at line 239 of file RISCVSubtarget.h.

Referenced by getCallLowering(), and RISCVSubtarget().

◆ InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector
protected

Definition at line 240 of file RISCVSubtarget.h.

Referenced by getInstructionSelector(), and RISCVSubtarget().

◆ Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer
protected

Definition at line 241 of file RISCVSubtarget.h.

◆ RegBankInfo

std::unique_ptr<RegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo
protected

Definition at line 242 of file RISCVSubtarget.h.

Referenced by getRegBankInfo(), and RISCVSubtarget().


The documentation for this class was generated from the following files: