llvm::RISCVSubtarget Class Reference

#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:

Public Types
enum	RISCVProcFamilyEnum : uint8_t { Others , SiFive7 }

Public Member Functions
	RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVFrameLowering *	getFrameLowering () const override
const RISCVInstrInfo *	getInstrInfo () const override
const RISCVRegisterInfo *	getRegisterInfo () const override
const RISCVTargetLowering *	getTargetLowering () const override
const SelectionDAGTargetInfo *	getSelectionDAGInfo () const override
bool	enableMachineScheduler () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
RISCVProcFamilyEnum	getProcFamily () const
	Returns RISC-V processor family.
bool	hasStdExtCOrZca () const
bool	hasStdExtZvl () const
bool	hasStdExtFOrZfinx () const
bool	hasStdExtDOrZdinx () const
bool	hasStdExtZfhOrZfhmin () const
bool	hasStdExtZfhOrZhinx () const
bool	hasStdExtZhinxOrZhinxmin () const
bool	hasStdExtZfhOrZfhminOrZhinxOrZhinxmin () const
bool	hasHalfFPLoadStoreMove () const
bool	is64Bit () const
MVT	getXLenVT () const
unsigned	getXLen () const
unsigned	getFLen () const
unsigned	getELEN () const
unsigned	getRealMinVLen () const
unsigned	getRealMaxVLen () const
RISCVABI::ABI	getTargetABI () const
bool	isSoftFPABI () const
bool	isRegisterReservedByUser (Register i) const
bool	hasMacroFusion () const
bool	hasVInstructions () const
bool	hasVInstructionsI64 () const
bool	hasVInstructionsF16 () const
bool	hasVInstructionsF32 () const
bool	hasVInstructionsF64 () const
bool	hasVInstructionsAnyF () const
bool	hasVInstructionsFullMultiply () const
unsigned	getMaxInterleaveFactor () const
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RegisterBankInfo *	getRegBankInfo () const override
bool	isTargetFuchsia () const
bool	useConstantPoolForLargeInts () const
unsigned	getMaxBuildIntsCost () const
unsigned	getMaxLMULForFixedLengthVectors () const
bool	useRVVForFixedLengthVectors () const
bool	enableSubRegLiveness () const override
void	getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override

Protected Member Functions
unsigned	getMaxRVVVectorSizeInBits () const
unsigned	getMinRVVVectorSizeInBits () const

Protected Attributes
std::unique_ptr< CallLowering >	CallLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RegisterBankInfo >	RegBankInfo

Detailed Description

Definition at line 35 of file RISCVSubtarget.h.

Member Enumeration Documentation

RISCVProcFamilyEnum

enum llvm::RISCVSubtarget::RISCVProcFamilyEnum : uint8_t

Enumerator
Others
SiFive7

Definition at line 37 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget	(	const Triple &	TT,
		StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS,
		StringRef	ABIName,
		unsigned	RVVVectorBitsMin,
		unsigned	RVVVectorLMULMax,
		const TargetMachine &	TM
	)

Definition at line 76 of file RISCVSubtarget.cpp.

References CallLoweringInfo, llvm::createRISCVInstructionSelector(), getTargetLowering(), InstrInfo, InstSelector, RegBankInfo, and TM.

Member Function Documentation

enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const

inlineoverride

Definition at line 99 of file RISCVSubtarget.h.

enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const

override

Definition at line 168 of file RISCVSubtarget.cpp.

References EnableSubRegLiveness.

getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const

override

Definition at line 95 of file RISCVSubtarget.cpp.

References CallLoweringInfo.

getELEN()

unsigned llvm::RISCVSubtarget::getELEN ( ) const

inline

Definition at line 142 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

Referenced by llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), getContainerForFixedLengthVector(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTTIImpl::getShuffleCost(), getWideningInterleave(), isDeinterleaveShuffle(), isInterleaveShuffle(), lowerBUILD_VECTOR(), lowerGetVectorLength(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const

inline

Definition at line 133 of file RISCVSubtarget.h.

Referenced by lowerBUILD_VECTOR().

getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 86 of file RISCVSubtarget.h.

getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 89 of file RISCVSubtarget.h.

References InstrInfo.

Referenced by emitFROUND(), EmitLoweredCascadedSelect(), llvm::RISCVFrameLowering::emitPrologue(), and emitSelectPseudo().

getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const

override

Definition at line 99 of file RISCVSubtarget.cpp.

References InstSelector.

getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const

override

Definition at line 103 of file RISCVSubtarget.cpp.

getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost

(

)

const

Definition at line 115 of file RISCVSubtarget.cpp.

References RISCVMaxBuildIntsCost.

Referenced by lowerConstant(), and llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm().

getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 178 of file RISCVSubtarget.h.

References hasVInstructions().

getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors

(

)

const

Definition at line 155 of file RISCVSubtarget.cpp.

References assert(), llvm::bit_floor(), hasVInstructions(), and RVVVectorLMULMax.

Referenced by useRVVForFixedLengthVectorVT().

getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const

protected

Definition at line 126 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const

protected

Definition at line 139 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMinVLen(), and useRVVForFixedLengthVectors().

getPostRAMutations()

void RISCVSubtarget::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation > > &  Mutations ) const

override

Definition at line 174 of file RISCVSubtarget.cpp.

References llvm::createRISCVMacroFusionDAGMutation().

getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const

inline

Definition at line 101 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const

inline

Definition at line 102 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const

inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 108 of file RISCVSubtarget.h.

getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const

inline

Definition at line 150 of file RISCVSubtarget.h.

References getMaxRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTTIImpl::getMaxVScale(), and lowerVectorIntrinsicScalars().

getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const

inline

Definition at line 146 of file RISCVSubtarget.h.

References getMinRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), getContainerForFixedLengthVector(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::LowerOperation(), lowerVectorIntrinsicScalars(), and useRVVForFixedLengthVectorVT().

getRegBankInfo()

const RegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const

override

Definition at line 107 of file RISCVSubtarget.cpp.

References RegBankInfo.

getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const

inlineoverride

Definition at line 90 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr(), llvm::RISCVFrameLowering::emitEpilogue(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVFrameLowering::hasBP(), isConvertibleToVMV_V_V(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVDAGToDAGISel::Select().

getSelectionDAGInfo()

const SelectionDAGTargetInfo * llvm::RISCVSubtarget::getSelectionDAGInfo ( ) const

inlineoverride

Definition at line 96 of file RISCVSubtarget.h.

getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const

inline

Definition at line 154 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 93 of file RISCVSubtarget.h.

Referenced by RISCVSubtarget(), and llvm::RISCVDAGToDAGISel::Select().

getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const

inline

Definition at line 132 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(), llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTTIImpl::getIntImmCostInst(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getVectorInstrCost(), llvm::RISCVDAGToDAGISel::hasAllNBitUsers(), llvm::RISCVInstrInfo::isBranchOffsetInRange(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::lowerInterleavedLoad(), llvm::RISCVTargetLowering::lowerInterleavedStore(), performBITREVERSECombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectShiftMaskXLen(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm(), llvm::RISCVTargetLowering::shouldExtendTypeInLibCall(), transformAddImmMulImm(), and transformAddShlImm().

getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const

inline

Definition at line 131 of file RISCVSubtarget.h.

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), llvm::RISCV::CC_RISCV_FastCC(), combine_CC(), combineBinOpToReduce(), llvm::RISCVTargetLowering::computeVLMax(), convertFromScalableVector(), convertToScalableVector(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), getVLOp(), getVSlidedown(), getVSlideup(), getWideningInterleave(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performSELECTCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::RISCVDAGToDAGISel::selectRVVSimm5(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), selectVSplatSimmHelper(), llvm::RISCVDAGToDAGISel::selectVSplatUimm5(), and tryMemPairCombine().

hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const

inline

Definition at line 126 of file RISCVSubtarget.h.

hasMacroFusion()

bool llvm::RISCVSubtarget::hasMacroFusion ( ) const

inline

Definition at line 165 of file RISCVSubtarget.h.

hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const

inline

Definition at line 114 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::getNop(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const

inline

Definition at line 117 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFPImmLegal(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const

inline

Definition at line 116 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZfhOrZfhmin()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZfhmin ( ) const

inline

Definition at line 118 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), hasStdExtZfhOrZfhminOrZhinxOrZhinxmin(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVTargetLowering::shouldConvertFpToSat().

hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZfhminOrZhinxOrZhinxmin ( ) const

inline

Definition at line 123 of file RISCVSubtarget.h.

References hasStdExtZfhOrZfhmin(), and hasStdExtZhinxOrZhinxmin().

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const

inline

Definition at line 119 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

hasStdExtZhinxOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZhinxOrZhinxmin ( ) const

inline

Definition at line 120 of file RISCVSubtarget.h.

Referenced by hasStdExtZfhOrZfhminOrZhinxOrZhinxmin(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVDAGToDAGISel::Select().

hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const

inline

Definition at line 115 of file RISCVSubtarget.h.

hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const

inline

Definition at line 168 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::canSplatOperand(), llvm::RISCV::CC_RISCV(), getELEN(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), getMaxInterleaveFactor(), getMaxLMULForFixedLengthVectors(), getMaxRVVVectorSizeInBits(), llvm::RISCVTTIImpl::getMaxVScale(), getMinRVVVectorSizeInBits(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), getScavSlotsNumForRVV(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::RISCVTargetLowering::shouldSinkOperands(), and useRVVForFixedLengthVectors().

hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const

inline

Definition at line 176 of file RISCVSubtarget.h.

References hasVInstructionsF32().

hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const

inline

Definition at line 170 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const

inline

Definition at line 172 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), hasVInstructionsAnyF(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const

inline

Definition at line 174 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const

inline

Definition at line 177 of file RISCVSubtarget.h.

hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const

inline

Definition at line 169 of file RISCVSubtarget.h.

Referenced by getELEN(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const

inline

Definition at line 130 of file RISCVSubtarget.h.

Referenced by emitFROUND(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::getJumpTableEncoding(), isCompressibleLoad(), isCompressibleStore(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::isSExtCheaperThanZExt(), llvm::RISCVTargetLowering::isTruncateFree(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVInstrInfo::movImm(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSRACombine(), performTRUNCATECombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), selectConstantAddr(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall(), llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(), llvm::RISCVTargetLowering::signExtendConstant(), and llvm::RISCVInstrInfo::verifyInstruction().

isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register  i ) const

inline

Definition at line 160 of file RISCVSubtarget.h.

References assert().

Referenced by llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVRegisterInfo::getReservedRegs(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerReturn().

isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const

inline

Definition at line 155 of file RISCVSubtarget.h.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64.

Referenced by llvm::RISCVTargetLowering::shouldExtendTypeInLibCall().

isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const

inline

Definition at line 202 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getIRStackGuard().

ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS
	)

useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts

(

)

const

Definition at line 111 of file RISCVSubtarget.cpp.

References RISCVDisableUsingConstantPoolForLargeInts.

Referenced by lowerConstant().

useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors

(

)

const

Definition at line 164 of file RISCVSubtarget.cpp.

References getMinRVVVectorSizeInBits(), and hasVInstructions().

Referenced by llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

Member Data Documentation

CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo

protected

Definition at line 184 of file RISCVSubtarget.h.

Referenced by getCallLowering(), and RISCVSubtarget().

InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector

protected

Definition at line 185 of file RISCVSubtarget.h.

Referenced by getInstructionSelector(), and RISCVSubtarget().

Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer

protected

Definition at line 186 of file RISCVSubtarget.h.

RegBankInfo

std::unique_ptr<RegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo

protected

Definition at line 187 of file RISCVSubtarget.h.

Referenced by getRegBankInfo(), and RISCVSubtarget().

---

The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVSubtarget.h
• lib/Target/RISCV/RISCVSubtarget.cpp