LLVM 17.0.0git
Public Types | Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::RISCVSubtarget Class Reference

#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:
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Collaboration diagram for llvm::RISCVSubtarget:
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Public Types

enum  RISCVProcFamilyEnum : uint8_t { Others , SiFive7 }
 

Public Member Functions

 RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
 
void ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
 
const RISCVFrameLowering * getFrameLowering () const override
 
const RISCVInstrInfo * getInstrInfo () const override
 
const RISCVRegisterInfo * getRegisterInfo () const override
 
const RISCVTargetLowering * getTargetLowering () const override
 
const SelectionDAGTargetInfo * getSelectionDAGInfo () const override
 
bool enableMachineScheduler () const override
 
RISCVProcFamilyEnum getProcFamily () const
 Returns RISCV processor family.
 
bool hasStdExtCOrZca () const
 
bool hasStdExtZvl () const
 
bool hasStdExtZfhOrZfhmin () const
 
bool is64Bit () const
 
MVT getXLenVT () const
 
unsigned getXLen () const
 
unsigned getFLen () const
 
unsigned getELEN () const
 
unsigned getRealMinVLen () const
 
unsigned getRealMaxVLen () const
 
RISCVABI::ABI getTargetABI () const
 
bool isRegisterReservedByUser (Register i) const
 
bool hasMacroFusion () const
 
bool hasVInstructions () const
 
bool hasVInstructionsI64 () const
 
bool hasVInstructionsF16 () const
 
bool hasVInstructionsF32 () const
 
bool hasVInstructionsF64 () const
 
bool hasVInstructionsAnyF () const
 
unsigned getMaxInterleaveFactor () const
 
const CallLowering * getCallLowering () const override
 
InstructionSelector * getInstructionSelector () const override
 
const LegalizerInfo * getLegalizerInfo () const override
 
const RegisterBankInfo * getRegBankInfo () const override
 
bool useConstantPoolForLargeInts () const
 
unsigned getMaxBuildIntsCost () const
 
unsigned getMaxLMULForFixedLengthVectors () const
 
bool useRVVForFixedLengthVectors () const
 
bool enableSubRegLiveness () const override
 
void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
 

Protected Member Functions

unsigned getMaxRVVVectorSizeInBits () const
 
unsigned getMinRVVVectorSizeInBits () const
 

Protected Attributes

std::unique_ptr< CallLowering > CallLoweringInfo
 
std::unique_ptr< InstructionSelector > InstSelector
 
std::unique_ptr< LegalizerInfo > Legalizer
 
std::unique_ptr< RegisterBankInfo > RegBankInfo
 

Detailed Description

Definition at line 35 of file RISCVSubtarget.h.

Member Enumeration Documentation

◆ RISCVProcFamilyEnum

enum llvm::RISCVSubtarget::RISCVProcFamilyEnum : uint8_t
Enumerator
Others 
SiFive7 

Definition at line 37 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

◆ RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget ( const Triple &  TT,
StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS,
StringRef  ABIName,
unsigned  RVVVectorBitsMin,
unsigned  RVVVectorLMULMax,
const TargetMachine &  TM 
)

Definition at line 76 of file RISCVSubtarget.cpp.

References CallLoweringInfo, llvm::createRISCVInstructionSelector(), getRegisterInfo(), getTargetLowering(), InstrInfo, InstSelector, RegBankInfo, and TM.

Member Function Documentation

◆ enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const
inlineoverride

Definition at line 96 of file RISCVSubtarget.h.

◆ enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const
override

Definition at line 167 of file RISCVSubtarget.cpp.

References EnableSubRegLiveness.

◆ getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const
override

Definition at line 95 of file RISCVSubtarget.cpp.

References CallLoweringInfo.

◆ getELEN()

unsigned llvm::RISCVSubtarget::getELEN ( ) const
inline

Definition at line 123 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

Referenced by llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), getContainerForFixedLengthVector(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), isInterleaveShuffle(), lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLEAsVNSRL(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

◆ getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const
inline

Definition at line 114 of file RISCVSubtarget.h.

◆ getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const
inlineoverride

Definition at line 83 of file RISCVSubtarget.h.

◆ getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const
inlineoverride

Definition at line 86 of file RISCVSubtarget.h.

References InstrInfo.

Referenced by emitFROUND(), EmitLoweredCascadedSelect(), llvm::RISCVFrameLowering::emitPrologue(), and emitSelectPseudo().

◆ getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const
override

Definition at line 99 of file RISCVSubtarget.cpp.

References InstSelector.

◆ getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const
override

Definition at line 103 of file RISCVSubtarget.cpp.

◆ getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost ( ) const

Definition at line 115 of file RISCVSubtarget.cpp.

References RISCVMaxBuildIntsCost.

Referenced by lowerConstant(), and llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm().

◆ getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const
inline

Definition at line 155 of file RISCVSubtarget.h.

References hasVInstructions().

◆ getMaxLMULForFixedLengthVectors()

unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors ( ) const

Definition at line 155 of file RISCVSubtarget.cpp.

References assert(), llvm::bit_floor(), hasVInstructions(), llvm::isPowerOf2_32(), and RVVVectorLMULMax.

Referenced by useRVVForFixedLengthVectorVT().

◆ getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const
protected

Definition at line 126 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

◆ getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const
protected

Definition at line 139 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMinVLen(), and useRVVForFixedLengthVectors().

◆ getPostRAMutations()

void RISCVSubtarget::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation > > &  Mutations) const
override

Definition at line 173 of file RISCVSubtarget.cpp.

References llvm::createRISCVMacroFusionDAGMutation().

◆ getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const
inline

Returns RISCV processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 102 of file RISCVSubtarget.h.

◆ getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const
inline

Definition at line 131 of file RISCVSubtarget.h.

References getMaxRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTTIImpl::getMaxVScale(), and lowerVectorIntrinsicScalars().

◆ getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const
inline

Definition at line 127 of file RISCVSubtarget.h.

References getMinRVVVectorSizeInBits().

Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), getContainerForFixedLengthVector(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::LowerOperation(), lowerVectorIntrinsicScalars(), and useRVVForFixedLengthVectorVT().

◆ getRegBankInfo()

const RegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const
override

Definition at line 107 of file RISCVSubtarget.cpp.

References RegBankInfo.

◆ getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const
inlineoverride

Definition at line 87 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr(), llvm::RISCVFrameLowering::emitEpilogue(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVFrameLowering::hasBP(), isConvertibleToVMV_V_V(), llvm::RISCVTargetLowering::LowerCall(), RISCVSubtarget(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVDAGToDAGISel::Select().

◆ getSelectionDAGInfo()

const SelectionDAGTargetInfo * llvm::RISCVSubtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 93 of file RISCVSubtarget.h.

◆ getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const
inline

Definition at line 135 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVTargetLowering::shouldExtendTypeInLibCall().

◆ getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const
inlineoverride

Definition at line 90 of file RISCVSubtarget.h.

Referenced by RISCVSubtarget(), and llvm::RISCVDAGToDAGISel::Select().

◆ getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const
inline

Definition at line 113 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(), llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(), llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTTIImpl::getIntImmCostInst(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getVectorInstrCost(), llvm::RISCVInstrInfo::hasAllNBitUsers(), llvm::RISCVDAGToDAGISel::hasAllNBitUsers(), llvm::RISCVInstrInfo::isBranchOffsetInRange(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerFormalArguments(), performBITREVERSECombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectShiftMaskXLen(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm(), transformAddImmMulImm(), and transformAddShlImm().

◆ getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const
inline

Definition at line 112 of file RISCVSubtarget.h.

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), CC_RISCV_FastCC(), combine_CC(), combineBinOpToReduce(), convertFromScalableVector(), convertToScalableVector(), getDefaultVLOps(), getVLOp(), getVSlidedown(), getVSlideup(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerScalarInsert(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVNSRL(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), matchSplatAsGather(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performSELECTCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::selectFPImm(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), llvm::RISCVDAGToDAGISel::selectRVVSimm5(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), selectVSplatSimmHelper(), and llvm::RISCVDAGToDAGISel::selectVSplatUimm5().

◆ hasMacroFusion()

bool llvm::RISCVSubtarget::hasMacroFusion ( ) const
inline

Definition at line 141 of file RISCVSubtarget.h.

◆ hasStdExtCOrZca()

bool llvm::RISCVSubtarget::hasStdExtCOrZca ( ) const
inline

Definition at line 108 of file RISCVSubtarget.h.

Referenced by llvm::RISCVInstrInfo::getNop(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

◆ hasStdExtZfhOrZfhmin()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZfhmin ( ) const
inline

Definition at line 110 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::hasBitPreservingFPLogic(), hasVInstructionsF16(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::RISCVTargetLowering::shouldConvertFpToSat().

◆ hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const
inline

Definition at line 109 of file RISCVSubtarget.h.

◆ hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const
inline

Definition at line 144 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVTargetLowering::canSplatOperand(), CC_RISCV(), getELEN(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), getMaxInterleaveFactor(), getMaxLMULForFixedLengthVectors(), getMaxRVVVectorSizeInBits(), llvm::RISCVTTIImpl::getMaxVScale(), getMinRVVVectorSizeInBits(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), getScavSlotsNumForRVV(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isLegalAddressingMode(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::RISCVTargetLowering::shouldSinkOperands(), and useRVVForFixedLengthVectors().

◆ hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const
inline

Definition at line 154 of file RISCVSubtarget.h.

References hasVInstructionsF32().

◆ hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const
inline

Definition at line 146 of file RISCVSubtarget.h.

References hasStdExtZfhOrZfhmin().

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const
inline

Definition at line 150 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), hasVInstructionsAnyF(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const
inline

Definition at line 152 of file RISCVSubtarget.h.

Referenced by llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

◆ hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const
inline

Definition at line 145 of file RISCVSubtarget.h.

Referenced by getELEN(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

◆ is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const
inline

Definition at line 111 of file RISCVSubtarget.h.

Referenced by emitFROUND(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::getJumpTableEncoding(), isCompressibleLoad(), isCompressibleStore(), llvm::RISCVTargetLowering::isSExtCheaperThanZExt(), llvm::RISCVTargetLowering::isTruncateFree(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVInstrInfo::movImm(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSRACombine(), performTRUNCATECombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), selectConstantAddr(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall(), llvm::RISCVTargetLowering::signExtendConstant(), and llvm::RISCVInstrInfo::verifyInstruction().

◆ isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register  i) const
inline

Definition at line 136 of file RISCVSubtarget.h.

References assert().

Referenced by llvm::RISCVFrameLowering::emitPrologue(), llvm::RISCVTargetLowering::getRegisterByName(), llvm::RISCVRegisterInfo::getReservedRegs(), llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerReturn().

◆ ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS 
)

◆ useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts ( ) const

Definition at line 111 of file RISCVSubtarget.cpp.

References RISCVDisableUsingConstantPoolForLargeInts.

Referenced by lowerConstant().

◆ useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors ( ) const

Definition at line 163 of file RISCVSubtarget.cpp.

References getMinRVVVectorSizeInBits(), and hasVInstructions().

Referenced by llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getCmpSelInstrCost(), llvm::RISCVTTIImpl::getExtendedReductionCost(), llvm::RISCVTTIImpl::getMinMaxReductionCost(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and useRVVForFixedLengthVectorVT().

Member Data Documentation

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo
protected

Definition at line 161 of file RISCVSubtarget.h.

Referenced by getCallLowering(), and RISCVSubtarget().

◆ InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector
protected

Definition at line 162 of file RISCVSubtarget.h.

Referenced by getInstructionSelector(), and RISCVSubtarget().

◆ Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer
protected

Definition at line 163 of file RISCVSubtarget.h.

◆ RegBankInfo

std::unique_ptr<RegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo
protected

Definition at line 164 of file RISCVSubtarget.h.

Referenced by getRegBankInfo(), and RISCVSubtarget().

The documentation for this class was generated from the following files:
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