LLVM  10.0.0svn
RISCVISelDAGToDAG.cpp
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1 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the RISCV target.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "RISCV.h"
15 #include "RISCVTargetMachine.h"
16 #include "Utils/RISCVMatInt.h"
19 #include "llvm/Support/Debug.h"
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "riscv-isel"
25 
26 // RISCV-specific code to select RISCV machine instructions for
27 // SelectionDAG operations.
28 namespace {
29 class RISCVDAGToDAGISel final : public SelectionDAGISel {
30  const RISCVSubtarget *Subtarget;
31 
32 public:
33  explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
34  : SelectionDAGISel(TargetMachine) {}
35 
36  StringRef getPassName() const override {
37  return "RISCV DAG->DAG Pattern Instruction Selection";
38  }
39 
40  bool runOnMachineFunction(MachineFunction &MF) override {
41  Subtarget = &MF.getSubtarget<RISCVSubtarget>();
43  }
44 
45  void PostprocessISelDAG() override;
46 
47  void Select(SDNode *Node) override;
48 
49  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
50  std::vector<SDValue> &OutOps) override;
51 
52  bool SelectAddrFI(SDValue Addr, SDValue &Base);
53 
54 // Include the pieces autogenerated from the target description.
55 #include "RISCVGenDAGISel.inc"
56 
57 private:
58  void doPeepholeLoadStoreADDI();
59 };
60 }
61 
62 void RISCVDAGToDAGISel::PostprocessISelDAG() {
63  doPeepholeLoadStoreADDI();
64 }
65 
66 static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
67  MVT XLenVT) {
69  RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq);
70 
71  SDNode *Result = nullptr;
72  SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
73  for (RISCVMatInt::Inst &Inst : Seq) {
74  SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
75  if (Inst.Opc == RISCV::LUI)
76  Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
77  else
78  Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);
79 
80  // Only the first instruction has X0 as its source.
81  SrcReg = SDValue(Result, 0);
82  }
83 
84  return Result;
85 }
86 
87 // Returns true if the Node is an ISD::AND with a constant argument. If so,
88 // set Mask to that constant value.
89 static bool isConstantMask(SDNode *Node, uint64_t &Mask) {
90  if (Node->getOpcode() == ISD::AND &&
91  Node->getOperand(1).getOpcode() == ISD::Constant) {
92  Mask = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
93  return true;
94  }
95  return false;
96 }
97 
99  // If we have a custom node, we have already selected.
100  if (Node->isMachineOpcode()) {
101  LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
102  Node->setNodeId(-1);
103  return;
104  }
105 
106  // Instruction Selection not handled by the auto-generated tablegen selection
107  // should be handled here.
108  unsigned Opcode = Node->getOpcode();
109  MVT XLenVT = Subtarget->getXLenVT();
110  SDLoc DL(Node);
111  EVT VT = Node->getValueType(0);
112 
113  switch (Opcode) {
114  case ISD::Constant: {
115  auto ConstNode = cast<ConstantSDNode>(Node);
116  if (VT == XLenVT && ConstNode->isNullValue()) {
117  SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
118  RISCV::X0, XLenVT);
119  ReplaceNode(Node, New.getNode());
120  return;
121  }
122  int64_t Imm = ConstNode->getSExtValue();
123  if (XLenVT == MVT::i64) {
124  ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));
125  return;
126  }
127  break;
128  }
129  case ISD::FrameIndex: {
130  SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
131  int FI = cast<FrameIndexSDNode>(Node)->getIndex();
132  SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
133  ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
134  return;
135  }
136  case ISD::SRL: {
137  if (!Subtarget->is64Bit())
138  break;
139  SDValue Op0 = Node->getOperand(0);
140  SDValue Op1 = Node->getOperand(1);
141  uint64_t Mask;
142  // Match (srl (and val, mask), imm) where the result would be a
143  // zero-extended 32-bit integer. i.e. the mask is 0xffffffff or the result
144  // is equivalent to this (SimplifyDemandedBits may have removed lower bits
145  // from the mask that aren't necessary due to the right-shifting).
146  if (Op1.getOpcode() == ISD::Constant &&
147  isConstantMask(Op0.getNode(), Mask)) {
148  uint64_t ShAmt = cast<ConstantSDNode>(Op1.getNode())->getZExtValue();
149 
150  if ((Mask | maskTrailingOnes<uint64_t>(ShAmt)) == 0xffffffff) {
151  SDValue ShAmtVal =
152  CurDAG->getTargetConstant(ShAmt, SDLoc(Node), XLenVT);
153  CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0.getOperand(0),
154  ShAmtVal);
155  return;
156  }
157  }
158  break;
159  }
161  assert(!Subtarget->is64Bit() && "READ_CYCLE_WIDE is only used on riscv32");
162 
163  ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ReadCycleWide, DL, MVT::i32,
165  Node->getOperand(0)));
166  return;
167  }
168 
169  // Select the default instruction.
170  SelectCode(Node);
171 }
172 
173 bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
174  const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
175  switch (ConstraintID) {
178  // We just support simple memory operands that have a single address
179  // operand and need no special handling.
180  OutOps.push_back(Op);
181  return false;
183  OutOps.push_back(Op);
184  return false;
185  default:
186  break;
187  }
188 
189  return true;
190 }
191 
192 bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {
193  if (auto FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
194  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());
195  return true;
196  }
197  return false;
198 }
199 
200 // Merge an ADDI into the offset of a load/store instruction where possible.
201 // (load (add base, off), 0) -> (load base, off)
202 // (store val, (add base, off)) -> (store val, base, off)
203 void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() {
204  SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
205  ++Position;
206 
207  while (Position != CurDAG->allnodes_begin()) {
208  SDNode *N = &*--Position;
209  // Skip dead nodes and any non-machine opcodes.
210  if (N->use_empty() || !N->isMachineOpcode())
211  continue;
212 
213  int OffsetOpIdx;
214  int BaseOpIdx;
215 
216  // Only attempt this optimisation for I-type loads and S-type stores.
217  switch (N->getMachineOpcode()) {
218  default:
219  continue;
220  case RISCV::LB:
221  case RISCV::LH:
222  case RISCV::LW:
223  case RISCV::LBU:
224  case RISCV::LHU:
225  case RISCV::LWU:
226  case RISCV::LD:
227  case RISCV::FLW:
228  case RISCV::FLD:
229  BaseOpIdx = 0;
230  OffsetOpIdx = 1;
231  break;
232  case RISCV::SB:
233  case RISCV::SH:
234  case RISCV::SW:
235  case RISCV::SD:
236  case RISCV::FSW:
237  case RISCV::FSD:
238  BaseOpIdx = 1;
239  OffsetOpIdx = 2;
240  break;
241  }
242 
243  // Currently, the load/store offset must be 0 to be considered for this
244  // peephole optimisation.
245  if (!isa<ConstantSDNode>(N->getOperand(OffsetOpIdx)) ||
246  N->getConstantOperandVal(OffsetOpIdx) != 0)
247  continue;
248 
249  SDValue Base = N->getOperand(BaseOpIdx);
250 
251  // If the base is an ADDI, we can merge it in to the load/store.
252  if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)
253  continue;
254 
255  SDValue ImmOperand = Base.getOperand(1);
256 
257  if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) {
258  ImmOperand = CurDAG->getTargetConstant(
259  Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType());
260  } else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
261  ImmOperand = CurDAG->getTargetGlobalAddress(
262  GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
263  GA->getOffset(), GA->getTargetFlags());
264  } else {
265  continue;
266  }
267 
268  LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
269  LLVM_DEBUG(Base->dump(CurDAG));
270  LLVM_DEBUG(dbgs() << "\nN: ");
271  LLVM_DEBUG(N->dump(CurDAG));
272  LLVM_DEBUG(dbgs() << "\n");
273 
274  // Modify the offset operand of the load/store.
275  if (BaseOpIdx == 0) // Load
276  CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand,
277  N->getOperand(2));
278  else // Store
279  CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0),
280  ImmOperand, N->getOperand(3));
281 
282  // The add-immediate may now be dead, in which case remove it.
283  if (Base.getNode()->use_empty())
284  CurDAG->RemoveDeadNode(Base.getNode());
285  }
286 }
287 
288 // This pass converts a legalized DAG into a RISCV-specific DAG, ready
289 // for instruction scheduling.
291  return new RISCVDAGToDAGISel(TM);
292 }
static bool isConstantMask(SDNode *Node, uint64_t &Mask)
EVT getValueType() const
Return the ValueType of the referenced return value.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void setNodeId(int Id)
Set unique node id.
SDNode * getNode() const
get the SDNode which holds the desired result
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
Position
Position to insert a new instruction relative to an existing instruction.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:596
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This instruction implements an extending load to FP stack slots.
bool isMachineOpcode() const
const SDValue & getOperand(unsigned Num) const
unsigned getMachineOpcode() const
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
Extended Value Type.
Definition: ValueTypes.h:33
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
bool use_empty() const
Return true if there are no uses of this node.
void dump() const
Dump this node, for debugging.
Iterator for intrusive lists based on ilist_node.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
static SDNode * selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm, MVT XLenVT)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:426
void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res)
Definition: RISCVMatInt.cpp:19
#define N
unsigned getOpcode() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
SDValue getRegister(unsigned Reg, EVT VT)
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
const SDValue & getOperand(unsigned i) const
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...