LLVM 17.0.0git
Enumerations
llvm::RISCVISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END , RET_FLAG , URET_FLAG , SRET_FLAG ,
  MRET_FLAG , CALL , SELECT_CC , BR_CC ,
  BuildPairF64 , SplitF64 , TAIL , ADD_LO ,
  HI , LLA , ADD_TPREL , LA_TLS_GD ,
  MULHSU , SLLW , SRAW , SRLW ,
  DIVW , DIVUW , REMUW , ROLW ,
  RORW , CLZW , CTZW , ABSW ,
  FMV_H_X , FMV_X_ANYEXTH , FMV_X_SIGNEXTH , FMV_W_X_RV64 ,
  FMV_X_ANYEXTW_RV64 , FCVT_X , FCVT_XU , FCVT_W_RV64 ,
  FCVT_WU_RV64 , FROUND , READ_CYCLE_WIDE , BREV8 ,
  ORC_B , ZIP , UNZIP , VMV_V_X_VL ,
  VFMV_V_F_VL , VMV_X_S , VMV_S_X_VL , VFMV_S_F_VL ,
  SPLAT_VECTOR_SPLIT_I64_VL , READ_VLENB , TRUNCATE_VECTOR_VL , VSLIDEUP_VL ,
  VSLIDEDOWN_VL , VSLIDE1UP_VL , VSLIDE1DOWN_VL , VID_VL ,
  VFNCVT_ROD_VL , VECREDUCE_ADD_VL , VECREDUCE_UMAX_VL , VECREDUCE_SMAX_VL ,
  VECREDUCE_UMIN_VL , VECREDUCE_SMIN_VL , VECREDUCE_AND_VL , VECREDUCE_OR_VL ,
  VECREDUCE_XOR_VL , VECREDUCE_FADD_VL , VECREDUCE_SEQ_FADD_VL , VECREDUCE_FMIN_VL ,
  VECREDUCE_FMAX_VL , ADD_VL , AND_VL , MUL_VL ,
  OR_VL , SDIV_VL , SHL_VL , SREM_VL ,
  SRA_VL , SRL_VL , SUB_VL , UDIV_VL ,
  UREM_VL , XOR_VL , SMIN_VL , SMAX_VL ,
  UMIN_VL , UMAX_VL , SADDSAT_VL , UADDSAT_VL ,
  SSUBSAT_VL , USUBSAT_VL , MULHS_VL , MULHU_VL ,
  FADD_VL , FSUB_VL , FMUL_VL , FDIV_VL ,
  FMINNUM_VL , FMAXNUM_VL , FNEG_VL , FABS_VL ,
  FSQRT_VL , FCOPYSIGN_VL , VFCVT_RTZ_X_F_VL , VFCVT_RTZ_XU_F_VL ,
  VFCVT_X_F_VL , VFCVT_XU_F_VL , VFROUND_NOEXCEPT_VL , VFCVT_RM_X_F_VL ,
  VFCVT_RM_XU_F_VL , SINT_TO_FP_VL , UINT_TO_FP_VL , VFCVT_RM_F_X_VL ,
  VFCVT_RM_F_XU_VL , FP_ROUND_VL , FP_EXTEND_VL , VFMADD_VL ,
  VFNMADD_VL , VFMSUB_VL , VFNMSUB_VL , VWMUL_VL ,
  VWMULU_VL , VWMULSU_VL , VWADD_VL , VWADDU_VL ,
  VWSUB_VL , VWSUBU_VL , VWADD_W_VL , VWADDU_W_VL ,
  VWSUB_W_VL , VWSUBU_W_VL , VNSRL_VL , SETCC_VL ,
  VSELECT_VL , VP_MERGE_VL , VMAND_VL , VMOR_VL ,
  VMXOR_VL , VMCLR_VL , VMSET_VL , VRGATHER_VX_VL ,
  VRGATHER_VV_VL , VRGATHEREI16_VV_VL , VSEXT_VL , VZEXT_VL ,
  VCPOP_VL , VFIRST_VL , READ_CSR , WRITE_CSR ,
  SWAP_CSR , STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE , STRICT_FCVT_WU_RV64 , LA = ISD::FIRST_TARGET_MEMORY_OPCODE ,
  LA_TLS_IE
}
 

Enumeration Type Documentation

◆ NodeType

Enumerator
FIRST_NUMBER 
RET_FLAG 
URET_FLAG 
SRET_FLAG 
MRET_FLAG 
CALL 
SELECT_CC 

Select with condition operator - This selects between a true value and a false value (ops #3 and #4) based on the boolean result of comparing the lhs and rhs (ops #0 and #1) of a conditional expression with the condition code in op #2, a XLenVT constant from the ISD::CondCode enum.

The lhs and rhs are XLenVT integers. The true and false values can be integer or floating point.

BR_CC 
BuildPairF64 
SplitF64 
TAIL 
ADD_LO 
HI 
LLA 
ADD_TPREL 
LA_TLS_GD 
MULHSU 
SLLW 
SRAW 
SRLW 
DIVW 
DIVUW 
REMUW 
ROLW 
RORW 
CLZW 
CTZW 
ABSW 
FMV_H_X 
FMV_X_ANYEXTH 
FMV_X_SIGNEXTH 
FMV_W_X_RV64 
FMV_X_ANYEXTW_RV64 
FCVT_X 
FCVT_XU 
FCVT_W_RV64 
FCVT_WU_RV64 
FROUND 
READ_CYCLE_WIDE 
BREV8 
ORC_B 
ZIP 
UNZIP 
VMV_V_X_VL 
VFMV_V_F_VL 
VMV_X_S 
VMV_S_X_VL 
VFMV_S_F_VL 
SPLAT_VECTOR_SPLIT_I64_VL 
READ_VLENB 
TRUNCATE_VECTOR_VL 
VSLIDEUP_VL 
VSLIDEDOWN_VL 
VSLIDE1UP_VL 
VSLIDE1DOWN_VL 
VID_VL 
VFNCVT_ROD_VL 
VECREDUCE_ADD_VL 
VECREDUCE_UMAX_VL 
VECREDUCE_SMAX_VL 
VECREDUCE_UMIN_VL 
VECREDUCE_SMIN_VL 
VECREDUCE_AND_VL 
VECREDUCE_OR_VL 
VECREDUCE_XOR_VL 
VECREDUCE_FADD_VL 
VECREDUCE_SEQ_FADD_VL 
VECREDUCE_FMIN_VL 
VECREDUCE_FMAX_VL 
ADD_VL 
AND_VL 
MUL_VL 
OR_VL 
SDIV_VL 
SHL_VL 
SREM_VL 
SRA_VL 
SRL_VL 
SUB_VL 
UDIV_VL 
UREM_VL 
XOR_VL 
SMIN_VL 
SMAX_VL 
UMIN_VL 
UMAX_VL 
SADDSAT_VL 
UADDSAT_VL 
SSUBSAT_VL 
USUBSAT_VL 
MULHS_VL 
MULHU_VL 
FADD_VL 
FSUB_VL 
FMUL_VL 
FDIV_VL 
FMINNUM_VL 
FMAXNUM_VL 
FNEG_VL 
FABS_VL 
FSQRT_VL 
FCOPYSIGN_VL 
VFCVT_RTZ_X_F_VL 
VFCVT_RTZ_XU_F_VL 
VFCVT_X_F_VL 
VFCVT_XU_F_VL 
VFROUND_NOEXCEPT_VL 
VFCVT_RM_X_F_VL 
VFCVT_RM_XU_F_VL 
SINT_TO_FP_VL 
UINT_TO_FP_VL 
VFCVT_RM_F_X_VL 
VFCVT_RM_F_XU_VL 
FP_ROUND_VL 
FP_EXTEND_VL 
VFMADD_VL 
VFNMADD_VL 
VFMSUB_VL 
VFNMSUB_VL 
VWMUL_VL 
VWMULU_VL 
VWMULSU_VL 
VWADD_VL 
VWADDU_VL 
VWSUB_VL 
VWSUBU_VL 
VWADD_W_VL 
VWADDU_W_VL 
VWSUB_W_VL 
VWSUBU_W_VL 
VNSRL_VL 
SETCC_VL 
VSELECT_VL 
VP_MERGE_VL 
VMAND_VL 
VMOR_VL 
VMXOR_VL 
VMCLR_VL 
VMSET_VL 
VRGATHER_VX_VL 
VRGATHER_VV_VL 
VRGATHEREI16_VV_VL 
VSEXT_VL 
VZEXT_VL 
VCPOP_VL 
VFIRST_VL 
READ_CSR 
WRITE_CSR 
SWAP_CSR 
STRICT_FCVT_W_RV64 
STRICT_FCVT_WU_RV64 
LA 
LA_TLS_IE 

Definition at line 28 of file RISCVISelLowering.h.