LLVM  14.0.0git
Public Member Functions | Static Public Member Functions | List of all members
llvm::RISCVDAGToDAGISel Class Reference

#include "Target/RISCV/RISCVISelDAGToDAG.h"

Inheritance diagram for llvm::RISCVDAGToDAGISel:
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Collaboration diagram for llvm::RISCVDAGToDAGISel:
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Public Member Functions

 RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine)
 
StringRef getPassName () const override
 getPassName - Return a nice clean name for a pass. More...
 
bool runOnMachineFunction (MachineFunction &MF) override
 runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis. More...
 
void PreprocessISelDAG () override
 PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts. More...
 
void PostprocessISelDAG () override
 PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection. More...
 
void Select (SDNode *Node) override
 Main hook for targets to transform nodes into machine nodes. More...
 
bool SelectInlineAsmMemoryOperand (const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
 SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint. More...
 
bool SelectAddrFI (SDValue Addr, SDValue &Base)
 
bool SelectBaseAddr (SDValue Addr, SDValue &Base)
 
bool selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
 
bool selectShiftMaskXLen (SDValue N, SDValue &ShAmt)
 
bool selectShiftMask32 (SDValue N, SDValue &ShAmt)
 
bool selectSExti32 (SDValue N, SDValue &Val)
 
bool selectZExti32 (SDValue N, SDValue &Val)
 
bool hasAllNBitUsers (SDNode *Node, unsigned Bits) const
 
bool hasAllHUsers (SDNode *Node) const
 
bool hasAllWUsers (SDNode *Node) const
 
bool selectVLOp (SDValue N, SDValue &VL)
 
bool selectVSplat (SDValue N, SDValue &SplatVal)
 
bool selectVSplatSimm5 (SDValue N, SDValue &SplatVal)
 
bool selectVSplatUimm5 (SDValue N, SDValue &SplatVal)
 
bool selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal)
 
bool selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal)
 
bool selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm)
 
template<unsigned Width>
bool selectRVVSimm5 (SDValue N, SDValue &Imm)
 
void addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
 
void selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided)
 
void selectVLSEGFF (SDNode *Node, bool IsMasked)
 
void selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
 
void selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided)
 
void selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
 
- Public Member Functions inherited from llvm::SelectionDAGISel
 SelectionDAGISel (TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
 
 ~SelectionDAGISel () override
 
const TargetLoweringgetTargetLowering () const
 
void getAnalysisUsage (AnalysisUsage &AU) const override
 getAnalysisUsage - Subclasses that override getAnalysisUsage must call this. More...
 
virtual void emitFunctionEntryCode ()
 
virtual bool IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const
 IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root. More...
 
bool CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
 CheckAndMask - The isel is trying to match something like (and X, 255). More...
 
bool CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
 CheckOrMask - The isel is trying to match something like (or X, 255). More...
 
virtual bool CheckPatternPredicate (unsigned PredNo) const
 CheckPatternPredicate - This function is generated by tblgen in the target. More...
 
virtual bool CheckNodePredicate (SDNode *N, unsigned PredNo) const
 CheckNodePredicate - This function is generated by tblgen in the target. More...
 
virtual bool CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
 CheckNodePredicateWithOperands - This function is generated by tblgen in the target. More...
 
virtual bool CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
 
virtual SDValue RunSDNodeXForm (SDValue V, unsigned XFormNo)
 
void SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
 
virtual bool ComplexPatternFuncMutatesDAG () const
 Return true if complex patterns for this target can mutate the DAG. More...
 
bool mayRaiseFPException (SDNode *Node) const
 Return whether the node may raise an FP exception. More...
 
bool isOrEquivalentToAdd (const SDNode *N) const
 
- Public Member Functions inherited from llvm::MachineFunctionPass
bool doInitialization (Module &) override
 doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run. More...
 
- Public Member Functions inherited from llvm::FunctionPass
 FunctionPass (char &pid)
 
PasscreatePrinterPass (raw_ostream &OS, const std::string &Banner) const override
 createPrinterPass - Get a function printer pass. More...
 
void assignPassManager (PMStack &PMS, PassManagerType T) override
 Find appropriate Function Pass Manager or Call Graph Pass Manager in the PM Stack and add self into that manager. More...
 
PassManagerType getPotentialPassManagerType () const override
 Return what kind of Pass Manager can manage this pass. More...
 
- Public Member Functions inherited from llvm::Pass
 Pass (PassKind K, char &pid)
 
 Pass (const Pass &)=delete
 
Passoperator= (const Pass &)=delete
 
virtual ~Pass ()
 
PassKind getPassKind () const
 
AnalysisID getPassID () const
 getPassID - Return the PassID number that corresponds to this pass. More...
 
virtual bool doFinalization (Module &)
 doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run. More...
 
virtual void print (raw_ostream &OS, const Module *M) const
 print - Print out the internal state of the pass. More...
 
void dump () const
 
virtual void preparePassManager (PMStack &)
 Check if available pass managers are suitable for this pass or not. More...
 
void setResolver (AnalysisResolver *AR)
 
AnalysisResolvergetResolver () const
 
virtual void releaseMemory ()
 releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed. More...
 
virtual void * getAdjustedAnalysisPointer (AnalysisID ID)
 getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance. More...
 
virtual ImmutablePassgetAsImmutablePass ()
 
virtual PMDataManagergetAsPMDataManager ()
 
virtual void verifyAnalysis () const
 verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information. More...
 
virtual void dumpPassStructure (unsigned Offset=0)
 
template<typename AnalysisType >
AnalysisType * getAnalysisIfAvailable () const
 getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it. More...
 
bool mustPreserveAnalysisID (char &AID) const
 mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID. More...
 
template<typename AnalysisType >
AnalysisType & getAnalysis () const
 getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More...
 
template<typename AnalysisType >
AnalysisType & getAnalysis (Function &F, bool *Changed=nullptr)
 getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More...
 
template<typename AnalysisType >
AnalysisType & getAnalysisID (AnalysisID PI) const
 
template<typename AnalysisType >
AnalysisType & getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr)
 

Static Public Member Functions

static RISCVCC::CondCode getRISCVCCForIntCC (ISD::CondCode CC)
 
- Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
 IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root. More...
 
static void InvalidateNodeId (SDNode *N)
 
static int getUninvalidatedNodeId (SDNode *N)
 
static void EnforceNodeIdInvariant (SDNode *N)
 
static int getNumFixedFromVariadicInfo (unsigned Flags)
 getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root. More...
 
- Static Public Member Functions inherited from llvm::Pass
static const PassInfolookupPassInfo (const void *TI)
 
static const PassInfolookupPassInfo (StringRef Arg)
 
static PasscreatePass (AnalysisID ID)
 

Additional Inherited Members

- Public Types inherited from llvm::SelectionDAGISel
enum  BuiltinOpcodes {
  OPC_Scope, OPC_RecordNode, OPC_RecordChild0, OPC_RecordChild1,
  OPC_RecordChild2, OPC_RecordChild3, OPC_RecordChild4, OPC_RecordChild5,
  OPC_RecordChild6, OPC_RecordChild7, OPC_RecordMemRef, OPC_CaptureGlueInput,
  OPC_MoveChild, OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2,
  OPC_MoveChild3, OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6,
  OPC_MoveChild7, OPC_MoveParent, OPC_CheckSame, OPC_CheckChild0Same,
  OPC_CheckChild1Same, OPC_CheckChild2Same, OPC_CheckChild3Same, OPC_CheckPatternPredicate,
  OPC_CheckPredicate, OPC_CheckPredicateWithOperands, OPC_CheckOpcode, OPC_SwitchOpcode,
  OPC_CheckType, OPC_CheckTypeRes, OPC_SwitchType, OPC_CheckChild0Type,
  OPC_CheckChild1Type, OPC_CheckChild2Type, OPC_CheckChild3Type, OPC_CheckChild4Type,
  OPC_CheckChild5Type, OPC_CheckChild6Type, OPC_CheckChild7Type, OPC_CheckInteger,
  OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, OPC_CheckChild3Integer,
  OPC_CheckChild4Integer, OPC_CheckCondCode, OPC_CheckChild2CondCode, OPC_CheckValueType,
  OPC_CheckComplexPat, OPC_CheckAndImm, OPC_CheckOrImm, OPC_CheckImmAllOnesV,
  OPC_CheckImmAllZerosV, OPC_CheckFoldableChainNode, OPC_EmitInteger, OPC_EmitStringInteger,
  OPC_EmitRegister, OPC_EmitRegister2, OPC_EmitConvertToTarget, OPC_EmitMergeInputChains,
  OPC_EmitMergeInputChains1_0, OPC_EmitMergeInputChains1_1, OPC_EmitMergeInputChains1_2, OPC_EmitCopyToReg,
  OPC_EmitCopyToReg2, OPC_EmitNodeXForm, OPC_EmitNode, OPC_EmitNode0,
  OPC_EmitNode1, OPC_EmitNode2, OPC_MorphNodeTo, OPC_MorphNodeTo0,
  OPC_MorphNodeTo1, OPC_MorphNodeTo2, OPC_CompleteMatch, OPC_Coverage
}
 
enum  {
  OPFL_None = 0, OPFL_Chain = 1, OPFL_GlueInput = 2, OPFL_GlueOutput = 4,
  OPFL_MemRefs = 8, OPFL_Variadic0 = 1<<4, OPFL_Variadic1 = 2<<4, OPFL_Variadic2 = 3<<4,
  OPFL_Variadic3 = 4<<4, OPFL_Variadic4 = 5<<4, OPFL_Variadic5 = 6<<4, OPFL_Variadic6 = 7<<4,
  OPFL_VariadicInfo = OPFL_Variadic6
}
 
- Public Attributes inherited from llvm::SelectionDAGISel
TargetMachineTM
 
const TargetLibraryInfoLibInfo
 
std::unique_ptr< FunctionLoweringInfoFuncInfo
 
SwiftErrorValueTrackingSwiftError
 
MachineFunctionMF
 
MachineRegisterInfoRegInfo
 
SelectionDAGCurDAG
 
std::unique_ptr< SelectionDAGBuilderSDB
 
AAResultsAA
 
GCFunctionInfoGFI
 
CodeGenOpt::Level OptLevel
 
const TargetInstrInfoTII
 
const TargetLoweringTLI
 
bool FastISelFailed
 
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
 
std::unique_ptr< OptimizationRemarkEmitterORE
 Current optimization remark emitter. More...
 
- Static Public Attributes inherited from llvm::SelectionDAGISel
static char ID = 0
 
- Protected Member Functions inherited from llvm::SelectionDAGISel
void ReplaceUses (SDValue F, SDValue T)
 ReplaceUses - replace all uses of the old node F with the use of the new node T. More...
 
void ReplaceUses (const SDValue *F, const SDValue *T, unsigned Num)
 ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T. More...
 
void ReplaceUses (SDNode *F, SDNode *T)
 ReplaceUses - replace all uses of the old node F with the use of the new node T. More...
 
void ReplaceNode (SDNode *F, SDNode *T)
 Replace all uses of F with T, then remove F from the DAG. More...
 
void SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
 SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen. More...
 
virtual StringRef getPatternForIndex (unsigned index)
 getPatternForIndex - Patterns selected by tablegen during ISEL More...
 
virtual StringRef getIncludePathForIndex (unsigned index)
 getIncludePathForIndex - get the td source location of pattern instantiation More...
 
bool shouldOptForSize (const MachineFunction *MF) const
 
- Protected Member Functions inherited from llvm::MachineFunctionPass
 MachineFunctionPass (char &ID)
 
virtual MachineFunctionProperties getRequiredProperties () const
 
virtual MachineFunctionProperties getSetProperties () const
 
virtual MachineFunctionProperties getClearedProperties () const
 
- Protected Member Functions inherited from llvm::FunctionPass
bool skipFunction (const Function &F) const
 Optional passes call this function to check whether the pass should be skipped. More...
 
- Protected Attributes inherited from llvm::SelectionDAGISel
unsigned DAGSize
 DAGSize - Size of DAG being instruction selected. More...
 

Detailed Description

Definition at line 23 of file RISCVISelDAGToDAG.h.

Constructor & Destructor Documentation

◆ RISCVDAGToDAGISel()

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( RISCVTargetMachine TargetMachine)
inlineexplicit

Definition at line 27 of file RISCVISelDAGToDAG.h.

Member Function Documentation

◆ addVectorLoadStoreOperands()

void RISCVDAGToDAGISel::addVectorLoadStoreOperands ( SDNode Node,
unsigned  SEWImm,
const SDLoc DL,
unsigned  CurOp,
bool  IsMasked,
bool  IsStridedOrIndexed,
SmallVectorImpl< SDValue > &  Operands,
bool  IsLoad = false,
MVT IndexVT = nullptr 
)

Definition at line 216 of file RISCVISelDAGToDAG.cpp.

◆ getPassName()

StringRef llvm::RISCVDAGToDAGISel::getPassName ( ) const
inlineoverridevirtual

getPassName - Return a nice clean name for a pass.

This usually implemented in terms of the name that is registered by one of the Registration templates, but can be overloaded directly.

Reimplemented from llvm::Pass.

Definition at line 30 of file RISCVISelDAGToDAG.h.

◆ getRISCVCCForIntCC()

static RISCVCC::CondCode llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC ( ISD::CondCode  CC)
inlinestatic

◆ hasAllHUsers()

bool llvm::RISCVDAGToDAGISel::hasAllHUsers ( SDNode Node) const
inline

Definition at line 62 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

◆ hasAllNBitUsers()

bool RISCVDAGToDAGISel::hasAllNBitUsers ( SDNode Node,
unsigned  Bits 
) const

Definition at line 1608 of file RISCVISelDAGToDAG.cpp.

Referenced by hasAllHUsers(), and hasAllWUsers().

◆ hasAllWUsers()

bool llvm::RISCVDAGToDAGISel::hasAllWUsers ( SDNode Node) const
inline

Definition at line 63 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

◆ PostprocessISelDAG()

void RISCVDAGToDAGISel::PostprocessISelDAG ( )
overridevirtual

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 110 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, N, and llvm::SelectionDAG::RemoveDeadNodes().

◆ PreprocessISelDAG()

void RISCVDAGToDAGISel::PreprocessISelDAG ( )
overridevirtual

◆ runOnMachineFunction()

bool llvm::RISCVDAGToDAGISel::runOnMachineFunction ( MachineFunction MF)
inlineoverridevirtual

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 34 of file RISCVISelDAGToDAG.h.

References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().

◆ Select()

void RISCVDAGToDAGISel::Select ( SDNode N)
overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 466 of file RISCVISelDAGToDAG.cpp.

◆ SelectAddrFI()

bool RISCVDAGToDAGISel::SelectAddrFI ( SDValue  Addr,
SDValue Base 
)

◆ SelectBaseAddr()

bool RISCVDAGToDAGISel::SelectBaseAddr ( SDValue  Addr,
SDValue Base 
)

◆ SelectInlineAsmMemoryOperand()

bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand ( const SDValue Op,
unsigned  ConstraintID,
std::vector< SDValue > &  OutOps 
)
overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 1497 of file RISCVISelDAGToDAG.cpp.

References llvm::InlineAsm::Constraint_A, and llvm::InlineAsm::Constraint_m.

◆ selectRVVSimm5() [1/2]

template<unsigned Width>
bool llvm::RISCVDAGToDAGISel::selectRVVSimm5 ( SDValue  N,
SDValue Imm 
)
inline

Definition at line 74 of file RISCVISelDAGToDAG.h.

References N, and selectRVVSimm5().

◆ selectRVVSimm5() [2/2]

bool RISCVDAGToDAGISel::selectRVVSimm5 ( SDValue  N,
unsigned  Width,
SDValue Imm 
)

◆ selectSExti32()

bool RISCVDAGToDAGISel::selectSExti32 ( SDValue  N,
SDValue Val 
)

◆ selectShiftMask()

bool RISCVDAGToDAGISel::selectShiftMask ( SDValue  N,
unsigned  ShiftWidth,
SDValue ShAmt 
)

◆ selectShiftMask32()

bool llvm::RISCVDAGToDAGISel::selectShiftMask32 ( SDValue  N,
SDValue ShAmt 
)
inline

Definition at line 54 of file RISCVISelDAGToDAG.h.

References N, and selectShiftMask().

◆ selectShiftMaskXLen()

bool llvm::RISCVDAGToDAGISel::selectShiftMaskXLen ( SDValue  N,
SDValue ShAmt 
)
inline

Definition at line 51 of file RISCVISelDAGToDAG.h.

References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().

◆ selectVLOp()

bool RISCVDAGToDAGISel::selectVLOp ( SDValue  N,
SDValue VL 
)

◆ selectVLSEG()

void RISCVDAGToDAGISel::selectVLSEG ( SDNode Node,
bool  IsMasked,
bool  IsStrided 
)

Definition at line 261 of file RISCVISelDAGToDAG.cpp.

◆ selectVLSEGFF()

void RISCVDAGToDAGISel::selectVLSEGFF ( SDNode Node,
bool  IsMasked 
)

Definition at line 302 of file RISCVISelDAGToDAG.cpp.

◆ selectVLXSEG()

void RISCVDAGToDAGISel::selectVLXSEG ( SDNode Node,
bool  IsMasked,
bool  IsOrdered 
)

Definition at line 347 of file RISCVISelDAGToDAG.cpp.

◆ selectVSplat()

bool RISCVDAGToDAGISel::selectVSplat ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatSimm5()

bool RISCVDAGToDAGISel::selectVSplatSimm5 ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatSimm5Plus1()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1 ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatSimm5Plus1NonZero()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatUimm5()

bool RISCVDAGToDAGISel::selectVSplatUimm5 ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSSEG()

void RISCVDAGToDAGISel::selectVSSEG ( SDNode Node,
bool  IsMasked,
bool  IsStrided 
)

Definition at line 395 of file RISCVISelDAGToDAG.cpp.

◆ selectVSXSEG()

void RISCVDAGToDAGISel::selectVSXSEG ( SDNode Node,
bool  IsMasked,
bool  IsOrdered 
)

Definition at line 427 of file RISCVISelDAGToDAG.cpp.

◆ selectZExti32()

bool RISCVDAGToDAGISel::selectZExti32 ( SDValue  N,
SDValue Val 
)

The documentation for this class was generated from the following files: