LLVM 20.0.0git
RISCVISelDAGToDAG.h
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1//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISC-V target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15
16#include "RISCV.h"
17#include "RISCVTargetMachine.h"
20
21// RISC-V specific code to select RISC-V machine instructions for
22// SelectionDAG operations.
23namespace llvm {
25 const RISCVSubtarget *Subtarget = nullptr;
26
27public:
29
33
35 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
37 }
38
39 void PreprocessISelDAG() override;
40 void PostprocessISelDAG() override;
41
42 void Select(SDNode *Node) override;
43
45 InlineAsm::ConstraintCode ConstraintID,
46 std::vector<SDValue> &OutOps) override;
47
51 bool IsRV32Zdinx = false);
53 return SelectAddrRegImm(Addr, Base, Offset, true);
54 }
56
57 bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
58 SDValue &Base, SDValue &Index, SDValue &Scale);
59
60 template <unsigned MaxShift>
62 SDValue &Scale) {
63 return SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale);
64 }
65
66 template <unsigned MaxShift, unsigned Bits>
68 SDValue &Scale) {
69 if (SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale)) {
70 if (Index.getOpcode() == ISD::AND) {
71 auto *C = dyn_cast<ConstantSDNode>(Index.getOperand(1));
72 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
73 Index = Index.getOperand(0);
74 return true;
75 }
76 }
77 }
78 return false;
79 }
80
82
86
87 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
89 return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
90 }
92 return selectShiftMask(N, 32, ShAmt);
93 }
94
95 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
97 return selectSETCC(N, ISD::SETNE, Val);
98 }
100 return selectSETCC(N, ISD::SETEQ, Val);
101 }
102
103 bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
104 template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
105 return selectSExtBits(N, Bits, Val);
106 }
107 bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
108 template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
109 return selectZExtBits(N, Bits, Val);
110 }
111
112 bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
113 template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
114 return selectSHXADDOp(N, ShAmt, Val);
115 }
116
117 bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
118 template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
119 return selectSHXADD_UWOp(N, ShAmt, Val);
120 }
121
123
124 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
125 const unsigned Depth = 0) const;
126 bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 8); }
127 bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
128 bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
129
130 bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
131
132 bool selectVLOp(SDValue N, SDValue &VL);
133
134 bool selectVSplat(SDValue N, SDValue &SplatVal);
135 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
136 bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
137 template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {
138 return selectVSplatUimm(N, Bits, Val);
139 }
140 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
142 // Matches the splat of a value which can be extended or truncated, such that
143 // only the bottom 8 bits are preserved.
144 bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
146
147 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
148 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
149 return selectRVVSimm5(N, Width, Imm);
150 }
151
152 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
153 const SDLoc &DL, unsigned CurOp,
154 bool IsMasked, bool IsStridedOrIndexed,
156 bool IsLoad = false, MVT *IndexVT = nullptr);
157
158 void selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
159 void selectVLSEGFF(SDNode *Node, unsigned NF, bool IsMasked);
160 void selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
161 void selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
162 void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
163
165
167
168 // Return the RISC-V condition code that matches the given DAG integer
169 // condition code. The CondCode must be one of those supported by the RISC-V
170 // ISA (see translateSetCCForBranch).
172 switch (CC) {
173 default:
174 llvm_unreachable("Unsupported CondCode");
175 case ISD::SETEQ:
176 return RISCVCC::COND_EQ;
177 case ISD::SETNE:
178 return RISCVCC::COND_NE;
179 case ISD::SETLT:
180 return RISCVCC::COND_LT;
181 case ISD::SETGE:
182 return RISCVCC::COND_GE;
183 case ISD::SETULT:
184 return RISCVCC::COND_LTU;
185 case ISD::SETUGE:
186 return RISCVCC::COND_GEU;
187 }
188 }
189
190// Include the pieces autogenerated from the target description.
191#include "RISCVGenDAGISel.inc"
192
193private:
194 bool doPeepholeSExtW(SDNode *Node);
195 bool doPeepholeMaskedRVV(MachineSDNode *Node);
196 bool doPeepholeMergeVVMFold();
197 bool doPeepholeNoRegPassThru();
198 bool performCombineVMergeAndVOps(SDNode *N);
199};
200
202public:
203 static char ID;
205 CodeGenOptLevel OptLevel);
206};
207
208namespace RISCV {
217};
218
227};
228
236};
237
246};
247
248struct VLEPseudo {
255};
256
257struct VSEPseudo {
263};
264
272};
273
274#define GET_RISCVVSSEGTable_DECL
275#define GET_RISCVVLSEGTable_DECL
276#define GET_RISCVVLXSEGTable_DECL
277#define GET_RISCVVSXSEGTable_DECL
278#define GET_RISCVVLETable_DECL
279#define GET_RISCVVSETable_DECL
280#define GET_RISCVVLXTable_DECL
281#define GET_RISCVVSXTable_DECL
282} // namespace RISCV
283
284} // namespace llvm
285
286#endif
AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
uint64_t Addr
uint32_t Index
mir Rename Register Operands
This class represents an Operation in the Expression.
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...
bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset, bool IsRV32Zdinx=false)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool selectVSplatUimmBits(SDValue N, SDValue &Val)
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset)
Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset should be all zeros.
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSETEQ(SDValue N, SDValue &Val)
void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
void selectVLSEGFF(SDNode *Node, unsigned NF, bool IsMasked)
bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)
void selectSF_VC_X_SE(SDNode *Node)
bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal)
bool hasAllHUsers(SDNode *Node) const
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool SelectAddrRegImmRV32Zdinx(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
bool hasAllWUsers(SDNode *Node) const
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool runOnMachineFunction(MachineFunction &MF) override
bool selectInvLogicImm(SDValue N, SDValue &Val)
bool selectSExtBits(SDValue N, SDValue &Val)
bool selectVSplat(SDValue N, SDValue &SplatVal)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool selectScalarFPAsInt(SDValue N, SDValue &Imm)
bool hasAllBUsers(SDNode *Node) const
void selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSETNE(SDValue N, SDValue &Val)
bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
void selectVSETVLI(SDNode *Node)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool selectVLOp(SDValue N, SDValue &VL)
bool trySignedBitfieldExtract(SDNode *Node)
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, SDValue &Imm)
void selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool selectSHXADDOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, SDValue &Val)
void selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered)
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool tryIndexedLoad(SDNode *Node)
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal)
unsigned getXLen() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineFunction * MF
CodeGenOptLevel OptLevel
virtual bool runOnMachineFunction(MachineFunction &mf)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:709
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1613
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
#define N