LLVM  16.0.0git
RISCVISelDAGToDAG.h
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1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the RISCV target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15 
16 #include "RISCV.h"
17 #include "RISCVTargetMachine.h"
19 
20 // RISCV-specific code to select RISCV machine instructions for
21 // SelectionDAG operations.
22 namespace llvm {
24  const RISCVSubtarget *Subtarget = nullptr;
25 
26 public:
30 
31  StringRef getPassName() const override {
32  return "RISCV DAG->DAG Pattern Instruction Selection";
33  }
34 
36  Subtarget = &MF.getSubtarget<RISCVSubtarget>();
38  }
39 
40  void PreprocessISelDAG() override;
41  void PostprocessISelDAG() override;
42 
43  void Select(SDNode *Node) override;
44 
45  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
46  std::vector<SDValue> &OutOps) override;
47 
51 
53 
54  bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
56  return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
57  }
59  return selectShiftMask(N, 32, ShAmt);
60  }
61 
62  bool selectSExti32(SDValue N, SDValue &Val);
63  bool selectZExti32(SDValue N, SDValue &Val);
64 
65  bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
67  return selectSHXADDOp(N, 1, Val);
68  }
70  return selectSHXADDOp(N, 2, Val);
71  }
73  return selectSHXADDOp(N, 3, Val);
74  }
75 
76  bool hasAllNBitUsers(SDNode *Node, unsigned Bits) const;
77  bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
78  bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
79 
80  bool selectVLOp(SDValue N, SDValue &VL);
81 
82  bool selectVSplat(SDValue N, SDValue &SplatVal);
83  bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
84  bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
85  bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
87 
88  bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
89  template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
90  return selectRVVSimm5(N, Width, Imm);
91  }
92 
93  void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
94  const SDLoc &DL, unsigned CurOp,
95  bool IsMasked, bool IsStridedOrIndexed,
97  bool IsLoad = false, MVT *IndexVT = nullptr);
98 
99  void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
100  void selectVLSEGFF(SDNode *Node, bool IsMasked);
101  void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
102  void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
103  void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
104 
105  void selectVSETVLI(SDNode *Node);
106 
107  // Return the RISC-V condition code that matches the given DAG integer
108  // condition code. The CondCode must be one of those supported by the RISC-V
109  // ISA (see translateSetCCForBranch).
111  switch (CC) {
112  default:
113  llvm_unreachable("Unsupported CondCode");
114  case ISD::SETEQ:
115  return RISCVCC::COND_EQ;
116  case ISD::SETNE:
117  return RISCVCC::COND_NE;
118  case ISD::SETLT:
119  return RISCVCC::COND_LT;
120  case ISD::SETGE:
121  return RISCVCC::COND_GE;
122  case ISD::SETULT:
123  return RISCVCC::COND_LTU;
124  case ISD::SETUGE:
125  return RISCVCC::COND_GEU;
126  }
127  }
128 
129 // Include the pieces autogenerated from the target description.
130 #include "RISCVGenDAGISel.inc"
131 
132 private:
133  bool doPeepholeSExtW(SDNode *Node);
134  bool doPeepholeMaskedRVV(SDNode *Node);
135  bool doPeepholeMergeVVMFold();
136 };
137 
138 namespace RISCV {
139 struct VLSEGPseudo {
148 };
149 
150 struct VLXSEGPseudo {
159 };
160 
161 struct VSSEGPseudo {
168 };
169 
170 struct VSXSEGPseudo {
178 };
179 
180 struct VLEPseudo {
188 };
189 
190 struct VSEPseudo {
196 };
197 
206 };
207 
212  uint8_t MaskOpIdx;
213 };
214 
215 #define GET_RISCVVSSEGTable_DECL
216 #define GET_RISCVVLSEGTable_DECL
217 #define GET_RISCVVLXSEGTable_DECL
218 #define GET_RISCVVSXSEGTable_DECL
219 #define GET_RISCVVLETable_DECL
220 #define GET_RISCVVSETable_DECL
221 #define GET_RISCVVLXTable_DECL
222 #define GET_RISCVVSXTable_DECL
223 #define GET_RISCVMaskedPseudosTable_DECL
224 #include "RISCVGenSearchableTables.inc"
225 } // namespace RISCV
226 
227 } // namespace llvm
228 
229 #endif
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1437
llvm::RISCV::VLX_VSXPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:199
llvm::RISCVDAGToDAGISel::selectVLXSEG
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
Definition: RISCVISelDAGToDAG.cpp:384
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCV::VLSEGPseudo
Definition: RISCVISelDAGToDAG.h:139
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1094
llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2388
llvm::RISCVCC::COND_GEU
@ COND_GEU
Definition: RISCVInstrInfo.h:36
llvm::RISCV::VSXSEGPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:176
llvm::RISCVDAGToDAGISel::PreprocessISelDAG
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
Definition: RISCVISelDAGToDAG.cpp:43
llvm::RISCVDAGToDAGISel::selectRVVSimm5
bool selectRVVSimm5(SDValue N, SDValue &Imm)
Definition: RISCVISelDAGToDAG.h:89
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1449
llvm::RISCV::VLEPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:185
llvm::RISCV::VLX_VSXPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:204
llvm::RISCV::VLXSEGPseudo
Definition: RISCVISelDAGToDAG.h:150
llvm::RISCVDAGToDAGISel::selectZExti32
bool selectZExti32(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.cpp:2094
llvm::RISCV::VLSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:146
llvm::RISCVDAGToDAGISel::selectVSETVLI
void selectVSETVLI(SDNode *Node)
Definition: RISCVISelDAGToDAG.cpp:512
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1444
llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
Definition: RISCVISelDAGToDAG.cpp:1850
llvm::RISCV::VSXSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:174
llvm::RISCV::VSSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:165
llvm::RISCV::VSSEGPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:164
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:458
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::RISCVDAGToDAGISel::selectVSplat
bool selectVSplat(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2342
llvm::RISCVDAGToDAGISel
Definition: RISCVISelDAGToDAG.h:23
llvm::RISCVDAGToDAGISel::getPassName
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: RISCVISelDAGToDAG.h:31
llvm::RISCV::RISCVMaskedPseudoInfo::UnmaskedPseudo
uint16_t UnmaskedPseudo
Definition: RISCVISelDAGToDAG.h:210
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::RISCV::VLX_VSXPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:200
llvm::RISCVDAGToDAGISel::selectSH1ADDOp
bool selectSH1ADDOp(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.h:66
llvm::RISCV::VLX_VSXPseudo
Definition: RISCVISelDAGToDAG.h:198
llvm::RISCV::VLXSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:155
llvm::RISCV::VLSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:141
llvm::RISCV::VLSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:145
llvm::RISCVDAGToDAGISel::selectVSSEG
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Definition: RISCVISelDAGToDAG.cpp:438
llvm::RISCV::VSSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:163
llvm::RISCV::VLXSEGPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:157
llvm::RISCV::VLSEGPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:142
llvm::RISCV::VLXSEGPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:153
llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2394
llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
Definition: RISCVISelDAGToDAG.cpp:1838
llvm::RISCV::VSSEGPseudo
Definition: RISCVISelDAGToDAG.h:161
llvm::RISCV::RISCVMaskedPseudoInfo
Definition: RISCVISelDAGToDAG.h:208
llvm::RISCV::RISCVMaskedPseudoInfo::UnmaskedTUPseudo
uint16_t UnmaskedTUPseudo
Definition: RISCVISelDAGToDAG.h:211
llvm::RISCVDAGToDAGISel::selectShiftMask
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.cpp:2033
llvm::RISCV::VLX_VSXPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:201
llvm::RISCVCC::COND_LT
@ COND_LT
Definition: RISCVInstrInfo.h:33
llvm::RISCV::VLEPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:181
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1446
llvm::RISCVDAGToDAGISel::selectSH3ADDOp
bool selectSH3ADDOp(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.h:72
llvm::SelectionDAGISel::OptLevel
CodeGenOpt::Level OptLevel
Definition: SelectionDAGISel.h:52
llvm::RISCV::VSSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:167
llvm::RISCVCC::COND_LTU
@ COND_LTU
Definition: RISCVInstrInfo.h:35
llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
Definition: RISCVISelDAGToDAG.cpp:1820
llvm::RISCV::VLXSEGPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:154
llvm::RISCVDAGToDAGISel::selectShiftMask32
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.h:58
llvm::RISCVDAGToDAGISel::SelectAddrRegImm
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
Definition: RISCVISelDAGToDAG.cpp:1943
llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
Definition: RISCVISelDAGToDAG.h:110
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::RISCV::VLX_VSXPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:205
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::RISCV::VSEPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:192
llvm::RISCV::VSEPseudo
Definition: RISCVISelDAGToDAG.h:190
llvm::RISCVDAGToDAGISel::selectVLOp
bool selectVLOp(SDValue N, SDValue &VL)
Definition: RISCVISelDAGToDAG.cpp:2318
llvm::RISCVDAGToDAGISel::selectVSXSEG
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
Definition: RISCVISelDAGToDAG.cpp:470
llvm::RISCVDAGToDAGISel::selectShiftMaskXLen
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.h:55
llvm::RISCVDAGToDAGISel::selectVSplatUimm5
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2402
llvm::RISCV::VSSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:166
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::RISCV::VSXSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:171
llvm::RISCVCC::COND_EQ
@ COND_EQ
Definition: RISCVInstrInfo.h:31
llvm::RISCV::VSEPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:194
llvm::RISCV::VLXSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:152
llvm::RISCVDAGToDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: RISCVISelDAGToDAG.h:35
llvm::RISCV::VLEPseudo::FF
uint16_t FF
Definition: RISCVISelDAGToDAG.h:184
llvm::RISCV::VLSEGPseudo::FF
uint16_t FF
Definition: RISCVISelDAGToDAG.h:144
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo
uint16_t MaskedPseudo
Definition: RISCVISelDAGToDAG.h:209
llvm::RISCVDAGToDAGISel::selectVLSEG
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Definition: RISCVISelDAGToDAG.cpp:296
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1438
llvm::RISCV::VLSEGPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:143
llvm::RISCVDAGToDAGISel::selectSH2ADDOp
bool selectSH2ADDOp(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.h:69
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::RISCV::VLXSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:156
llvm::RISCVDAGToDAGISel::hasAllWUsers
bool hasAllWUsers(SDNode *Node) const
Definition: RISCVISelDAGToDAG.h:78
llvm::RISCV::RISCVMaskedPseudoInfo::MaskOpIdx
uint8_t MaskOpIdx
Definition: RISCVISelDAGToDAG.h:212
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVDAGToDAGISel::selectVSplatSimm5
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2383
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)
Definition: RISCVISelDAGToDAG.h:27
llvm::RISCV::VSEPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:195
SelectionDAGISel.h
llvm::RISCV::VLSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:140
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RISCV::VSXSEGPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:173
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RISCV::VSEPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:191
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCV::VLSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:147
Node
Definition: ItaniumDemangle.h:155
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::RISCV::VSXSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:172
llvm::RISCV::VSEPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:193
llvm::SelectionDAGISel::MF
MachineFunction * MF
Definition: SelectionDAGISel.h:46
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1447
llvm::RISCV::VLXSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:151
uint16_t
llvm::RISCV::VLX_VSXPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:202
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::RISCV::VSXSEGPseudo
Definition: RISCVISelDAGToDAG.h:170
llvm::RISCVDAGToDAGISel::PostprocessISelDAG
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
Definition: RISCVISelDAGToDAG.cpp:135
llvm::RISCVDAGToDAGISel::selectVLSEGFF
void selectVLSEGFF(SDNode *Node, bool IsMasked)
Definition: RISCVISelDAGToDAG.cpp:339
llvm::RISCV::VLEPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:182
llvm::RISCV::VLEPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:186
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:200
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:141
llvm::RISCV::VLX_VSXPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:203
llvm::RISCVCC::COND_GE
@ COND_GE
Definition: RISCVInstrInfo.h:34
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm
bool tryShrinkShlLogicImm(SDNode *Node)
Definition: RISCVISelDAGToDAG.cpp:582
llvm::RISCV::VSXSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:177
llvm::RISCVCC::CondCode
CondCode
Definition: RISCVInstrInfo.h:30
llvm::SelectionDAGISel
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
Definition: SelectionDAGISel.h:40
N
#define N
llvm::RISCVDAGToDAGISel::selectRVVSimm5
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
Definition: RISCVISelDAGToDAG.cpp:2419
llvm::RISCV::VLEPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:183
llvm::RISCVDAGToDAGISel::Select
void Select(SDNode *Node) override
Main hook for targets to transform nodes into machine nodes.
Definition: RISCVISelDAGToDAG.cpp:660
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::RISCV::VLXSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:158
llvm::SelectionDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: SelectionDAGISel.cpp:371
llvm::RISCV::VSXSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:175
llvm::RISCVDAGToDAGISel::selectSHXADDOp
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
Definition: RISCVISelDAGToDAG.cpp:2115
llvm::RISCV::VLEPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:187
llvm::RISCV::VLEPseudo
Definition: RISCVISelDAGToDAG.h:180
llvm::RISCVDAGToDAGISel::hasAllHUsers
bool hasAllHUsers(SDNode *Node) const
Definition: RISCVISelDAGToDAG.h:77
llvm::RISCVDAGToDAGISel::hasAllNBitUsers
bool hasAllNBitUsers(SDNode *Node, unsigned Bits) const
Definition: RISCVISelDAGToDAG.cpp:2218
llvm::RISCVDAGToDAGISel::selectSExti32
bool selectSExti32(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.cpp:2079
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::RISCVCC::COND_NE
@ COND_NE
Definition: RISCVInstrInfo.h:32
llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
Definition: RISCVISelDAGToDAG.cpp:249
RISCVTargetMachine.h
llvm::RISCV::VSSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:162