LLVM 17.0.0git
RISCVISelDAGToDAG.h
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1//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISCV target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15
16#include "RISCV.h"
17#include "RISCVTargetMachine.h"
20
21// RISCV-specific code to select RISCV machine instructions for
22// SelectionDAG operations.
23namespace llvm {
25 const RISCVSubtarget *Subtarget = nullptr;
26
27public:
28 static char ID;
29
31
35
37 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
39 }
40
41 void PreprocessISelDAG() override;
42 void PostprocessISelDAG() override;
43
44 void Select(SDNode *Node) override;
45
46 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
47 std::vector<SDValue> &OutOps) override;
48
52
53 bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
54 SDValue &Base, SDValue &Index, SDValue &Scale);
55
56 template <unsigned MaxShift>
58 SDValue &Scale) {
59 return SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale);
60 }
61
62 template <unsigned MaxShift, unsigned Bits>
64 SDValue &Scale) {
65 if (SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale)) {
66 if (Index.getOpcode() == ISD::AND) {
67 auto *C = dyn_cast<ConstantSDNode>(Index.getOperand(1));
68 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
69 Index = Index.getOperand(0);
70 return true;
71 }
72 }
73 }
74 return false;
75 }
76
80
81 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
83 return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
84 }
86 return selectShiftMask(N, 32, ShAmt);
87 }
88
89 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
91 return selectSETCC(N, ISD::SETNE, Val);
92 }
94 return selectSETCC(N, ISD::SETEQ, Val);
95 }
96
97 bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
98 template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
99 return selectSExtBits(N, Bits, Val);
100 }
101 bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
102 template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
103 return selectZExtBits(N, Bits, Val);
104 }
105
106 bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
107 template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
108 return selectSHXADDOp(N, ShAmt, Val);
109 }
110
111 bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
112 template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
113 return selectSHXADD_UWOp(N, ShAmt, Val);
114 }
115
116 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
117 const unsigned Depth = 0) const;
118 bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
119 bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
120
121 bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
122
123 bool selectVLOp(SDValue N, SDValue &VL);
124
125 bool selectVSplat(SDValue N, SDValue &SplatVal);
126 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
127 bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
128 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
130 bool selectFPImm(SDValue N, SDValue &Imm);
131
132 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
133 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
134 return selectRVVSimm5(N, Width, Imm);
135 }
136
137 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
138 const SDLoc &DL, unsigned CurOp,
139 bool IsMasked, bool IsStridedOrIndexed,
141 bool IsLoad = false, MVT *IndexVT = nullptr);
142
143 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
144 void selectVLSEGFF(SDNode *Node, bool IsMasked);
145 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
146 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
147 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
148
150
151 // Return the RISC-V condition code that matches the given DAG integer
152 // condition code. The CondCode must be one of those supported by the RISC-V
153 // ISA (see translateSetCCForBranch).
155 switch (CC) {
156 default:
157 llvm_unreachable("Unsupported CondCode");
158 case ISD::SETEQ:
159 return RISCVCC::COND_EQ;
160 case ISD::SETNE:
161 return RISCVCC::COND_NE;
162 case ISD::SETLT:
163 return RISCVCC::COND_LT;
164 case ISD::SETGE:
165 return RISCVCC::COND_GE;
166 case ISD::SETULT:
167 return RISCVCC::COND_LTU;
168 case ISD::SETUGE:
169 return RISCVCC::COND_GEU;
170 }
171 }
172
173// Include the pieces autogenerated from the target description.
174#include "RISCVGenDAGISel.inc"
175
176private:
177 bool doPeepholeSExtW(SDNode *Node);
178 bool doPeepholeMaskedRVV(SDNode *Node);
179 bool doPeepholeMergeVVMFold();
180 bool performVMergeToVAdd(SDNode *N);
181 bool performCombineVMergeAndVOps(SDNode *N, bool IsTA);
182};
183
184namespace RISCV {
194};
195
205};
206
214};
215
224};
225
226struct VLEPseudo {
234};
235
236struct VSEPseudo {
242};
243
252};
253
258 uint8_t MaskOpIdx;
259};
260
261#define GET_RISCVVSSEGTable_DECL
262#define GET_RISCVVLSEGTable_DECL
263#define GET_RISCVVLXSEGTable_DECL
264#define GET_RISCVVSXSEGTable_DECL
265#define GET_RISCVVLETable_DECL
266#define GET_RISCVVSETable_DECL
267#define GET_RISCVVLXTable_DECL
268#define GET_RISCVVSXTable_DECL
269#define GET_RISCVMaskedPseudosTable_DECL
270#include "RISCVGenSearchableTables.inc"
271} // namespace RISCV
272
273} // namespace llvm
274
275#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
uint64_t Addr
mir Rename Register Operands
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...
bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal)
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSETEQ(SDValue N, SDValue &Val)
void selectVLSEGFF(SDNode *Node, bool IsMasked)
bool selectFPImm(SDValue N, SDValue &Imm)
bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)
bool hasAllHUsers(SDNode *Node) const
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
bool hasAllWUsers(SDNode *Node) const
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSExtBits(SDValue N, SDValue &Val)
bool selectVSplat(SDValue N, SDValue &SplatVal)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSETNE(SDValue N, SDValue &Val)
bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
void selectVSETVLI(SDNode *Node)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVLOp(SDValue N, SDValue &VL)
bool trySignedBitfieldExtract(SDNode *Node)
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, SDValue &Imm)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)
bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool selectSHXADDOp(SDValue N, SDValue &Val)
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectZExtBits(SDValue N, SDValue &Val)
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool tryIndexedLoad(SDNode *Node)
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
unsigned getXLen() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
CodeGenOpt::Level OptLevel
MachineFunction * MF
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:679
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1447
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
#define N