LLVM 19.0.0git
RISCVISelDAGToDAG.h
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1//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISC-V target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15
16#include "RISCV.h"
17#include "RISCVTargetMachine.h"
20
21// RISC-V specific code to select RISC-V machine instructions for
22// SelectionDAG operations.
23namespace llvm {
25 const RISCVSubtarget *Subtarget = nullptr;
26
27public:
28 static char ID;
29
31
35
37 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
39 }
40
41 void PreprocessISelDAG() override;
42 void PostprocessISelDAG() override;
43
44 void Select(SDNode *Node) override;
45
47 InlineAsm::ConstraintCode ConstraintID,
48 std::vector<SDValue> &OutOps) override;
49
53 bool IsINX = false);
55 return SelectAddrRegImm(Addr, Base, Offset, true);
56 }
58
59 bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
60 SDValue &Base, SDValue &Index, SDValue &Scale);
61
62 template <unsigned MaxShift>
64 SDValue &Scale) {
65 return SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale);
66 }
67
68 template <unsigned MaxShift, unsigned Bits>
70 SDValue &Scale) {
71 if (SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale)) {
72 if (Index.getOpcode() == ISD::AND) {
73 auto *C = dyn_cast<ConstantSDNode>(Index.getOperand(1));
74 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
75 Index = Index.getOperand(0);
76 return true;
77 }
78 }
79 }
80 return false;
81 }
82
86
87 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
89 return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
90 }
92 return selectShiftMask(N, 32, ShAmt);
93 }
94
95 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
97 return selectSETCC(N, ISD::SETNE, Val);
98 }
100 return selectSETCC(N, ISD::SETEQ, Val);
101 }
102
103 bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
104 template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
105 return selectSExtBits(N, Bits, Val);
106 }
107 bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
108 template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
109 return selectZExtBits(N, Bits, Val);
110 }
111
112 bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
113 template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
114 return selectSHXADDOp(N, ShAmt, Val);
115 }
116
117 bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
118 template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
119 return selectSHXADD_UWOp(N, ShAmt, Val);
120 }
121
122 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
123 const unsigned Depth = 0) const;
124 bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
125 bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
126
127 bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
128
129 bool selectVLOp(SDValue N, SDValue &VL);
130
131 bool selectVSplat(SDValue N, SDValue &SplatVal);
132 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
133 bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
134 template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {
135 return selectVSplatUimm(N, Bits, Val);
136 }
137 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
139 // Matches the splat of a value which can be extended or truncated, such that
140 // only the bottom 8 bits are preserved.
141 bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
142 bool selectFPImm(SDValue N, SDValue &Imm);
143
144 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
145 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
146 return selectRVVSimm5(N, Width, Imm);
147 }
148
149 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
150 const SDLoc &DL, unsigned CurOp,
151 bool IsMasked, bool IsStridedOrIndexed,
153 bool IsLoad = false, MVT *IndexVT = nullptr);
154
155 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
156 void selectVLSEGFF(SDNode *Node, bool IsMasked);
157 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
158 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
159 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
160
162
164
165 // Return the RISC-V condition code that matches the given DAG integer
166 // condition code. The CondCode must be one of those supported by the RISC-V
167 // ISA (see translateSetCCForBranch).
169 switch (CC) {
170 default:
171 llvm_unreachable("Unsupported CondCode");
172 case ISD::SETEQ:
173 return RISCVCC::COND_EQ;
174 case ISD::SETNE:
175 return RISCVCC::COND_NE;
176 case ISD::SETLT:
177 return RISCVCC::COND_LT;
178 case ISD::SETGE:
179 return RISCVCC::COND_GE;
180 case ISD::SETULT:
181 return RISCVCC::COND_LTU;
182 case ISD::SETUGE:
183 return RISCVCC::COND_GEU;
184 }
185 }
186
187// Include the pieces autogenerated from the target description.
188#include "RISCVGenDAGISel.inc"
189
190private:
191 bool doPeepholeSExtW(SDNode *Node);
192 bool doPeepholeMaskedRVV(MachineSDNode *Node);
193 bool doPeepholeMergeVVMFold();
194 bool doPeepholeNoRegPassThru();
195 bool performCombineVMergeAndVOps(SDNode *N);
196};
197
198namespace RISCV {
207};
208
217};
218
226};
227
236};
237
238struct VLEPseudo {
245};
246
247struct VSEPseudo {
253};
254
262};
263
267 uint8_t MaskOpIdx;
268 uint8_t MaskAffectsResult : 1;
269};
270
271#define GET_RISCVVSSEGTable_DECL
272#define GET_RISCVVLSEGTable_DECL
273#define GET_RISCVVLXSEGTable_DECL
274#define GET_RISCVVSXSEGTable_DECL
275#define GET_RISCVVLETable_DECL
276#define GET_RISCVVSETable_DECL
277#define GET_RISCVVLXTable_DECL
278#define GET_RISCVVSXTable_DECL
279#define GET_RISCVMaskedPseudosTable_DECL
280#include "RISCVGenSearchableTables.inc"
281} // namespace RISCV
282
283} // namespace llvm
284
285#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
uint64_t Addr
mir Rename Register Operands
This class represents an Operation in the Expression.
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...
bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool SelectAddrRegImmINX(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectVSplatUimmBits(SDValue N, SDValue &Val)
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset)
Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSETEQ(SDValue N, SDValue &Val)
void selectVLSEGFF(SDNode *Node, bool IsMasked)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
bool selectFPImm(SDValue N, SDValue &Imm)
bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)
void selectSF_VC_X_SE(SDNode *Node)
bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal)
bool hasAllHUsers(SDNode *Node) const
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
bool hasAllWUsers(SDNode *Node) const
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool selectSExtBits(SDValue N, SDValue &Val)
bool selectVSplat(SDValue N, SDValue &SplatVal)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSETNE(SDValue N, SDValue &Val)
bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
void selectVSETVLI(SDNode *Node)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool selectVLOp(SDValue N, SDValue &VL)
bool trySignedBitfieldExtract(SDNode *Node)
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, SDValue &Imm)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false)
bool selectSHXADDOp(SDValue N, SDValue &Val)
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectZExtBits(SDValue N, SDValue &Val)
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool tryIndexedLoad(SDNode *Node)
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal)
unsigned getXLen() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineFunction * MF
CodeGenOptLevel OptLevel
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1512
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
#define N