LLVM 19.0.0git
RISCVISelDAGToDAG.h
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1//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISC-V target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15
16#include "RISCV.h"
17#include "RISCVTargetMachine.h"
20
21// RISC-V specific code to select RISC-V machine instructions for
22// SelectionDAG operations.
23namespace llvm {
25 const RISCVSubtarget *Subtarget = nullptr;
26
27public:
29
33
35 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
37 }
38
39 void PreprocessISelDAG() override;
40 void PostprocessISelDAG() override;
41
42 void Select(SDNode *Node) override;
43
45 InlineAsm::ConstraintCode ConstraintID,
46 std::vector<SDValue> &OutOps) override;
47
51 bool IsINX = false);
53 return SelectAddrRegImm(Addr, Base, Offset, true);
54 }
56
57 bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
58 SDValue &Base, SDValue &Index, SDValue &Scale);
59
60 template <unsigned MaxShift>
62 SDValue &Scale) {
63 return SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale);
64 }
65
66 template <unsigned MaxShift, unsigned Bits>
68 SDValue &Scale) {
69 if (SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale)) {
70 if (Index.getOpcode() == ISD::AND) {
71 auto *C = dyn_cast<ConstantSDNode>(Index.getOperand(1));
72 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
73 Index = Index.getOperand(0);
74 return true;
75 }
76 }
77 }
78 return false;
79 }
80
82
86
87 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
89 return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
90 }
92 return selectShiftMask(N, 32, ShAmt);
93 }
94
95 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
97 return selectSETCC(N, ISD::SETNE, Val);
98 }
100 return selectSETCC(N, ISD::SETEQ, Val);
101 }
102
103 bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
104 template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
105 return selectSExtBits(N, Bits, Val);
106 }
107 bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
108 template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
109 return selectZExtBits(N, Bits, Val);
110 }
111
112 bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
113 template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
114 return selectSHXADDOp(N, ShAmt, Val);
115 }
116
117 bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
118 template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
119 return selectSHXADD_UWOp(N, ShAmt, Val);
120 }
121
122 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
123 const unsigned Depth = 0) const;
124 bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 8); }
125 bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
126 bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
127
128 bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
129
130 bool selectVLOp(SDValue N, SDValue &VL);
131
132 bool selectVSplat(SDValue N, SDValue &SplatVal);
133 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
134 bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
135 template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {
136 return selectVSplatUimm(N, Bits, Val);
137 }
138 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
140 // Matches the splat of a value which can be extended or truncated, such that
141 // only the bottom 8 bits are preserved.
142 bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
143 bool selectFPImm(SDValue N, SDValue &Imm);
144
145 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
146 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
147 return selectRVVSimm5(N, Width, Imm);
148 }
149
150 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
151 const SDLoc &DL, unsigned CurOp,
152 bool IsMasked, bool IsStridedOrIndexed,
154 bool IsLoad = false, MVT *IndexVT = nullptr);
155
156 void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
157 void selectVLSEGFF(SDNode *Node, bool IsMasked);
158 void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
159 void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
160 void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
161
163
165
166 // Return the RISC-V condition code that matches the given DAG integer
167 // condition code. The CondCode must be one of those supported by the RISC-V
168 // ISA (see translateSetCCForBranch).
170 switch (CC) {
171 default:
172 llvm_unreachable("Unsupported CondCode");
173 case ISD::SETEQ:
174 return RISCVCC::COND_EQ;
175 case ISD::SETNE:
176 return RISCVCC::COND_NE;
177 case ISD::SETLT:
178 return RISCVCC::COND_LT;
179 case ISD::SETGE:
180 return RISCVCC::COND_GE;
181 case ISD::SETULT:
182 return RISCVCC::COND_LTU;
183 case ISD::SETUGE:
184 return RISCVCC::COND_GEU;
185 }
186 }
187
188// Include the pieces autogenerated from the target description.
189#include "RISCVGenDAGISel.inc"
190
191private:
192 bool doPeepholeSExtW(SDNode *Node);
193 bool doPeepholeMaskedRVV(MachineSDNode *Node);
194 bool doPeepholeMergeVVMFold();
195 bool doPeepholeNoRegPassThru();
196 bool performCombineVMergeAndVOps(SDNode *N);
197};
198
200public:
201 static char ID;
203 CodeGenOptLevel OptLevel);
204};
205
206namespace RISCV {
215};
216
225};
226
234};
235
244};
245
246struct VLEPseudo {
253};
254
255struct VSEPseudo {
261};
262
270};
271
272#define GET_RISCVVSSEGTable_DECL
273#define GET_RISCVVLSEGTable_DECL
274#define GET_RISCVVLXSEGTable_DECL
275#define GET_RISCVVSXSEGTable_DECL
276#define GET_RISCVVLETable_DECL
277#define GET_RISCVVSETable_DECL
278#define GET_RISCVVLXTable_DECL
279#define GET_RISCVVSXTable_DECL
280} // namespace RISCV
281
282} // namespace llvm
283
284#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
uint64_t Addr
mir Rename Register Operands
This class represents an Operation in the Expression.
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...
bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool SelectAddrRegImmINX(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectVSplatUimmBits(SDValue N, SDValue &Val)
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset)
Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSETEQ(SDValue N, SDValue &Val)
void selectVLSEGFF(SDNode *Node, bool IsMasked)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
bool selectFPImm(SDValue N, SDValue &Imm)
bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)
void selectSF_VC_X_SE(SDNode *Node)
bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal)
bool hasAllHUsers(SDNode *Node) const
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
bool hasAllWUsers(SDNode *Node) const
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool runOnMachineFunction(MachineFunction &MF) override
bool selectSExtBits(SDValue N, SDValue &Val)
bool selectVSplat(SDValue N, SDValue &SplatVal)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool hasAllBUsers(SDNode *Node) const
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSETNE(SDValue N, SDValue &Val)
bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
void selectVSETVLI(SDNode *Node)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool selectVLOp(SDValue N, SDValue &VL)
bool trySignedBitfieldExtract(SDNode *Node)
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, SDValue &Imm)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false)
bool selectSHXADDOp(SDValue N, SDValue &Val)
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectZExtBits(SDValue N, SDValue &Val)
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool tryIndexedLoad(SDNode *Node)
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal)
unsigned getXLen() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineFunction * MF
CodeGenOptLevel OptLevel
virtual bool runOnMachineFunction(MachineFunction &mf)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:688
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1548
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
#define N