13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
47 std::vector<SDValue> &OutOps)
override;
56 template <
unsigned MaxShift>
62 template <
unsigned MaxShift,
unsigned Bits>
67 auto *
C = dyn_cast<ConstantSDNode>(
Index.getOperand(1));
68 if (
C &&
C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
117 const unsigned Depth = 0)
const;
138 const SDLoc &
DL,
unsigned CurOp,
139 bool IsMasked,
bool IsStridedOrIndexed,
141 bool IsLoad =
false,
MVT *IndexVT =
nullptr);
174#include "RISCVGenDAGISel.inc"
179 bool doPeepholeMergeVVMFold();
180 bool performVMergeToVAdd(
SDNode *
N);
181 bool performCombineVMergeAndVOps(
SDNode *
N,
bool IsTA);
261#define GET_RISCVVSSEGTable_DECL
262#define GET_RISCVVLSEGTable_DECL
263#define GET_RISCVVLXSEGTable_DECL
264#define GET_RISCVVSXSEGTable_DECL
265#define GET_RISCVVLETable_DECL
266#define GET_RISCVVSETable_DECL
267#define GET_RISCVVLXTable_DECL
268#define GET_RISCVVSXTable_DECL
269#define GET_RISCVMaskedPseudosTable_DECL
270#include "RISCVGenSearchableTables.inc"
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
mir Rename Register Operands
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...
bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal)
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSETEQ(SDValue N, SDValue &Val)
void selectVLSEGFF(SDNode *Node, bool IsMasked)
bool selectFPImm(SDValue N, SDValue &Imm)
bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)
bool hasAllHUsers(SDNode *Node) const
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
bool hasAllWUsers(SDNode *Node) const
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSExtBits(SDValue N, SDValue &Val)
RISCVDAGToDAGISel()=delete
bool selectVSplat(SDValue N, SDValue &SplatVal)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSETNE(SDValue N, SDValue &Val)
bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
void selectVSETVLI(SDNode *Node)
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVLOp(SDValue N, SDValue &VL)
bool trySignedBitfieldExtract(SDNode *Node)
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
bool selectRVVSimm5(SDValue N, SDValue &Imm)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)
bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool selectSHXADDOp(SDValue N, SDValue &Val)
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectZExtBits(SDValue N, SDValue &Val)
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool tryIndexedLoad(SDNode *Node)
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
CodeGenOpt::Level OptLevel
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Primary interface to the complete machine description for the target machine.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Level
Code generation optimization level.
@ AND
Bitwise operators - logical and, logical or, logical xor.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
This is an optimization pass for GlobalISel generic memory operations.
uint16_t UnmaskedTUPseudo