LLVM  14.0.0git
RISCVSubtarget.h
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1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
17 #include "RISCVFrameLowering.h"
18 #include "RISCVISelLowering.h"
19 #include "RISCVInstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
36  virtual void anchor();
37  bool HasStdExtM = false;
38  bool HasStdExtA = false;
39  bool HasStdExtF = false;
40  bool HasStdExtD = false;
41  bool HasStdExtC = false;
42  bool HasStdExtZba = false;
43  bool HasStdExtZbb = false;
44  bool HasStdExtZbc = false;
45  bool HasStdExtZbe = false;
46  bool HasStdExtZbf = false;
47  bool HasStdExtZbm = false;
48  bool HasStdExtZbp = false;
49  bool HasStdExtZbr = false;
50  bool HasStdExtZbs = false;
51  bool HasStdExtZbt = false;
52  bool HasStdExtV = false;
53  bool HasStdExtZvlsseg = false;
54  bool HasStdExtZvamo = false;
55  bool HasStdExtZfhmin = false;
56  bool HasStdExtZfh = false;
57  bool HasRV64 = false;
58  bool IsRV32E = false;
59  bool EnableLinkerRelax = false;
60  bool EnableRVCHintInstrs = true;
61  bool EnableSaveRestore = false;
62  unsigned XLen = 32;
63  MVT XLenVT = MVT::i32;
64  uint8_t MaxInterleaveFactor = 2;
66  BitVector UserReservedRegister;
67  RISCVFrameLowering FrameLowering;
68  RISCVInstrInfo InstrInfo;
70  RISCVTargetLowering TLInfo;
72 
73  /// Initializes using the passed in CPU and feature strings so that we can
74  /// use initializer lists for subtarget initialization.
75  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
76  StringRef CPU,
77  StringRef TuneCPU,
78  StringRef FS,
79  StringRef ABIName);
80 
81 public:
82  // Initializes the data members to match that of the specified triple.
83  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
84  StringRef FS, StringRef ABIName, const TargetMachine &TM);
85 
86  // Parses features string setting specified subtarget options. The
87  // definition of this function is auto-generated by tblgen.
89 
90  const RISCVFrameLowering *getFrameLowering() const override {
91  return &FrameLowering;
92  }
93  const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
94  const RISCVRegisterInfo *getRegisterInfo() const override {
95  return &RegInfo;
96  }
97  const RISCVTargetLowering *getTargetLowering() const override {
98  return &TLInfo;
99  }
100  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
101  return &TSInfo;
102  }
103  bool enableMachineScheduler() const override { return true; }
104  bool hasStdExtM() const { return HasStdExtM; }
105  bool hasStdExtA() const { return HasStdExtA; }
106  bool hasStdExtF() const { return HasStdExtF; }
107  bool hasStdExtD() const { return HasStdExtD; }
108  bool hasStdExtC() const { return HasStdExtC; }
109  bool hasStdExtZba() const { return HasStdExtZba; }
110  bool hasStdExtZbb() const { return HasStdExtZbb; }
111  bool hasStdExtZbc() const { return HasStdExtZbc; }
112  bool hasStdExtZbe() const { return HasStdExtZbe; }
113  bool hasStdExtZbf() const { return HasStdExtZbf; }
114  bool hasStdExtZbm() const { return HasStdExtZbm; }
115  bool hasStdExtZbp() const { return HasStdExtZbp; }
116  bool hasStdExtZbr() const { return HasStdExtZbr; }
117  bool hasStdExtZbs() const { return HasStdExtZbs; }
118  bool hasStdExtZbt() const { return HasStdExtZbt; }
119  bool hasStdExtV() const { return HasStdExtV; }
120  bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
121  bool hasStdExtZvamo() const { return HasStdExtZvamo; }
122  bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
123  bool hasStdExtZfh() const { return HasStdExtZfh; }
124  bool is64Bit() const { return HasRV64; }
125  bool isRV32E() const { return IsRV32E; }
126  bool enableLinkerRelax() const { return EnableLinkerRelax; }
127  bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
128  bool enableSaveRestore() const { return EnableSaveRestore; }
129  MVT getXLenVT() const { return XLenVT; }
130  unsigned getXLen() const { return XLen; }
131  RISCVABI::ABI getTargetABI() const { return TargetABI; }
133  assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
134  return UserReservedRegister[i];
135  }
136 
137  // Vector codegen related methods.
138  bool hasVInstructions() const { return HasStdExtV; }
139  bool hasVInstructionsI64() const { return HasStdExtV; }
140  bool hasVInstructionsF16() const { return HasStdExtV && hasStdExtZfh(); }
141  bool hasVInstructionsF32() const { return HasStdExtV && hasStdExtF(); }
142  bool hasVInstructionsF64() const { return HasStdExtV && hasStdExtD(); }
143  // F16 and F64 both require F32.
144  bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
145  unsigned getMaxInterleaveFactor() const {
146  return hasVInstructions() ? MaxInterleaveFactor : 1;
147  }
148 
149 protected:
150  // GlobalISel related APIs.
151  std::unique_ptr<CallLowering> CallLoweringInfo;
152  std::unique_ptr<InstructionSelector> InstSelector;
153  std::unique_ptr<LegalizerInfo> Legalizer;
154  std::unique_ptr<RegisterBankInfo> RegBankInfo;
155 
156 public:
157  const CallLowering *getCallLowering() const override;
159  const LegalizerInfo *getLegalizerInfo() const override;
160  const RegisterBankInfo *getRegBankInfo() const override;
161 
162  // Return the known range for the bit length of RVV data registers. A value
163  // of 0 means nothing is known about that particular limit beyond what's
164  // implied by the architecture.
165  unsigned getMaxRVVVectorSizeInBits() const;
166  unsigned getMinRVVVectorSizeInBits() const;
167  unsigned getMaxLMULForFixedLengthVectors() const;
168  unsigned getMaxELENForFixedLengthVectors() const;
169  bool useRVVForFixedLengthVectors() const;
170 };
171 } // End llvm namespace
172 
173 #endif
i
i
Definition: README.txt:29
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:165
llvm::RISCVSubtarget::hasVInstructionsF16
bool hasVInstructionsF16() const
Definition: RISCVSubtarget.h:140
llvm::X86AS::FS
@ FS
Definition: X86.h:188
CallLowering.h
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:97
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:132
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:138
llvm::RISCVSubtarget::hasStdExtZbe
bool hasStdExtZbe() const
Definition: RISCVSubtarget.h:112
RegisterBankInfo.h
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:97
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVSubtarget::hasStdExtZbs
bool hasStdExtZbs() const
Definition: RISCVSubtarget.h:117
llvm::RISCVSubtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: RISCVSubtarget.h:153
llvm::RISCVSubtarget::hasStdExtD
bool hasStdExtD() const
Definition: RISCVSubtarget.h:107
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:151
llvm::RISCVSubtarget::hasVInstructionsI64
bool hasVInstructionsI64() const
Definition: RISCVSubtarget.h:139
LegalizerInfo.h
llvm::RISCVSubtarget::getFrameLowering
const RISCVFrameLowering * getFrameLowering() const override
Definition: RISCVSubtarget.h:90
llvm::RISCVSubtarget::hasStdExtZbt
bool hasStdExtZbt() const
Definition: RISCVSubtarget.h:118
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:81
llvm::RISCVSubtarget::is64Bit
bool is64Bit() const
Definition: RISCVSubtarget.h:124
llvm::RISCVSubtarget::hasStdExtZbc
bool hasStdExtZbc() const
Definition: RISCVSubtarget.h:111
llvm::RISCVSubtarget::hasVInstructionsF64
bool hasVInstructionsF64() const
Definition: RISCVSubtarget.h:142
llvm::RISCVSubtarget::hasStdExtZfhmin
bool hasStdExtZfhmin() const
Definition: RISCVSubtarget.h:122
TargetMachine.h
llvm::RISCVSubtarget::getMaxELENForFixedLengthVectors
unsigned getMaxELENForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:155
llvm::RISCVFrameLowering
Definition: RISCVFrameLowering.h:22
llvm::RISCVSubtarget::getXLenVT
MVT getXLenVT() const
Definition: RISCVSubtarget.h:129
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::RISCVSubtarget::hasStdExtZvlsseg
bool hasStdExtZvlsseg() const
Definition: RISCVSubtarget.h:120
llvm::RISCVSubtarget::hasStdExtZbm
bool hasStdExtZbm() const
Definition: RISCVSubtarget.h:114
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:110
llvm::BitVector
Definition: BitVector.h:74
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:93
llvm::RISCVSubtarget::hasStdExtZbp
bool hasStdExtZbp() const
Definition: RISCVSubtarget.h:115
llvm::RISCVSubtarget::getTargetABI
RISCVABI::ABI getTargetABI() const
Definition: RISCVSubtarget.h:131
llvm::RISCVSubtarget::hasStdExtC
bool hasStdExtC() const
Definition: RISCVSubtarget.h:108
llvm::RISCVSubtarget::enableRVCHintInstrs
bool enableRVCHintInstrs() const
Definition: RISCVSubtarget.h:127
InstructionSelector.h
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:113
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::RISCVSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: RISCVSubtarget.h:145
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::RISCVSubtarget::enableSaveRestore
bool enableSaveRestore() const
Definition: RISCVSubtarget.h:128
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:146
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVSubtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: RISCVSubtarget.h:100
llvm::RISCVSubtarget::hasStdExtZba
bool hasStdExtZba() const
Definition: RISCVSubtarget.h:109
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:109
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:43
RegInfo
Definition: AMDGPUAsmParser.cpp:2384
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:94
TargetSubtargetInfo.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVSubtarget::hasVInstructionsAnyF
bool hasVInstructionsAnyF() const
Definition: RISCVSubtarget.h:144
llvm::RISCVSubtarget::hasStdExtZfh
bool hasStdExtZfh() const
Definition: RISCVSubtarget.h:123
llvm::RISCVSubtarget::hasStdExtZbr
bool hasStdExtZbr() const
Definition: RISCVSubtarget.h:116
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:152
RISCVISelLowering.h
llvm::RISCVSubtarget::hasVInstructionsF32
bool hasVInstructionsF32() const
Definition: RISCVSubtarget.h:141
llvm::RISCVSubtarget::isRV32E
bool isRV32E() const
Definition: RISCVSubtarget.h:125
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:130
RISCVInstrInfo.h
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:295
RISCVBaseInfo.h
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:105
llvm::RISCVSubtarget::hasStdExtZvamo
bool hasStdExtZvamo() const
Definition: RISCVSubtarget.h:121
llvm::RISCVSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: RISCVSubtarget.h:103
SelectionDAGTargetInfo.h
llvm::RISCVSubtarget::hasStdExtA
bool hasStdExtA() const
Definition: RISCVSubtarget.h:105
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:312
RISCVFrameLowering.h
RISCVGenSubtargetInfo
llvm::RISCVSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: RISCVSubtarget.h:154
llvm::RISCVSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1108
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:129
llvm::RISCVSubtarget::hasStdExtM
bool hasStdExtM() const
Definition: RISCVSubtarget.h:104
llvm::RISCVSubtarget::hasStdExtF
bool hasStdExtF() const
Definition: RISCVSubtarget.h:106
llvm::CallLowering
Definition: CallLowering.h:43
llvm::RISCVSubtarget::enableLinkerRelax
bool enableLinkerRelax() const
Definition: RISCVSubtarget.h:126
llvm::RISCVSubtarget::hasStdExtZbf
bool hasStdExtZbf() const
Definition: RISCVSubtarget.h:113
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:304
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:119
llvm::RISCVSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: RISCVSubtarget.cpp:101