LLVM  14.0.0git
RISCVSubtarget.h
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1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
17 #include "RISCVFrameLowering.h"
18 #include "RISCVISelLowering.h"
19 #include "RISCVInstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
36  virtual void anchor();
37  bool HasStdExtM = false;
38  bool HasStdExtA = false;
39  bool HasStdExtF = false;
40  bool HasStdExtD = false;
41  bool HasStdExtC = false;
42  bool HasStdExtB = false;
43  bool HasStdExtZba = false;
44  bool HasStdExtZbb = false;
45  bool HasStdExtZbc = false;
46  bool HasStdExtZbe = false;
47  bool HasStdExtZbf = false;
48  bool HasStdExtZbm = false;
49  bool HasStdExtZbp = false;
50  bool HasStdExtZbr = false;
51  bool HasStdExtZbs = false;
52  bool HasStdExtZbt = false;
53  bool HasStdExtZbproposedc = false;
54  bool HasStdExtV = false;
55  bool HasStdExtZvlsseg = false;
56  bool HasStdExtZvamo = false;
57  bool HasStdExtZfh = false;
58  bool HasRV64 = false;
59  bool IsRV32E = false;
60  bool EnableLinkerRelax = false;
61  bool EnableRVCHintInstrs = true;
62  bool EnableSaveRestore = false;
63  unsigned XLen = 32;
64  MVT XLenVT = MVT::i32;
65  uint8_t MaxInterleaveFactor = 2;
67  BitVector UserReservedRegister;
68  RISCVFrameLowering FrameLowering;
69  RISCVInstrInfo InstrInfo;
71  RISCVTargetLowering TLInfo;
73 
74  /// Initializes using the passed in CPU and feature strings so that we can
75  /// use initializer lists for subtarget initialization.
76  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
77  StringRef CPU,
78  StringRef TuneCPU,
79  StringRef FS,
80  StringRef ABIName);
81 
82 public:
83  // Initializes the data members to match that of the specified triple.
84  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
85  StringRef FS, StringRef ABIName, const TargetMachine &TM);
86 
87  // Parses features string setting specified subtarget options. The
88  // definition of this function is auto-generated by tblgen.
90 
91  const RISCVFrameLowering *getFrameLowering() const override {
92  return &FrameLowering;
93  }
94  const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
95  const RISCVRegisterInfo *getRegisterInfo() const override {
96  return &RegInfo;
97  }
98  const RISCVTargetLowering *getTargetLowering() const override {
99  return &TLInfo;
100  }
101  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
102  return &TSInfo;
103  }
104  bool enableMachineScheduler() const override { return true; }
105  bool hasStdExtM() const { return HasStdExtM; }
106  bool hasStdExtA() const { return HasStdExtA; }
107  bool hasStdExtF() const { return HasStdExtF; }
108  bool hasStdExtD() const { return HasStdExtD; }
109  bool hasStdExtC() const { return HasStdExtC; }
110  bool hasStdExtB() const { return HasStdExtB; }
111  bool hasStdExtZba() const { return HasStdExtZba; }
112  bool hasStdExtZbb() const { return HasStdExtZbb; }
113  bool hasStdExtZbc() const { return HasStdExtZbc; }
114  bool hasStdExtZbe() const { return HasStdExtZbe; }
115  bool hasStdExtZbf() const { return HasStdExtZbf; }
116  bool hasStdExtZbm() const { return HasStdExtZbm; }
117  bool hasStdExtZbp() const { return HasStdExtZbp; }
118  bool hasStdExtZbr() const { return HasStdExtZbr; }
119  bool hasStdExtZbs() const { return HasStdExtZbs; }
120  bool hasStdExtZbt() const { return HasStdExtZbt; }
121  bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
122  bool hasStdExtV() const { return HasStdExtV; }
123  bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
124  bool hasStdExtZvamo() const { return HasStdExtZvamo; }
125  bool hasStdExtZfh() const { return HasStdExtZfh; }
126  bool is64Bit() const { return HasRV64; }
127  bool isRV32E() const { return IsRV32E; }
128  bool enableLinkerRelax() const { return EnableLinkerRelax; }
129  bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
130  bool enableSaveRestore() const { return EnableSaveRestore; }
131  MVT getXLenVT() const { return XLenVT; }
132  unsigned getXLen() const { return XLen; }
133  RISCVABI::ABI getTargetABI() const { return TargetABI; }
135  assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
136  return UserReservedRegister[i];
137  }
138  unsigned getMaxInterleaveFactor() const {
139  return hasStdExtV() ? MaxInterleaveFactor : 1;
140  }
141 
142 protected:
143  // GlobalISel related APIs.
144  std::unique_ptr<CallLowering> CallLoweringInfo;
145  std::unique_ptr<InstructionSelector> InstSelector;
146  std::unique_ptr<LegalizerInfo> Legalizer;
147  std::unique_ptr<RegisterBankInfo> RegBankInfo;
148 
149 public:
150  const CallLowering *getCallLowering() const override;
152  const LegalizerInfo *getLegalizerInfo() const override;
153  const RegisterBankInfo *getRegBankInfo() const override;
154 
155  // Return the known range for the bit length of RVV data registers. A value
156  // of 0 means nothing is known about that particular limit beyond what's
157  // implied by the architecture.
158  unsigned getMaxRVVVectorSizeInBits() const;
159  unsigned getMinRVVVectorSizeInBits() const;
160  unsigned getMaxLMULForFixedLengthVectors() const;
161  bool useRVVForFixedLengthVectors() const;
162 };
163 } // End llvm namespace
164 
165 #endif
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Definition: README.txt:29
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:148
CallLowering.h
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:98
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:134
llvm::RISCVSubtarget::hasStdExtZbe
bool hasStdExtZbe() const
Definition: RISCVSubtarget.h:114
RegisterBankInfo.h
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:92
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVSubtarget::hasStdExtZbs
bool hasStdExtZbs() const
Definition: RISCVSubtarget.h:119
llvm::RISCVSubtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: RISCVSubtarget.h:146
llvm::RISCVSubtarget::hasStdExtD
bool hasStdExtD() const
Definition: RISCVSubtarget.h:108
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:144
LegalizerInfo.h
llvm::RISCVSubtarget::getFrameLowering
const RISCVFrameLowering * getFrameLowering() const override
Definition: RISCVSubtarget.h:91
llvm::RISCVSubtarget::hasStdExtZbt
bool hasStdExtZbt() const
Definition: RISCVSubtarget.h:120
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:76
llvm::RISCVSubtarget::is64Bit
bool is64Bit() const
Definition: RISCVSubtarget.h:126
llvm::RISCVSubtarget::hasStdExtZbc
bool hasStdExtZbc() const
Definition: RISCVSubtarget.h:113
TargetMachine.h
llvm::RISCVSubtarget::hasStdExtB
bool hasStdExtB() const
Definition: RISCVSubtarget.h:110
llvm::RISCVFrameLowering
Definition: RISCVFrameLowering.h:22
llvm::RISCVSubtarget::getXLenVT
MVT getXLenVT() const
Definition: RISCVSubtarget.h:131
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::RISCVSubtarget::hasStdExtZvlsseg
bool hasStdExtZvlsseg() const
Definition: RISCVSubtarget.h:123
llvm::RISCVSubtarget::hasStdExtZbm
bool hasStdExtZbm() const
Definition: RISCVSubtarget.h:116
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:112
llvm::BitVector
Definition: BitVector.h:74
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:94
llvm::RISCVSubtarget::hasStdExtZbp
bool hasStdExtZbp() const
Definition: RISCVSubtarget.h:117
llvm::RISCVSubtarget::getTargetABI
RISCVABI::ABI getTargetABI() const
Definition: RISCVSubtarget.h:133
llvm::RISCVSubtarget::hasStdExtC
bool hasStdExtC() const
Definition: RISCVSubtarget.h:109
llvm::RISCVSubtarget::enableRVCHintInstrs
bool enableRVCHintInstrs() const
Definition: RISCVSubtarget.h:129
InstructionSelector.h
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:108
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::RISCVSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: RISCVSubtarget.h:138
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVSubtarget::enableSaveRestore
bool enableSaveRestore() const
Definition: RISCVSubtarget.h:130
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:140
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVSubtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: RISCVSubtarget.h:101
llvm::RISCVSubtarget::hasStdExtZba
bool hasStdExtZba() const
Definition: RISCVSubtarget.h:111
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:104
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:27
RegInfo
Definition: AMDGPUAsmParser.cpp:2366
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:95
TargetSubtargetInfo.h
llvm::RISCVSubtarget::hasStdExtZbproposedc
bool hasStdExtZbproposedc() const
Definition: RISCVSubtarget.h:121
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVSubtarget::hasStdExtZfh
bool hasStdExtZfh() const
Definition: RISCVSubtarget.h:125
llvm::RISCVSubtarget::hasStdExtZbr
bool hasStdExtZbr() const
Definition: RISCVSubtarget.h:118
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:145
RISCVISelLowering.h
llvm::RISCVSubtarget::isRV32E
bool isRV32E() const
Definition: RISCVSubtarget.h:127
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:132
RISCVInstrInfo.h
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:288
RISCVBaseInfo.h
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:100
llvm::RISCVSubtarget::hasStdExtZvamo
bool hasStdExtZvamo() const
Definition: RISCVSubtarget.h:124
llvm::RISCVSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: RISCVSubtarget.h:104
SelectionDAGTargetInfo.h
llvm::RISCVSubtarget::hasStdExtA
bool hasStdExtA() const
Definition: RISCVSubtarget.h:106
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:285
RISCVFrameLowering.h
RISCVGenSubtargetInfo
llvm::RISCVSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: RISCVSubtarget.h:147
llvm::RISCVSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1083
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:123
llvm::RISCVSubtarget::hasStdExtM
bool hasStdExtM() const
Definition: RISCVSubtarget.h:105
llvm::RISCVSubtarget::hasStdExtF
bool hasStdExtF() const
Definition: RISCVSubtarget.h:107
llvm::CallLowering
Definition: CallLowering.h:43
llvm::RISCVSubtarget::enableLinkerRelax
bool enableLinkerRelax() const
Definition: RISCVSubtarget.h:128
llvm::RISCVSubtarget::hasStdExtZbf
bool hasStdExtZbf() const
Definition: RISCVSubtarget.h:115
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:277
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:122
llvm::RISCVSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: RISCVSubtarget.cpp:96