LLVM  15.0.0git
RISCVSubtarget.h
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1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
17 #include "RISCVFrameLowering.h"
18 #include "RISCVISelLowering.h"
19 #include "RISCVInstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
36 public:
37  enum RISCVProcFamilyEnum : uint8_t {
40  };
41 
42 private:
43  virtual void anchor();
44 
45  RISCVProcFamilyEnum RISCVProcFamily = Others;
46 
47  bool HasStdExtM = false;
48  bool HasStdExtA = false;
49  bool HasStdExtF = false;
50  bool HasStdExtD = false;
51  bool HasStdExtC = false;
52  bool HasStdExtZihintpause = false;
53  bool HasStdExtZba = false;
54  bool HasStdExtZbb = false;
55  bool HasStdExtZbc = false;
56  bool HasStdExtZbe = false;
57  bool HasStdExtZbf = false;
58  bool HasStdExtZbm = false;
59  bool HasStdExtZbp = false;
60  bool HasStdExtZbr = false;
61  bool HasStdExtZbs = false;
62  bool HasStdExtZbt = false;
63  bool HasStdExtV = false;
64  bool HasStdExtZve32x = false;
65  bool HasStdExtZve32f = false;
66  bool HasStdExtZve64x = false;
67  bool HasStdExtZve64f = false;
68  bool HasStdExtZve64d = false;
69  bool HasStdExtZvfh = false;
70  bool HasStdExtZfhmin = false;
71  bool HasStdExtZfh = false;
72  bool HasStdExtZfinx = false;
73  bool HasStdExtZdinx = false;
74  bool HasStdExtZhinxmin = false;
75  bool HasStdExtZhinx = false;
76  bool HasStdExtZbkb = false;
77  bool HasStdExtZbkc = false;
78  bool HasStdExtZbkx = false;
79  bool HasStdExtZknd = false;
80  bool HasStdExtZkne = false;
81  bool HasStdExtZknh = false;
82  bool HasStdExtZksed = false;
83  bool HasStdExtZksh = false;
84  bool HasStdExtZkr = false;
85  bool HasStdExtZkn = false;
86  bool HasStdExtZks = false;
87  bool HasStdExtZkt = false;
88  bool HasStdExtZk = false;
89  bool HasRV64 = false;
90  bool IsRV32E = false;
91  bool EnableLinkerRelax = false;
92  bool EnableRVCHintInstrs = true;
93  bool EnableDefaultUnroll = true;
94  bool EnableSaveRestore = false;
95  unsigned XLen = 32;
96  unsigned ZvlLen = 0;
97  MVT XLenVT = MVT::i32;
98  uint8_t MaxInterleaveFactor = 2;
100  BitVector UserReservedRegister;
101  RISCVFrameLowering FrameLowering;
102  RISCVInstrInfo InstrInfo;
104  RISCVTargetLowering TLInfo;
105  SelectionDAGTargetInfo TSInfo;
106 
107  /// Initializes using the passed in CPU and feature strings so that we can
108  /// use initializer lists for subtarget initialization.
109  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
110  StringRef CPU,
111  StringRef TuneCPU,
112  StringRef FS,
113  StringRef ABIName);
114 
115 public:
116  // Initializes the data members to match that of the specified triple.
117  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
118  StringRef FS, StringRef ABIName, const TargetMachine &TM);
119 
120  // Parses features string setting specified subtarget options. The
121  // definition of this function is auto-generated by tblgen.
123 
124  const RISCVFrameLowering *getFrameLowering() const override {
125  return &FrameLowering;
126  }
127  const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
128  const RISCVRegisterInfo *getRegisterInfo() const override {
129  return &RegInfo;
130  }
131  const RISCVTargetLowering *getTargetLowering() const override {
132  return &TLInfo;
133  }
134  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
135  return &TSInfo;
136  }
137  bool enableMachineScheduler() const override { return true; }
138 
139  /// Returns RISCV processor family.
140  /// Avoid this function! CPU specifics should be kept local to this class
141  /// and preferably modeled with SubtargetFeatures or properties in
142  /// initializeProperties().
143  RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
144 
145  bool hasStdExtM() const { return HasStdExtM; }
146  bool hasStdExtA() const { return HasStdExtA; }
147  bool hasStdExtF() const { return HasStdExtF; }
148  bool hasStdExtD() const { return HasStdExtD; }
149  bool hasStdExtC() const { return HasStdExtC; }
150  bool hasStdExtV() const { return HasStdExtV; }
151  bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
152  bool hasStdExtZba() const { return HasStdExtZba; }
153  bool hasStdExtZbb() const { return HasStdExtZbb; }
154  bool hasStdExtZbc() const { return HasStdExtZbc; }
155  bool hasStdExtZbe() const { return HasStdExtZbe; }
156  bool hasStdExtZbf() const { return HasStdExtZbf; }
157  bool hasStdExtZbm() const { return HasStdExtZbm; }
158  bool hasStdExtZbp() const { return HasStdExtZbp; }
159  bool hasStdExtZbr() const { return HasStdExtZbr; }
160  bool hasStdExtZbs() const { return HasStdExtZbs; }
161  bool hasStdExtZbt() const { return HasStdExtZbt; }
162  bool hasStdExtZvl() const { return ZvlLen != 0; }
163  bool hasStdExtZvfh() const { return HasStdExtZvfh; }
164  bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
165  bool hasStdExtZfh() const { return HasStdExtZfh; }
166  bool hasStdExtZfinx() const { return HasStdExtZfinx; }
167  bool hasStdExtZdinx() const { return HasStdExtZdinx; }
168  bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
169  bool hasStdExtZhinx() const { return HasStdExtZhinx; }
170  bool hasStdExtZbkb() const { return HasStdExtZbkb; }
171  bool hasStdExtZbkc() const { return HasStdExtZbkc; }
172  bool hasStdExtZbkx() const { return HasStdExtZbkx; }
173  bool hasStdExtZknd() const { return HasStdExtZknd; }
174  bool hasStdExtZkne() const { return HasStdExtZkne; }
175  bool hasStdExtZknh() const { return HasStdExtZknh; }
176  bool hasStdExtZksed() const { return HasStdExtZksed; }
177  bool hasStdExtZksh() const { return HasStdExtZksh; }
178  bool hasStdExtZkr() const { return HasStdExtZkr; }
179  bool is64Bit() const { return HasRV64; }
180  bool isRV32E() const { return IsRV32E; }
181  bool enableLinkerRelax() const { return EnableLinkerRelax; }
182  bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
183  bool enableDefaultUnroll() const { return EnableDefaultUnroll; }
184  bool enableSaveRestore() const { return EnableSaveRestore; }
185  MVT getXLenVT() const { return XLenVT; }
186  unsigned getXLen() const { return XLen; }
187  unsigned getFLen() const {
188  if (HasStdExtD)
189  return 64;
190 
191  if (HasStdExtF)
192  return 32;
193 
194  return 0;
195  }
196  unsigned getELEN() const {
197  assert(hasVInstructions() && "Expected V extension");
198  return hasVInstructionsI64() ? 64 : 32;
199  }
200  unsigned getMinVLen() const { return ZvlLen; }
201  unsigned getMaxVLen() const { return 65536; }
202  unsigned getRealMinVLen() const {
203  unsigned VLen = getMinRVVVectorSizeInBits();
204  return VLen == 0 ? getMinVLen() : VLen;
205  }
206  unsigned getRealMaxVLen() const {
207  unsigned VLen = getMaxRVVVectorSizeInBits();
208  return VLen == 0 ? getMaxVLen() : VLen;
209  }
210  RISCVABI::ABI getTargetABI() const { return TargetABI; }
212  assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
213  return UserReservedRegister[i];
214  }
215 
216  // Vector codegen related methods.
217  bool hasVInstructions() const { return HasStdExtZve32x; }
218  bool hasVInstructionsI64() const { return HasStdExtZve64x; }
219  bool hasVInstructionsF16() const { return HasStdExtZvfh && HasStdExtZfh; }
220  // FIXME: Consider Zfinx in the future
221  bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
222  // FIXME: Consider Zdinx in the future
223  bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
224  // F16 and F64 both require F32.
225  bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
226  unsigned getMaxInterleaveFactor() const {
227  return hasVInstructions() ? MaxInterleaveFactor : 1;
228  }
229 
230 protected:
231  // GlobalISel related APIs.
232  std::unique_ptr<CallLowering> CallLoweringInfo;
233  std::unique_ptr<InstructionSelector> InstSelector;
234  std::unique_ptr<LegalizerInfo> Legalizer;
235  std::unique_ptr<RegisterBankInfo> RegBankInfo;
236 
237 public:
238  const CallLowering *getCallLowering() const override;
240  const LegalizerInfo *getLegalizerInfo() const override;
241  const RegisterBankInfo *getRegBankInfo() const override;
242 
243  bool useConstantPoolForLargeInts() const;
244 
245  // Maximum cost used for building integers, integers will be put into constant
246  // pool if exceeded.
247  unsigned getMaxBuildIntsCost() const;
248 
249  // Return the known range for the bit length of RVV data registers. A value
250  // of 0 means nothing is known about that particular limit beyond what's
251  // implied by the architecture.
252  unsigned getMaxRVVVectorSizeInBits() const;
253  unsigned getMinRVVVectorSizeInBits() const;
254  unsigned getMaxLMULForFixedLengthVectors() const;
255  bool useRVVForFixedLengthVectors() const;
256 
257  bool enableSubRegLiveness() const override;
258 };
259 } // End llvm namespace
260 
261 #endif
i
i
Definition: README.txt:29
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:199
llvm::RISCVSubtarget::hasVInstructionsF16
bool hasVInstructionsF16() const
Definition: RISCVSubtarget.h:219
CallLowering.h
llvm::RISCVSubtarget::getTargetLowering
const RISCVTargetLowering * getTargetLowering() const override
Definition: RISCVSubtarget.h:131
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:211
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:217
llvm::RISCVSubtarget::getRealMaxVLen
unsigned getRealMaxVLen() const
Definition: RISCVSubtarget.h:206
llvm::RISCVSubtarget::hasStdExtZbe
bool hasStdExtZbe() const
Definition: RISCVSubtarget.h:155
llvm::RISCVSubtarget::hasStdExtZksed
bool hasStdExtZksed() const
Definition: RISCVSubtarget.h:176
RegisterBankInfo.h
llvm::RISCVSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: RISCVSubtarget.cpp:203
llvm::RISCVSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: RISCVSubtarget.cpp:105
llvm::RISCVSubtarget::Others
@ Others
Definition: RISCVSubtarget.h:38
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::RISCVSubtarget::hasStdExtZbs
bool hasStdExtZbs() const
Definition: RISCVSubtarget.h:160
llvm::RISCVSubtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: RISCVSubtarget.h:234
llvm::RISCVSubtarget::hasStdExtZhinx
bool hasStdExtZhinx() const
Definition: RISCVSubtarget.h:169
llvm::RISCVSubtarget::hasStdExtD
bool hasStdExtD() const
Definition: RISCVSubtarget.h:148
llvm::RISCVSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: RISCVSubtarget.h:232
llvm::RISCVSubtarget::hasVInstructionsI64
bool hasVInstructionsI64() const
Definition: RISCVSubtarget.h:218
LegalizerInfo.h
llvm::RISCVSubtarget::hasStdExtZihintpause
bool hasStdExtZihintpause() const
Definition: RISCVSubtarget.h:151
llvm::RISCVSubtarget::getFrameLowering
const RISCVFrameLowering * getFrameLowering() const override
Definition: RISCVSubtarget.h:124
llvm::RISCVSubtarget::getFLen
unsigned getFLen() const
Definition: RISCVSubtarget.h:187
llvm::RISCVSubtarget::hasStdExtZbt
bool hasStdExtZbt() const
Definition: RISCVSubtarget.h:161
llvm::RISCVSubtarget::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
Definition: RISCVSubtarget.cpp:89
llvm::RISCVSubtarget::hasStdExtZbkx
bool hasStdExtZbkx() const
Definition: RISCVSubtarget.h:172
llvm::RISCVSubtarget::is64Bit
bool is64Bit() const
Definition: RISCVSubtarget.h:179
llvm::RISCVSubtarget::hasStdExtZbc
bool hasStdExtZbc() const
Definition: RISCVSubtarget.h:154
llvm::RISCVSubtarget::hasVInstructionsF64
bool hasVInstructionsF64() const
Definition: RISCVSubtarget.h:223
llvm::RISCVSubtarget::hasStdExtZfhmin
bool hasStdExtZfhmin() const
Definition: RISCVSubtarget.h:164
TargetMachine.h
llvm::RISCVFrameLowering
Definition: RISCVFrameLowering.h:22
llvm::RISCVSubtarget::getXLenVT
MVT getXLenVT() const
Definition: RISCVSubtarget.h:185
llvm::RISCVSubtarget::getELEN
unsigned getELEN() const
Definition: RISCVSubtarget.h:196
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::RISCVSubtarget::hasStdExtZfinx
bool hasStdExtZfinx() const
Definition: RISCVSubtarget.h:166
llvm::RISCVSubtarget::hasStdExtZbm
bool hasStdExtZbm() const
Definition: RISCVSubtarget.h:157
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:153
llvm::BitVector
Definition: BitVector.h:75
llvm::RISCVSubtarget::enableDefaultUnroll
bool enableDefaultUnroll() const
Definition: RISCVSubtarget.h:183
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:127
llvm::RISCVSubtarget::hasStdExtZbp
bool hasStdExtZbp() const
Definition: RISCVSubtarget.h:158
llvm::RISCVSubtarget::hasStdExtZdinx
bool hasStdExtZdinx() const
Definition: RISCVSubtarget.h:167
llvm::RISCVSubtarget::getRealMinVLen
unsigned getRealMinVLen() const
Definition: RISCVSubtarget.h:202
llvm::RISCVSubtarget::getTargetABI
RISCVABI::ABI getTargetABI() const
Definition: RISCVSubtarget.h:210
llvm::RISCVSubtarget::hasStdExtC
bool hasStdExtC() const
Definition: RISCVSubtarget.h:149
llvm::RISCVSubtarget::enableRVCHintInstrs
bool enableRVCHintInstrs() const
Definition: RISCVSubtarget.h:182
InstructionSelector.h
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:136
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::RISCVSubtarget::hasStdExtZknh
bool hasStdExtZknh() const
Definition: RISCVSubtarget.h:175
llvm::RISCVSubtarget::getProcFamily
RISCVProcFamilyEnum getProcFamily() const
Returns RISCV processor family.
Definition: RISCVSubtarget.h:143
llvm::RISCVSubtarget::getMaxBuildIntsCost
unsigned getMaxBuildIntsCost() const
Definition: RISCVSubtarget.cpp:125
llvm::RISCVSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: RISCVSubtarget.h:226
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVSubtarget::getMaxVLen
unsigned getMaxVLen() const
Definition: RISCVSubtarget.h:201
llvm::RISCVSubtarget::getMinVLen
unsigned getMinVLen() const
Definition: RISCVSubtarget.h:200
llvm::RISCVSubtarget::enableSaveRestore
bool enableSaveRestore() const
Definition: RISCVSubtarget.h:184
llvm::RISCVSubtarget::getMaxLMULForFixedLengthVectors
unsigned getMaxLMULForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:190
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVSubtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: RISCVSubtarget.h:134
llvm::RISCVSubtarget::hasStdExtZba
bool hasStdExtZba() const
Definition: RISCVSubtarget.h:152
llvm::RISCVSubtarget::hasStdExtZkne
bool hasStdExtZkne() const
Definition: RISCVSubtarget.h:174
llvm::RISCVSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: RISCVSubtarget.cpp:117
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
RegInfo
Definition: AMDGPUAsmParser.cpp:2500
llvm::RISCVSubtarget::hasStdExtZbkc
bool hasStdExtZbkc() const
Definition: RISCVSubtarget.h:171
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:128
llvm::RISCVSubtarget::hasStdExtZkr
bool hasStdExtZkr() const
Definition: RISCVSubtarget.h:178
TargetSubtargetInfo.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVSubtarget::hasStdExtZknd
bool hasStdExtZknd() const
Definition: RISCVSubtarget.h:173
llvm::RISCVSubtarget::hasVInstructionsAnyF
bool hasVInstructionsAnyF() const
Definition: RISCVSubtarget.h:225
llvm::RISCVSubtarget::hasStdExtZfh
bool hasStdExtZfh() const
Definition: RISCVSubtarget.h:165
llvm::RISCVSubtarget::hasStdExtZbr
bool hasStdExtZbr() const
Definition: RISCVSubtarget.h:159
llvm::RISCVSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: RISCVSubtarget.h:233
RISCVISelLowering.h
llvm::RISCVSubtarget::hasVInstructionsF32
bool hasVInstructionsF32() const
Definition: RISCVSubtarget.h:221
llvm::RISCVSubtarget::isRV32E
bool isRV32E() const
Definition: RISCVSubtarget.h:180
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::RISCVSubtarget::hasStdExtZbkb
bool hasStdExtZbkb() const
Definition: RISCVSubtarget.h:170
llvm::RISCVSubtarget::hasStdExtZhinxmin
bool hasStdExtZhinxmin() const
Definition: RISCVSubtarget.h:168
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:186
RISCVInstrInfo.h
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:325
RISCVBaseInfo.h
llvm::RISCVSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: RISCVSubtarget.cpp:113
llvm::RISCVSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: RISCVSubtarget.h:137
SelectionDAGTargetInfo.h
llvm::RISCVSubtarget::hasStdExtA
bool hasStdExtA() const
Definition: RISCVSubtarget.h:146
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:355
llvm::RISCVSubtarget::hasStdExtZvl
bool hasStdExtZvl() const
Definition: RISCVSubtarget.h:162
RISCVFrameLowering.h
llvm::RISCVSubtarget::RISCVProcFamilyEnum
RISCVProcFamilyEnum
Definition: RISCVSubtarget.h:37
RISCVGenSubtargetInfo
llvm::RISCVSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: RISCVSubtarget.h:235
llvm::RISCVSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:161
llvm::RISCVSubtarget::SiFive7
@ SiFive7
Definition: RISCVSubtarget.h:39
llvm::RISCVSubtarget::hasStdExtZksh
bool hasStdExtZksh() const
Definition: RISCVSubtarget.h:177
llvm::RISCVSubtarget::hasStdExtZvfh
bool hasStdExtZvfh() const
Definition: RISCVSubtarget.h:163
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::RISCVSubtarget::hasStdExtM
bool hasStdExtM() const
Definition: RISCVSubtarget.h:145
llvm::RISCVSubtarget::hasStdExtF
bool hasStdExtF() const
Definition: RISCVSubtarget.h:147
llvm::CallLowering
Definition: CallLowering.h:44
llvm::RISCVSubtarget::enableLinkerRelax
bool enableLinkerRelax() const
Definition: RISCVSubtarget.h:181
llvm::RISCVSubtarget::hasStdExtZbf
bool hasStdExtZbf() const
Definition: RISCVSubtarget.h:156
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:347
llvm::RISCVSubtarget::useConstantPoolForLargeInts
bool useConstantPoolForLargeInts() const
Definition: RISCVSubtarget.cpp:121
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:150
llvm::RISCVSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: RISCVSubtarget.cpp:109