13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
29#define GET_SUBTARGETINFO_HEADER
30#include "RISCVGenSubtargetInfo.inc"
43 virtual void anchor();
47#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
48 bool ATTRIBUTE = DEFAULT;
49#include "RISCVGenSubtargetInfo.inc"
54 unsigned RVVVectorBitsMin;
55 unsigned RVVVectorBitsMax;
56 uint8_t MaxInterleaveFactor = 2;
58 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
59 Align PrefFunctionAlignment;
60 Align PrefLoopAlignment;
87 return &FrameLowering;
110#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
111 bool GETTER() const { return ATTRIBUTE; }
112#include "RISCVGenSubtargetInfo.inc"
135 return VLen == 0 ? ZvlLen : VLen;
139 return VLen == 0 ? 65536 : VLen;
143 assert(i < RISCV::NUM_TARGET_REGS &&
"Register out of range");
144 return UserReservedRegister[i];
199 &Mutations)
const override;
This file describes how to lower LLVM calls to machine code calls.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Provides the logic to select generic machine instructions.
RISCVABI::ABI getTargetABI() const
bool hasStdExtCOrZca() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool hasVInstructionsI64() const
bool hasVInstructionsF64() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool isTargetFuchsia() const
bool hasMacroFusion() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasStdExtZfhOrZfhmin() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructionsF16() const
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
Align getPrefLoopAlignment() const
bool hasVInstructions() const
bool hasVInstructionsAnyF() const
bool useConstantPoolForLargeInts() const
Align getPrefFunctionAlignment() const
RISCVProcFamilyEnum getProcFamily() const
Returns RISCV processor family.
unsigned getMaxRVVVectorSizeInBits() const
unsigned getRealMaxVLen() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
std::unique_ptr< CallLowering > CallLoweringInfo
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
unsigned getMaxInterleaveFactor() const
bool enableSubRegLiveness() const override
bool hasStdExtZvl() const
const RISCVFrameLowering * getFrameLowering() const override
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
Triple - Helper class for working with autoconf configuration names.
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.