LLVM 18.0.0git
RISCVSubtarget.h
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1//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15
17#include "RISCVFrameLowering.h"
18#include "RISCVISelLowering.h"
19#include "RISCVInstrInfo.h"
26#include "llvm/IR/DataLayout.h"
28
29#define GET_SUBTARGETINFO_HEADER
30#include "RISCVGenSubtargetInfo.inc"
31
32namespace llvm {
33class StringRef;
34
35namespace RISCVTuneInfoTable {
36
38 const char *Name;
41};
42
43#define GET_RISCVTuneInfoTable_DECL
44#include "RISCVGenSearchableTables.inc"
45} // namespace RISCVTuneInfoTable
46
48public:
49 enum RISCVProcFamilyEnum : uint8_t {
52 };
53
54private:
55 virtual void anchor();
56
57 RISCVProcFamilyEnum RISCVProcFamily = Others;
58
59#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
60 bool ATTRIBUTE = DEFAULT;
61#include "RISCVGenSubtargetInfo.inc"
62
63 unsigned ZvlLen = 0;
64 unsigned RVVVectorBitsMin;
65 unsigned RVVVectorBitsMax;
66 uint8_t MaxInterleaveFactor = 2;
68 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
70
71 RISCVFrameLowering FrameLowering;
72 RISCVInstrInfo InstrInfo;
76
77 /// Initializes using the passed in CPU and feature strings so that we can
78 /// use initializer lists for subtarget initialization.
79 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
80 StringRef CPU,
81 StringRef TuneCPU,
82 StringRef FS,
83 StringRef ABIName);
84
85public:
86 // Initializes the data members to match that of the specified triple.
87 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
88 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
89 unsigned RVVVectorLMULMax, const TargetMachine &TM);
90
91 // Parses features string setting specified subtarget options. The
92 // definition of this function is auto-generated by tblgen.
94
95 const RISCVFrameLowering *getFrameLowering() const override {
96 return &FrameLowering;
97 }
98 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
99 const RISCVRegisterInfo *getRegisterInfo() const override {
100 return &RegInfo;
101 }
102 const RISCVTargetLowering *getTargetLowering() const override {
103 return &TLInfo;
104 }
106 return &TSInfo;
107 }
108 bool enableMachineScheduler() const override { return true; }
109
111 return Align(TuneInfo->PrefFunctionAlignment);
112 }
114 return Align(TuneInfo->PrefLoopAlignment);
115 }
116
117 /// Returns RISC-V processor family.
118 /// Avoid this function! CPU specifics should be kept local to this class
119 /// and preferably modeled with SubtargetFeatures or properties in
120 /// initializeProperties().
121 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
122
123#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
124 bool GETTER() const { return ATTRIBUTE; }
125#include "RISCVGenSubtargetInfo.inc"
126
127 bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
128 bool hasStdExtZvl() const { return ZvlLen != 0; }
129 bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
130 bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
131 bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
132 bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
134 return HasStdExtZhinx || HasStdExtZhinxmin;
135 }
138 }
140 return hasStdExtZfhOrZfhmin() || HasStdExtZfbfmin;
141 }
142 bool is64Bit() const { return IsRV64; }
143 MVT getXLenVT() const {
144 return is64Bit() ? MVT::i64 : MVT::i32;
145 }
146 unsigned getXLen() const {
147 return is64Bit() ? 64 : 32;
148 }
149 unsigned getFLen() const {
150 if (HasStdExtD)
151 return 64;
152
153 if (HasStdExtF)
154 return 32;
155
156 return 0;
157 }
158 unsigned getELen() const {
159 assert(hasVInstructions() && "Expected V extension");
160 return hasVInstructionsI64() ? 64 : 32;
161 }
162 unsigned getRealMinVLen() const {
163 unsigned VLen = getMinRVVVectorSizeInBits();
164 return VLen == 0 ? ZvlLen : VLen;
165 }
166 unsigned getRealMaxVLen() const {
167 unsigned VLen = getMaxRVVVectorSizeInBits();
168 return VLen == 0 ? 65536 : VLen;
169 }
170 RISCVABI::ABI getTargetABI() const { return TargetABI; }
171 bool isSoftFPABI() const {
172 return TargetABI == RISCVABI::ABI_LP64 ||
173 TargetABI == RISCVABI::ABI_ILP32 ||
174 TargetABI == RISCVABI::ABI_ILP32E;
175 }
177 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
178 return UserReservedRegister[i];
179 }
180
181 bool hasMacroFusion() const { return hasLUIADDIFusion(); }
182
183 // Vector codegen related methods.
184 bool hasVInstructions() const { return HasStdExtZve32x; }
185 bool hasVInstructionsI64() const { return HasStdExtZve64x; }
187 return HasStdExtZvfhmin || HasStdExtZvfh;
188 }
189 bool hasVInstructionsF16() const { return HasStdExtZvfh; }
190 bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
191 bool hasVInstructionsF32() const { return HasStdExtZve32f; }
192 bool hasVInstructionsF64() const { return HasStdExtZve64d; }
193 // F16 and F64 both require F32.
194 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
195 bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
196 unsigned getMaxInterleaveFactor() const {
197 return hasVInstructions() ? MaxInterleaveFactor : 1;
198 }
199
200 // Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
201 // vector hardware implementation which may be less than VLEN.
202 unsigned getDLenFactor() const {
203 if (DLenFactor2)
204 return 2;
205 return 1;
206 }
207
208protected:
209 // GlobalISel related APIs.
210 std::unique_ptr<CallLowering> CallLoweringInfo;
211 std::unique_ptr<InstructionSelector> InstSelector;
212 std::unique_ptr<LegalizerInfo> Legalizer;
213 std::unique_ptr<RegisterBankInfo> RegBankInfo;
214
215 // Return the known range for the bit length of RVV data registers as set
216 // at the command line. A value of 0 means nothing is known about that particular
217 // limit beyond what's implied by the architecture.
218 // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
219 unsigned getMaxRVVVectorSizeInBits() const;
220 unsigned getMinRVVVectorSizeInBits() const;
221
222public:
223 const CallLowering *getCallLowering() const override;
225 const LegalizerInfo *getLegalizerInfo() const override;
226 const RegisterBankInfo *getRegBankInfo() const override;
227
228 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
229
230 bool useConstantPoolForLargeInts() const;
231
232 // Maximum cost used for building integers, integers will be put into constant
233 // pool if exceeded.
234 unsigned getMaxBuildIntsCost() const;
235
236 unsigned getMaxLMULForFixedLengthVectors() const;
237 bool useRVVForFixedLengthVectors() const;
238
239 bool enableSubRegLiveness() const override;
240
241 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
242 &Mutations) const override;
243
244 bool useAA() const override;
245};
246} // End llvm namespace
247
248#endif
This file describes how to lower LLVM calls to machine code calls.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
return InstrInfo
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Machine Value Type.
RISCVABI::ABI getTargetABI() const
bool hasStdExtCOrZca() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool hasVInstructionsI64() const
bool hasVInstructionsF64() const
bool hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() const
bool hasStdExtDOrZdinx() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasStdExtZfhOrZhinx() const
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool isTargetFuchsia() const
unsigned getDLenFactor() const
bool hasMacroFusion() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasStdExtZfhOrZfhmin() const
bool hasVInstructionsF16Minimal() const
unsigned getXLen() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructionsF16() const
bool hasVInstructionsBF16() const
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
Align getPrefLoopAlignment() const
bool hasVInstructions() const
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
bool hasVInstructionsAnyF() const
bool useConstantPoolForLargeInts() const
Align getPrefFunctionAlignment() const
RISCVProcFamilyEnum getProcFamily() const
Returns RISC-V processor family.
unsigned getMaxRVVVectorSizeInBits() const
unsigned getRealMaxVLen() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
bool hasStdExtZhinxOrZhinxmin() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
std::unique_ptr< CallLowering > CallLoweringInfo
bool hasVInstructionsFullMultiply() const
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
unsigned getMaxInterleaveFactor() const
bool enableSubRegLiveness() const override
unsigned getELen() const
bool hasStdExtFOrZfinx() const
bool hasStdExtZvl() const
bool isSoftFPABI() const
bool hasHalfFPLoadStoreMove() const
const RISCVFrameLowering * getFrameLowering() const override
unsigned getFLen() const
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39