LLVM 17.0.0git
RISCVSubtarget.h
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1//===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the RISCV specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15
17#include "RISCVFrameLowering.h"
18#include "RISCVISelLowering.h"
19#include "RISCVInstrInfo.h"
26#include "llvm/IR/DataLayout.h"
28
29#define GET_SUBTARGETINFO_HEADER
30#include "RISCVGenSubtargetInfo.inc"
31
32namespace llvm {
33class StringRef;
34
36public:
37 enum RISCVProcFamilyEnum : uint8_t {
40 };
41
42private:
43 virtual void anchor();
44
45 RISCVProcFamilyEnum RISCVProcFamily = Others;
46
47#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
48 bool ATTRIBUTE = DEFAULT;
49#include "RISCVGenSubtargetInfo.inc"
50
51 unsigned XLen = 32;
52 unsigned ZvlLen = 0;
53 MVT XLenVT = MVT::i32;
54 unsigned RVVVectorBitsMin;
55 unsigned RVVVectorBitsMax;
56 uint8_t MaxInterleaveFactor = 2;
58 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
59 Align PrefFunctionAlignment;
60 Align PrefLoopAlignment;
61
62 RISCVFrameLowering FrameLowering;
63 RISCVInstrInfo InstrInfo;
67
68 /// Initializes using the passed in CPU and feature strings so that we can
69 /// use initializer lists for subtarget initialization.
70 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
71 StringRef CPU,
72 StringRef TuneCPU,
73 StringRef FS,
74 StringRef ABIName);
75
76public:
77 // Initializes the data members to match that of the specified triple.
78 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
79 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
80 unsigned RVVVectorLMULMax, const TargetMachine &TM);
81
82 // Parses features string setting specified subtarget options. The
83 // definition of this function is auto-generated by tblgen.
85
86 const RISCVFrameLowering *getFrameLowering() const override {
87 return &FrameLowering;
88 }
89 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
90 const RISCVRegisterInfo *getRegisterInfo() const override {
91 return &RegInfo;
92 }
93 const RISCVTargetLowering *getTargetLowering() const override {
94 return &TLInfo;
95 }
97 return &TSInfo;
98 }
99 bool enableMachineScheduler() const override { return true; }
100
101 Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
102 Align getPrefLoopAlignment() const { return PrefLoopAlignment; }
103
104 /// Returns RISCV processor family.
105 /// Avoid this function! CPU specifics should be kept local to this class
106 /// and preferably modeled with SubtargetFeatures or properties in
107 /// initializeProperties().
108 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
109
110#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
111 bool GETTER() const { return ATTRIBUTE; }
112#include "RISCVGenSubtargetInfo.inc"
113
114 bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
115 bool hasStdExtZvl() const { return ZvlLen != 0; }
116 bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
117 bool is64Bit() const { return IsRV64; }
118 MVT getXLenVT() const { return XLenVT; }
119 unsigned getXLen() const { return XLen; }
120 unsigned getFLen() const {
121 if (HasStdExtD)
122 return 64;
123
124 if (HasStdExtF)
125 return 32;
126
127 return 0;
128 }
129 unsigned getELEN() const {
130 assert(hasVInstructions() && "Expected V extension");
131 return hasVInstructionsI64() ? 64 : 32;
132 }
133 unsigned getRealMinVLen() const {
134 unsigned VLen = getMinRVVVectorSizeInBits();
135 return VLen == 0 ? ZvlLen : VLen;
136 }
137 unsigned getRealMaxVLen() const {
138 unsigned VLen = getMaxRVVVectorSizeInBits();
139 return VLen == 0 ? 65536 : VLen;
140 }
141 RISCVABI::ABI getTargetABI() const { return TargetABI; }
143 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
144 return UserReservedRegister[i];
145 }
146
147 bool hasMacroFusion() const { return hasLUIADDIFusion(); }
148
149 // Vector codegen related methods.
150 bool hasVInstructions() const { return HasStdExtZve32x; }
151 bool hasVInstructionsI64() const { return HasStdExtZve64x; }
152 bool hasVInstructionsF16() const {
153 return HasStdExtZvfh && hasStdExtZfhOrZfhmin();
154 }
155 // FIXME: Consider Zfinx in the future
156 bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
157 // FIXME: Consider Zdinx in the future
158 bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
159 // F16 and F64 both require F32.
160 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
161 unsigned getMaxInterleaveFactor() const {
162 return hasVInstructions() ? MaxInterleaveFactor : 1;
163 }
164
165protected:
166 // GlobalISel related APIs.
167 std::unique_ptr<CallLowering> CallLoweringInfo;
168 std::unique_ptr<InstructionSelector> InstSelector;
169 std::unique_ptr<LegalizerInfo> Legalizer;
170 std::unique_ptr<RegisterBankInfo> RegBankInfo;
171
172 // Return the known range for the bit length of RVV data registers as set
173 // at the command line. A value of 0 means nothing is known about that particular
174 // limit beyond what's implied by the architecture.
175 // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
176 unsigned getMaxRVVVectorSizeInBits() const;
177 unsigned getMinRVVVectorSizeInBits() const;
178
179public:
180 const CallLowering *getCallLowering() const override;
182 const LegalizerInfo *getLegalizerInfo() const override;
183 const RegisterBankInfo *getRegBankInfo() const override;
184
185 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
186
187 bool useConstantPoolForLargeInts() const;
188
189 // Maximum cost used for building integers, integers will be put into constant
190 // pool if exceeded.
191 unsigned getMaxBuildIntsCost() const;
192
193 unsigned getMaxLMULForFixedLengthVectors() const;
194 bool useRVVForFixedLengthVectors() const;
195
196 bool enableSubRegLiveness() const override;
197
198 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
199 &Mutations) const override;
200};
201} // End llvm namespace
202
203#endif
This file describes how to lower LLVM calls to machine code calls.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
return InstrInfo
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Provides the logic to select generic machine instructions.
Machine Value Type.
RISCVABI::ABI getTargetABI() const
bool hasStdExtCOrZca() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool hasVInstructionsI64() const
bool hasVInstructionsF64() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool isTargetFuchsia() const
bool hasMacroFusion() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasStdExtZfhOrZfhmin() const
unsigned getXLen() const
unsigned getELEN() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructionsF16() const
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
Align getPrefLoopAlignment() const
bool hasVInstructions() const
bool hasVInstructionsAnyF() const
bool useConstantPoolForLargeInts() const
Align getPrefFunctionAlignment() const
RISCVProcFamilyEnum getProcFamily() const
Returns RISCV processor family.
unsigned getMaxRVVVectorSizeInBits() const
unsigned getRealMaxVLen() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
std::unique_ptr< CallLowering > CallLoweringInfo
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
unsigned getMaxInterleaveFactor() const
bool enableSubRegLiveness() const override
bool hasStdExtZvl() const
const RISCVFrameLowering * getFrameLowering() const override
unsigned getFLen() const
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39