13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H
18#define GET_REGBANK_DECLARATIONS
19#include "RISCVGenRegisterBank.inc"
23class TargetRegisterInfo;
27#define GET_TARGET_REGBANK_CLASS
28#include "RISCVGenRegisterBank.inc"
37 LLT Ty)
const override;
Representation of each machine instruction.
This class provides the information for the target register banks.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Holds all the information related to register banks.
unsigned HwMode
Current HwMode for the target.
This class implements the register bank concept.
This is an optimization pass for GlobalISel generic memory operations.