LLVM 19.0.0git
RISCVRegisterBankInfo.h
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1//===-- RISCVRegisterBankInfo.h ---------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for RISC-V.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H
15
17
18#define GET_REGBANK_DECLARATIONS
19#include "RISCVGenRegisterBank.inc"
20
21namespace llvm {
22
23class TargetRegisterInfo;
24
26protected:
27#define GET_TARGET_REGBANK_CLASS
28#include "RISCVGenRegisterBank.inc"
29};
30
31/// This class provides the information for the target register banks.
33public:
35
37 LLT Ty) const override;
38
39 const InstructionMapping &
40 getInstrMapping(const MachineInstr &MI) const override;
41
42private:
43 /// \returns true if \p MI only uses and defines FPRs.
44 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
45 const TargetRegisterInfo &TRI) const;
46
47 /// \returns true if \p MI only uses FPRs.
48 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
49 const TargetRegisterInfo &TRI) const;
50
51 /// \returns true if any use of \p Def only user FPRs.
52 bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI,
53 const TargetRegisterInfo &TRI) const;
54
55 /// \returns true if \p MI only defines FPRs.
56 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
57 const TargetRegisterInfo &TRI) const;
58};
59} // end namespace llvm
60#endif
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This class provides the information for the target register banks.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Holds all the information related to register banks.
unsigned HwMode
Current HwMode for the target.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18