22#define GET_TARGET_REGBANK_IMPL
23#include "RISCVGenRegisterBank.inc"
118 switch (RC.
getID()) {
121 case RISCV::GPRRegClassID:
122 case RISCV::GPRF16RegClassID:
123 case RISCV::GPRF32RegClassID:
124 case RISCV::GPRNoX0RegClassID:
125 case RISCV::GPRNoX0X2RegClassID:
126 case RISCV::GPRJALRRegClassID:
127 case RISCV::GPRJALRNonX7RegClassID:
128 case RISCV::GPRTCRegClassID:
129 case RISCV::GPRTCNonX7RegClassID:
130 case RISCV::GPRC_and_GPRTCRegClassID:
131 case RISCV::GPRCRegClassID:
132 case RISCV::GPRC_and_SR07RegClassID:
133 case RISCV::SR07RegClassID:
134 case RISCV::SPRegClassID:
135 case RISCV::GPRX0RegClassID:
137 case RISCV::FPR64RegClassID:
138 case RISCV::FPR16RegClassID:
139 case RISCV::FPR32RegClassID:
140 case RISCV::FPR64CRegClassID:
141 case RISCV::FPR32CRegClassID:
143 case RISCV::VMRegClassID:
144 case RISCV::VRRegClassID:
145 case RISCV::VRNoV0RegClassID:
146 case RISCV::VRM2RegClassID:
147 case RISCV::VRM2NoV0RegClassID:
148 case RISCV::VRM4RegClassID:
149 case RISCV::VRM4NoV0RegClassID:
150 case RISCV::VMV0RegClassID:
151 case RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID:
152 case RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID:
153 case RISCV::VRM8RegClassID:
154 case RISCV::VRM8NoV0RegClassID:
155 case RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID:
179bool RISCVRegisterBankInfo::hasFPConstraints(
187 if (
MI.getOpcode() != TargetOpcode::COPY)
196 switch (
MI.getOpcode()) {
197 case TargetOpcode::G_FPTOSI:
198 case TargetOpcode::G_FPTOUI:
199 case TargetOpcode::G_FCMP:
205 return hasFPConstraints(
MI,
MRI,
TRI);
211 switch (
MI.getOpcode()) {
212 case TargetOpcode::G_SITOFP:
213 case TargetOpcode::G_UITOFP:
219 return hasFPConstraints(
MI,
MRI,
TRI);
222bool RISCVRegisterBankInfo::anyUseOnlyUseFP(
226 MRI.use_nodbg_instructions(Def),
235 else if (
Size == 128)
237 else if (
Size == 256)
239 else if (
Size == 512)
249 const unsigned Opc =
MI.getOpcode();
265 assert((GPRSize == 32 || GPRSize == 64) &&
"Unexpected GPR size");
267 unsigned NumOperands =
MI.getNumOperands();
273 case TargetOpcode::G_ADD:
274 case TargetOpcode::G_SUB:
275 case TargetOpcode::G_SHL:
276 case TargetOpcode::G_ASHR:
277 case TargetOpcode::G_LSHR:
278 case TargetOpcode::G_AND:
279 case TargetOpcode::G_OR:
280 case TargetOpcode::G_XOR:
281 case TargetOpcode::G_MUL:
282 case TargetOpcode::G_SDIV:
283 case TargetOpcode::G_SREM:
284 case TargetOpcode::G_SMULH:
285 case TargetOpcode::G_SMAX:
286 case TargetOpcode::G_SMIN:
287 case TargetOpcode::G_UDIV:
288 case TargetOpcode::G_UREM:
289 case TargetOpcode::G_UMULH:
290 case TargetOpcode::G_UMAX:
291 case TargetOpcode::G_UMIN:
292 case TargetOpcode::G_PTR_ADD:
293 case TargetOpcode::G_PTRTOINT:
294 case TargetOpcode::G_INTTOPTR:
295 case TargetOpcode::G_FADD:
296 case TargetOpcode::G_FSUB:
297 case TargetOpcode::G_FMUL:
298 case TargetOpcode::G_FDIV:
299 case TargetOpcode::G_FABS:
300 case TargetOpcode::G_FNEG:
301 case TargetOpcode::G_FSQRT:
302 case TargetOpcode::G_FMAXNUM:
303 case TargetOpcode::G_FMINNUM: {
304 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
313 Mapping = GPRValueMapping;
317 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
318 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
320 "Operand has incompatible type");
329 case TargetOpcode::G_SEXTLOAD:
330 case TargetOpcode::G_ZEXTLOAD:
333 case TargetOpcode::G_IMPLICIT_DEF: {
335 LLT DstTy =
MRI.getType(Dst);
337 auto Mapping = GPRValueMapping;
345 else if (anyUseOnlyUseFP(Dst,
MRI,
TRI))
356 case TargetOpcode::G_LOAD: {
357 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
358 OpdsMapping[0] = GPRValueMapping;
359 OpdsMapping[1] = GPRValueMapping;
370 if (anyUseOnlyUseFP(
MI.getOperand(0).getReg(),
MRI,
TRI))
379 case TargetOpcode::G_STORE: {
380 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
381 OpdsMapping[0] = GPRValueMapping;
382 OpdsMapping[1] = GPRValueMapping;
395 case TargetOpcode::G_SELECT: {
396 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
399 auto &Sel = cast<GSelect>(
MI);
400 LLT TestTy =
MRI.getType(Sel.getCondReg());
401 assert(TestTy.
isVector() &&
"Unexpected condition argument type");
402 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] =
424 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
426 return onlyUsesFP(UseMI, MRI, TRI);
453 OpdsMapping[1] = GPRValueMapping;
459 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
462 case TargetOpcode::G_FPTOSI:
463 case TargetOpcode::G_FPTOUI:
464 case RISCV::G_FCLASS: {
465 LLT Ty =
MRI.getType(
MI.getOperand(1).getReg());
466 OpdsMapping[0] = GPRValueMapping;
470 case TargetOpcode::G_SITOFP:
471 case TargetOpcode::G_UITOFP: {
472 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
474 OpdsMapping[1] = GPRValueMapping;
477 case TargetOpcode::G_FCMP: {
478 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
482 OpdsMapping[0] = GPRValueMapping;
486 case TargetOpcode::G_MERGE_VALUES: {
488 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
492 OpdsMapping[1] = GPRValueMapping;
493 OpdsMapping[2] = GPRValueMapping;
497 case TargetOpcode::G_UNMERGE_VALUES: {
499 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
502 OpdsMapping[0] = GPRValueMapping;
503 OpdsMapping[1] = GPRValueMapping;
510 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
511 auto &MO =
MI.getOperand(
Idx);
512 if (!MO.isReg() || !MO.getReg())
514 LLT Ty =
MRI.getType(MO.getReg());
524 OpdsMapping[
Idx] = GPRValueMapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
unsigned const TargetRegisterInfo * TRI
static const RegisterBankInfo::ValueMapping * getFPValueMapping(unsigned Size)
static const RegisterBankInfo::ValueMapping * getVRBValueMapping(unsigned Size)
This file declares the targeting of the RegisterBankInfo class for RISC-V.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
RISCVRegisterBankInfo(unsigned HwMode)
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const RegisterBankInfo::PartialMapping PartMappings[]
const RegisterBankInfo::ValueMapping ValueMappings[]
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.