LLVM 19.0.0git
RISCVRegisterInfo.h
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1//===-- RISCVRegisterInfo.h - RISC-V Register Information Impl --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
15
17
18#define GET_REGINFO_HEADER
19#include "RISCVGenRegisterInfo.inc"
20
21namespace llvm {
22
24
25 RISCVRegisterInfo(unsigned HwMode);
26
28 CallingConv::ID) const override;
29
30 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
31
32 BitVector getReservedRegs(const MachineFunction &MF) const override;
33 bool isAsmClobberable(const MachineFunction &MF,
34 MCRegister PhysReg) const override;
35
36 const uint32_t *getNoPreservedMask() const override;
37
38 // Update DestReg to have the value SrcReg plus an offset. This is
39 // used during frame layout, and we may need to ensure that if we
40 // split the offset internally that the DestReg is always aligned,
41 // assuming that source reg was.
43 const DebugLoc &DL, Register DestReg, Register SrcReg,
45 MaybeAlign RequiredAlign) const;
46
48 unsigned FIOperandNum,
49 RegScavenger *RS = nullptr) const override;
50
51 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
52
53 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
54
55 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
56 int64_t Offset) const override;
57
59 int64_t Offset) const override;
60
62 int64_t Offset) const override;
63
65 int Idx) const override;
66
69
70 Register getFrameRegister(const MachineFunction &MF) const override;
71
72 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
73 return true;
74 }
75
76 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
77 return true;
78 }
79
82 unsigned Kind = 0) const override {
83 return &RISCV::GPRRegClass;
84 }
85
88 const MachineFunction &) const override;
89
91 SmallVectorImpl<uint64_t> &Ops) const override;
92
93 unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
94
97 const MachineFunction &MF, const VirtRegMap *VRM,
98 const LiveRegMatrix *Matrix) const override;
99
100 const TargetRegisterClass *
101 getLargestSuperClass(const TargetRegisterClass *RC) const override {
102 if (RISCV::VRM8RegClass.hasSubClassEq(RC))
103 return &RISCV::VRM8RegClass;
104 if (RISCV::VRM4RegClass.hasSubClassEq(RC))
105 return &RISCV::VRM4RegClass;
106 if (RISCV::VRM2RegClass.hasSubClassEq(RC))
107 return &RISCV::VRM2RegClass;
108 if (RISCV::VRRegClass.hasSubClassEq(RC))
109 return &RISCV::VRRegClass;
110 return RC;
111 }
112
114 const TargetRegisterClass *RC) const override {
115 return RISCV::VRRegClass.hasSubClassEq(RC) ||
116 RISCV::VRM2RegClass.hasSubClassEq(RC) ||
117 RISCV::VRM4RegClass.hasSubClassEq(RC) ||
118 RISCV::VRM8RegClass.hasSubClassEq(RC);
119 }
120};
121}
122
123#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
Live Register Matrix
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerVRELOAD(MachineBasicBlock::iterator II) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
const TargetRegisterClass * getLargestSuperClass(const TargetRegisterClass *RC) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
bool doesRegClassHavePseudoInitUndef(const TargetRegisterClass *RC) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void lowerVSPILL(MachineBasicBlock::iterator II) const
Register getFrameRegister(const MachineFunction &MF) const override
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * getNoPreservedMask() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override