LLVM 19.0.0git
RISCVRegisterInfo.h
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1//===-- RISCVRegisterInfo.h - RISC-V Register Information Impl --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
15
18
19#define GET_REGINFO_HEADER
20#include "RISCVGenRegisterInfo.inc"
21
22namespace llvm {
23
24namespace RISCVRI {
25enum {
26 // The IsVRegClass value of this RegisterClass.
29 // The VLMul value of this RegisterClass. This value is valid iff IsVRegClass
30 // is true.
33
34 // The NF value of this RegisterClass. This value is valid iff IsVRegClass is
35 // true.
37 NFShiftMask = 0b111 << NFShift,
38};
39
40/// \returns the IsVRegClass for the register class.
41static inline bool isVRegClass(uint64_t TSFlags) {
42 return TSFlags & IsVRegClassShiftMask >> IsVRegClassShift;
43}
44
45/// \returns the LMUL for the register class.
46static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) {
47 return static_cast<RISCVII::VLMUL>((TSFlags & VLMulShiftMask) >> VLMulShift);
48}
49
50/// \returns the NF for the register class.
51static inline unsigned getNF(uint64_t TSFlags) {
52 return static_cast<unsigned>((TSFlags & NFShiftMask) >> NFShift) + 1;
53}
54} // namespace RISCVRI
55
57
58 RISCVRegisterInfo(unsigned HwMode);
59
61 CallingConv::ID) const override;
62
63 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
64
65 BitVector getReservedRegs(const MachineFunction &MF) const override;
66 bool isAsmClobberable(const MachineFunction &MF,
67 MCRegister PhysReg) const override;
68
69 const uint32_t *getNoPreservedMask() const override;
70
71 // Update DestReg to have the value SrcReg plus an offset. This is
72 // used during frame layout, and we may need to ensure that if we
73 // split the offset internally that the DestReg is always aligned,
74 // assuming that source reg was.
76 const DebugLoc &DL, Register DestReg, Register SrcReg,
78 MaybeAlign RequiredAlign) const;
79
81 unsigned FIOperandNum,
82 RegScavenger *RS = nullptr) const override;
83
84 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
85
86 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
87
88 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
89 int64_t Offset) const override;
90
92 int64_t Offset) const override;
93
95 int64_t Offset) const override;
96
98 int Idx) const override;
99
102
103 Register getFrameRegister(const MachineFunction &MF) const override;
104
105 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
106 return true;
107 }
108
109 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
110 return true;
111 }
112
113 const TargetRegisterClass *
115 unsigned Kind = 0) const override {
116 return &RISCV::GPRRegClass;
117 }
118
119 const TargetRegisterClass *
121 const MachineFunction &) const override;
122
124 SmallVectorImpl<uint64_t> &Ops) const override;
125
126 unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
127
130 const MachineFunction &MF, const VirtRegMap *VRM,
131 const LiveRegMatrix *Matrix) const override;
132
133 const TargetRegisterClass *
134 getLargestSuperClass(const TargetRegisterClass *RC) const override {
135 if (RISCV::VRM8RegClass.hasSubClassEq(RC))
136 return &RISCV::VRM8RegClass;
137 if (RISCV::VRM4RegClass.hasSubClassEq(RC))
138 return &RISCV::VRM4RegClass;
139 if (RISCV::VRM2RegClass.hasSubClassEq(RC))
140 return &RISCV::VRM2RegClass;
141 if (RISCV::VRRegClass.hasSubClassEq(RC))
142 return &RISCV::VRRegClass;
143 return RC;
144 }
145
147 const TargetRegisterClass *RC) const override {
148 return isVRRegClass(RC);
149 }
150
151 static bool isVRRegClass(const TargetRegisterClass *RC) {
152 return RISCVRI::isVRegClass(RC->TSFlags) &&
153 RISCVRI::getNF(RC->TSFlags) == 1;
154 }
155
156 static bool isVRNRegClass(const TargetRegisterClass *RC) {
157 return RISCVRI::isVRegClass(RC->TSFlags) && RISCVRI::getNF(RC->TSFlags) > 1;
158 }
159
160 static bool isRVVRegClass(const TargetRegisterClass *RC) {
161 return RISCVRI::isVRegClass(RC->TSFlags);
162 }
163};
164} // namespace llvm
165
166#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
Live Register Matrix
uint64_t IntrinsicInst * II
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
const uint8_t TSFlags
Configurable target specific flags.
static RISCVII::VLMUL getLMul(uint64_t TSFlags)
static unsigned getNF(uint64_t TSFlags)
static bool isVRegClass(uint64_t TSFlags)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerVRELOAD(MachineBasicBlock::iterator II) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static bool isVRNRegClass(const TargetRegisterClass *RC)
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
const TargetRegisterClass * getLargestSuperClass(const TargetRegisterClass *RC) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
bool doesRegClassHavePseudoInitUndef(const TargetRegisterClass *RC) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
static bool isRVVRegClass(const TargetRegisterClass *RC)
void lowerVSPILL(MachineBasicBlock::iterator II) const
Register getFrameRegister(const MachineFunction &MF) const override
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * getNoPreservedMask() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
static bool isVRRegClass(const TargetRegisterClass *RC)
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override