LLVM  14.0.0git
RISCVRegisterInfo.h
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1 //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
15 
17 
18 #define GET_REGINFO_HEADER
19 #include "RISCVGenRegisterInfo.inc"
20 
21 namespace llvm {
22 
24 
25  RISCVRegisterInfo(unsigned HwMode);
26 
28  CallingConv::ID) const override;
29 
30  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
31 
32  BitVector getReservedRegs(const MachineFunction &MF) const override;
33  bool isAsmClobberable(const MachineFunction &MF,
34  MCRegister PhysReg) const override;
35 
36  bool isConstantPhysReg(MCRegister PhysReg) const override;
37 
38  const uint32_t *getNoPreservedMask() const override;
39 
41  int &FrameIdx) const override;
42 
44  unsigned FIOperandNum,
45  RegScavenger *RS = nullptr) const override;
46 
47  Register getFrameRegister(const MachineFunction &MF) const override;
48 
49  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
50  return true;
51  }
52 
53  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
54  return true;
55  }
56 
57  const TargetRegisterClass *
59  unsigned Kind = 0) const override {
60  return &RISCV::GPRRegClass;
61  }
62 
63  const TargetRegisterClass *
65  const MachineFunction &) const override;
66 
68  SmallVectorImpl<uint64_t> &Ops) const override;
69 
70  unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
71 };
72 }
73 
74 #endif
llvm::RISCVRegisterInfo::getRegisterCostTableIndex
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:352
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::RISCVRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:289
llvm::RISCVRegisterInfo::RISCVRegisterInfo
RISCVRegisterInfo(unsigned HwMode)
Definition: RISCVRegisterInfo.cpp:45
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::RISCVRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: RISCVRegisterInfo.h:58
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::RISCVRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: RISCVRegisterInfo.cpp:50
llvm::RISCVRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.h:49
llvm::RISCVRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: RISCVRegisterInfo.cpp:118
llvm::RISCVRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: RISCVRegisterInfo.cpp:295
llvm::RISCVRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
Definition: RISCVRegisterInfo.cpp:317
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::RISCVRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:77
llvm::BitVector
Definition: BitVector.h:74
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: RISCVRegisterInfo.cpp:159
llvm::RISCVRegisterInfo::getOffsetOpcodes
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Definition: RISCVRegisterInfo.cpp:324
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::RISCVRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.h:53
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::RISCVRegisterInfo::hasReservedSpillSlot
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Definition: RISCVRegisterInfo.cpp:144
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
uint16_t
RISCVGenRegisterInfo
llvm::SmallVectorImpl< uint64_t >
llvm::RISCVRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: RISCVRegisterInfo.cpp:122
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::RISCVRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: RISCVRegisterInfo.cpp:113