LLVM  15.0.0git
RISCVRegisterInfo.cpp
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1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
16 #include "RISCVSubtarget.h"
26 
27 #define GET_REGINFO_TARGET_DESC
28 #include "RISCVGenRegisterInfo.inc"
29 
30 using namespace llvm;
31 
32 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
33 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
34 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
35 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
36  "Register list not consecutive");
37 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
38 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
39  "Register list not consecutive");
40 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
41 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
42  "Register list not consecutive");
43 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
44 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
45 
47  : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
48  /*PC*/0, HwMode) {}
49 
50 const MCPhysReg *
52  auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
54  return CSR_NoRegs_SaveList;
55  if (MF->getFunction().hasFnAttribute("interrupt")) {
56  if (Subtarget.hasStdExtD())
57  return CSR_XLEN_F64_Interrupt_SaveList;
58  if (Subtarget.hasStdExtF())
59  return CSR_XLEN_F32_Interrupt_SaveList;
60  return CSR_Interrupt_SaveList;
61  }
62 
63  switch (Subtarget.getTargetABI()) {
64  default:
65  llvm_unreachable("Unrecognized ABI");
67  case RISCVABI::ABI_LP64:
68  return CSR_ILP32_LP64_SaveList;
71  return CSR_ILP32F_LP64F_SaveList;
74  return CSR_ILP32D_LP64D_SaveList;
75  }
76 }
77 
79  const RISCVFrameLowering *TFI = getFrameLowering(MF);
80  BitVector Reserved(getNumRegs());
81 
82  // Mark any registers requested to be reserved as such
83  for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
85  markSuperRegs(Reserved, Reg);
86  }
87 
88  // Use markSuperRegs to ensure any register aliases are also reserved
89  markSuperRegs(Reserved, RISCV::X0); // zero
90  markSuperRegs(Reserved, RISCV::X2); // sp
91  markSuperRegs(Reserved, RISCV::X3); // gp
92  markSuperRegs(Reserved, RISCV::X4); // tp
93  if (TFI->hasFP(MF))
94  markSuperRegs(Reserved, RISCV::X8); // fp
95  // Reserve the base register if we need to realign the stack and allocate
96  // variable-sized objects at runtime.
97  if (TFI->hasBP(MF))
98  markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
99 
100  // V registers for code generation. We handle them manually.
101  markSuperRegs(Reserved, RISCV::VL);
102  markSuperRegs(Reserved, RISCV::VTYPE);
103  markSuperRegs(Reserved, RISCV::VXSAT);
104  markSuperRegs(Reserved, RISCV::VXRM);
105  markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
106 
107  // Floating point environment registers.
108  markSuperRegs(Reserved, RISCV::FRM);
109  markSuperRegs(Reserved, RISCV::FFLAGS);
110 
111  assert(checkAllSuperRegsMarked(Reserved));
112  return Reserved;
113 }
114 
116  MCRegister PhysReg) const {
117  return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
118 }
119 
121  return PhysReg == RISCV::X0 || PhysReg == RISCV::VLENB;
122 }
123 
125  return CSR_NoRegs_RegMask;
126 }
127 
128 // Frame indexes representing locations of CSRs which are given a fixed location
129 // by save/restore libcalls.
130 static const std::pair<unsigned, int> FixedCSRFIMap[] = {
131  {/*ra*/ RISCV::X1, -1},
132  {/*s0*/ RISCV::X8, -2},
133  {/*s1*/ RISCV::X9, -3},
134  {/*s2*/ RISCV::X18, -4},
135  {/*s3*/ RISCV::X19, -5},
136  {/*s4*/ RISCV::X20, -6},
137  {/*s5*/ RISCV::X21, -7},
138  {/*s6*/ RISCV::X22, -8},
139  {/*s7*/ RISCV::X23, -9},
140  {/*s8*/ RISCV::X24, -10},
141  {/*s9*/ RISCV::X25, -11},
142  {/*s10*/ RISCV::X26, -12},
143  {/*s11*/ RISCV::X27, -13}
144 };
145 
147  Register Reg,
148  int &FrameIdx) const {
149  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
150  if (!RVFI->useSaveRestoreLibCalls(MF))
151  return false;
152 
153  const auto *FII =
154  llvm::find_if(FixedCSRFIMap, [&](auto P) { return P.first == Reg; });
155  if (FII == std::end(FixedCSRFIMap))
156  return false;
157 
158  FrameIdx = FII->second;
159  return true;
160 }
161 
163  int SPAdj, unsigned FIOperandNum,
164  RegScavenger *RS) const {
165  assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
166 
167  MachineInstr &MI = *II;
168  MachineFunction &MF = *MI.getParent()->getParent();
170  const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
171  DebugLoc DL = MI.getDebugLoc();
172 
173  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
174  Register FrameReg;
175  StackOffset Offset =
176  getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
177  bool IsRVVSpill = RISCV::isRVVSpill(MI, /*CheckFIs*/ false);
178  if (!IsRVVSpill)
179  Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
180 
181  if (!isInt<32>(Offset.getFixed())) {
183  "Frame offsets outside of the signed 32-bit range not supported");
184  }
185 
186  MachineBasicBlock &MBB = *MI.getParent();
187  bool FrameRegIsKill = false;
188 
189  // If required, pre-compute the scalable factor amount which will be used in
190  // later offset computation. Since this sequence requires up to two scratch
191  // registers -- after which one is made free -- this grants us better
192  // scavenging of scratch registers as only up to two are live at one time,
193  // rather than three.
194  Register ScalableFactorRegister;
195  unsigned ScalableAdjOpc = RISCV::ADD;
196  if (Offset.getScalable()) {
197  int64_t ScalableValue = Offset.getScalable();
198  if (ScalableValue < 0) {
199  ScalableValue = -ScalableValue;
200  ScalableAdjOpc = RISCV::SUB;
201  }
202  // 1. Get vlenb && multiply vlen with the number of vector registers.
203  ScalableFactorRegister =
204  TII->getVLENFactoredAmount(MF, MBB, II, DL, ScalableValue);
205  }
206 
207  if (!isInt<12>(Offset.getFixed())) {
208  // The offset won't fit in an immediate, so use a scratch register instead
209  // Modify Offset and FrameReg appropriately
210  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
211  TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
212  if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
213  BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
214  .addReg(FrameReg)
215  .addReg(ScratchReg, RegState::Kill);
216  MI.eraseFromParent();
217  return;
218  }
219  BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
220  .addReg(FrameReg)
221  .addReg(ScratchReg, RegState::Kill);
222  Offset = StackOffset::get(0, Offset.getScalable());
223  FrameReg = ScratchReg;
224  FrameRegIsKill = true;
225  }
226 
227  if (!Offset.getScalable()) {
228  // Offset = (fixed offset, 0)
229  MI.getOperand(FIOperandNum)
230  .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
231  if (!IsRVVSpill)
232  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
233  else {
234  if (Offset.getFixed()) {
235  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
236  BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
237  .addReg(FrameReg, getKillRegState(FrameRegIsKill))
238  .addImm(Offset.getFixed());
239  MI.getOperand(FIOperandNum)
240  .ChangeToRegister(ScratchReg, false, false, true);
241  }
242  }
243  } else {
244  // Offset = (fixed offset, scalable offset)
245  // Step 1, the scalable offset, has already been computed.
246  assert(ScalableFactorRegister &&
247  "Expected pre-computation of scalable factor in earlier step");
248 
249  // 2. Calculate address: FrameReg + result of multiply
250  if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
251  BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), MI.getOperand(0).getReg())
252  .addReg(FrameReg, getKillRegState(FrameRegIsKill))
253  .addReg(ScalableFactorRegister, RegState::Kill);
254  MI.eraseFromParent();
255  return;
256  }
257  Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
258  BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), VL)
259  .addReg(FrameReg, getKillRegState(FrameRegIsKill))
260  .addReg(ScalableFactorRegister, RegState::Kill);
261 
262  if (IsRVVSpill && Offset.getFixed()) {
263  // Scalable load/store has no immediate argument. We need to add the
264  // fixed part into the load/store base address.
265  BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL)
266  .addReg(VL)
267  .addImm(Offset.getFixed());
268  }
269 
270  // 3. Replace address register with calculated address register
271  MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true);
272  if (!IsRVVSpill)
273  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
274  }
275 
276  auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());
277  if (ZvlssegInfo) {
278  Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
279  BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
280  uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
281  if (ShiftAmount != 0)
282  BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
283  .addReg(VL)
284  .addImm(ShiftAmount);
285  // The last argument of pseudo spilling opcode for zvlsseg is the length of
286  // one element of zvlsseg types. For example, for vint32m2x2_t, it will be
287  // the length of vint32m2_t.
288  MI.getOperand(FIOperandNum + 1).ChangeToRegister(VL, /*isDef=*/false);
289  }
290 }
291 
293  const TargetFrameLowering *TFI = getFrameLowering(MF);
294  return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
295 }
296 
297 const uint32_t *
299  CallingConv::ID CC) const {
300  auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
301 
302  if (CC == CallingConv::GHC)
303  return CSR_NoRegs_RegMask;
304  switch (Subtarget.getTargetABI()) {
305  default:
306  llvm_unreachable("Unrecognized ABI");
307  case RISCVABI::ABI_ILP32:
308  case RISCVABI::ABI_LP64:
309  return CSR_ILP32_LP64_RegMask;
311  case RISCVABI::ABI_LP64F:
312  return CSR_ILP32F_LP64F_RegMask;
314  case RISCVABI::ABI_LP64D:
315  return CSR_ILP32D_LP64D_RegMask;
316  }
317 }
318 
319 const TargetRegisterClass *
321  const MachineFunction &) const {
322  if (RC == &RISCV::VMV0RegClass)
323  return &RISCV::VRRegClass;
324  return RC;
325 }
326 
328  SmallVectorImpl<uint64_t> &Ops) const {
329  // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
330  // to represent one vector register. The dwarf offset is
331  // VLENB * scalable_offset / 8.
332  assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
333 
334  // Add fixed-sized offset using existing DIExpression interface.
335  DIExpression::appendOffset(Ops, Offset.getFixed());
336 
337  unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);
338  int64_t VLENBSized = Offset.getScalable() / 8;
339  if (VLENBSized > 0) {
340  Ops.push_back(dwarf::DW_OP_constu);
341  Ops.push_back(VLENBSized);
342  Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
343  Ops.push_back(dwarf::DW_OP_mul);
344  Ops.push_back(dwarf::DW_OP_plus);
345  } else if (VLENBSized < 0) {
346  Ops.push_back(dwarf::DW_OP_constu);
347  Ops.push_back(-VLENBSized);
348  Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
349  Ops.push_back(dwarf::DW_OP_mul);
350  Ops.push_back(dwarf::DW_OP_minus);
351  }
352 }
353 
354 unsigned
356  return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
357 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:353
llvm::RISCVRegisterInfo::getRegisterCostTableIndex
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:355
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
TargetFrameLowering.h
llvm::RISCVRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:292
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
DebugInfoMetadata.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::RISCVRegisterInfo::RISCVRegisterInfo
RISCVRegisterInfo(unsigned HwMode)
Definition: RISCVRegisterInfo.cpp:46
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:215
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
getDwarfRegNum
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:178
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
llvm::RISCVRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: RISCVRegisterInfo.cpp:51
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:348
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:352
llvm::RISCVRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: RISCVRegisterInfo.cpp:120
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:667
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::RISCVRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: RISCVRegisterInfo.cpp:298
llvm::RISCVRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
Definition: RISCVRegisterInfo.cpp:320
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::RISCVFrameLowering
Definition: RISCVFrameLowering.h:22
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:623
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:350
llvm::RISCVRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: RISCVRegisterInfo.cpp:78
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::BitVector
Definition: BitVector.h:75
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::RISCVRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: RISCVRegisterInfo.cpp:162
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::RISCVRegisterInfo::getOffsetOpcodes
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Definition: RISCVRegisterInfo.cpp:327
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
Dwarf.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: RISCVFrameLowering.cpp:227
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::RISCVRegisterInfo::hasReservedSpillSlot
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Definition: RISCVRegisterInfo.cpp:146
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1383
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:354
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
uint16_t
MachineFrameInfo.h
RISCVGenRegisterInfo
FixedCSRFIMap
static const std::pair< unsigned, int > FixedCSRFIMap[]
Definition: RISCVRegisterInfo.cpp:130
llvm::RISCV::isRVVSpill
bool isRVVSpill(const MachineInstr &MI, bool CheckFIs)
Definition: RISCVInstrInfo.cpp:1880
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
RISCVSubtarget.h
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
RISCVMachineFunctionInfo.h
llvm::SmallVectorImpl< uint64_t >
llvm::RISCV::isRVVSpillForZvlsseg
Optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
Definition: RISCVInstrInfo.cpp:1893
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:349
llvm::RISCVRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: RISCVRegisterInfo.cpp:124
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
RegisterScavenging.h
llvm::RISCVFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:236
MachineFunction.h
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
RISCVRegisterInfo.h
llvm::RISCVRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: RISCVRegisterInfo.cpp:115
llvm::StackOffset::get
static StackOffset get(ScalarTy Fixed, ScalarTy Scalable)
Definition: TypeSize.h:145