LLVM 20.0.0git
RISCVRegisterInfo.cpp
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1//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterInfo.h"
14#include "RISCV.h"
16#include "RISCVSubtarget.h"
17#include "llvm/ADT/SmallSet.h"
27
28#define GET_REGINFO_TARGET_DESC
29#include "RISCVGenRegisterInfo.inc"
30
31using namespace llvm;
32
33static cl::opt<bool> DisableCostPerUse("riscv-disable-cost-per-use",
34 cl::init(false), cl::Hidden);
35static cl::opt<bool>
36 DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
37 cl::init(false),
38 cl::desc("Disable two address hints for register "
39 "allocation"));
40
41static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
42static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
43static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
44static_assert(RISCV::F31_H == RISCV::F0_H + 31,
45 "Register list not consecutive");
46static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
47static_assert(RISCV::F31_F == RISCV::F0_F + 31,
48 "Register list not consecutive");
49static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
50static_assert(RISCV::F31_D == RISCV::F0_D + 31,
51 "Register list not consecutive");
52static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
53static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
54
56 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
57 /*PC*/0, HwMode) {}
58
59const MCPhysReg *
61 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
63 return CSR_NoRegs_SaveList;
64 if (MF->getFunction().hasFnAttribute("interrupt")) {
65 if (Subtarget.hasStdExtD())
66 return CSR_XLEN_F64_Interrupt_SaveList;
67 if (Subtarget.hasStdExtF())
68 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
69 : CSR_XLEN_F32_Interrupt_SaveList;
70 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
71 : CSR_Interrupt_SaveList;
72 }
73
74 bool HasVectorCSR =
76 Subtarget.hasVInstructions();
77
78 switch (Subtarget.getTargetABI()) {
79 default:
80 llvm_unreachable("Unrecognized ABI");
83 return CSR_ILP32E_LP64E_SaveList;
86 if (HasVectorCSR)
87 return CSR_ILP32_LP64_V_SaveList;
88 return CSR_ILP32_LP64_SaveList;
91 if (HasVectorCSR)
92 return CSR_ILP32F_LP64F_V_SaveList;
93 return CSR_ILP32F_LP64F_SaveList;
96 if (HasVectorCSR)
97 return CSR_ILP32D_LP64D_V_SaveList;
98 return CSR_ILP32D_LP64D_SaveList;
99 }
100}
101
103 const RISCVFrameLowering *TFI = getFrameLowering(MF);
104 BitVector Reserved(getNumRegs());
105 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
106
107 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
108 // Mark any GPRs requested to be reserved as such
109 if (Subtarget.isRegisterReservedByUser(Reg))
110 markSuperRegs(Reserved, Reg);
111
112 // Mark all the registers defined as constant in TableGen as reserved.
113 if (isConstantPhysReg(Reg))
114 markSuperRegs(Reserved, Reg);
115 }
116
117 // Use markSuperRegs to ensure any register aliases are also reserved
118 markSuperRegs(Reserved, RISCV::X2); // sp
119 markSuperRegs(Reserved, RISCV::X3); // gp
120 markSuperRegs(Reserved, RISCV::X4); // tp
121 if (TFI->hasFP(MF))
122 markSuperRegs(Reserved, RISCV::X8); // fp
123 // Reserve the base register if we need to realign the stack and allocate
124 // variable-sized objects at runtime.
125 if (TFI->hasBP(MF))
126 markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
127
128 // Additionally reserve dummy register used to form the register pair
129 // beginning with 'x0' for instructions that take register pairs.
130 markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
131
132 // There are only 16 GPRs for RVE.
133 if (Subtarget.hasStdExtE())
134 for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
135 markSuperRegs(Reserved, Reg);
136
137 // V registers for code generation. We handle them manually.
138 markSuperRegs(Reserved, RISCV::VL);
139 markSuperRegs(Reserved, RISCV::VTYPE);
140 markSuperRegs(Reserved, RISCV::VXSAT);
141 markSuperRegs(Reserved, RISCV::VXRM);
142
143 // Floating point environment registers.
144 markSuperRegs(Reserved, RISCV::FRM);
145 markSuperRegs(Reserved, RISCV::FFLAGS);
146
147 // SiFive VCIX state registers.
148 markSuperRegs(Reserved, RISCV::VCIX_STATE);
149
151 if (Subtarget.hasStdExtE())
152 report_fatal_error("Graal reserved registers do not exist in RVE");
153 markSuperRegs(Reserved, RISCV::X23);
154 markSuperRegs(Reserved, RISCV::X27);
155 }
156
157 // Shadow stack pointer.
158 markSuperRegs(Reserved, RISCV::SSP);
159
160 assert(checkAllSuperRegsMarked(Reserved));
161 return Reserved;
162}
163
165 MCRegister PhysReg) const {
166 return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
167}
168
170 return CSR_NoRegs_RegMask;
171}
172
175 const DebugLoc &DL, Register DestReg,
178 MaybeAlign RequiredAlign) const {
179
180 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
181 return;
182
186 const RISCVInstrInfo *TII = ST.getInstrInfo();
187
188 bool KillSrcReg = false;
189
190 if (Offset.getScalable()) {
191 unsigned ScalableAdjOpc = RISCV::ADD;
192 int64_t ScalableValue = Offset.getScalable();
193 if (ScalableValue < 0) {
194 ScalableValue = -ScalableValue;
195 ScalableAdjOpc = RISCV::SUB;
196 }
197 // Get vlenb and multiply vlen with the number of vector registers.
198 Register ScratchReg = DestReg;
199 if (DestReg == SrcReg)
200 ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
201
202 assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
203 assert(ScalableValue % 8 == 0 &&
204 "Reserve the stack by the multiple of one vector size.");
205 assert(isInt<32>(ScalableValue / 8) &&
206 "Expect the number of vector registers within 32-bits.");
207 uint32_t NumOfVReg = ScalableValue / 8;
208 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), ScratchReg)
209 .setMIFlag(Flag);
210
211 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
212 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
213 unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD :
214 (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
215 BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
216 .addReg(ScratchReg, RegState::Kill).addReg(SrcReg)
217 .setMIFlag(Flag);
218 } else {
219 TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag);
220 BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
221 .addReg(SrcReg).addReg(ScratchReg, RegState::Kill)
222 .setMIFlag(Flag);
223 }
224 SrcReg = DestReg;
225 KillSrcReg = true;
226 }
227
228 int64_t Val = Offset.getFixed();
229 if (DestReg == SrcReg && Val == 0)
230 return;
231
232 const uint64_t Align = RequiredAlign.valueOrOne().value();
233
234 if (isInt<12>(Val)) {
235 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
236 .addReg(SrcReg, getKillRegState(KillSrcReg))
237 .addImm(Val)
238 .setMIFlag(Flag);
239 return;
240 }
241
242 // Try to split the offset across two ADDIs. We need to keep the intermediate
243 // result aligned after each ADDI. We need to determine the maximum value we
244 // can put in each ADDI. In the negative direction, we can use -2048 which is
245 // always sufficiently aligned. In the positive direction, we need to find the
246 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
247 // created with LUI.
248 assert(Align < 2048 && "Required alignment too large");
249 int64_t MaxPosAdjStep = 2048 - Align;
250 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
251 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
252 Val -= FirstAdj;
253 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
254 .addReg(SrcReg, getKillRegState(KillSrcReg))
255 .addImm(FirstAdj)
256 .setMIFlag(Flag);
257 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
258 .addReg(DestReg, RegState::Kill)
259 .addImm(Val)
260 .setMIFlag(Flag);
261 return;
262 }
263
264 // Use shNadd if doing so lets us materialize a 12 bit immediate with a single
265 // instruction. This saves 1 instruction over the full lui/addi+add fallback
266 // path. We avoid anything which can be done with a single lui as it might
267 // be compressible. Note that the sh1add case is fully covered by the 2x addi
268 // case just above and is thus ommitted.
269 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
270 unsigned Opc = 0;
271 if (isShiftedInt<12, 3>(Val)) {
272 Opc = RISCV::SH3ADD;
273 Val = Val >> 3;
274 } else if (isShiftedInt<12, 2>(Val)) {
275 Opc = RISCV::SH2ADD;
276 Val = Val >> 2;
277 }
278 if (Opc) {
279 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
280 TII->movImm(MBB, II, DL, ScratchReg, Val, Flag);
281 BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
282 .addReg(ScratchReg, RegState::Kill)
283 .addReg(SrcReg, getKillRegState(KillSrcReg))
284 .setMIFlag(Flag);
285 return;
286 }
287 }
288
289 unsigned Opc = RISCV::ADD;
290 if (Val < 0) {
291 Val = -Val;
292 Opc = RISCV::SUB;
293 }
294
295 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
296 TII->movImm(MBB, II, DL, ScratchReg, Val, Flag);
297 BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
298 .addReg(SrcReg, getKillRegState(KillSrcReg))
299 .addReg(ScratchReg, RegState::Kill)
300 .setMIFlag(Flag);
301}
302
303// Split a VSPILLx_Mx pseudo into multiple whole register stores separated by
304// LMUL*VLENB bytes.
306 DebugLoc DL = II->getDebugLoc();
307 MachineBasicBlock &MBB = *II->getParent();
310 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
311 const TargetInstrInfo *TII = STI.getInstrInfo();
313
314 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode());
315 unsigned NF = ZvlssegInfo->first;
316 unsigned LMUL = ZvlssegInfo->second;
317 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
318 unsigned Opcode, SubRegIdx;
319 switch (LMUL) {
320 default:
321 llvm_unreachable("LMUL must be 1, 2, or 4.");
322 case 1:
323 Opcode = RISCV::VS1R_V;
324 SubRegIdx = RISCV::sub_vrm1_0;
325 break;
326 case 2:
327 Opcode = RISCV::VS2R_V;
328 SubRegIdx = RISCV::sub_vrm2_0;
329 break;
330 case 4:
331 Opcode = RISCV::VS4R_V;
332 SubRegIdx = RISCV::sub_vrm4_0;
333 break;
334 }
335 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
336 "Unexpected subreg numbering");
337 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
338 "Unexpected subreg numbering");
339 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
340 "Unexpected subreg numbering");
341
342 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
343 // Optimize for constant VLEN.
344 if (auto VLEN = STI.getRealVLen()) {
345 const int64_t VLENB = *VLEN / 8;
346 int64_t Offset = VLENB * LMUL;
347 STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
348 } else {
349 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
350 uint32_t ShiftAmount = Log2_32(LMUL);
351 if (ShiftAmount != 0)
352 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
353 .addReg(VL)
354 .addImm(ShiftAmount);
355 }
356
357 Register SrcReg = II->getOperand(0).getReg();
358 Register Base = II->getOperand(1).getReg();
359 bool IsBaseKill = II->getOperand(1).isKill();
360 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
361 for (unsigned I = 0; I < NF; ++I) {
362 // Adding implicit-use of super register to describe we are using part of
363 // super register, that prevents machine verifier complaining when part of
364 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
365 // detail.
366 BuildMI(MBB, II, DL, TII->get(Opcode))
367 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
368 .addReg(Base, getKillRegState(I == NF - 1))
369 .addMemOperand(*(II->memoperands_begin()))
370 .addReg(SrcReg, RegState::Implicit);
371 if (I != NF - 1)
372 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
373 .addReg(Base, getKillRegState(I != 0 || IsBaseKill))
374 .addReg(VL, getKillRegState(I == NF - 2));
375 Base = NewBase;
376 }
377 II->eraseFromParent();
378}
379
380// Split a VSPILLx_Mx pseudo into multiple whole register loads separated by
381// LMUL*VLENB bytes.
383 DebugLoc DL = II->getDebugLoc();
384 MachineBasicBlock &MBB = *II->getParent();
387 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
388 const TargetInstrInfo *TII = STI.getInstrInfo();
390
391 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode());
392 unsigned NF = ZvlssegInfo->first;
393 unsigned LMUL = ZvlssegInfo->second;
394 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
395 unsigned Opcode, SubRegIdx;
396 switch (LMUL) {
397 default:
398 llvm_unreachable("LMUL must be 1, 2, or 4.");
399 case 1:
400 Opcode = RISCV::VL1RE8_V;
401 SubRegIdx = RISCV::sub_vrm1_0;
402 break;
403 case 2:
404 Opcode = RISCV::VL2RE8_V;
405 SubRegIdx = RISCV::sub_vrm2_0;
406 break;
407 case 4:
408 Opcode = RISCV::VL4RE8_V;
409 SubRegIdx = RISCV::sub_vrm4_0;
410 break;
411 }
412 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
413 "Unexpected subreg numbering");
414 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
415 "Unexpected subreg numbering");
416 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
417 "Unexpected subreg numbering");
418
419 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
420 // Optimize for constant VLEN.
421 if (auto VLEN = STI.getRealVLen()) {
422 const int64_t VLENB = *VLEN / 8;
423 int64_t Offset = VLENB * LMUL;
424 STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
425 } else {
426 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
427 uint32_t ShiftAmount = Log2_32(LMUL);
428 if (ShiftAmount != 0)
429 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
430 .addReg(VL)
431 .addImm(ShiftAmount);
432 }
433
434 Register DestReg = II->getOperand(0).getReg();
435 Register Base = II->getOperand(1).getReg();
436 bool IsBaseKill = II->getOperand(1).isKill();
437 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
438 for (unsigned I = 0; I < NF; ++I) {
439 BuildMI(MBB, II, DL, TII->get(Opcode),
440 TRI->getSubReg(DestReg, SubRegIdx + I))
441 .addReg(Base, getKillRegState(I == NF - 1))
442 .addMemOperand(*(II->memoperands_begin()));
443 if (I != NF - 1)
444 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
445 .addReg(Base, getKillRegState(I != 0 || IsBaseKill))
446 .addReg(VL, getKillRegState(I == NF - 2));
447 Base = NewBase;
448 }
449 II->eraseFromParent();
450}
451
453 int SPAdj, unsigned FIOperandNum,
454 RegScavenger *RS) const {
455 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
456
457 MachineInstr &MI = *II;
458 MachineFunction &MF = *MI.getParent()->getParent();
461 DebugLoc DL = MI.getDebugLoc();
462
463 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
464 Register FrameReg;
466 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
467 bool IsRVVSpill = RISCV::isRVVSpill(MI);
468 if (!IsRVVSpill)
469 Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
470
471 if (Offset.getScalable() &&
472 ST.getRealMinVLen() == ST.getRealMaxVLen()) {
473 // For an exact VLEN value, scalable offsets become constant and thus
474 // can be converted entirely into fixed offsets.
475 int64_t FixedValue = Offset.getFixed();
476 int64_t ScalableValue = Offset.getScalable();
477 assert(ScalableValue % 8 == 0 &&
478 "Scalable offset is not a multiple of a single vector size.");
479 int64_t NumOfVReg = ScalableValue / 8;
480 int64_t VLENB = ST.getRealMinVLen() / 8;
481 Offset = StackOffset::getFixed(FixedValue + NumOfVReg * VLENB);
482 }
483
484 if (!isInt<32>(Offset.getFixed())) {
486 "Frame offsets outside of the signed 32-bit range not supported");
487 }
488
489 if (!IsRVVSpill) {
490 int64_t Val = Offset.getFixed();
491 int64_t Lo12 = SignExtend64<12>(Val);
492 unsigned Opc = MI.getOpcode();
493 if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
494 // We chose to emit the canonical immediate sequence rather than folding
495 // the offset into the using add under the theory that doing so doesn't
496 // save dynamic instruction count and some target may fuse the canonical
497 // 32 bit immediate sequence. We still need to clear the portion of the
498 // offset encoded in the immediate.
499 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
500 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
501 Opc == RISCV::PREFETCH_W) &&
502 (Lo12 & 0b11111) != 0) {
503 // Prefetch instructions require the offset to be 32 byte aligned.
504 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
505 } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
506 Opc == RISCV::PseudoRV32ZdinxSD) &&
507 Lo12 >= 2044) {
508 // This instruction will be split into 2 instructions. The second
509 // instruction will add 4 to the immediate. If that would overflow 12
510 // bits, we can't fold the offset.
511 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
512 } else {
513 // We can encode an add with 12 bit signed immediate in the immediate
514 // operand of our user instruction. As a result, the remaining
515 // offset can by construction, at worst, a LUI and a ADD.
516 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Lo12);
518 Offset.getScalable());
519 }
520 }
521
522 if (Offset.getScalable() || Offset.getFixed()) {
523 Register DestReg;
524 if (MI.getOpcode() == RISCV::ADDI)
525 DestReg = MI.getOperand(0).getReg();
526 else
527 DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
528 adjustReg(*II->getParent(), II, DL, DestReg, FrameReg, Offset,
529 MachineInstr::NoFlags, std::nullopt);
530 MI.getOperand(FIOperandNum).ChangeToRegister(DestReg, /*IsDef*/false,
531 /*IsImp*/false,
532 /*IsKill*/true);
533 } else {
534 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*IsDef*/false,
535 /*IsImp*/false,
536 /*IsKill*/false);
537 }
538
539 // If after materializing the adjustment, we have a pointless ADDI, remove it
540 if (MI.getOpcode() == RISCV::ADDI &&
541 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
542 MI.getOperand(2).getImm() == 0) {
543 MI.eraseFromParent();
544 return true;
545 }
546
547 // Handle spill/fill of synthetic register classes for segment operations to
548 // ensure correctness in the edge case one gets spilled. There are many
549 // possible optimizations here, but given the extreme rarity of such spills,
550 // we prefer simplicity of implementation for now.
551 switch (MI.getOpcode()) {
552 case RISCV::PseudoVSPILL2_M1:
553 case RISCV::PseudoVSPILL2_M2:
554 case RISCV::PseudoVSPILL2_M4:
555 case RISCV::PseudoVSPILL3_M1:
556 case RISCV::PseudoVSPILL3_M2:
557 case RISCV::PseudoVSPILL4_M1:
558 case RISCV::PseudoVSPILL4_M2:
559 case RISCV::PseudoVSPILL5_M1:
560 case RISCV::PseudoVSPILL6_M1:
561 case RISCV::PseudoVSPILL7_M1:
562 case RISCV::PseudoVSPILL8_M1:
564 return true;
565 case RISCV::PseudoVRELOAD2_M1:
566 case RISCV::PseudoVRELOAD2_M2:
567 case RISCV::PseudoVRELOAD2_M4:
568 case RISCV::PseudoVRELOAD3_M1:
569 case RISCV::PseudoVRELOAD3_M2:
570 case RISCV::PseudoVRELOAD4_M1:
571 case RISCV::PseudoVRELOAD4_M2:
572 case RISCV::PseudoVRELOAD5_M1:
573 case RISCV::PseudoVRELOAD6_M1:
574 case RISCV::PseudoVRELOAD7_M1:
575 case RISCV::PseudoVRELOAD8_M1:
577 return true;
578 }
579
580 return false;
581}
582
584 const MachineFunction &MF) const {
585 return true;
586}
587
588// Returns true if the instruction's frame index reference would be better
589// served by a base register other than FP or SP.
590// Used by LocalStackSlotAllocation pass to determine which frame index
591// references it should create new base registers for.
593 int64_t Offset) const {
594 unsigned FIOperandNum = 0;
595 for (; !MI->getOperand(FIOperandNum).isFI(); FIOperandNum++)
596 assert(FIOperandNum < MI->getNumOperands() &&
597 "Instr doesn't have FrameIndex operand");
598
599 // For RISC-V, The machine instructions that include a FrameIndex operand
600 // are load/store, ADDI instructions.
601 unsigned MIFrm = RISCVII::getFormat(MI->getDesc().TSFlags);
602 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
603 return false;
604 // We only generate virtual base registers for loads and stores, so
605 // return false for everything else.
606 if (!MI->mayLoad() && !MI->mayStore())
607 return false;
608
609 const MachineFunction &MF = *MI->getMF();
610 const MachineFrameInfo &MFI = MF.getFrameInfo();
611 const RISCVFrameLowering *TFI = getFrameLowering(MF);
612 const MachineRegisterInfo &MRI = MF.getRegInfo();
613
614 if (TFI->hasFP(MF) && !shouldRealignStack(MF)) {
615 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
616 // Estimate the stack size used to store callee saved registers(
617 // excludes reserved registers).
618 unsigned CalleeSavedSize = 0;
619 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R;
620 ++R) {
621 if (Subtarget.isRegisterReservedByUser(Reg))
622 continue;
623
624 if (RISCV::GPRRegClass.contains(Reg))
625 CalleeSavedSize += getSpillSize(RISCV::GPRRegClass);
626 else if (RISCV::FPR64RegClass.contains(Reg))
627 CalleeSavedSize += getSpillSize(RISCV::FPR64RegClass);
628 else if (RISCV::FPR32RegClass.contains(Reg))
629 CalleeSavedSize += getSpillSize(RISCV::FPR32RegClass);
630 // Ignore vector registers.
631 }
632
633 int64_t MaxFPOffset = Offset - CalleeSavedSize;
634 return !isFrameOffsetLegal(MI, RISCV::X8, MaxFPOffset);
635 }
636
637 // Assume 128 bytes spill slots size to estimate the maximum possible
638 // offset relative to the stack pointer.
639 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
640 // real one for RISC-V.
641 int64_t MaxSPOffset = Offset + 128;
642 MaxSPOffset += MFI.getLocalFrameSize();
643 return !isFrameOffsetLegal(MI, RISCV::X2, MaxSPOffset);
644}
645
646// Determine whether a given base register plus offset immediate is
647// encodable to resolve a frame index.
649 Register BaseReg,
650 int64_t Offset) const {
651 unsigned FIOperandNum = 0;
652 while (!MI->getOperand(FIOperandNum).isFI()) {
653 FIOperandNum++;
654 assert(FIOperandNum < MI->getNumOperands() &&
655 "Instr does not have a FrameIndex operand!");
656 }
657
658 Offset += getFrameIndexInstrOffset(MI, FIOperandNum);
659 return isInt<12>(Offset);
660}
661
662// Insert defining instruction(s) for a pointer to FrameIdx before
663// insertion point I.
664// Return materialized frame pointer.
666 int FrameIdx,
667 int64_t Offset) const {
669 DebugLoc DL;
670 if (MBBI != MBB->end())
671 DL = MBBI->getDebugLoc();
673 MachineRegisterInfo &MFI = MF->getRegInfo();
675
676 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass);
677 BuildMI(*MBB, MBBI, DL, TII->get(RISCV::ADDI), BaseReg)
678 .addFrameIndex(FrameIdx)
679 .addImm(Offset);
680 return BaseReg;
681}
682
683// Resolve a frame index operand of an instruction to reference the
684// indicated base register plus offset instead.
686 int64_t Offset) const {
687 unsigned FIOperandNum = 0;
688 while (!MI.getOperand(FIOperandNum).isFI()) {
689 FIOperandNum++;
690 assert(FIOperandNum < MI.getNumOperands() &&
691 "Instr does not have a FrameIndex operand!");
692 }
693
694 Offset += getFrameIndexInstrOffset(&MI, FIOperandNum);
695 // FrameIndex Operands are always represented as a
696 // register followed by an immediate.
697 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
698 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
699}
700
701// Get the offset from the referenced frame index in the instruction,
702// if there is one.
704 int Idx) const {
705 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
706 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
707 "The MI must be I or S format.");
708 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
709 "FrameIndex operand");
710 return MI->getOperand(Idx + 1).getImm();
711}
712
714 const TargetFrameLowering *TFI = getFrameLowering(MF);
715 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
716}
717
718const uint32_t *
720 CallingConv::ID CC) const {
721 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
722
723 if (CC == CallingConv::GHC)
724 return CSR_NoRegs_RegMask;
725 switch (Subtarget.getTargetABI()) {
726 default:
727 llvm_unreachable("Unrecognized ABI");
730 return CSR_ILP32E_LP64E_RegMask;
734 return CSR_ILP32_LP64_V_RegMask;
735 return CSR_ILP32_LP64_RegMask;
739 return CSR_ILP32F_LP64F_V_RegMask;
740 return CSR_ILP32F_LP64F_RegMask;
744 return CSR_ILP32D_LP64D_V_RegMask;
745 return CSR_ILP32D_LP64D_RegMask;
746 }
747}
748
751 const MachineFunction &) const {
752 if (RC == &RISCV::VMV0RegClass)
753 return &RISCV::VRRegClass;
754 if (RC == &RISCV::VRNoV0RegClass)
755 return &RISCV::VRRegClass;
756 if (RC == &RISCV::VRM2NoV0RegClass)
757 return &RISCV::VRM2RegClass;
758 if (RC == &RISCV::VRM4NoV0RegClass)
759 return &RISCV::VRM4RegClass;
760 if (RC == &RISCV::VRM8NoV0RegClass)
761 return &RISCV::VRM8RegClass;
762 return RC;
763}
764
766 SmallVectorImpl<uint64_t> &Ops) const {
767 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
768 // to represent one vector register. The dwarf offset is
769 // VLENB * scalable_offset / 8.
770 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
771
772 // Add fixed-sized offset using existing DIExpression interface.
773 DIExpression::appendOffset(Ops, Offset.getFixed());
774
775 unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);
776 int64_t VLENBSized = Offset.getScalable() / 8;
777 if (VLENBSized > 0) {
778 Ops.push_back(dwarf::DW_OP_constu);
779 Ops.push_back(VLENBSized);
780 Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
781 Ops.push_back(dwarf::DW_OP_mul);
782 Ops.push_back(dwarf::DW_OP_plus);
783 } else if (VLENBSized < 0) {
784 Ops.push_back(dwarf::DW_OP_constu);
785 Ops.push_back(-VLENBSized);
786 Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
787 Ops.push_back(dwarf::DW_OP_mul);
788 Ops.push_back(dwarf::DW_OP_minus);
789 }
790}
791
792unsigned
794 return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() &&
796 ? 1
797 : 0;
798}
799
800// Add two address hints to improve chances of being able to use a compressed
801// instruction.
803 Register VirtReg, ArrayRef<MCPhysReg> Order,
805 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
806 const MachineRegisterInfo *MRI = &MF.getRegInfo();
807 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
808
809 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
810 VirtReg, Order, Hints, MF, VRM, Matrix);
811
812 if (!VRM || DisableRegAllocHints)
813 return BaseImplRetVal;
814
815 // Add any two address hints after any copy hints.
816 SmallSet<Register, 4> TwoAddrHints;
817
818 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
819 bool NeedGPRC) -> void {
820 Register Reg = MO.getReg();
821 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
822 // TODO: Support GPRPair subregisters? Need to be careful with even/odd
823 // registers. If the virtual register is an odd register of a pair and the
824 // physical register is even (or vice versa), we should not add the hint.
825 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(PhysReg)) &&
826 !MO.getSubReg() && !VRRegMO.getSubReg()) {
827 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
828 TwoAddrHints.insert(PhysReg);
829 }
830 };
831
832 // This is all of the compressible binary instructions. If an instruction
833 // needs GPRC register class operands \p NeedGPRC will be set to true.
834 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
835 NeedGPRC = false;
836 switch (MI.getOpcode()) {
837 default:
838 return false;
839 case RISCV::AND:
840 case RISCV::OR:
841 case RISCV::XOR:
842 case RISCV::SUB:
843 case RISCV::ADDW:
844 case RISCV::SUBW:
845 NeedGPRC = true;
846 return true;
847 case RISCV::ANDI: {
848 NeedGPRC = true;
849 if (!MI.getOperand(2).isImm())
850 return false;
851 int64_t Imm = MI.getOperand(2).getImm();
852 if (isInt<6>(Imm))
853 return true;
854 // c.zext.b
855 return Subtarget.hasStdExtZcb() && Imm == 255;
856 }
857 case RISCV::SRAI:
858 case RISCV::SRLI:
859 NeedGPRC = true;
860 return true;
861 case RISCV::ADD:
862 case RISCV::SLLI:
863 return true;
864 case RISCV::ADDI:
865 case RISCV::ADDIW:
866 return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm());
867 case RISCV::MUL:
868 case RISCV::SEXT_B:
869 case RISCV::SEXT_H:
870 case RISCV::ZEXT_H_RV32:
871 case RISCV::ZEXT_H_RV64:
872 // c.mul, c.sext.b, c.sext.h, c.zext.h
873 NeedGPRC = true;
874 return Subtarget.hasStdExtZcb();
875 case RISCV::ADD_UW:
876 // c.zext.w
877 NeedGPRC = true;
878 return Subtarget.hasStdExtZcb() && MI.getOperand(2).isReg() &&
879 MI.getOperand(2).getReg() == RISCV::X0;
880 case RISCV::XORI:
881 // c.not
882 NeedGPRC = true;
883 return Subtarget.hasStdExtZcb() && MI.getOperand(2).isImm() &&
884 MI.getOperand(2).getImm() == -1;
885 }
886 };
887
888 // Returns true if this operand is compressible. For non-registers it always
889 // returns true. Immediate range was already checked in isCompressible.
890 // For registers, it checks if the register is a GPRC register. reg-reg
891 // instructions that require GPRC need all register operands to be GPRC.
892 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
893 if (!MO.isReg())
894 return true;
895 Register Reg = MO.getReg();
896 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
897 return PhysReg && RISCV::GPRCRegClass.contains(PhysReg);
898 };
899
900 for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
901 const MachineInstr &MI = *MO.getParent();
902 unsigned OpIdx = MO.getOperandNo();
903 bool NeedGPRC;
904 if (isCompressible(MI, NeedGPRC)) {
905 if (OpIdx == 0 && MI.getOperand(1).isReg()) {
906 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
907 MI.getOpcode() == RISCV::ADD_UW ||
908 isCompressibleOpnd(MI.getOperand(2)))
909 tryAddHint(MO, MI.getOperand(1), NeedGPRC);
910 if (MI.isCommutable() && MI.getOperand(2).isReg() &&
911 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1))))
912 tryAddHint(MO, MI.getOperand(2), NeedGPRC);
913 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
914 isCompressibleOpnd(MI.getOperand(2)))) {
915 tryAddHint(MO, MI.getOperand(0), NeedGPRC);
916 } else if (MI.isCommutable() && OpIdx == 2 &&
917 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) {
918 tryAddHint(MO, MI.getOperand(0), NeedGPRC);
919 }
920 }
921 }
922
923 for (MCPhysReg OrderReg : Order)
924 if (TwoAddrHints.count(OrderReg))
925 Hints.push_back(OrderReg);
926
927 return BaseImplRetVal;
928}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Live Register Matrix
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
static cl::opt< bool > DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden, cl::init(false), cl::desc("Disable two address hints for register " "allocation"))
static cl::opt< bool > DisableCostPerUse("riscv-disable-cost-per-use", cl::init(false), cl::Hidden)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:195
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
A debug info location.
Definition: DebugLoc.h:33
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:281
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:743
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasBP(const MachineFunction &MF) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
std::optional< unsigned > getRealVLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
static StackOffset get(int64_t Fixed, int64_t Scalable)
Definition: TypeSize.h:44
Information about stack frame layout on the target.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetInstrInfo * getInstrInfo() const
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ RISCV_VectorCall
Calling convention used for RISC-V V-extension.
Definition: CallingConv.h:268
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
@ GRAAL
Used by GraalVM. Two additional registers are reserved.
Definition: CallingConv.h:255
MCRegister getBPReg()
static unsigned getFormat(uint64_t TSFlags)
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
bool isRVVSpill(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:340
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
unsigned getKillRegState(bool B)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1886
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:141
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerVRELOAD(MachineBasicBlock::iterator II) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
RISCVRegisterInfo(unsigned HwMode)
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void lowerVSPILL(MachineBasicBlock::iterator II) const
Register getFrameRegister(const MachineFunction &MF) const override
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * getNoPreservedMask() const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override